1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
4 * Copyright 2018, Socionext Inc.
5 * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/iopoll.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/resource.h>
22 #define PCL_PHY_CLKCTRL 0x0000
23 #define PORT_SEL_MASK GENMASK(11, 9)
24 #define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1)
26 #define PCL_PHY_TEST_I 0x2000
27 #define TESTI_DAT_MASK GENMASK(13, 6)
28 #define TESTI_ADR_MASK GENMASK(5, 1)
29 #define TESTI_WR_EN BIT(0)
31 #define PCL_PHY_TEST_O 0x2004
32 #define TESTO_DAT_MASK GENMASK(7, 0)
34 #define PCL_PHY_RESET 0x200c
35 #define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */
36 #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */
39 #define SG_USBPCIESEL 0x590
40 #define SG_USBPCIESEL_PCIE BIT(0)
43 #define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */
45 #define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */
46 #define RX_EQ_ADJ_VAL 0
47 #define PCL_PHY_R26 26
48 #define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */
49 #define VCO_CTRL_INIT_VAL 5
51 struct uniphier_pciephy_priv {
54 struct clk *clk, *clk_gio;
55 struct reset_control *rst, *rst_gio;
56 const struct uniphier_pciephy_soc_data *data;
59 struct uniphier_pciephy_soc_data {
61 void (*set_phymode)(struct regmap *regmap);
64 static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv,
67 /* need to read TESTO twice after accessing TESTI */
68 writel(data, priv->base + PCL_PHY_TEST_I);
69 readl(priv->base + PCL_PHY_TEST_O);
70 readl(priv->base + PCL_PHY_TEST_O);
73 static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
74 u32 reg, u32 mask, u32 param)
78 /* read previous data */
79 val = FIELD_PREP(TESTI_DAT_MASK, 1);
80 val |= FIELD_PREP(TESTI_ADR_MASK, reg);
81 uniphier_pciephy_testio_write(priv, val);
82 val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK;
87 val = FIELD_PREP(TESTI_DAT_MASK, val);
88 val |= FIELD_PREP(TESTI_ADR_MASK, reg);
89 uniphier_pciephy_testio_write(priv, val);
90 uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN);
91 uniphier_pciephy_testio_write(priv, val);
93 /* read current data as dummy */
94 val = FIELD_PREP(TESTI_DAT_MASK, 1);
95 val |= FIELD_PREP(TESTI_ADR_MASK, reg);
96 uniphier_pciephy_testio_write(priv, val);
97 readl(priv->base + PCL_PHY_TEST_O);
100 static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv)
104 val = readl(priv->base + PCL_PHY_RESET);
105 val &= ~PCL_PHY_RESET_N;
106 val |= PCL_PHY_RESET_N_MNMODE;
107 writel(val, priv->base + PCL_PHY_RESET);
110 static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv)
114 val = readl(priv->base + PCL_PHY_RESET);
115 val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N;
116 writel(val, priv->base + PCL_PHY_RESET);
119 static int uniphier_pciephy_init(struct phy *phy)
121 struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
125 ret = clk_prepare_enable(priv->clk);
129 ret = clk_prepare_enable(priv->clk_gio);
131 goto out_clk_disable;
133 ret = reset_control_deassert(priv->rst);
135 goto out_clk_gio_disable;
137 ret = reset_control_deassert(priv->rst_gio);
141 /* support only 1 port */
142 val = readl(priv->base + PCL_PHY_CLKCTRL);
143 val &= ~PORT_SEL_MASK;
145 writel(val, priv->base + PCL_PHY_CLKCTRL);
147 /* legacy controller doesn't have phy_reset and parameters */
148 if (priv->data->is_legacy)
151 uniphier_pciephy_set_param(priv, PCL_PHY_R00,
152 RX_EQ_ADJ_EN, RX_EQ_ADJ_EN);
153 uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ,
154 FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));
155 uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL,
156 FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));
159 uniphier_pciephy_deassert(priv);
165 reset_control_assert(priv->rst);
167 clk_disable_unprepare(priv->clk_gio);
169 clk_disable_unprepare(priv->clk);
174 static int uniphier_pciephy_exit(struct phy *phy)
176 struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
178 if (!priv->data->is_legacy)
179 uniphier_pciephy_assert(priv);
180 reset_control_assert(priv->rst_gio);
181 reset_control_assert(priv->rst);
182 clk_disable_unprepare(priv->clk_gio);
183 clk_disable_unprepare(priv->clk);
188 static const struct phy_ops uniphier_pciephy_ops = {
189 .init = uniphier_pciephy_init,
190 .exit = uniphier_pciephy_exit,
191 .owner = THIS_MODULE,
194 static int uniphier_pciephy_probe(struct platform_device *pdev)
196 struct uniphier_pciephy_priv *priv;
197 struct phy_provider *phy_provider;
198 struct device *dev = &pdev->dev;
199 struct regmap *regmap;
202 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
206 priv->data = of_device_get_match_data(dev);
207 if (WARN_ON(!priv->data))
212 priv->base = devm_platform_ioremap_resource(pdev, 0);
213 if (IS_ERR(priv->base))
214 return PTR_ERR(priv->base);
216 if (priv->data->is_legacy) {
217 priv->clk_gio = devm_clk_get(dev, "gio");
218 if (IS_ERR(priv->clk_gio))
219 return PTR_ERR(priv->clk_gio);
222 devm_reset_control_get_shared(dev, "gio");
223 if (IS_ERR(priv->rst_gio))
224 return PTR_ERR(priv->rst_gio);
226 priv->clk = devm_clk_get(dev, "link");
227 if (IS_ERR(priv->clk))
228 return PTR_ERR(priv->clk);
230 priv->rst = devm_reset_control_get_shared(dev, "link");
231 if (IS_ERR(priv->rst))
232 return PTR_ERR(priv->rst);
234 priv->clk = devm_clk_get(dev, NULL);
235 if (IS_ERR(priv->clk))
236 return PTR_ERR(priv->clk);
238 priv->rst = devm_reset_control_get_shared(dev, NULL);
239 if (IS_ERR(priv->rst))
240 return PTR_ERR(priv->rst);
243 phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops);
247 regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
249 if (!IS_ERR(regmap) && priv->data->set_phymode)
250 priv->data->set_phymode(regmap);
252 phy_set_drvdata(phy, priv);
253 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
255 return PTR_ERR_OR_ZERO(phy_provider);
258 static void uniphier_pciephy_ld20_setmode(struct regmap *regmap)
260 regmap_update_bits(regmap, SG_USBPCIESEL,
261 SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
264 static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
268 static const struct uniphier_pciephy_soc_data uniphier_ld20_data = {
270 .set_phymode = uniphier_pciephy_ld20_setmode,
273 static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
277 static const struct of_device_id uniphier_pciephy_match[] = {
279 .compatible = "socionext,uniphier-pro5-pcie-phy",
280 .data = &uniphier_pro5_data,
283 .compatible = "socionext,uniphier-ld20-pcie-phy",
284 .data = &uniphier_ld20_data,
287 .compatible = "socionext,uniphier-pxs3-pcie-phy",
288 .data = &uniphier_pxs3_data,
292 MODULE_DEVICE_TABLE(of, uniphier_pciephy_match);
294 static struct platform_driver uniphier_pciephy_driver = {
295 .probe = uniphier_pciephy_probe,
297 .name = "uniphier-pcie-phy",
298 .of_match_table = uniphier_pciephy_match,
301 module_platform_driver(uniphier_pciephy_driver);
303 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
304 MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller");
305 MODULE_LICENSE("GPL v2");