1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * Authors: Kamil Debski <k.debski@samsung.com>
9 #include <linux/delay.h>
11 #include <linux/phy/phy.h>
12 #include "phy-samsung-usb2.h"
14 /* Exynos USB PHY registers */
16 /* PHY power control */
17 #define S5PV210_UPHYPWR 0x0
19 #define S5PV210_UPHYPWR_PHY0_SUSPEND BIT(0)
20 #define S5PV210_UPHYPWR_PHY0_PWR BIT(3)
21 #define S5PV210_UPHYPWR_PHY0_OTG_PWR BIT(4)
22 #define S5PV210_UPHYPWR_PHY0 ( \
23 S5PV210_UPHYPWR_PHY0_SUSPEND | \
24 S5PV210_UPHYPWR_PHY0_PWR | \
25 S5PV210_UPHYPWR_PHY0_OTG_PWR)
27 #define S5PV210_UPHYPWR_PHY1_SUSPEND BIT(6)
28 #define S5PV210_UPHYPWR_PHY1_PWR BIT(7)
29 #define S5PV210_UPHYPWR_PHY1 ( \
30 S5PV210_UPHYPWR_PHY1_SUSPEND | \
31 S5PV210_UPHYPWR_PHY1_PWR)
33 /* PHY clock control */
34 #define S5PV210_UPHYCLK 0x4
36 #define S5PV210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
37 #define S5PV210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
38 #define S5PV210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
39 #define S5PV210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
41 #define S5PV210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
42 #define S5PV210_UPHYCLK_PHY0_COMMON_ON BIT(4)
43 #define S5PV210_UPHYCLK_PHY1_COMMON_ON BIT(7)
45 /* PHY reset control */
46 #define S5PV210_UPHYRST 0x8
48 #define S5PV210_URSTCON_PHY0 BIT(0)
49 #define S5PV210_URSTCON_OTG_HLINK BIT(1)
50 #define S5PV210_URSTCON_OTG_PHYLINK BIT(2)
51 #define S5PV210_URSTCON_PHY1_ALL BIT(3)
52 #define S5PV210_URSTCON_HOST_LINK_ALL BIT(4)
54 /* Isolation, configured in the power management unit */
55 #define S5PV210_USB_ISOL_OFFSET 0x680c
56 #define S5PV210_USB_ISOL_DEVICE BIT(0)
57 #define S5PV210_USB_ISOL_HOST BIT(1)
67 * s5pv210_rate_to_clk() converts the supplied clock rate to the value that
68 * can be written to the phy register.
70 static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg)
74 *reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ;
77 *reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ;
80 *reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ;
89 static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on)
91 struct samsung_usb2_phy_driver *drv = inst->drv;
94 switch (inst->cfg->id) {
96 mask = S5PV210_USB_ISOL_DEVICE;
99 mask = S5PV210_USB_ISOL_HOST;
105 regmap_update_bits(drv->reg_pmu, S5PV210_USB_ISOL_OFFSET,
106 mask, on ? 0 : mask);
109 static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
111 struct samsung_usb2_phy_driver *drv = inst->drv;
117 switch (inst->cfg->id) {
119 phypwr = S5PV210_UPHYPWR_PHY0;
120 rstbits = S5PV210_URSTCON_PHY0;
123 phypwr = S5PV210_UPHYPWR_PHY1;
124 rstbits = S5PV210_URSTCON_PHY1_ALL |
125 S5PV210_URSTCON_HOST_LINK_ALL;
130 writel(drv->ref_reg_val, drv->reg_phy + S5PV210_UPHYCLK);
132 pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
134 writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
136 rst = readl(drv->reg_phy + S5PV210_UPHYRST);
138 writel(rst, drv->reg_phy + S5PV210_UPHYRST);
141 writel(rst, drv->reg_phy + S5PV210_UPHYRST);
142 /* The following delay is necessary for the reset sequence to be
147 pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
149 writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
153 static int s5pv210_power_on(struct samsung_usb2_phy_instance *inst)
155 s5pv210_isol(inst, 0);
156 s5pv210_phy_pwr(inst, 1);
161 static int s5pv210_power_off(struct samsung_usb2_phy_instance *inst)
163 s5pv210_phy_pwr(inst, 0);
164 s5pv210_isol(inst, 1);
169 static const struct samsung_usb2_common_phy s5pv210_phys[S5PV210_NUM_PHYS] = {
172 .id = S5PV210_DEVICE,
173 .power_on = s5pv210_power_on,
174 .power_off = s5pv210_power_off,
179 .power_on = s5pv210_power_on,
180 .power_off = s5pv210_power_off,
184 const struct samsung_usb2_phy_config s5pv210_usb2_phy_config = {
185 .num_phys = ARRAY_SIZE(s5pv210_phys),
186 .phys = s5pv210_phys,
187 .rate_to_clk = s5pv210_rate_to_clk,