drivers/phy/samsung/phy-exynos-mipi-video.c

   1 /*
   2  * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
   3  *
   4  * Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
   5  * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_device.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/regmap.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/soc/samsung/exynos-regs-pmu.h>
  23 #include <linux/mfd/syscon.h>
  24
  25 enum exynos_mipi_phy_id {
  26         EXYNOS_MIPI_PHY_ID_NONE = -1,
  27         EXYNOS_MIPI_PHY_ID_CSIS0,
  28         EXYNOS_MIPI_PHY_ID_DSIM0,
  29         EXYNOS_MIPI_PHY_ID_CSIS1,
  30         EXYNOS_MIPI_PHY_ID_DSIM1,
  31         EXYNOS_MIPI_PHY_ID_CSIS2,
  32         EXYNOS_MIPI_PHYS_NUM
  33 };
  34
  35 enum exynos_mipi_phy_regmap_id {
  36         EXYNOS_MIPI_REGMAP_PMU,
  37         EXYNOS_MIPI_REGMAP_DISP,
  38         EXYNOS_MIPI_REGMAP_CAM0,
  39         EXYNOS_MIPI_REGMAP_CAM1,
  40         EXYNOS_MIPI_REGMAPS_NUM
  41 };
  42
  43 struct mipi_phy_device_desc {
  44         int num_phys;
  45         int num_regmaps;
  46         const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
  47         struct exynos_mipi_phy_desc {
  48                 enum exynos_mipi_phy_id coupled_phy_id;
  49                 u32 enable_val;
  50                 unsigned int enable_reg;
  51                 enum exynos_mipi_phy_regmap_id enable_map;
  52                 u32 resetn_val;
  53                 unsigned int resetn_reg;
  54                 enum exynos_mipi_phy_regmap_id resetn_map;
  55         } phys[EXYNOS_MIPI_PHYS_NUM];
  56 };
  57
  58 static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
  59         .num_regmaps = 1,
  60         .regmap_names = {"syscon"},
  61         .num_phys = 4,
  62         .phys = {
  63                 {
  64                         /* EXYNOS_MIPI_PHY_ID_CSIS0 */
  65                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
  66                         .enable_val = EXYNOS4_PHY_ENABLE,
  67                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  68                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  69                         .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  70                         .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  71                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  72                 }, {
  73                         /* EXYNOS_MIPI_PHY_ID_DSIM0 */
  74                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
  75                         .enable_val = EXYNOS4_PHY_ENABLE,
  76                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  77                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  78                         .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
  79                         .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  80                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  81                 }, {
  82                         /* EXYNOS_MIPI_PHY_ID_CSIS1 */
  83                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
  84                         .enable_val = EXYNOS4_PHY_ENABLE,
  85                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  86                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  87                         .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  88                         .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  89                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  90                 }, {
  91                         /* EXYNOS_MIPI_PHY_ID_DSIM1 */
  92                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
  93                         .enable_val = EXYNOS4_PHY_ENABLE,
  94                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  95                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  96                         .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
  97                         .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  98                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  99                 },
 100         },
 101 };
 102
 103 static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
 104         .num_regmaps = 1,
 105         .regmap_names = {"syscon"},
 106         .num_phys = 5,
 107         .phys = {
 108                 {
 109                         /* EXYNOS_MIPI_PHY_ID_CSIS0 */
 110                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
 111                         .enable_val = EXYNOS4_PHY_ENABLE,
 112                         .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
 113                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 114                         .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
 115                         .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
 116                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
 117                 }, {
 118                         /* EXYNOS_MIPI_PHY_ID_DSIM0 */
 119                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
 120                         .enable_val = EXYNOS4_PHY_ENABLE,
 121                         .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
 122                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 123                         .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
 124                         .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
 125                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
 126                 }, {
 127                         /* EXYNOS_MIPI_PHY_ID_CSIS1 */
 128                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
 129                         .enable_val = EXYNOS4_PHY_ENABLE,
 130                         .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
 131                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 132                         .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
 133                         .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
 134                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
 135                 }, {
 136                         /* EXYNOS_MIPI_PHY_ID_DSIM1 */
 137                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
 138                         .enable_val = EXYNOS4_PHY_ENABLE,
 139                         .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
 140                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 141                         .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
 142                         .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
 143                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
 144                 }, {
 145                         /* EXYNOS_MIPI_PHY_ID_CSIS2 */
 146                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
 147                         .enable_val = EXYNOS4_PHY_ENABLE,
 148                         .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
 149                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 150                         .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
 151                         .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
 152                         .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
 153                 },
 154         },
 155 };
 156
 157 #define EXYNOS5433_SYSREG_DISP_MIPI_PHY         0x100C
 158 #define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON    0x1014
 159 #define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON    0x1020
 160
 161 static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
 162         .num_regmaps = 4,
 163         .regmap_names = {
 164                 "samsung,pmu-syscon",
 165                 "samsung,disp-sysreg",
 166                 "samsung,cam0-sysreg",
 167                 "samsung,cam1-sysreg"
 168         },
 169         .num_phys = 5,
 170         .phys = {
 171                 {
 172                         /* EXYNOS_MIPI_PHY_ID_CSIS0 */
 173                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
 174                         .enable_val = EXYNOS4_PHY_ENABLE,
 175                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
 176                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 177                         .resetn_val = BIT(0),
 178                         .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
 179                         .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
 180                 }, {
 181                         /* EXYNOS_MIPI_PHY_ID_DSIM0 */
 182                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
 183                         .enable_val = EXYNOS4_PHY_ENABLE,
 184                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
 185                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 186                         .resetn_val = BIT(0),
 187                         .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
 188                         .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
 189                 }, {
 190                         /* EXYNOS_MIPI_PHY_ID_CSIS1 */
 191                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
 192                         .enable_val = EXYNOS4_PHY_ENABLE,
 193                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
 194                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 195                         .resetn_val = BIT(1),
 196                         .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
 197                         .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
 198                 }, {
 199                         /* EXYNOS_MIPI_PHY_ID_DSIM1 */
 200                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
 201                         .enable_val = EXYNOS4_PHY_ENABLE,
 202                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
 203                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 204                         .resetn_val = BIT(1),
 205                         .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
 206                         .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
 207                 }, {
 208                         /* EXYNOS_MIPI_PHY_ID_CSIS2 */
 209                         .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
 210                         .enable_val = EXYNOS4_PHY_ENABLE,
 211                         .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),
 212                         .enable_map = EXYNOS_MIPI_REGMAP_PMU,
 213                         .resetn_val = BIT(0),
 214                         .resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
 215                         .resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
 216                 },
 217         },
 218 };
 219
 220 struct exynos_mipi_video_phy {
 221         struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
 222         int num_phys;
 223         struct video_phy_desc {
 224                 struct phy *phy;
 225                 unsigned int index;
 226                 const struct exynos_mipi_phy_desc *data;
 227         } phys[EXYNOS_MIPI_PHYS_NUM];
 228         spinlock_t slock;
 229 };
 230
 231 static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
 232                            struct exynos_mipi_video_phy *state, unsigned int on)
 233 {
 234         u32 val;
 235
 236         spin_lock(&state->slock);
 237
 238         /* disable in PMU sysreg */
 239         if (!on && data->coupled_phy_id >= 0 &&
 240             state->phys[data->coupled_phy_id].phy->power_count == 0) {
 241                 regmap_read(state->regmaps[data->enable_map], data->enable_reg,
 242                             &val);
 243                 val &= ~data->enable_val;
 244                 regmap_write(state->regmaps[data->enable_map], data->enable_reg,
 245                              val);
 246         }
 247
 248         /* PHY reset */
 249         regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
 250         val = on ? (val | data->resetn_val) : (val & ~data->resetn_val);
 251         regmap_write(state->regmaps[data->resetn_map], data->resetn_reg, val);
 252
 253         /* enable in PMU sysreg */
 254         if (on) {
 255                 regmap_read(state->regmaps[data->enable_map], data->enable_reg,
 256                             &val);
 257                 val |= data->enable_val;
 258                 regmap_write(state->regmaps[data->enable_map], data->enable_reg,
 259                              val);
 260         }
 261
 262         spin_unlock(&state->slock);
 263
 264         return 0;
 265 }
 266
 267 #define to_mipi_video_phy(desc) \
 268         container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
 269
 270 static int exynos_mipi_video_phy_power_on(struct phy *phy)
 271 {
 272         struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
 273         struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
 274
 275         return __set_phy_state(phy_desc->data, state, 1);
 276 }
 277
 278 static int exynos_mipi_video_phy_power_off(struct phy *phy)
 279 {
 280         struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
 281         struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
 282
 283         return __set_phy_state(phy_desc->data, state, 0);
 284 }
 285
 286 static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
 287                                         struct of_phandle_args *args)
 288 {
 289         struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
 290
 291         if (WARN_ON(args->args[0] >= state->num_phys))
 292                 return ERR_PTR(-ENODEV);
 293
 294         return state->phys[args->args[0]].phy;
 295 }
 296
 297 static const struct phy_ops exynos_mipi_video_phy_ops = {
 298         .power_on       = exynos_mipi_video_phy_power_on,
 299         .power_off      = exynos_mipi_video_phy_power_off,
 300         .owner          = THIS_MODULE,
 301 };
 302
 303 static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
 304 {
 305         const struct mipi_phy_device_desc *phy_dev;
 306         struct exynos_mipi_video_phy *state;
 307         struct device *dev = &pdev->dev;
 308         struct device_node *np = dev->of_node;
 309         struct phy_provider *phy_provider;
 310         unsigned int i;
 311
 312         phy_dev = of_device_get_match_data(dev);
 313         if (!phy_dev)
 314                 return -ENODEV;
 315
 316         state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
 317         if (!state)
 318                 return -ENOMEM;
 319
 320         for (i = 0; i < phy_dev->num_regmaps; i++) {
 321                 state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
 322                                                 phy_dev->regmap_names[i]);
 323                 if (IS_ERR(state->regmaps[i]))
 324                         return PTR_ERR(state->regmaps[i]);
 325         }
 326         state->num_phys = phy_dev->num_phys;
 327         spin_lock_init(&state->slock);
 328
 329         dev_set_drvdata(dev, state);
 330
 331         for (i = 0; i < state->num_phys; i++) {
 332                 struct phy *phy = devm_phy_create(dev, NULL,
 333                                                   &exynos_mipi_video_phy_ops);
 334                 if (IS_ERR(phy)) {
 335                         dev_err(dev, "failed to create PHY %d\n", i);
 336                         return PTR_ERR(phy);
 337                 }
 338
 339                 state->phys[i].phy = phy;
 340                 state->phys[i].index = i;
 341                 state->phys[i].data = &phy_dev->phys[i];
 342                 phy_set_drvdata(phy, &state->phys[i]);
 343         }
 344
 345         phy_provider = devm_of_phy_provider_register(dev,
 346                                         exynos_mipi_video_phy_xlate);
 347
 348         return PTR_ERR_OR_ZERO(phy_provider);
 349 }
 350
 351 static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
 352         {
 353                 .compatible = "samsung,s5pv210-mipi-video-phy",
 354                 .data = &s5pv210_mipi_phy,
 355         }, {
 356                 .compatible = "samsung,exynos5420-mipi-video-phy",
 357                 .data = &exynos5420_mipi_phy,
 358         }, {
 359                 .compatible = "samsung,exynos5433-mipi-video-phy",
 360                 .data = &exynos5433_mipi_phy,
 361         },
 362         { /* sentinel */ },
 363 };
 364 MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
 365
 366 static struct platform_driver exynos_mipi_video_phy_driver = {
 367         .probe  = exynos_mipi_video_phy_probe,
 368         .driver = {
 369                 .of_match_table = exynos_mipi_video_phy_of_match,
 370                 .name  = "exynos-mipi-video-phy",
 371         }
 372 };
 373 module_platform_driver(exynos_mipi_video_phy_driver);
 374
 375 MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
 376 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
 377 MODULE_LICENSE("GPL v2");