drivers/phy/rockchip/phy-rockchip-inno-usb2.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   4  *
   5  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/delay.h>
  11 #include <linux/extcon-provider.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/power_supply.h>
  26 #include <linux/regmap.h>
  27 #include <linux/mfd/syscon.h>
  28 #include <linux/usb/of.h>
  29 #include <linux/usb/otg.h>
  30
  31 #define BIT_WRITEABLE_SHIFT     16
  32 #define SCHEDULE_DELAY          (60 * HZ)
  33 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  34
  35 enum rockchip_usb2phy_port_id {
  36         USB2PHY_PORT_OTG,
  37         USB2PHY_PORT_HOST,
  38         USB2PHY_NUM_PORTS,
  39 };
  40
  41 enum rockchip_usb2phy_host_state {
  42         PHY_STATE_HS_ONLINE     = 0,
  43         PHY_STATE_DISCONNECT    = 1,
  44         PHY_STATE_CONNECT       = 2,
  45         PHY_STATE_FS_LS_ONLINE  = 4,
  46 };
  47
  48 /**
  49  * enum usb_chg_state - Different states involved in USB charger detection.
  50  * @USB_CHG_STATE_UNDEFINED:    USB charger is not connected or detection
  51  *                              process is not yet started.
  52  * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact.
  53  * @USB_CHG_STATE_DCD_DONE:     Data pin contact is detected.
  54  * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects
  55  *                              between SDP and DCP/CDP).
  56  * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
  57  *                                between DCP and CDP).
  58  * @USB_CHG_STATE_DETECTED:     USB charger type is determined.
  59  */
  60 enum usb_chg_state {
  61         USB_CHG_STATE_UNDEFINED = 0,
  62         USB_CHG_STATE_WAIT_FOR_DCD,
  63         USB_CHG_STATE_DCD_DONE,
  64         USB_CHG_STATE_PRIMARY_DONE,
  65         USB_CHG_STATE_SECONDARY_DONE,
  66         USB_CHG_STATE_DETECTED,
  67 };
  68
  69 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  70         EXTCON_USB,
  71         EXTCON_USB_HOST,
  72         EXTCON_CHG_USB_SDP,
  73         EXTCON_CHG_USB_CDP,
  74         EXTCON_CHG_USB_DCP,
  75         EXTCON_CHG_USB_SLOW,
  76         EXTCON_NONE,
  77 };
  78
  79 struct usb2phy_reg {
  80         unsigned int    offset;
  81         unsigned int    bitend;
  82         unsigned int    bitstart;
  83         unsigned int    disable;
  84         unsigned int    enable;
  85 };
  86
  87 /**
  88  * struct rockchip_chg_det_reg - usb charger detect registers
  89  * @cp_det: charging port detected successfully.
  90  * @dcp_det: dedicated charging port detected successfully.
  91  * @dp_det: assert data pin connect successfully.
  92  * @idm_sink_en: open dm sink curren.
  93  * @idp_sink_en: open dp sink current.
  94  * @idp_src_en: open dm source current.
  95  * @rdm_pdwn_en: open dm pull down resistor.
  96  * @vdm_src_en: open dm voltage source.
  97  * @vdp_src_en: open dp voltage source.
  98  * @opmode: utmi operational mode.
  99  */
 100 struct rockchip_chg_det_reg {
 101         struct usb2phy_reg      cp_det;
 102         struct usb2phy_reg      dcp_det;
 103         struct usb2phy_reg      dp_det;
 104         struct usb2phy_reg      idm_sink_en;
 105         struct usb2phy_reg      idp_sink_en;
 106         struct usb2phy_reg      idp_src_en;
 107         struct usb2phy_reg      rdm_pdwn_en;
 108         struct usb2phy_reg      vdm_src_en;
 109         struct usb2phy_reg      vdp_src_en;
 110         struct usb2phy_reg      opmode;
 111 };
 112
 113 /**
 114  * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
 115  * @phy_sus: phy suspend register.
 116  * @bvalid_det_en: vbus valid rise detection enable register.
 117  * @bvalid_det_st: vbus valid rise detection status register.
 118  * @bvalid_det_clr: vbus valid rise detection clear register.
 119  * @id_det_en: id detection enable register.
 120  * @id_det_st: id detection state register.
 121  * @id_det_clr: id detection clear register.
 122  * @ls_det_en: linestate detection enable register.
 123  * @ls_det_st: linestate detection state register.
 124  * @ls_det_clr: linestate detection clear register.
 125  * @utmi_avalid: utmi vbus avalid status register.
 126  * @utmi_bvalid: utmi vbus bvalid status register.
 127  * @utmi_id: utmi id state register.
 128  * @utmi_ls: utmi linestate state register.
 129  * @utmi_hstdet: utmi host disconnect register.
 130  */
 131 struct rockchip_usb2phy_port_cfg {
 132         struct usb2phy_reg      phy_sus;
 133         struct usb2phy_reg      bvalid_det_en;
 134         struct usb2phy_reg      bvalid_det_st;
 135         struct usb2phy_reg      bvalid_det_clr;
 136         struct usb2phy_reg      id_det_en;
 137         struct usb2phy_reg      id_det_st;
 138         struct usb2phy_reg      id_det_clr;
 139         struct usb2phy_reg      ls_det_en;
 140         struct usb2phy_reg      ls_det_st;
 141         struct usb2phy_reg      ls_det_clr;
 142         struct usb2phy_reg      utmi_avalid;
 143         struct usb2phy_reg      utmi_bvalid;
 144         struct usb2phy_reg      utmi_id;
 145         struct usb2phy_reg      utmi_ls;
 146         struct usb2phy_reg      utmi_hstdet;
 147 };
 148
 149 /**
 150  * struct rockchip_usb2phy_cfg - usb-phy configuration.
 151  * @reg: the address offset of grf for usb-phy config.
 152  * @num_ports: specify how many ports that the phy has.
 153  * @clkout_ctl: keep on/turn off output clk of phy.
 154  * @port_cfgs: usb-phy port configurations.
 155  * @chg_det: charger detection registers.
 156  */
 157 struct rockchip_usb2phy_cfg {
 158         unsigned int    reg;
 159         unsigned int    num_ports;
 160         struct usb2phy_reg      clkout_ctl;
 161         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 162         const struct rockchip_chg_det_reg       chg_det;
 163 };
 164
 165 /**
 166  * struct rockchip_usb2phy_port - usb-phy port data.
 167  * @phy: generic phy.
 168  * @port_id: flag for otg port or host port.
 169  * @suspended: phy suspended flag.
 170  * @vbus_attached: otg device vbus status.
 171  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 172  * @id_irq: IRQ number assigned for ID pin detection.
 173  * @ls_irq: IRQ number assigned for linestate detection.
 174  * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
 175  *               irqs to one irq in otg-port.
 176  * @mutex: for register updating in sm_work.
 177  * @chg_work: charge detect work.
 178  * @otg_sm_work: OTG state machine work.
 179  * @sm_work: HOST state machine work.
 180  * @port_cfg: port register configuration, assigned by driver data.
 181  * @event_nb: hold event notification callback.
 182  * @state: define OTG enumeration states before device reset.
 183  * @mode: the dr_mode of the controller.
 184  */
 185 struct rockchip_usb2phy_port {
 186         struct phy      *phy;
 187         unsigned int    port_id;
 188         bool            suspended;
 189         bool            vbus_attached;
 190         int             bvalid_irq;
 191         int             id_irq;
 192         int             ls_irq;
 193         int             otg_mux_irq;
 194         struct mutex    mutex;
 195         struct          delayed_work chg_work;
 196         struct          delayed_work otg_sm_work;
 197         struct          delayed_work sm_work;
 198         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 199         struct notifier_block   event_nb;
 200         enum usb_otg_state      state;
 201         enum usb_dr_mode        mode;
 202 };
 203
 204 /**
 205  * struct rockchip_usb2phy - usb2.0 phy driver data.
 206  * @dev: pointer to device.
 207  * @grf: General Register Files regmap.
 208  * @usbgrf: USB General Register Files regmap.
 209  * @clk: clock struct of phy input clk.
 210  * @clk480m: clock struct of phy output clk.
 211  * @clk480m_hw: clock struct of phy output clk management.
 212  * @chg_state: states involved in USB charger detection.
 213  * @chg_type: USB charger types.
 214  * @dcd_retries: The retry count used to track Data contact
 215  *               detection process.
 216  * @edev: extcon device for notification registration
 217  * @irq: muxed interrupt for single irq configuration
 218  * @phy_cfg: phy register configuration, assigned by driver data.
 219  * @ports: phy port instance.
 220  */
 221 struct rockchip_usb2phy {
 222         struct device   *dev;
 223         struct regmap   *grf;
 224         struct regmap   *usbgrf;
 225         struct clk      *clk;
 226         struct clk      *clk480m;
 227         struct clk_hw   clk480m_hw;
 228         enum usb_chg_state      chg_state;
 229         enum power_supply_type  chg_type;
 230         u8                      dcd_retries;
 231         struct extcon_dev       *edev;
 232         int                     irq;
 233         const struct rockchip_usb2phy_cfg       *phy_cfg;
 234         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 235 };
 236
 237 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
 238 {
 239         return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
 240 }
 241
 242 static inline int property_enable(struct regmap *base,
 243                                   const struct usb2phy_reg *reg, bool en)
 244 {
 245         unsigned int val, mask, tmp;
 246
 247         tmp = en ? reg->enable : reg->disable;
 248         mask = GENMASK(reg->bitend, reg->bitstart);
 249         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 250
 251         return regmap_write(base, reg->offset, val);
 252 }
 253
 254 static inline bool property_enabled(struct regmap *base,
 255                                     const struct usb2phy_reg *reg)
 256 {
 257         int ret;
 258         unsigned int tmp, orig;
 259         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 260
 261         ret = regmap_read(base, reg->offset, &orig);
 262         if (ret)
 263                 return false;
 264
 265         tmp = (orig & mask) >> reg->bitstart;
 266         return tmp != reg->disable;
 267 }
 268
 269 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
 270 {
 271         struct rockchip_usb2phy *rphy =
 272                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 273         struct regmap *base = get_reg_base(rphy);
 274         int ret;
 275
 276         /* turn on 480m clk output if it is off */
 277         if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
 278                 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
 279                 if (ret)
 280                         return ret;
 281
 282                 /* waiting for the clk become stable */
 283                 usleep_range(1200, 1300);
 284         }
 285
 286         return 0;
 287 }
 288
 289 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
 290 {
 291         struct rockchip_usb2phy *rphy =
 292                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 293         struct regmap *base = get_reg_base(rphy);
 294
 295         /* turn off 480m clk output */
 296         property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
 297 }
 298
 299 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
 300 {
 301         struct rockchip_usb2phy *rphy =
 302                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 303         struct regmap *base = get_reg_base(rphy);
 304
 305         return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
 306 }
 307
 308 static unsigned long
 309 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 310                                      unsigned long parent_rate)
 311 {
 312         return 480000000;
 313 }
 314
 315 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 316         .prepare = rockchip_usb2phy_clk480m_prepare,
 317         .unprepare = rockchip_usb2phy_clk480m_unprepare,
 318         .is_prepared = rockchip_usb2phy_clk480m_prepared,
 319         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 320 };
 321
 322 static void rockchip_usb2phy_clk480m_unregister(void *data)
 323 {
 324         struct rockchip_usb2phy *rphy = data;
 325
 326         of_clk_del_provider(rphy->dev->of_node);
 327         clk_unregister(rphy->clk480m);
 328 }
 329
 330 static int
 331 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 332 {
 333         struct device_node *node = rphy->dev->of_node;
 334         struct clk_init_data init;
 335         const char *clk_name;
 336         int ret = 0;
 337
 338         init.flags = 0;
 339         init.name = "clk_usbphy_480m";
 340         init.ops = &rockchip_usb2phy_clkout_ops;
 341
 342         /* optional override of the clockname */
 343         of_property_read_string(node, "clock-output-names", &init.name);
 344
 345         if (rphy->clk) {
 346                 clk_name = __clk_get_name(rphy->clk);
 347                 init.parent_names = &clk_name;
 348                 init.num_parents = 1;
 349         } else {
 350                 init.parent_names = NULL;
 351                 init.num_parents = 0;
 352         }
 353
 354         rphy->clk480m_hw.init = &init;
 355
 356         /* register the clock */
 357         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 358         if (IS_ERR(rphy->clk480m)) {
 359                 ret = PTR_ERR(rphy->clk480m);
 360                 goto err_ret;
 361         }
 362
 363         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 364         if (ret < 0)
 365                 goto err_clk_provider;
 366
 367         return devm_add_action_or_reset(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy);
 368
 369 err_clk_provider:
 370         clk_unregister(rphy->clk480m);
 371 err_ret:
 372         return ret;
 373 }
 374
 375 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 376 {
 377         int ret;
 378         struct device_node *node = rphy->dev->of_node;
 379         struct extcon_dev *edev;
 380
 381         if (of_property_read_bool(node, "extcon")) {
 382                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 383                 if (IS_ERR(edev)) {
 384                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 385                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 386                         return PTR_ERR(edev);
 387                 }
 388         } else {
 389                 /* Initialize extcon device */
 390                 edev = devm_extcon_dev_allocate(rphy->dev,
 391                                                 rockchip_usb2phy_extcon_cable);
 392
 393                 if (IS_ERR(edev))
 394                         return -ENOMEM;
 395
 396                 ret = devm_extcon_dev_register(rphy->dev, edev);
 397                 if (ret) {
 398                         dev_err(rphy->dev, "failed to register extcon device\n");
 399                         return ret;
 400                 }
 401         }
 402
 403         rphy->edev = edev;
 404
 405         return 0;
 406 }
 407
 408 static int rockchip_usb2phy_init(struct phy *phy)
 409 {
 410         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 411         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 412         int ret = 0;
 413
 414         mutex_lock(&rport->mutex);
 415
 416         if (rport->port_id == USB2PHY_PORT_OTG) {
 417                 if (rport->mode != USB_DR_MODE_HOST &&
 418                     rport->mode != USB_DR_MODE_UNKNOWN) {
 419                         /* clear bvalid status and enable bvalid detect irq */
 420                         ret = property_enable(rphy->grf,
 421                                               &rport->port_cfg->bvalid_det_clr,
 422                                               true);
 423                         if (ret)
 424                                 goto out;
 425
 426                         ret = property_enable(rphy->grf,
 427                                               &rport->port_cfg->bvalid_det_en,
 428                                               true);
 429                         if (ret)
 430                                 goto out;
 431
 432                         /* clear id status and enable id detect irq */
 433                         ret = property_enable(rphy->grf,
 434                                               &rport->port_cfg->id_det_clr,
 435                                               true);
 436                         if (ret)
 437                                 goto out;
 438
 439                         ret = property_enable(rphy->grf,
 440                                               &rport->port_cfg->id_det_en,
 441                                               true);
 442                         if (ret)
 443                                 goto out;
 444
 445                         schedule_delayed_work(&rport->otg_sm_work,
 446                                               OTG_SCHEDULE_DELAY * 3);
 447                 } else {
 448                         /* If OTG works in host only mode, do nothing. */
 449                         dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
 450                 }
 451         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 452                 /* clear linestate and enable linestate detect irq */
 453                 ret = property_enable(rphy->grf,
 454                                       &rport->port_cfg->ls_det_clr, true);
 455                 if (ret)
 456                         goto out;
 457
 458                 ret = property_enable(rphy->grf,
 459                                       &rport->port_cfg->ls_det_en, true);
 460                 if (ret)
 461                         goto out;
 462
 463                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 464         }
 465
 466 out:
 467         mutex_unlock(&rport->mutex);
 468         return ret;
 469 }
 470
 471 static int rockchip_usb2phy_power_on(struct phy *phy)
 472 {
 473         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 474         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 475         struct regmap *base = get_reg_base(rphy);
 476         int ret;
 477
 478         dev_dbg(&rport->phy->dev, "port power on\n");
 479
 480         if (!rport->suspended)
 481                 return 0;
 482
 483         ret = clk_prepare_enable(rphy->clk480m);
 484         if (ret)
 485                 return ret;
 486
 487         ret = property_enable(base, &rport->port_cfg->phy_sus, false);
 488         if (ret) {
 489                 clk_disable_unprepare(rphy->clk480m);
 490                 return ret;
 491         }
 492
 493         /* waiting for the utmi_clk to become stable */
 494         usleep_range(1500, 2000);
 495
 496         rport->suspended = false;
 497         return 0;
 498 }
 499
 500 static int rockchip_usb2phy_power_off(struct phy *phy)
 501 {
 502         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 503         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 504         struct regmap *base = get_reg_base(rphy);
 505         int ret;
 506
 507         dev_dbg(&rport->phy->dev, "port power off\n");
 508
 509         if (rport->suspended)
 510                 return 0;
 511
 512         ret = property_enable(base, &rport->port_cfg->phy_sus, true);
 513         if (ret)
 514                 return ret;
 515
 516         rport->suspended = true;
 517         clk_disable_unprepare(rphy->clk480m);
 518
 519         return 0;
 520 }
 521
 522 static int rockchip_usb2phy_exit(struct phy *phy)
 523 {
 524         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 525
 526         if (rport->port_id == USB2PHY_PORT_OTG &&
 527             rport->mode != USB_DR_MODE_HOST &&
 528             rport->mode != USB_DR_MODE_UNKNOWN) {
 529                 cancel_delayed_work_sync(&rport->otg_sm_work);
 530                 cancel_delayed_work_sync(&rport->chg_work);
 531         } else if (rport->port_id == USB2PHY_PORT_HOST)
 532                 cancel_delayed_work_sync(&rport->sm_work);
 533
 534         return 0;
 535 }
 536
 537 static const struct phy_ops rockchip_usb2phy_ops = {
 538         .init           = rockchip_usb2phy_init,
 539         .exit           = rockchip_usb2phy_exit,
 540         .power_on       = rockchip_usb2phy_power_on,
 541         .power_off      = rockchip_usb2phy_power_off,
 542         .owner          = THIS_MODULE,
 543 };
 544
 545 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 546 {
 547         struct rockchip_usb2phy_port *rport =
 548                 container_of(work, struct rockchip_usb2phy_port,
 549                              otg_sm_work.work);
 550         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 551         static unsigned int cable;
 552         unsigned long delay;
 553         bool vbus_attach, sch_work, notify_charger;
 554
 555         vbus_attach = property_enabled(rphy->grf,
 556                                        &rport->port_cfg->utmi_bvalid);
 557
 558         sch_work = false;
 559         notify_charger = false;
 560         delay = OTG_SCHEDULE_DELAY;
 561         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 562                 usb_otg_state_string(rport->state));
 563
 564         switch (rport->state) {
 565         case OTG_STATE_UNDEFINED:
 566                 rport->state = OTG_STATE_B_IDLE;
 567                 if (!vbus_attach)
 568                         rockchip_usb2phy_power_off(rport->phy);
 569                 fallthrough;
 570         case OTG_STATE_B_IDLE:
 571                 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
 572                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 573                         rport->state = OTG_STATE_A_HOST;
 574                         rockchip_usb2phy_power_on(rport->phy);
 575                         return;
 576                 } else if (vbus_attach) {
 577                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 578                         switch (rphy->chg_state) {
 579                         case USB_CHG_STATE_UNDEFINED:
 580                                 schedule_delayed_work(&rport->chg_work, 0);
 581                                 return;
 582                         case USB_CHG_STATE_DETECTED:
 583                                 switch (rphy->chg_type) {
 584                                 case POWER_SUPPLY_TYPE_USB:
 585                                         dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
 586                                         rockchip_usb2phy_power_on(rport->phy);
 587                                         rport->state = OTG_STATE_B_PERIPHERAL;
 588                                         notify_charger = true;
 589                                         sch_work = true;
 590                                         cable = EXTCON_CHG_USB_SDP;
 591                                         break;
 592                                 case POWER_SUPPLY_TYPE_USB_DCP:
 593                                         dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
 594                                         rockchip_usb2phy_power_off(rport->phy);
 595                                         notify_charger = true;
 596                                         sch_work = true;
 597                                         cable = EXTCON_CHG_USB_DCP;
 598                                         break;
 599                                 case POWER_SUPPLY_TYPE_USB_CDP:
 600                                         dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
 601                                         rockchip_usb2phy_power_on(rport->phy);
 602                                         rport->state = OTG_STATE_B_PERIPHERAL;
 603                                         notify_charger = true;
 604                                         sch_work = true;
 605                                         cable = EXTCON_CHG_USB_CDP;
 606                                         break;
 607                                 default:
 608                                         break;
 609                                 }
 610                                 break;
 611                         default:
 612                                 break;
 613                         }
 614                 } else {
 615                         notify_charger = true;
 616                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 617                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 618                 }
 619
 620                 if (rport->vbus_attached != vbus_attach) {
 621                         rport->vbus_attached = vbus_attach;
 622
 623                         if (notify_charger && rphy->edev) {
 624                                 extcon_set_state_sync(rphy->edev,
 625                                                         cable, vbus_attach);
 626                                 if (cable == EXTCON_CHG_USB_SDP)
 627                                         extcon_set_state_sync(rphy->edev,
 628                                                               EXTCON_USB,
 629                                                               vbus_attach);
 630                         }
 631                 }
 632                 break;
 633         case OTG_STATE_B_PERIPHERAL:
 634                 if (!vbus_attach) {
 635                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 636                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 637                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 638                         rport->state = OTG_STATE_B_IDLE;
 639                         delay = 0;
 640                         rockchip_usb2phy_power_off(rport->phy);
 641                 }
 642                 sch_work = true;
 643                 break;
 644         case OTG_STATE_A_HOST:
 645                 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
 646                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 647                         rport->state = OTG_STATE_B_IDLE;
 648                         rockchip_usb2phy_power_off(rport->phy);
 649                 }
 650                 break;
 651         default:
 652                 break;
 653         }
 654
 655         if (sch_work)
 656                 schedule_delayed_work(&rport->otg_sm_work, delay);
 657 }
 658
 659 static const char *chg_to_string(enum power_supply_type chg_type)
 660 {
 661         switch (chg_type) {
 662         case POWER_SUPPLY_TYPE_USB:
 663                 return "USB_SDP_CHARGER";
 664         case POWER_SUPPLY_TYPE_USB_DCP:
 665                 return "USB_DCP_CHARGER";
 666         case POWER_SUPPLY_TYPE_USB_CDP:
 667                 return "USB_CDP_CHARGER";
 668         default:
 669                 return "INVALID_CHARGER";
 670         }
 671 }
 672
 673 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 674                                     bool en)
 675 {
 676         struct regmap *base = get_reg_base(rphy);
 677
 678         property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 679         property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
 680 }
 681
 682 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 683                                             bool en)
 684 {
 685         struct regmap *base = get_reg_base(rphy);
 686
 687         property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 688         property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 689 }
 690
 691 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 692                                               bool en)
 693 {
 694         struct regmap *base = get_reg_base(rphy);
 695
 696         property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 697         property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 698 }
 699
 700 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 701 #define CHG_DCD_MAX_RETRIES     6
 702 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 703 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 704 static void rockchip_chg_detect_work(struct work_struct *work)
 705 {
 706         struct rockchip_usb2phy_port *rport =
 707                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 708         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 709         struct regmap *base = get_reg_base(rphy);
 710         bool is_dcd, tmout, vout;
 711         unsigned long delay;
 712
 713         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 714                 rphy->chg_state);
 715         switch (rphy->chg_state) {
 716         case USB_CHG_STATE_UNDEFINED:
 717                 if (!rport->suspended)
 718                         rockchip_usb2phy_power_off(rport->phy);
 719                 /* put the controller in non-driving mode */
 720                 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
 721                 /* Start DCD processing stage 1 */
 722                 rockchip_chg_enable_dcd(rphy, true);
 723                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 724                 rphy->dcd_retries = 0;
 725                 delay = CHG_DCD_POLL_TIME;
 726                 break;
 727         case USB_CHG_STATE_WAIT_FOR_DCD:
 728                 /* get data contact detection status */
 729                 is_dcd = property_enabled(rphy->grf,
 730                                           &rphy->phy_cfg->chg_det.dp_det);
 731                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 732                 /* stage 2 */
 733                 if (is_dcd || tmout) {
 734                         /* stage 4 */
 735                         /* Turn off DCD circuitry */
 736                         rockchip_chg_enable_dcd(rphy, false);
 737                         /* Voltage Source on DP, Probe on DM */
 738                         rockchip_chg_enable_primary_det(rphy, true);
 739                         delay = CHG_PRIMARY_DET_TIME;
 740                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 741                 } else {
 742                         /* stage 3 */
 743                         delay = CHG_DCD_POLL_TIME;
 744                 }
 745                 break;
 746         case USB_CHG_STATE_DCD_DONE:
 747                 vout = property_enabled(rphy->grf,
 748                                         &rphy->phy_cfg->chg_det.cp_det);
 749                 rockchip_chg_enable_primary_det(rphy, false);
 750                 if (vout) {
 751                         /* Voltage Source on DM, Probe on DP  */
 752                         rockchip_chg_enable_secondary_det(rphy, true);
 753                         delay = CHG_SECONDARY_DET_TIME;
 754                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 755                 } else {
 756                         if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
 757                                 /* floating charger found */
 758                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 759                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 760                                 delay = 0;
 761                         } else {
 762                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 763                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 764                                 delay = 0;
 765                         }
 766                 }
 767                 break;
 768         case USB_CHG_STATE_PRIMARY_DONE:
 769                 vout = property_enabled(rphy->grf,
 770                                         &rphy->phy_cfg->chg_det.dcp_det);
 771                 /* Turn off voltage source */
 772                 rockchip_chg_enable_secondary_det(rphy, false);
 773                 if (vout)
 774                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 775                 else
 776                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 777                 fallthrough;
 778         case USB_CHG_STATE_SECONDARY_DONE:
 779                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 780                 fallthrough;
 781         case USB_CHG_STATE_DETECTED:
 782                 /* put the controller in normal mode */
 783                 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
 784                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 785                 dev_dbg(&rport->phy->dev, "charger = %s\n",
 786                          chg_to_string(rphy->chg_type));
 787                 return;
 788         default:
 789                 return;
 790         }
 791
 792         schedule_delayed_work(&rport->chg_work, delay);
 793 }
 794
 795 /*
 796  * The function manage host-phy port state and suspend/resume phy port
 797  * to save power.
 798  *
 799  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 800  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 801  * disconnected or HS disconnected, actually, we just only need get the
 802  * device is disconnected at last through rearm the delayed work,
 803  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 804  *
 805  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 806  * some clk related APIs, so do not invoke it from interrupt context directly.
 807  */
 808 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 809 {
 810         struct rockchip_usb2phy_port *rport =
 811                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 812         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 813         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 814                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 815         unsigned int ul, uhd, state;
 816         unsigned int ul_mask, uhd_mask;
 817         int ret;
 818
 819         mutex_lock(&rport->mutex);
 820
 821         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 822         if (ret < 0)
 823                 goto next_schedule;
 824
 825         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
 826         if (ret < 0)
 827                 goto next_schedule;
 828
 829         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 830                            rport->port_cfg->utmi_hstdet.bitstart);
 831         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 832                           rport->port_cfg->utmi_ls.bitstart);
 833
 834         /* stitch on utmi_ls and utmi_hstdet as phy state */
 835         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 836                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 837
 838         switch (state) {
 839         case PHY_STATE_HS_ONLINE:
 840                 dev_dbg(&rport->phy->dev, "HS online\n");
 841                 break;
 842         case PHY_STATE_FS_LS_ONLINE:
 843                 /*
 844                  * For FS/LS device, the online state share with connect state
 845                  * from utmi_ls and utmi_hstdet register, so we distinguish
 846                  * them via suspended flag.
 847                  *
 848                  * Plus, there are two cases, one is D- Line pull-up, and D+
 849                  * line pull-down, the state is 4; another is D+ line pull-up,
 850                  * and D- line pull-down, the state is 2.
 851                  */
 852                 if (!rport->suspended) {
 853                         /* D- line pull-up, D+ line pull-down */
 854                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 855                         break;
 856                 }
 857                 fallthrough;
 858         case PHY_STATE_CONNECT:
 859                 if (rport->suspended) {
 860                         dev_dbg(&rport->phy->dev, "Connected\n");
 861                         rockchip_usb2phy_power_on(rport->phy);
 862                         rport->suspended = false;
 863                 } else {
 864                         /* D+ line pull-up, D- line pull-down */
 865                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 866                 }
 867                 break;
 868         case PHY_STATE_DISCONNECT:
 869                 if (!rport->suspended) {
 870                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 871                         rockchip_usb2phy_power_off(rport->phy);
 872                         rport->suspended = true;
 873                 }
 874
 875                 /*
 876                  * activate the linestate detection to get the next device
 877                  * plug-in irq.
 878                  */
 879                 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
 880                 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
 881
 882                 /*
 883                  * we don't need to rearm the delayed work when the phy port
 884                  * is suspended.
 885                  */
 886                 mutex_unlock(&rport->mutex);
 887                 return;
 888         default:
 889                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 890                 break;
 891         }
 892
 893 next_schedule:
 894         mutex_unlock(&rport->mutex);
 895         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 896 }
 897
 898 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 899 {
 900         struct rockchip_usb2phy_port *rport = data;
 901         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 902
 903         if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
 904                 return IRQ_NONE;
 905
 906         mutex_lock(&rport->mutex);
 907
 908         /* disable linestate detect irq and clear its status */
 909         property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
 910         property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
 911
 912         mutex_unlock(&rport->mutex);
 913
 914         /*
 915          * In this case for host phy port, a new device is plugged in,
 916          * meanwhile, if the phy port is suspended, we need rearm the work to
 917          * resume it and mange its states; otherwise, we do nothing about that.
 918          */
 919         if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
 920                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
 921
 922         return IRQ_HANDLED;
 923 }
 924
 925 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 926 {
 927         struct rockchip_usb2phy_port *rport = data;
 928         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 929
 930         if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
 931                 return IRQ_NONE;
 932
 933         /* clear bvalid detect irq pending status */
 934         property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
 935
 936         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 937
 938         return IRQ_HANDLED;
 939 }
 940
 941 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
 942 {
 943         struct rockchip_usb2phy_port *rport = data;
 944         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 945         bool id;
 946
 947         if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st))
 948                 return IRQ_NONE;
 949
 950         /* clear id detect irq pending status */
 951         property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true);
 952
 953         id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
 954         extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
 955
 956         return IRQ_HANDLED;
 957 }
 958
 959 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
 960 {
 961         irqreturn_t ret = IRQ_NONE;
 962
 963         ret |= rockchip_usb2phy_bvalid_irq(irq, data);
 964         ret |= rockchip_usb2phy_id_irq(irq, data);
 965
 966         return ret;
 967 }
 968
 969 static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
 970 {
 971         struct rockchip_usb2phy *rphy = data;
 972         struct rockchip_usb2phy_port *rport;
 973         irqreturn_t ret = IRQ_NONE;
 974         unsigned int index;
 975
 976         for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
 977                 rport = &rphy->ports[index];
 978                 if (!rport->phy)
 979                         continue;
 980
 981                 switch (rport->port_id) {
 982                 case USB2PHY_PORT_OTG:
 983                         if (rport->mode != USB_DR_MODE_HOST &&
 984                             rport->mode != USB_DR_MODE_UNKNOWN)
 985                                 ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
 986                         break;
 987                 case USB2PHY_PORT_HOST:
 988                         ret |= rockchip_usb2phy_linestate_irq(irq, rport);
 989                         break;
 990                 }
 991         }
 992
 993         return ret;
 994 }
 995
 996 static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
 997                                           struct rockchip_usb2phy_port *rport,
 998                                           struct device_node *child_np)
 999 {
1000         int ret;
1001
1002         /*
1003          * If the usb2 phy used combined irq for otg and host port,
1004          * don't need to init otg and host port irq separately.
1005          */
1006         if (rphy->irq > 0)
1007                 return 0;
1008
1009         switch (rport->port_id) {
1010         case USB2PHY_PORT_HOST:
1011                 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1012                 if (rport->ls_irq < 0) {
1013                         dev_err(rphy->dev, "no linestate irq provided\n");
1014                         return rport->ls_irq;
1015                 }
1016
1017                 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1018                                                 rockchip_usb2phy_linestate_irq,
1019                                                 IRQF_ONESHOT,
1020                                                 "rockchip_usb2phy", rport);
1021                 if (ret) {
1022                         dev_err(rphy->dev, "failed to request linestate irq handle\n");
1023                         return ret;
1024                 }
1025                 break;
1026         case USB2PHY_PORT_OTG:
1027                 /*
1028                  * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
1029                  * interrupts muxed together, so probe the otg-mux interrupt first,
1030                  * if not found, then look for the regular interrupts one by one.
1031                  */
1032                 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1033                 if (rport->otg_mux_irq > 0) {
1034                         ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
1035                                                         NULL,
1036                                                         rockchip_usb2phy_otg_mux_irq,
1037                                                         IRQF_ONESHOT,
1038                                                         "rockchip_usb2phy_otg",
1039                                                         rport);
1040                         if (ret) {
1041                                 dev_err(rphy->dev,
1042                                         "failed to request otg-mux irq handle\n");
1043                                 return ret;
1044                         }
1045                 } else {
1046                         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1047                         if (rport->bvalid_irq < 0) {
1048                                 dev_err(rphy->dev, "no vbus valid irq provided\n");
1049                                 ret = rport->bvalid_irq;
1050                                 return ret;
1051                         }
1052
1053                         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1054                                                         NULL,
1055                                                         rockchip_usb2phy_bvalid_irq,
1056                                                         IRQF_ONESHOT,
1057                                                         "rockchip_usb2phy_bvalid",
1058                                                         rport);
1059                         if (ret) {
1060                                 dev_err(rphy->dev,
1061                                         "failed to request otg-bvalid irq handle\n");
1062                                 return ret;
1063                         }
1064
1065                         rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1066                         if (rport->id_irq < 0) {
1067                                 dev_err(rphy->dev, "no otg-id irq provided\n");
1068                                 ret = rport->id_irq;
1069                                 return ret;
1070                         }
1071
1072                         ret = devm_request_threaded_irq(rphy->dev, rport->id_irq,
1073                                                         NULL,
1074                                                         rockchip_usb2phy_id_irq,
1075                                                         IRQF_ONESHOT,
1076                                                         "rockchip_usb2phy_id",
1077                                                         rport);
1078                         if (ret) {
1079                                 dev_err(rphy->dev,
1080                                         "failed to request otg-id irq handle\n");
1081                                 return ret;
1082                         }
1083                 }
1084                 break;
1085         default:
1086                 return -EINVAL;
1087         }
1088
1089         return 0;
1090 }
1091
1092 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1093                                            struct rockchip_usb2phy_port *rport,
1094                                            struct device_node *child_np)
1095 {
1096         int ret;
1097
1098         rport->port_id = USB2PHY_PORT_HOST;
1099         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1100         rport->suspended = true;
1101
1102         mutex_init(&rport->mutex);
1103         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1104
1105         ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1106         if (ret) {
1107                 dev_err(rphy->dev, "failed to setup host irq\n");
1108                 return ret;
1109         }
1110
1111         return 0;
1112 }
1113
1114 static int rockchip_otg_event(struct notifier_block *nb,
1115                               unsigned long event, void *ptr)
1116 {
1117         struct rockchip_usb2phy_port *rport =
1118                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1119
1120         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1121
1122         return NOTIFY_DONE;
1123 }
1124
1125 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1126                                           struct rockchip_usb2phy_port *rport,
1127                                           struct device_node *child_np)
1128 {
1129         int ret, id;
1130
1131         rport->port_id = USB2PHY_PORT_OTG;
1132         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1133         rport->state = OTG_STATE_UNDEFINED;
1134
1135         /*
1136          * set suspended flag to true, but actually don't
1137          * put phy in suspend mode, it aims to enable usb
1138          * phy and clock in power_on() called by usb controller
1139          * driver during probe.
1140          */
1141         rport->suspended = true;
1142         rport->vbus_attached = false;
1143
1144         mutex_init(&rport->mutex);
1145
1146         rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1147         if (rport->mode == USB_DR_MODE_HOST ||
1148             rport->mode == USB_DR_MODE_UNKNOWN) {
1149                 ret = 0;
1150                 goto out;
1151         }
1152
1153         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1154         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1155
1156         ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1157         if (ret) {
1158                 dev_err(rphy->dev, "failed to init irq for host port\n");
1159                 goto out;
1160         }
1161
1162         if (!IS_ERR(rphy->edev)) {
1163                 rport->event_nb.notifier_call = rockchip_otg_event;
1164
1165                 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1166                                         EXTCON_USB_HOST, &rport->event_nb);
1167                 if (ret) {
1168                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1169                         goto out;
1170                 }
1171
1172                 if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
1173                         /* do initial sync of usb state */
1174                         id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
1175                         extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
1176                 }
1177         }
1178
1179 out:
1180         return ret;
1181 }
1182
1183 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1184 {
1185         struct device *dev = &pdev->dev;
1186         struct device_node *np = dev->of_node;
1187         struct device_node *child_np;
1188         struct phy_provider *provider;
1189         struct rockchip_usb2phy *rphy;
1190         const struct rockchip_usb2phy_cfg *phy_cfgs;
1191         const struct of_device_id *match;
1192         unsigned int reg;
1193         int index, ret;
1194
1195         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1196         if (!rphy)
1197                 return -ENOMEM;
1198
1199         match = of_match_device(dev->driver->of_match_table, dev);
1200         if (!match || !match->data) {
1201                 dev_err(dev, "phy configs are not assigned!\n");
1202                 return -EINVAL;
1203         }
1204
1205         if (!dev->parent || !dev->parent->of_node) {
1206                 rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
1207                 if (IS_ERR(rphy->grf)) {
1208                         dev_err(dev, "failed to locate usbgrf\n");
1209                         return PTR_ERR(rphy->grf);
1210                 }
1211         }
1212
1213         else {
1214                 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1215                 if (IS_ERR(rphy->grf))
1216                         return PTR_ERR(rphy->grf);
1217         }
1218
1219         if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1220                 rphy->usbgrf =
1221                         syscon_regmap_lookup_by_phandle(dev->of_node,
1222                                                         "rockchip,usbgrf");
1223                 if (IS_ERR(rphy->usbgrf))
1224                         return PTR_ERR(rphy->usbgrf);
1225         } else {
1226                 rphy->usbgrf = NULL;
1227         }
1228
1229         if (of_property_read_u32_index(np, "reg", 0, &reg)) {
1230                 dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1231                         np);
1232                 return -EINVAL;
1233         }
1234
1235         /* support address_cells=2 */
1236         if (reg == 0) {
1237                 if (of_property_read_u32_index(np, "reg", 1, &reg)) {
1238                         dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1239                                 np);
1240                         return -EINVAL;
1241                 }
1242         }
1243
1244         rphy->dev = dev;
1245         phy_cfgs = match->data;
1246         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1247         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1248         rphy->irq = platform_get_irq_optional(pdev, 0);
1249         platform_set_drvdata(pdev, rphy);
1250
1251         ret = rockchip_usb2phy_extcon_register(rphy);
1252         if (ret)
1253                 return ret;
1254
1255         /* find out a proper config which can be matched with dt. */
1256         index = 0;
1257         while (phy_cfgs[index].reg) {
1258                 if (phy_cfgs[index].reg == reg) {
1259                         rphy->phy_cfg = &phy_cfgs[index];
1260                         break;
1261                 }
1262
1263                 ++index;
1264         }
1265
1266         if (!rphy->phy_cfg) {
1267                 dev_err(dev, "no phy-config can be matched with %pOFn node\n",
1268                         np);
1269                 return -EINVAL;
1270         }
1271
1272         rphy->clk = of_clk_get_by_name(np, "phyclk");
1273         if (!IS_ERR(rphy->clk)) {
1274                 clk_prepare_enable(rphy->clk);
1275         } else {
1276                 dev_info(&pdev->dev, "no phyclk specified\n");
1277                 rphy->clk = NULL;
1278         }
1279
1280         ret = rockchip_usb2phy_clk480m_register(rphy);
1281         if (ret) {
1282                 dev_err(dev, "failed to register 480m output clock\n");
1283                 goto disable_clks;
1284         }
1285
1286         index = 0;
1287         for_each_available_child_of_node(np, child_np) {
1288                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1289                 struct phy *phy;
1290
1291                 /* This driver aims to support both otg-port and host-port */
1292                 if (!of_node_name_eq(child_np, "host-port") &&
1293                     !of_node_name_eq(child_np, "otg-port"))
1294                         goto next_child;
1295
1296                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1297                 if (IS_ERR(phy)) {
1298                         dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n");
1299                         ret = PTR_ERR(phy);
1300                         goto put_child;
1301                 }
1302
1303                 rport->phy = phy;
1304                 phy_set_drvdata(rport->phy, rport);
1305
1306                 /* initialize otg/host port separately */
1307                 if (of_node_name_eq(child_np, "host-port")) {
1308                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1309                                                               child_np);
1310                         if (ret)
1311                                 goto put_child;
1312                 } else {
1313                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1314                                                              child_np);
1315                         if (ret)
1316                                 goto put_child;
1317                 }
1318
1319 next_child:
1320                 /* to prevent out of boundary */
1321                 if (++index >= rphy->phy_cfg->num_ports) {
1322                         of_node_put(child_np);
1323                         break;
1324                 }
1325         }
1326
1327         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1328
1329         if (rphy->irq > 0) {
1330                 ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
1331                                                 rockchip_usb2phy_irq,
1332                                                 IRQF_ONESHOT,
1333                                                 "rockchip_usb2phy",
1334                                                 rphy);
1335                 if (ret) {
1336                         dev_err(rphy->dev,
1337                                 "failed to request usb2phy irq handle\n");
1338                         goto put_child;
1339                 }
1340         }
1341
1342         return PTR_ERR_OR_ZERO(provider);
1343
1344 put_child:
1345         of_node_put(child_np);
1346 disable_clks:
1347         if (rphy->clk) {
1348                 clk_disable_unprepare(rphy->clk);
1349                 clk_put(rphy->clk);
1350         }
1351         return ret;
1352 }
1353
1354 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1355         {
1356                 .reg = 0x760,
1357                 .num_ports      = 2,
1358                 .clkout_ctl     = { 0x0768, 4, 4, 1, 0 },
1359                 .port_cfgs      = {
1360                         [USB2PHY_PORT_OTG] = {
1361                                 .phy_sus        = { 0x0760, 15, 0, 0, 0x1d1 },
1362                                 .bvalid_det_en  = { 0x0680, 3, 3, 0, 1 },
1363                                 .bvalid_det_st  = { 0x0690, 3, 3, 0, 1 },
1364                                 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1365                                 .id_det_en      = { 0x0680, 6, 5, 0, 3 },
1366                                 .id_det_st      = { 0x0690, 6, 5, 0, 3 },
1367                                 .id_det_clr     = { 0x06a0, 6, 5, 0, 3 },
1368                                 .ls_det_en      = { 0x0680, 2, 2, 0, 1 },
1369                                 .ls_det_st      = { 0x0690, 2, 2, 0, 1 },
1370                                 .ls_det_clr     = { 0x06a0, 2, 2, 0, 1 },
1371                                 .utmi_bvalid    = { 0x0480, 4, 4, 0, 1 },
1372                                 .utmi_id        = { 0x0480, 1, 1, 0, 1 },
1373                                 .utmi_ls        = { 0x0480, 3, 2, 0, 1 },
1374                         },
1375                         [USB2PHY_PORT_HOST] = {
1376                                 .phy_sus        = { 0x0764, 15, 0, 0, 0x1d1 },
1377                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1378                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1379                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 }
1380                         }
1381                 },
1382                 .chg_det = {
1383                         .opmode         = { 0x0760, 3, 0, 5, 1 },
1384                         .cp_det         = { 0x0884, 4, 4, 0, 1 },
1385                         .dcp_det        = { 0x0884, 3, 3, 0, 1 },
1386                         .dp_det         = { 0x0884, 5, 5, 0, 1 },
1387                         .idm_sink_en    = { 0x0768, 8, 8, 0, 1 },
1388                         .idp_sink_en    = { 0x0768, 7, 7, 0, 1 },
1389                         .idp_src_en     = { 0x0768, 9, 9, 0, 1 },
1390                         .rdm_pdwn_en    = { 0x0768, 10, 10, 0, 1 },
1391                         .vdm_src_en     = { 0x0768, 12, 12, 0, 1 },
1392                         .vdp_src_en     = { 0x0768, 11, 11, 0, 1 },
1393                 },
1394         },
1395         {
1396                 .reg = 0x800,
1397                 .num_ports      = 2,
1398                 .clkout_ctl     = { 0x0808, 4, 4, 1, 0 },
1399                 .port_cfgs      = {
1400                         [USB2PHY_PORT_OTG] = {
1401                                 .phy_sus        = { 0x800, 15, 0, 0, 0x1d1 },
1402                                 .ls_det_en      = { 0x0684, 0, 0, 0, 1 },
1403                                 .ls_det_st      = { 0x0694, 0, 0, 0, 1 },
1404                                 .ls_det_clr     = { 0x06a4, 0, 0, 0, 1 }
1405                         },
1406                         [USB2PHY_PORT_HOST] = {
1407                                 .phy_sus        = { 0x804, 15, 0, 0, 0x1d1 },
1408                                 .ls_det_en      = { 0x0684, 1, 1, 0, 1 },
1409                                 .ls_det_st      = { 0x0694, 1, 1, 0, 1 },
1410                                 .ls_det_clr     = { 0x06a4, 1, 1, 0, 1 }
1411                         }
1412                 },
1413         },
1414         { /* sentinel */ }
1415 };
1416
1417 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
1418         {
1419                 .reg = 0x100,
1420                 .num_ports      = 2,
1421                 .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
1422                 .port_cfgs      = {
1423                         [USB2PHY_PORT_OTG] = {
1424                                 .phy_sus        = { 0x0100, 8, 0, 0, 0x1d1 },
1425                                 .bvalid_det_en  = { 0x3020, 3, 2, 0, 3 },
1426                                 .bvalid_det_st  = { 0x3024, 3, 2, 0, 3 },
1427                                 .bvalid_det_clr = { 0x3028, 3, 2, 0, 3 },
1428                                 .id_det_en      = { 0x3020, 5, 4, 0, 3 },
1429                                 .id_det_st      = { 0x3024, 5, 4, 0, 3 },
1430                                 .id_det_clr     = { 0x3028, 5, 4, 0, 3 },
1431                                 .ls_det_en      = { 0x3020, 0, 0, 0, 1 },
1432                                 .ls_det_st      = { 0x3024, 0, 0, 0, 1 },
1433                                 .ls_det_clr     = { 0x3028, 0, 0, 0, 1 },
1434                                 .utmi_avalid    = { 0x0120, 10, 10, 0, 1 },
1435                                 .utmi_bvalid    = { 0x0120, 9, 9, 0, 1 },
1436                                 .utmi_id        = { 0x0120, 6, 6, 0, 1 },
1437                                 .utmi_ls        = { 0x0120, 5, 4, 0, 1 },
1438                         },
1439                         [USB2PHY_PORT_HOST] = {
1440                                 .phy_sus        = { 0x0104, 8, 0, 0, 0x1d1 },
1441                                 .ls_det_en      = { 0x3020, 1, 1, 0, 1 },
1442                                 .ls_det_st      = { 0x3024, 1, 1, 0, 1 },
1443                                 .ls_det_clr     = { 0x3028, 1, 1, 0, 1 },
1444                                 .utmi_ls        = { 0x0120, 17, 16, 0, 1 },
1445                                 .utmi_hstdet    = { 0x0120, 19, 19, 0, 1 }
1446                         }
1447                 },
1448                 .chg_det = {
1449                         .opmode         = { 0x0100, 3, 0, 5, 1 },
1450                         .cp_det         = { 0x0120, 24, 24, 0, 1 },
1451                         .dcp_det        = { 0x0120, 23, 23, 0, 1 },
1452                         .dp_det         = { 0x0120, 25, 25, 0, 1 },
1453                         .idm_sink_en    = { 0x0108, 8, 8, 0, 1 },
1454                         .idp_sink_en    = { 0x0108, 7, 7, 0, 1 },
1455                         .idp_src_en     = { 0x0108, 9, 9, 0, 1 },
1456                         .rdm_pdwn_en    = { 0x0108, 10, 10, 0, 1 },
1457                         .vdm_src_en     = { 0x0108, 12, 12, 0, 1 },
1458                         .vdp_src_en     = { 0x0108, 11, 11, 0, 1 },
1459                 },
1460         },
1461         { /* sentinel */ }
1462 };
1463
1464 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1465         {
1466                 .reg = 0x100,
1467                 .num_ports      = 2,
1468                 .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
1469                 .port_cfgs      = {
1470                         [USB2PHY_PORT_OTG] = {
1471                                 .phy_sus        = { 0x0100, 15, 0, 0, 0x1d1 },
1472                                 .bvalid_det_en  = { 0x0110, 3, 2, 0, 3 },
1473                                 .bvalid_det_st  = { 0x0114, 3, 2, 0, 3 },
1474                                 .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
1475                                 .id_det_en      = { 0x0110, 5, 4, 0, 3 },
1476                                 .id_det_st      = { 0x0114, 5, 4, 0, 3 },
1477                                 .id_det_clr     = { 0x0118, 5, 4, 0, 3 },
1478                                 .ls_det_en      = { 0x0110, 0, 0, 0, 1 },
1479                                 .ls_det_st      = { 0x0114, 0, 0, 0, 1 },
1480                                 .ls_det_clr     = { 0x0118, 0, 0, 0, 1 },
1481                                 .utmi_avalid    = { 0x0120, 10, 10, 0, 1 },
1482                                 .utmi_bvalid    = { 0x0120, 9, 9, 0, 1 },
1483                                 .utmi_id        = { 0x0120, 6, 6, 0, 1 },
1484                                 .utmi_ls        = { 0x0120, 5, 4, 0, 1 },
1485                         },
1486                         [USB2PHY_PORT_HOST] = {
1487                                 .phy_sus        = { 0x104, 15, 0, 0, 0x1d1 },
1488                                 .ls_det_en      = { 0x110, 1, 1, 0, 1 },
1489                                 .ls_det_st      = { 0x114, 1, 1, 0, 1 },
1490                                 .ls_det_clr     = { 0x118, 1, 1, 0, 1 },
1491                                 .utmi_ls        = { 0x120, 17, 16, 0, 1 },
1492                                 .utmi_hstdet    = { 0x120, 19, 19, 0, 1 }
1493                         }
1494                 },
1495                 .chg_det = {
1496                         .opmode         = { 0x0100, 3, 0, 5, 1 },
1497                         .cp_det         = { 0x0120, 24, 24, 0, 1 },
1498                         .dcp_det        = { 0x0120, 23, 23, 0, 1 },
1499                         .dp_det         = { 0x0120, 25, 25, 0, 1 },
1500                         .idm_sink_en    = { 0x0108, 8, 8, 0, 1 },
1501                         .idp_sink_en    = { 0x0108, 7, 7, 0, 1 },
1502                         .idp_src_en     = { 0x0108, 9, 9, 0, 1 },
1503                         .rdm_pdwn_en    = { 0x0108, 10, 10, 0, 1 },
1504                         .vdm_src_en     = { 0x0108, 12, 12, 0, 1 },
1505                         .vdp_src_en     = { 0x0108, 11, 11, 0, 1 },
1506                 },
1507         },
1508         { /* sentinel */ }
1509 };
1510
1511 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1512         {
1513                 .reg = 0x700,
1514                 .num_ports      = 2,
1515                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1516                 .port_cfgs      = {
1517                         [USB2PHY_PORT_HOST] = {
1518                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1519                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1520                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1521                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1522                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1523                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1524                         }
1525                 },
1526         },
1527         { /* sentinel */ }
1528 };
1529
1530 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1531         {
1532                 .reg            = 0xe450,
1533                 .num_ports      = 2,
1534                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1535                 .port_cfgs      = {
1536                         [USB2PHY_PORT_OTG] = {
1537                                 .phy_sus        = { 0xe454, 1, 0, 2, 1 },
1538                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1539                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1540                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1541                                 .id_det_en      = { 0xe3c0, 5, 4, 0, 3 },
1542                                 .id_det_st      = { 0xe3e0, 5, 4, 0, 3 },
1543                                 .id_det_clr     = { 0xe3d0, 5, 4, 0, 3 },
1544                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1545                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1546                                 .utmi_id        = { 0xe2ac, 8, 8, 0, 1 },
1547                         },
1548                         [USB2PHY_PORT_HOST] = {
1549                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1550                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1551                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1552                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1553                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1554                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1555                         }
1556                 },
1557                 .chg_det = {
1558                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1559                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1560                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1561                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1562                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1563                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1564                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1565                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1566                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1567                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1568                 },
1569         },
1570         {
1571                 .reg            = 0xe460,
1572                 .num_ports      = 2,
1573                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1574                 .port_cfgs      = {
1575                         [USB2PHY_PORT_OTG] = {
1576                                 .phy_sus        = { 0xe464, 1, 0, 2, 1 },
1577                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1578                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1579                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1580                                 .id_det_en      = { 0xe3c0, 10, 9, 0, 3 },
1581                                 .id_det_st      = { 0xe3e0, 10, 9, 0, 3 },
1582                                 .id_det_clr     = { 0xe3d0, 10, 9, 0, 3 },
1583                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1584                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1585                                 .utmi_id        = { 0xe2ac, 11, 11, 0, 1 },
1586                         },
1587                         [USB2PHY_PORT_HOST] = {
1588                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1589                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1590                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1591                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1592                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1593                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1594                         }
1595                 },
1596         },
1597         { /* sentinel */ }
1598 };
1599
1600 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
1601         {
1602                 .reg = 0xfe8a0000,
1603                 .num_ports      = 2,
1604                 .clkout_ctl     = { 0x0008, 4, 4, 1, 0 },
1605                 .port_cfgs      = {
1606                         [USB2PHY_PORT_OTG] = {
1607                                 .phy_sus        = { 0x0000, 8, 0, 0, 0x1d1 },
1608                                 .bvalid_det_en  = { 0x0080, 3, 2, 0, 3 },
1609                                 .bvalid_det_st  = { 0x0084, 3, 2, 0, 3 },
1610                                 .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 },
1611                                 .id_det_en      = { 0x0080, 5, 4, 0, 3 },
1612                                 .id_det_st      = { 0x0084, 5, 4, 0, 3 },
1613                                 .id_det_clr     = { 0x0088, 5, 4, 0, 3 },
1614                                 .utmi_avalid    = { 0x00c0, 10, 10, 0, 1 },
1615                                 .utmi_bvalid    = { 0x00c0, 9, 9, 0, 1 },
1616                                 .utmi_id        = { 0x00c0, 6, 6, 0, 1 },
1617                         },
1618                         [USB2PHY_PORT_HOST] = {
1619                                 /* Select suspend control from controller */
1620                                 .phy_sus        = { 0x0004, 8, 0, 0x1d2, 0x1d2 },
1621                                 .ls_det_en      = { 0x0080, 1, 1, 0, 1 },
1622                                 .ls_det_st      = { 0x0084, 1, 1, 0, 1 },
1623                                 .ls_det_clr     = { 0x0088, 1, 1, 0, 1 },
1624                                 .utmi_ls        = { 0x00c0, 17, 16, 0, 1 },
1625                                 .utmi_hstdet    = { 0x00c0, 19, 19, 0, 1 }
1626                         }
1627                 },
1628                 .chg_det = {
1629                         .opmode         = { 0x0000, 3, 0, 5, 1 },
1630                         .cp_det         = { 0x00c0, 24, 24, 0, 1 },
1631                         .dcp_det        = { 0x00c0, 23, 23, 0, 1 },
1632                         .dp_det         = { 0x00c0, 25, 25, 0, 1 },
1633                         .idm_sink_en    = { 0x0008, 8, 8, 0, 1 },
1634                         .idp_sink_en    = { 0x0008, 7, 7, 0, 1 },
1635                         .idp_src_en     = { 0x0008, 9, 9, 0, 1 },
1636                         .rdm_pdwn_en    = { 0x0008, 10, 10, 0, 1 },
1637                         .vdm_src_en     = { 0x0008, 12, 12, 0, 1 },
1638                         .vdp_src_en     = { 0x0008, 11, 11, 0, 1 },
1639                 },
1640         },
1641         {
1642                 .reg = 0xfe8b0000,
1643                 .num_ports      = 2,
1644                 .clkout_ctl     = { 0x0008, 4, 4, 1, 0 },
1645                 .port_cfgs      = {
1646                         [USB2PHY_PORT_OTG] = {
1647                                 .phy_sus        = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
1648                                 .ls_det_en      = { 0x0080, 0, 0, 0, 1 },
1649                                 .ls_det_st      = { 0x0084, 0, 0, 0, 1 },
1650                                 .ls_det_clr     = { 0x0088, 0, 0, 0, 1 },
1651                                 .utmi_ls        = { 0x00c0, 5, 4, 0, 1 },
1652                                 .utmi_hstdet    = { 0x00c0, 7, 7, 0, 1 }
1653                         },
1654                         [USB2PHY_PORT_HOST] = {
1655                                 .phy_sus        = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1656                                 .ls_det_en      = { 0x0080, 1, 1, 0, 1 },
1657                                 .ls_det_st      = { 0x0084, 1, 1, 0, 1 },
1658                                 .ls_det_clr     = { 0x0088, 1, 1, 0, 1 },
1659                                 .utmi_ls        = { 0x00c0, 17, 16, 0, 1 },
1660                                 .utmi_hstdet    = { 0x00c0, 19, 19, 0, 1 }
1661                         }
1662                 },
1663         },
1664         { /* sentinel */ }
1665 };
1666
1667 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1668         {
1669                 .reg = 0x100,
1670                 .num_ports      = 2,
1671                 .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
1672                 .port_cfgs      = {
1673                         [USB2PHY_PORT_OTG] = {
1674                                 .phy_sus        = { 0x0100, 15, 0, 0, 0x1d1 },
1675                                 .bvalid_det_en  = { 0x0680, 3, 3, 0, 1 },
1676                                 .bvalid_det_st  = { 0x0690, 3, 3, 0, 1 },
1677                                 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1678                                 .ls_det_en      = { 0x0680, 2, 2, 0, 1 },
1679                                 .ls_det_st      = { 0x0690, 2, 2, 0, 1 },
1680                                 .ls_det_clr     = { 0x06a0, 2, 2, 0, 1 },
1681                                 .utmi_bvalid    = { 0x0804, 10, 10, 0, 1 },
1682                                 .utmi_ls        = { 0x0804, 13, 12, 0, 1 },
1683                         },
1684                         [USB2PHY_PORT_HOST] = {
1685                                 .phy_sus        = { 0x0104, 15, 0, 0, 0x1d1 },
1686                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1687                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1688                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1689                                 .utmi_ls        = { 0x0804, 9, 8, 0, 1 },
1690                                 .utmi_hstdet    = { 0x0804, 7, 7, 0, 1 }
1691                         }
1692                 },
1693                 .chg_det = {
1694                         .opmode         = { 0x0100, 3, 0, 5, 1 },
1695                         .cp_det         = { 0x0804, 1, 1, 0, 1 },
1696                         .dcp_det        = { 0x0804, 0, 0, 0, 1 },
1697                         .dp_det         = { 0x0804, 2, 2, 0, 1 },
1698                         .idm_sink_en    = { 0x0108, 8, 8, 0, 1 },
1699                         .idp_sink_en    = { 0x0108, 7, 7, 0, 1 },
1700                         .idp_src_en     = { 0x0108, 9, 9, 0, 1 },
1701                         .rdm_pdwn_en    = { 0x0108, 10, 10, 0, 1 },
1702                         .vdm_src_en     = { 0x0108, 12, 12, 0, 1 },
1703                         .vdp_src_en     = { 0x0108, 11, 11, 0, 1 },
1704                 },
1705         },
1706         { /* sentinel */ }
1707 };
1708
1709 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1710         { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
1711         { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1712         { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
1713         { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1714         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1715         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1716         { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
1717         { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
1718         {}
1719 };
1720 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1721
1722 static struct platform_driver rockchip_usb2phy_driver = {
1723         .probe          = rockchip_usb2phy_probe,
1724         .driver         = {
1725                 .name   = "rockchip-usb2phy",
1726                 .of_match_table = rockchip_usb2phy_dt_match,
1727         },
1728 };
1729 module_platform_driver(rockchip_usb2phy_driver);
1730
1731 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1732 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1733 MODULE_LICENSE("GPL v2");