2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/extcon.h>
21 #include <linux/interrupt.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/jiffies.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/power_supply.h>
35 #include <linux/regmap.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/usb/of.h>
38 #include <linux/usb/otg.h>
40 #define BIT_WRITEABLE_SHIFT 16
41 #define SCHEDULE_DELAY (60 * HZ)
42 #define OTG_SCHEDULE_DELAY (2 * HZ)
44 enum rockchip_usb2phy_port_id {
50 enum rockchip_usb2phy_host_state {
51 PHY_STATE_HS_ONLINE = 0,
52 PHY_STATE_DISCONNECT = 1,
53 PHY_STATE_CONNECT = 2,
54 PHY_STATE_FS_LS_ONLINE = 4,
58 * Different states involved in USB charger detection.
59 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
60 * process is not yet started.
61 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
62 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
63 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
64 * between SDP and DCP/CDP).
65 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
66 * between DCP and CDP).
67 * USB_CHG_STATE_DETECTED USB charger type is determined.
70 USB_CHG_STATE_UNDEFINED = 0,
71 USB_CHG_STATE_WAIT_FOR_DCD,
72 USB_CHG_STATE_DCD_DONE,
73 USB_CHG_STATE_PRIMARY_DONE,
74 USB_CHG_STATE_SECONDARY_DONE,
75 USB_CHG_STATE_DETECTED,
78 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
91 unsigned int bitstart;
97 * struct rockchip_chg_det_reg: usb charger detect registers
98 * @cp_det: charging port detected successfully.
99 * @dcp_det: dedicated charging port detected successfully.
100 * @dp_det: assert data pin connect successfully.
101 * @idm_sink_en: open dm sink curren.
102 * @idp_sink_en: open dp sink current.
103 * @idp_src_en: open dm source current.
104 * @rdm_pdwn_en: open dm pull down resistor.
105 * @vdm_src_en: open dm voltage source.
106 * @vdp_src_en: open dp voltage source.
107 * @opmode: utmi operational mode.
109 struct rockchip_chg_det_reg {
110 struct usb2phy_reg cp_det;
111 struct usb2phy_reg dcp_det;
112 struct usb2phy_reg dp_det;
113 struct usb2phy_reg idm_sink_en;
114 struct usb2phy_reg idp_sink_en;
115 struct usb2phy_reg idp_src_en;
116 struct usb2phy_reg rdm_pdwn_en;
117 struct usb2phy_reg vdm_src_en;
118 struct usb2phy_reg vdp_src_en;
119 struct usb2phy_reg opmode;
123 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
124 * @phy_sus: phy suspend register.
125 * @bvalid_det_en: vbus valid rise detection enable register.
126 * @bvalid_det_st: vbus valid rise detection status register.
127 * @bvalid_det_clr: vbus valid rise detection clear register.
128 * @ls_det_en: linestate detection enable register.
129 * @ls_det_st: linestate detection state register.
130 * @ls_det_clr: linestate detection clear register.
131 * @utmi_avalid: utmi vbus avalid status register.
132 * @utmi_bvalid: utmi vbus bvalid status register.
133 * @utmi_ls: utmi linestate state register.
134 * @utmi_hstdet: utmi host disconnect register.
136 struct rockchip_usb2phy_port_cfg {
137 struct usb2phy_reg phy_sus;
138 struct usb2phy_reg bvalid_det_en;
139 struct usb2phy_reg bvalid_det_st;
140 struct usb2phy_reg bvalid_det_clr;
141 struct usb2phy_reg ls_det_en;
142 struct usb2phy_reg ls_det_st;
143 struct usb2phy_reg ls_det_clr;
144 struct usb2phy_reg utmi_avalid;
145 struct usb2phy_reg utmi_bvalid;
146 struct usb2phy_reg utmi_ls;
147 struct usb2phy_reg utmi_hstdet;
151 * struct rockchip_usb2phy_cfg: usb-phy configuration.
152 * @reg: the address offset of grf for usb-phy config.
153 * @num_ports: specify how many ports that the phy has.
154 * @clkout_ctl: keep on/turn off output clk of phy.
155 * @chg_det: charger detection registers.
157 struct rockchip_usb2phy_cfg {
159 unsigned int num_ports;
160 struct usb2phy_reg clkout_ctl;
161 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
162 const struct rockchip_chg_det_reg chg_det;
166 * struct rockchip_usb2phy_port: usb-phy port data.
167 * @port_id: flag for otg port or host port.
168 * @suspended: phy suspended flag.
169 * @utmi_avalid: utmi avalid status usage flag.
170 * true - use avalid to get vbus status
171 * flase - use bvalid to get vbus status
172 * @vbus_attached: otg device vbus status.
173 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
174 * @ls_irq: IRQ number assigned for linestate detection.
175 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
176 * irqs to one irq in otg-port.
177 * @mutex: for register updating in sm_work.
178 * @chg_work: charge detect work.
179 * @otg_sm_work: OTG state machine work.
180 * @sm_work: HOST state machine work.
181 * @phy_cfg: port register configuration, assigned by driver data.
182 * @event_nb: hold event notification callback.
183 * @state: define OTG enumeration states before device reset.
184 * @mode: the dr_mode of the controller.
186 struct rockchip_usb2phy_port {
188 unsigned int port_id;
196 struct delayed_work chg_work;
197 struct delayed_work otg_sm_work;
198 struct delayed_work sm_work;
199 const struct rockchip_usb2phy_port_cfg *port_cfg;
200 struct notifier_block event_nb;
201 enum usb_otg_state state;
202 enum usb_dr_mode mode;
206 * struct rockchip_usb2phy: usb2.0 phy driver data.
207 * @grf: General Register Files regmap.
208 * @usbgrf: USB General Register Files regmap.
209 * @clk: clock struct of phy input clk.
210 * @clk480m: clock struct of phy output clk.
211 * @clk_hw: clock struct of phy output clk management.
212 * @chg_state: states involved in USB charger detection.
213 * @chg_type: USB charger types.
214 * @dcd_retries: The retry count used to track Data contact
216 * @edev: extcon device for notification registration
217 * @phy_cfg: phy register configuration, assigned by driver data.
218 * @ports: phy port instance.
220 struct rockchip_usb2phy {
223 struct regmap *usbgrf;
226 struct clk_hw clk480m_hw;
227 enum usb_chg_state chg_state;
228 enum power_supply_type chg_type;
230 struct extcon_dev *edev;
231 const struct rockchip_usb2phy_cfg *phy_cfg;
232 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
235 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
237 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
240 static inline int property_enable(struct regmap *base,
241 const struct usb2phy_reg *reg, bool en)
243 unsigned int val, mask, tmp;
245 tmp = en ? reg->enable : reg->disable;
246 mask = GENMASK(reg->bitend, reg->bitstart);
247 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
249 return regmap_write(base, reg->offset, val);
252 static inline bool property_enabled(struct regmap *base,
253 const struct usb2phy_reg *reg)
256 unsigned int tmp, orig;
257 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
259 ret = regmap_read(base, reg->offset, &orig);
263 tmp = (orig & mask) >> reg->bitstart;
264 return tmp == reg->enable;
267 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
269 struct rockchip_usb2phy *rphy =
270 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
271 struct regmap *base = get_reg_base(rphy);
274 /* turn on 480m clk output if it is off */
275 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
276 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
280 /* waiting for the clk become stable */
281 usleep_range(1200, 1300);
287 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
289 struct rockchip_usb2phy *rphy =
290 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
291 struct regmap *base = get_reg_base(rphy);
293 /* turn off 480m clk output */
294 property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
297 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
299 struct rockchip_usb2phy *rphy =
300 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
301 struct regmap *base = get_reg_base(rphy);
303 return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
307 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
308 unsigned long parent_rate)
313 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
314 .prepare = rockchip_usb2phy_clk480m_prepare,
315 .unprepare = rockchip_usb2phy_clk480m_unprepare,
316 .is_prepared = rockchip_usb2phy_clk480m_prepared,
317 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
320 static void rockchip_usb2phy_clk480m_unregister(void *data)
322 struct rockchip_usb2phy *rphy = data;
324 of_clk_del_provider(rphy->dev->of_node);
325 clk_unregister(rphy->clk480m);
329 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
331 struct device_node *node = rphy->dev->of_node;
332 struct clk_init_data init;
333 const char *clk_name;
337 init.name = "clk_usbphy_480m";
338 init.ops = &rockchip_usb2phy_clkout_ops;
340 /* optional override of the clockname */
341 of_property_read_string(node, "clock-output-names", &init.name);
344 clk_name = __clk_get_name(rphy->clk);
345 init.parent_names = &clk_name;
346 init.num_parents = 1;
348 init.parent_names = NULL;
349 init.num_parents = 0;
352 rphy->clk480m_hw.init = &init;
354 /* register the clock */
355 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
356 if (IS_ERR(rphy->clk480m)) {
357 ret = PTR_ERR(rphy->clk480m);
361 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
363 goto err_clk_provider;
365 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
368 goto err_unreg_action;
373 of_clk_del_provider(node);
375 clk_unregister(rphy->clk480m);
380 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
383 struct device_node *node = rphy->dev->of_node;
384 struct extcon_dev *edev;
386 if (of_property_read_bool(node, "extcon")) {
387 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
389 if (PTR_ERR(edev) != -EPROBE_DEFER)
390 dev_err(rphy->dev, "Invalid or missing extcon\n");
391 return PTR_ERR(edev);
394 /* Initialize extcon device */
395 edev = devm_extcon_dev_allocate(rphy->dev,
396 rockchip_usb2phy_extcon_cable);
401 ret = devm_extcon_dev_register(rphy->dev, edev);
403 dev_err(rphy->dev, "failed to register extcon device\n");
413 static int rockchip_usb2phy_init(struct phy *phy)
415 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
416 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
419 mutex_lock(&rport->mutex);
421 if (rport->port_id == USB2PHY_PORT_OTG) {
422 if (rport->mode != USB_DR_MODE_HOST &&
423 rport->mode != USB_DR_MODE_UNKNOWN) {
424 /* clear bvalid status and enable bvalid detect irq */
425 ret = property_enable(rphy->grf,
426 &rport->port_cfg->bvalid_det_clr,
431 ret = property_enable(rphy->grf,
432 &rport->port_cfg->bvalid_det_en,
437 schedule_delayed_work(&rport->otg_sm_work,
438 OTG_SCHEDULE_DELAY * 3);
440 /* If OTG works in host only mode, do nothing. */
441 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
443 } else if (rport->port_id == USB2PHY_PORT_HOST) {
444 /* clear linestate and enable linestate detect irq */
445 ret = property_enable(rphy->grf,
446 &rport->port_cfg->ls_det_clr, true);
450 ret = property_enable(rphy->grf,
451 &rport->port_cfg->ls_det_en, true);
455 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
459 mutex_unlock(&rport->mutex);
463 static int rockchip_usb2phy_power_on(struct phy *phy)
465 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
466 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
467 struct regmap *base = get_reg_base(rphy);
470 dev_dbg(&rport->phy->dev, "port power on\n");
472 if (!rport->suspended)
475 ret = clk_prepare_enable(rphy->clk480m);
479 ret = property_enable(base, &rport->port_cfg->phy_sus, false);
481 clk_disable_unprepare(rphy->clk480m);
485 /* waiting for the utmi_clk to become stable */
486 usleep_range(1500, 2000);
488 rport->suspended = false;
492 static int rockchip_usb2phy_power_off(struct phy *phy)
494 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
495 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
496 struct regmap *base = get_reg_base(rphy);
499 dev_dbg(&rport->phy->dev, "port power off\n");
501 if (rport->suspended)
504 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
508 rport->suspended = true;
509 clk_disable_unprepare(rphy->clk480m);
514 static int rockchip_usb2phy_exit(struct phy *phy)
516 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
518 if (rport->port_id == USB2PHY_PORT_OTG &&
519 rport->mode != USB_DR_MODE_HOST &&
520 rport->mode != USB_DR_MODE_UNKNOWN) {
521 cancel_delayed_work_sync(&rport->otg_sm_work);
522 cancel_delayed_work_sync(&rport->chg_work);
523 } else if (rport->port_id == USB2PHY_PORT_HOST)
524 cancel_delayed_work_sync(&rport->sm_work);
529 static const struct phy_ops rockchip_usb2phy_ops = {
530 .init = rockchip_usb2phy_init,
531 .exit = rockchip_usb2phy_exit,
532 .power_on = rockchip_usb2phy_power_on,
533 .power_off = rockchip_usb2phy_power_off,
534 .owner = THIS_MODULE,
537 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
539 struct rockchip_usb2phy_port *rport =
540 container_of(work, struct rockchip_usb2phy_port,
542 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
543 static unsigned int cable;
545 bool vbus_attach, sch_work, notify_charger;
547 if (rport->utmi_avalid)
548 vbus_attach = property_enabled(rphy->grf,
549 &rport->port_cfg->utmi_avalid);
551 vbus_attach = property_enabled(rphy->grf,
552 &rport->port_cfg->utmi_bvalid);
555 notify_charger = false;
556 delay = OTG_SCHEDULE_DELAY;
557 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
558 usb_otg_state_string(rport->state));
560 switch (rport->state) {
561 case OTG_STATE_UNDEFINED:
562 rport->state = OTG_STATE_B_IDLE;
564 rockchip_usb2phy_power_off(rport->phy);
566 case OTG_STATE_B_IDLE:
567 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
568 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
569 rport->state = OTG_STATE_A_HOST;
570 rockchip_usb2phy_power_on(rport->phy);
572 } else if (vbus_attach) {
573 dev_dbg(&rport->phy->dev, "vbus_attach\n");
574 switch (rphy->chg_state) {
575 case USB_CHG_STATE_UNDEFINED:
576 schedule_delayed_work(&rport->chg_work, 0);
578 case USB_CHG_STATE_DETECTED:
579 switch (rphy->chg_type) {
580 case POWER_SUPPLY_TYPE_USB:
581 dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
582 rockchip_usb2phy_power_on(rport->phy);
583 rport->state = OTG_STATE_B_PERIPHERAL;
584 notify_charger = true;
586 cable = EXTCON_CHG_USB_SDP;
588 case POWER_SUPPLY_TYPE_USB_DCP:
589 dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
590 rockchip_usb2phy_power_off(rport->phy);
591 notify_charger = true;
593 cable = EXTCON_CHG_USB_DCP;
595 case POWER_SUPPLY_TYPE_USB_CDP:
596 dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
597 rockchip_usb2phy_power_on(rport->phy);
598 rport->state = OTG_STATE_B_PERIPHERAL;
599 notify_charger = true;
601 cable = EXTCON_CHG_USB_CDP;
611 notify_charger = true;
612 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
613 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
616 if (rport->vbus_attached != vbus_attach) {
617 rport->vbus_attached = vbus_attach;
619 if (notify_charger && rphy->edev) {
620 extcon_set_state_sync(rphy->edev,
622 if (cable == EXTCON_CHG_USB_SDP)
623 extcon_set_state_sync(rphy->edev,
629 case OTG_STATE_B_PERIPHERAL:
631 dev_dbg(&rport->phy->dev, "usb disconnect\n");
632 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
633 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
634 rport->state = OTG_STATE_B_IDLE;
636 rockchip_usb2phy_power_off(rport->phy);
640 case OTG_STATE_A_HOST:
641 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
642 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
643 rport->state = OTG_STATE_B_IDLE;
644 rockchip_usb2phy_power_off(rport->phy);
652 schedule_delayed_work(&rport->otg_sm_work, delay);
655 static const char *chg_to_string(enum power_supply_type chg_type)
658 case POWER_SUPPLY_TYPE_USB:
659 return "USB_SDP_CHARGER";
660 case POWER_SUPPLY_TYPE_USB_DCP:
661 return "USB_DCP_CHARGER";
662 case POWER_SUPPLY_TYPE_USB_CDP:
663 return "USB_CDP_CHARGER";
665 return "INVALID_CHARGER";
669 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
672 struct regmap *base = get_reg_base(rphy);
674 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
675 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
678 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
681 struct regmap *base = get_reg_base(rphy);
683 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
684 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
687 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
690 struct regmap *base = get_reg_base(rphy);
692 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
693 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
696 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
697 #define CHG_DCD_MAX_RETRIES 6
698 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
699 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
700 static void rockchip_chg_detect_work(struct work_struct *work)
702 struct rockchip_usb2phy_port *rport =
703 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
704 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
705 struct regmap *base = get_reg_base(rphy);
706 bool is_dcd, tmout, vout;
709 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
711 switch (rphy->chg_state) {
712 case USB_CHG_STATE_UNDEFINED:
713 if (!rport->suspended)
714 rockchip_usb2phy_power_off(rport->phy);
715 /* put the controller in non-driving mode */
716 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
717 /* Start DCD processing stage 1 */
718 rockchip_chg_enable_dcd(rphy, true);
719 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
720 rphy->dcd_retries = 0;
721 delay = CHG_DCD_POLL_TIME;
723 case USB_CHG_STATE_WAIT_FOR_DCD:
724 /* get data contact detection status */
725 is_dcd = property_enabled(rphy->grf,
726 &rphy->phy_cfg->chg_det.dp_det);
727 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
729 if (is_dcd || tmout) {
731 /* Turn off DCD circuitry */
732 rockchip_chg_enable_dcd(rphy, false);
733 /* Voltage Source on DP, Probe on DM */
734 rockchip_chg_enable_primary_det(rphy, true);
735 delay = CHG_PRIMARY_DET_TIME;
736 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
739 delay = CHG_DCD_POLL_TIME;
742 case USB_CHG_STATE_DCD_DONE:
743 vout = property_enabled(rphy->grf,
744 &rphy->phy_cfg->chg_det.cp_det);
745 rockchip_chg_enable_primary_det(rphy, false);
747 /* Voltage Source on DM, Probe on DP */
748 rockchip_chg_enable_secondary_det(rphy, true);
749 delay = CHG_SECONDARY_DET_TIME;
750 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
752 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
753 /* floating charger found */
754 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
755 rphy->chg_state = USB_CHG_STATE_DETECTED;
758 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
759 rphy->chg_state = USB_CHG_STATE_DETECTED;
764 case USB_CHG_STATE_PRIMARY_DONE:
765 vout = property_enabled(rphy->grf,
766 &rphy->phy_cfg->chg_det.dcp_det);
767 /* Turn off voltage source */
768 rockchip_chg_enable_secondary_det(rphy, false);
770 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
772 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
774 case USB_CHG_STATE_SECONDARY_DONE:
775 rphy->chg_state = USB_CHG_STATE_DETECTED;
778 case USB_CHG_STATE_DETECTED:
779 /* put the controller in normal mode */
780 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
781 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
782 dev_info(&rport->phy->dev, "charger = %s\n",
783 chg_to_string(rphy->chg_type));
789 schedule_delayed_work(&rport->chg_work, delay);
793 * The function manage host-phy port state and suspend/resume phy port
796 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
797 * devices is disconnect or not. Besides, we do not need care it is FS/LS
798 * disconnected or HS disconnected, actually, we just only need get the
799 * device is disconnected at last through rearm the delayed work,
800 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
802 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
803 * some clk related APIs, so do not invoke it from interrupt context directly.
805 static void rockchip_usb2phy_sm_work(struct work_struct *work)
807 struct rockchip_usb2phy_port *rport =
808 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
809 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
810 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
811 rport->port_cfg->utmi_hstdet.bitstart + 1;
812 unsigned int ul, uhd, state;
813 unsigned int ul_mask, uhd_mask;
816 mutex_lock(&rport->mutex);
818 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
822 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
826 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
827 rport->port_cfg->utmi_hstdet.bitstart);
828 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
829 rport->port_cfg->utmi_ls.bitstart);
831 /* stitch on utmi_ls and utmi_hstdet as phy state */
832 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
833 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
836 case PHY_STATE_HS_ONLINE:
837 dev_dbg(&rport->phy->dev, "HS online\n");
839 case PHY_STATE_FS_LS_ONLINE:
841 * For FS/LS device, the online state share with connect state
842 * from utmi_ls and utmi_hstdet register, so we distinguish
843 * them via suspended flag.
845 * Plus, there are two cases, one is D- Line pull-up, and D+
846 * line pull-down, the state is 4; another is D+ line pull-up,
847 * and D- line pull-down, the state is 2.
849 if (!rport->suspended) {
850 /* D- line pull-up, D+ line pull-down */
851 dev_dbg(&rport->phy->dev, "FS/LS online\n");
855 case PHY_STATE_CONNECT:
856 if (rport->suspended) {
857 dev_dbg(&rport->phy->dev, "Connected\n");
858 rockchip_usb2phy_power_on(rport->phy);
859 rport->suspended = false;
861 /* D+ line pull-up, D- line pull-down */
862 dev_dbg(&rport->phy->dev, "FS/LS online\n");
865 case PHY_STATE_DISCONNECT:
866 if (!rport->suspended) {
867 dev_dbg(&rport->phy->dev, "Disconnected\n");
868 rockchip_usb2phy_power_off(rport->phy);
869 rport->suspended = true;
873 * activate the linestate detection to get the next device
876 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
877 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
880 * we don't need to rearm the delayed work when the phy port
883 mutex_unlock(&rport->mutex);
886 dev_dbg(&rport->phy->dev, "unknown phy state\n");
891 mutex_unlock(&rport->mutex);
892 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
895 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
897 struct rockchip_usb2phy_port *rport = data;
898 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
900 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
903 mutex_lock(&rport->mutex);
905 /* disable linestate detect irq and clear its status */
906 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
907 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
909 mutex_unlock(&rport->mutex);
912 * In this case for host phy port, a new device is plugged in,
913 * meanwhile, if the phy port is suspended, we need rearm the work to
914 * resume it and mange its states; otherwise, we do nothing about that.
916 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
917 rockchip_usb2phy_sm_work(&rport->sm_work.work);
922 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
924 struct rockchip_usb2phy_port *rport = data;
925 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
927 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
930 mutex_lock(&rport->mutex);
932 /* clear bvalid detect irq pending status */
933 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
935 mutex_unlock(&rport->mutex);
937 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
942 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
944 struct rockchip_usb2phy_port *rport = data;
945 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
947 if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
948 return rockchip_usb2phy_bvalid_irq(irq, data);
953 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
954 struct rockchip_usb2phy_port *rport,
955 struct device_node *child_np)
959 rport->port_id = USB2PHY_PORT_HOST;
960 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
961 rport->suspended = true;
963 mutex_init(&rport->mutex);
964 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
966 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
967 if (rport->ls_irq < 0) {
968 dev_err(rphy->dev, "no linestate irq provided\n");
969 return rport->ls_irq;
972 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
973 rockchip_usb2phy_linestate_irq,
975 "rockchip_usb2phy", rport);
977 dev_err(rphy->dev, "failed to request linestate irq handle\n");
984 static int rockchip_otg_event(struct notifier_block *nb,
985 unsigned long event, void *ptr)
987 struct rockchip_usb2phy_port *rport =
988 container_of(nb, struct rockchip_usb2phy_port, event_nb);
990 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
995 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
996 struct rockchip_usb2phy_port *rport,
997 struct device_node *child_np)
1001 rport->port_id = USB2PHY_PORT_OTG;
1002 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1003 rport->state = OTG_STATE_UNDEFINED;
1006 * set suspended flag to true, but actually don't
1007 * put phy in suspend mode, it aims to enable usb
1008 * phy and clock in power_on() called by usb controller
1009 * driver during probe.
1011 rport->suspended = true;
1012 rport->vbus_attached = false;
1014 mutex_init(&rport->mutex);
1016 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1017 if (rport->mode == USB_DR_MODE_HOST ||
1018 rport->mode == USB_DR_MODE_UNKNOWN) {
1023 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1024 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1026 rport->utmi_avalid =
1027 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1030 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
1031 * interrupts muxed together, so probe the otg-mux interrupt first,
1032 * if not found, then look for the regular interrupts one by one.
1034 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1035 if (rport->otg_mux_irq > 0) {
1036 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
1038 rockchip_usb2phy_otg_mux_irq,
1040 "rockchip_usb2phy_otg",
1044 "failed to request otg-mux irq handle\n");
1048 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1049 if (rport->bvalid_irq < 0) {
1050 dev_err(rphy->dev, "no vbus valid irq provided\n");
1051 ret = rport->bvalid_irq;
1055 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1057 rockchip_usb2phy_bvalid_irq,
1059 "rockchip_usb2phy_bvalid",
1063 "failed to request otg-bvalid irq handle\n");
1068 if (!IS_ERR(rphy->edev)) {
1069 rport->event_nb.notifier_call = rockchip_otg_event;
1071 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1072 EXTCON_USB_HOST, &rport->event_nb);
1074 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1081 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1083 struct device *dev = &pdev->dev;
1084 struct device_node *np = dev->of_node;
1085 struct device_node *child_np;
1086 struct phy_provider *provider;
1087 struct rockchip_usb2phy *rphy;
1088 const struct rockchip_usb2phy_cfg *phy_cfgs;
1089 const struct of_device_id *match;
1093 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1097 match = of_match_device(dev->driver->of_match_table, dev);
1098 if (!match || !match->data) {
1099 dev_err(dev, "phy configs are not assigned!\n");
1103 if (!dev->parent || !dev->parent->of_node)
1106 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1107 if (IS_ERR(rphy->grf))
1108 return PTR_ERR(rphy->grf);
1110 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1112 syscon_regmap_lookup_by_phandle(dev->of_node,
1114 if (IS_ERR(rphy->usbgrf))
1115 return PTR_ERR(rphy->usbgrf);
1117 rphy->usbgrf = NULL;
1120 if (of_property_read_u32(np, "reg", ®)) {
1121 dev_err(dev, "the reg property is not assigned in %s node\n",
1127 phy_cfgs = match->data;
1128 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1129 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1130 platform_set_drvdata(pdev, rphy);
1132 ret = rockchip_usb2phy_extcon_register(rphy);
1136 /* find out a proper config which can be matched with dt. */
1138 while (phy_cfgs[index].reg) {
1139 if (phy_cfgs[index].reg == reg) {
1140 rphy->phy_cfg = &phy_cfgs[index];
1147 if (!rphy->phy_cfg) {
1148 dev_err(dev, "no phy-config can be matched with %s node\n",
1153 rphy->clk = of_clk_get_by_name(np, "phyclk");
1154 if (!IS_ERR(rphy->clk)) {
1155 clk_prepare_enable(rphy->clk);
1157 dev_info(&pdev->dev, "no phyclk specified\n");
1161 ret = rockchip_usb2phy_clk480m_register(rphy);
1163 dev_err(dev, "failed to register 480m output clock\n");
1168 for_each_available_child_of_node(np, child_np) {
1169 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1172 /* This driver aims to support both otg-port and host-port */
1173 if (of_node_cmp(child_np->name, "host-port") &&
1174 of_node_cmp(child_np->name, "otg-port"))
1177 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1179 dev_err(dev, "failed to create phy\n");
1185 phy_set_drvdata(rport->phy, rport);
1187 /* initialize otg/host port separately */
1188 if (!of_node_cmp(child_np->name, "host-port")) {
1189 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1194 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1201 /* to prevent out of boundary */
1202 if (++index >= rphy->phy_cfg->num_ports)
1206 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1207 return PTR_ERR_OR_ZERO(provider);
1210 of_node_put(child_np);
1213 clk_disable_unprepare(rphy->clk);
1219 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1223 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1225 [USB2PHY_PORT_OTG] = {
1226 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 },
1227 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1228 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1229 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1230 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1231 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1232 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1233 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1234 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1236 [USB2PHY_PORT_HOST] = {
1237 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 },
1238 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1239 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1240 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1244 .opmode = { 0x0760, 3, 0, 5, 1 },
1245 .cp_det = { 0x0884, 4, 4, 0, 1 },
1246 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1247 .dp_det = { 0x0884, 5, 5, 0, 1 },
1248 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1249 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1250 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1251 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1252 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1253 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1259 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1261 [USB2PHY_PORT_OTG] = {
1262 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 },
1263 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1264 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1265 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1267 [USB2PHY_PORT_HOST] = {
1268 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 },
1269 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1270 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1271 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1278 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1282 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1284 [USB2PHY_PORT_OTG] = {
1285 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1286 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1287 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1288 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1289 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1290 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1291 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1292 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1293 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1294 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1296 [USB2PHY_PORT_HOST] = {
1297 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
1298 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1299 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1300 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1301 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1302 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1306 .opmode = { 0x0100, 3, 0, 5, 1 },
1307 .cp_det = { 0x0120, 24, 24, 0, 1 },
1308 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1309 .dp_det = { 0x0120, 25, 25, 0, 1 },
1310 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1311 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1312 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1313 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1314 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1315 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1321 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1325 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1327 [USB2PHY_PORT_HOST] = {
1328 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1329 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1330 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1331 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1332 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1333 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1340 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1344 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1346 [USB2PHY_PORT_OTG] = {
1347 .phy_sus = { 0xe454, 1, 0, 2, 1 },
1348 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1349 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1350 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1351 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1352 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1354 [USB2PHY_PORT_HOST] = {
1355 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1356 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1357 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1358 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1359 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1360 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1364 .opmode = { 0xe454, 3, 0, 5, 1 },
1365 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1366 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1367 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1368 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1369 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1370 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1371 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1372 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1373 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1379 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1381 [USB2PHY_PORT_OTG] = {
1382 .phy_sus = { 0xe464, 1, 0, 2, 1 },
1383 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1384 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1385 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1386 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1387 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1389 [USB2PHY_PORT_HOST] = {
1390 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1391 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1392 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1393 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1394 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1395 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1402 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1406 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1408 [USB2PHY_PORT_OTG] = {
1409 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1410 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1411 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1412 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1413 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1414 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1415 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1416 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 },
1417 .utmi_ls = { 0x0804, 13, 12, 0, 1 },
1419 [USB2PHY_PORT_HOST] = {
1420 .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 },
1421 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1422 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1423 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1424 .utmi_ls = { 0x0804, 9, 8, 0, 1 },
1425 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 }
1429 .opmode = { 0x0100, 3, 0, 5, 1 },
1430 .cp_det = { 0x0804, 1, 1, 0, 1 },
1431 .dcp_det = { 0x0804, 0, 0, 0, 1 },
1432 .dp_det = { 0x0804, 2, 2, 0, 1 },
1433 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1434 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1435 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1436 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1437 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1438 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1444 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1445 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1446 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1447 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1448 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1449 { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
1452 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1454 static struct platform_driver rockchip_usb2phy_driver = {
1455 .probe = rockchip_usb2phy_probe,
1457 .name = "rockchip-usb2phy",
1458 .of_match_table = rockchip_usb2phy_dt_match,
1461 module_platform_driver(rockchip_usb2phy_driver);
1463 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1464 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1465 MODULE_LICENSE("GPL v2");