1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
6 * Heiko Stuebner <heiko@sntech.de>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/nvmem-consumer.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/phy/phy.h>
22 #include <linux/slab.h>
24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
27 #define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0)
29 #define RK3228_BYPASS_RXSENSE_EN BIT(2)
30 #define RK3228_BYPASS_PWRON_EN BIT(1)
31 #define RK3228_BYPASS_PLLPD_EN BIT(0)
33 #define RK3228_BYPASS_PDATA_EN BIT(4)
34 #define RK3228_PDATAEN_DISABLE BIT(0)
36 #define RK3228_BYPASS_AUTO_TERM_RES_CAL BIT(7)
37 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
39 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
41 #define RK3228_POST_PLL_CTRL_MANUAL BIT(0)
43 #define RK3228_POST_PLL_POWER_DOWN BIT(5)
44 #define RK3228_PRE_PLL_POWER_DOWN BIT(4)
45 #define RK3228_RXSENSE_CLK_CH_ENABLE BIT(3)
46 #define RK3228_RXSENSE_DATA_CH2_ENABLE BIT(2)
47 #define RK3228_RXSENSE_DATA_CH1_ENABLE BIT(1)
48 #define RK3228_RXSENSE_DATA_CH0_ENABLE BIT(0)
50 #define RK3228_BANDGAP_ENABLE BIT(4)
51 #define RK3228_TMDS_DRIVER_ENABLE GENMASK(3, 0)
53 #define RK3228_PRE_PLL_FB_DIV_8_MASK BIT(7)
54 #define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
55 #define RK3228_PCLK_VCO_DIV_5_MASK BIT(5)
56 #define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
57 #define RK3228_PRE_PLL_PRE_DIV_MASK GENMASK(4, 0)
58 #define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
60 #define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
62 #define RK3228_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)
63 #define RK3228_PRE_PLL_PCLK_DIV_B_SHIFT 5
64 #define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
65 #define RK3228_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)
66 #define RK3228_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
68 #define RK3228_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)
69 #define RK3228_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
70 #define RK3228_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)
71 #define RK3228_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
73 #define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4)
74 #define RK3228_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4)
75 #define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2)
76 #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
77 #define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0)
78 #define RK3228_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0)
80 #define RK3228_PRE_PLL_LOCK_STATUS BIT(0)
82 #define RK3228_POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6)
83 #define RK3228_POST_PLL_PRE_DIV_MASK GENMASK(4, 0)
84 #define RK3228_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
86 #define RK3228_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
88 #define RK3228_POST_PLL_FB_DIV_8_MASK BIT(7)
89 #define RK3228_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
90 #define RK3228_POST_PLL_POST_DIV_MASK GENMASK(5, 4)
91 #define RK3228_POST_PLL_POST_DIV(x) UPDATE(x, 5, 4)
92 #define RK3228_POST_PLL_LOCK_STATUS BIT(0)
94 #define RK3228_TMDS_CH_TA_ENABLE GENMASK(7, 4)
96 #define RK3228_TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6)
97 #define RK3228_TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4)
98 #define RK3228_TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)
99 #define RK3228_TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0)
101 #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4)
102 #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4)
103 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2)
104 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)
105 #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0)
106 #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0)
108 #define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4)
109 #define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0)
111 #define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4)
112 #define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0)
115 #define RK3328_BYPASS_RXSENSE_EN BIT(2)
116 #define RK3328_BYPASS_POWERON_EN BIT(1)
117 #define RK3328_BYPASS_PLLPD_EN BIT(0)
119 #define RK3328_INT_POL_HIGH BIT(7)
120 #define RK3328_BYPASS_PDATA_EN BIT(4)
121 #define RK3328_PDATA_EN BIT(0)
123 #define RK3328_INT_TMDS_CLK(x) UPDATE(x, 7, 4)
124 #define RK3328_INT_TMDS_D2(x) UPDATE(x, 3, 0)
126 #define RK3328_INT_TMDS_D1(x) UPDATE(x, 7, 4)
127 #define RK3328_INT_TMDS_D0(x) UPDATE(x, 3, 0)
128 /* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */
129 #define RK3328_INT_AGND_LOW_PULSE_LOCKED BIT(3)
130 #define RK3328_INT_RXSENSE_LOW_PULSE_LOCKED BIT(2)
131 #define RK3328_INT_VSS_AGND_ESD_DET BIT(1)
132 #define RK3328_INT_AGND_VSS_ESD_DET BIT(0)
134 #define RK3328_PCLK_VCO_DIV_5_MASK BIT(1)
135 #define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1)
136 #define RK3328_PRE_PLL_POWER_DOWN BIT(0)
138 #define RK3328_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0)
139 #define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0)
141 /* unset means center spread */
142 #define RK3328_SPREAD_SPECTRUM_MOD_DOWN BIT(7)
143 #define RK3328_SPREAD_SPECTRUM_MOD_DISABLE BIT(6)
144 #define RK3328_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4)
145 #define RK3328_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)
146 #define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0)
148 #define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
150 #define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0)
151 #define RK3328_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0)
152 #define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2)
153 #define RK3328_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2)
154 #define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4)
155 #define RK3328_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4)
157 #define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT 5
158 #define RK3328_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)
159 #define RK3328_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
160 #define RK3328_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)
161 #define RK3328_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
163 #define RK3328_PRE_PLL_PCLK_DIV_C_SHIFT 5
164 #define RK3328_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)
165 #define RK3328_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
166 #define RK3328_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)
167 #define RK3328_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
169 #define RK3328_PRE_PLL_LOCK_STATUS BIT(0)
171 #define RK3328_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2)
172 #define RK3328_POST_PLL_REFCLK_SEL_TMDS BIT(1)
173 #define RK3328_POST_PLL_POWER_DOWN BIT(0)
175 #define RK3328_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
176 #define RK3328_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
178 #define RK3328_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
180 #define RK3328_POST_PLL_POST_DIV_MASK GENMASK(1, 0)
181 #define RK3328_POST_PLL_POST_DIV_2 0x0
182 #define RK3328_POST_PLL_POST_DIV_4 0x1
183 #define RK3328_POST_PLL_POST_DIV_8 0x3
185 #define RK3328_POST_PLL_LOCK_STATUS BIT(0)
187 #define RK3328_BANDGAP_ENABLE BIT(2)
189 #define RK3328_TMDS_CLK_DRIVER_EN BIT(3)
190 #define RK3328_TMDS_D2_DRIVER_EN BIT(2)
191 #define RK3328_TMDS_D1_DRIVER_EN BIT(1)
192 #define RK3328_TMDS_D0_DRIVER_EN BIT(0)
193 #define RK3328_TMDS_DRIVER_ENABLE (RK3328_TMDS_CLK_DRIVER_EN | \
194 RK3328_TMDS_D2_DRIVER_EN | \
195 RK3328_TMDS_D1_DRIVER_EN | \
196 RK3328_TMDS_D0_DRIVER_EN)
198 #define RK3328_BYPASS_TERM_RESISTOR_CALIB BIT(7)
199 #define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0)
201 #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 0)
203 #define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1)
204 #define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1)
205 #define RK3328_TERM_RESISTOR_75 UPDATE(2, 2, 1)
206 #define RK3328_TERM_RESISTOR_100 UPDATE(3, 2, 1)
207 /* REG 0xc8 - 0xcb */
208 #define RK3328_ESD_DETECT_MASK GENMASK(7, 6)
209 #define RK3328_ESD_DETECT_340MV (0x0 << 6)
210 #define RK3328_ESD_DETECT_280MV (0x1 << 6)
211 #define RK3328_ESD_DETECT_260MV (0x2 << 6)
212 #define RK3328_ESD_DETECT_240MV (0x3 << 6)
213 /* resistors can be used in parallel */
214 #define RK3328_TMDS_TERM_RESIST_MASK GENMASK(5, 0)
215 #define RK3328_TMDS_TERM_RESIST_75 BIT(5)
216 #define RK3328_TMDS_TERM_RESIST_150 BIT(4)
217 #define RK3328_TMDS_TERM_RESIST_300 BIT(3)
218 #define RK3328_TMDS_TERM_RESIST_600 BIT(2)
219 #define RK3328_TMDS_TERM_RESIST_1000 BIT(1)
220 #define RK3328_TMDS_TERM_RESIST_2000 BIT(0)
222 #define RK3328_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0)
224 #define RK3328_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0)
226 #define RK3328_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0)
228 struct inno_hdmi_phy_drv_data;
230 struct inno_hdmi_phy {
232 struct regmap *regmap;
241 const struct inno_hdmi_phy_drv_data *plat_data;
247 unsigned long pixclock;
250 struct pre_pll_config {
251 unsigned long pixclock;
252 unsigned long tmdsclock;
266 struct post_pll_config {
267 unsigned long tmdsclock;
275 unsigned long tmdsclock;
279 struct inno_hdmi_phy_ops {
280 int (*init)(struct inno_hdmi_phy *inno);
281 int (*power_on)(struct inno_hdmi_phy *inno,
282 const struct post_pll_config *cfg,
283 const struct phy_config *phy_cfg);
284 void (*power_off)(struct inno_hdmi_phy *inno);
287 struct inno_hdmi_phy_drv_data {
288 const struct inno_hdmi_phy_ops *ops;
289 const struct clk_ops *clk_ops;
290 const struct phy_config *phy_cfg_table;
293 static const struct pre_pll_config pre_pll_cfg_table[] = {
294 { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
295 { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
296 { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
297 { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
298 { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
299 { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
300 { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
301 { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
302 { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
303 { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
304 { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
305 {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
306 {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
307 {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
308 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
309 {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
310 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
311 {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
312 {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
313 {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
314 {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
315 {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
316 {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
317 {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
318 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
322 static const struct post_pll_config post_pll_cfg_table[] = {
323 {33750000, 1, 40, 8, 1},
324 {33750000, 1, 80, 8, 2},
325 {74250000, 1, 40, 8, 1},
326 {74250000, 18, 80, 8, 2},
327 {148500000, 2, 40, 4, 3},
328 {297000000, 4, 40, 2, 3},
329 {594000000, 8, 40, 1, 3},
333 /* phy tuning values for an undocumented set of registers */
334 static const struct phy_config rk3228_phy_cfg[] = {
336 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
337 0x00, 0x00, 0x00, 0x00, 0x00,
341 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
342 0x00, 0x00, 0x00, 0x00, 0x00,
346 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
347 0x00, 0x00, 0x00, 0x00, 0x00,
349 }, { /* sentinel */ },
352 /* phy tuning values for an undocumented set of registers */
353 static const struct phy_config rk3328_phy_cfg[] = {
355 0x07, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x08, 0x08, 0x08,
356 0x00, 0xac, 0xcc, 0xcc, 0xcc,
360 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08,
361 0x3f, 0xac, 0xcc, 0xcd, 0xdd,
365 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
366 0x00, 0xac, 0xcc, 0xcc, 0xcc,
368 }, { /* sentinel */ },
371 static inline struct inno_hdmi_phy *to_inno_hdmi_phy(struct clk_hw *hw)
373 return container_of(hw, struct inno_hdmi_phy, hw);
377 * The register description of the IP block does not use any distinct names
378 * but instead the databook simply numbers the registers in one-increments.
379 * As the registers are obviously 32bit sized, the inno_* functions
380 * translate the databook register names to the actual registers addresses.
382 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
384 regmap_write(inno->regmap, reg * 4, val);
387 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
391 regmap_read(inno->regmap, reg * 4, &val);
396 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
399 regmap_update_bits(inno->regmap, reg * 4, mask, val);
402 #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
403 regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
404 sleep_us, timeout_us)
406 static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
409 int bus_width = phy_get_bus_width(inno->phy);
418 return (u64)rate * bus_width / 8;
424 static irqreturn_t inno_hdmi_phy_rk3328_hardirq(int irq, void *dev_id)
426 struct inno_hdmi_phy *inno = dev_id;
427 int intr_stat1, intr_stat2, intr_stat3;
429 intr_stat1 = inno_read(inno, 0x04);
430 intr_stat2 = inno_read(inno, 0x06);
431 intr_stat3 = inno_read(inno, 0x08);
434 inno_write(inno, 0x04, intr_stat1);
436 inno_write(inno, 0x06, intr_stat2);
438 inno_write(inno, 0x08, intr_stat3);
440 if (intr_stat1 || intr_stat2 || intr_stat3)
441 return IRQ_WAKE_THREAD;
446 static irqreturn_t inno_hdmi_phy_rk3328_irq(int irq, void *dev_id)
448 struct inno_hdmi_phy *inno = dev_id;
450 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
451 usleep_range(10, 20);
452 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
457 static int inno_hdmi_phy_power_on(struct phy *phy)
459 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
460 const struct post_pll_config *cfg = post_pll_cfg_table;
461 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
462 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno,
467 dev_err(inno->dev, "TMDS clock is zero!\n");
471 if (!inno->plat_data->ops->power_on)
474 for (; cfg->tmdsclock != 0; cfg++)
475 if (tmdsclock <= cfg->tmdsclock &&
476 cfg->version & inno->chip_version)
479 for (; phy_cfg->tmdsclock != 0; phy_cfg++)
480 if (tmdsclock <= phy_cfg->tmdsclock)
483 if (cfg->tmdsclock == 0 || phy_cfg->tmdsclock == 0)
486 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
488 ret = clk_prepare_enable(inno->phyclk);
492 ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
494 clk_disable_unprepare(inno->phyclk);
501 static int inno_hdmi_phy_power_off(struct phy *phy)
503 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
505 if (!inno->plat_data->ops->power_off)
508 inno->plat_data->ops->power_off(inno);
510 clk_disable_unprepare(inno->phyclk);
512 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
517 static const struct phy_ops inno_hdmi_phy_ops = {
518 .owner = THIS_MODULE,
519 .power_on = inno_hdmi_phy_power_on,
520 .power_off = inno_hdmi_phy_power_off,
524 struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno,
527 const struct pre_pll_config *cfg = pre_pll_cfg_table;
528 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
530 for (; cfg->pixclock != 0; cfg++)
531 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
534 if (cfg->pixclock == 0)
535 return ERR_PTR(-EINVAL);
540 static int inno_hdmi_phy_rk3228_clk_is_prepared(struct clk_hw *hw)
542 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
545 status = inno_read(inno, 0xe0) & RK3228_PRE_PLL_POWER_DOWN;
546 return status ? 0 : 1;
549 static int inno_hdmi_phy_rk3228_clk_prepare(struct clk_hw *hw)
551 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
553 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
557 static void inno_hdmi_phy_rk3228_clk_unprepare(struct clk_hw *hw)
559 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
561 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
562 RK3228_PRE_PLL_POWER_DOWN);
566 unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(struct clk_hw *hw,
567 unsigned long parent_rate)
569 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
570 u8 nd, no_a, no_b, no_d;
574 nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK;
575 nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1;
576 nf |= inno_read(inno, 0xe3);
577 vco = parent_rate * nf;
579 if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) {
582 no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK;
585 no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK;
586 no_b >>= RK3228_PRE_PLL_PCLK_DIV_B_SHIFT;
588 no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK;
590 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
593 inno->pixclock = vco;
595 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
600 static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw,
602 unsigned long *parent_rate)
604 const struct pre_pll_config *cfg = pre_pll_cfg_table;
606 rate = (rate / 1000) * 1000;
608 for (; cfg->pixclock != 0; cfg++)
609 if (cfg->pixclock == rate && !cfg->fracdiv)
612 if (cfg->pixclock == 0)
615 return cfg->pixclock;
618 static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
620 unsigned long parent_rate)
622 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
623 const struct pre_pll_config *cfg = pre_pll_cfg_table;
624 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
628 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
629 __func__, rate, tmdsclock);
631 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
635 /* Power down PRE-PLL */
636 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
637 RK3228_PRE_PLL_POWER_DOWN);
639 inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK |
640 RK3228_PCLK_VCO_DIV_5_MASK |
641 RK3228_PRE_PLL_PRE_DIV_MASK,
642 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) |
643 RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) |
644 RK3228_PRE_PLL_PRE_DIV(cfg->prediv));
645 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
646 inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK |
647 RK3228_PRE_PLL_PCLK_DIV_A_MASK,
648 RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) |
649 RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a));
650 inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK |
651 RK3228_PRE_PLL_PCLK_DIV_D_MASK,
652 RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
653 RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));
654 inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK |
655 RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK |
656 RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK,
657 RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
658 RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
659 RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
661 /* Power up PRE-PLL */
662 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
664 /* Wait for Pre-PLL lock */
665 ret = inno_poll(inno, 0xe8, v, v & RK3228_PRE_PLL_LOCK_STATUS,
668 dev_err(inno->dev, "Pre-PLL locking failed\n");
672 inno->pixclock = rate;
677 static const struct clk_ops inno_hdmi_phy_rk3228_clk_ops = {
678 .prepare = inno_hdmi_phy_rk3228_clk_prepare,
679 .unprepare = inno_hdmi_phy_rk3228_clk_unprepare,
680 .is_prepared = inno_hdmi_phy_rk3228_clk_is_prepared,
681 .recalc_rate = inno_hdmi_phy_rk3228_clk_recalc_rate,
682 .round_rate = inno_hdmi_phy_rk3228_clk_round_rate,
683 .set_rate = inno_hdmi_phy_rk3228_clk_set_rate,
686 static int inno_hdmi_phy_rk3328_clk_is_prepared(struct clk_hw *hw)
688 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
691 status = inno_read(inno, 0xa0) & RK3328_PRE_PLL_POWER_DOWN;
692 return status ? 0 : 1;
695 static int inno_hdmi_phy_rk3328_clk_prepare(struct clk_hw *hw)
697 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
699 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
703 static void inno_hdmi_phy_rk3328_clk_unprepare(struct clk_hw *hw)
705 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
707 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
708 RK3328_PRE_PLL_POWER_DOWN);
712 unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
713 unsigned long parent_rate)
715 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
717 u8 nd, no_a, no_b, no_c, no_d;
721 nd = inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK;
722 nf = ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8);
723 nf |= inno_read(inno, 0xa3);
724 vco = parent_rate * nf;
726 if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) {
727 frac = inno_read(inno, 0xd3) |
728 (inno_read(inno, 0xd2) << 8) |
729 (inno_read(inno, 0xd1) << 16);
730 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
733 if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) {
736 no_a = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK;
737 no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
738 no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
740 no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
741 no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT;
743 no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
745 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
748 inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
750 dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
751 __func__, inno->pixclock, vco);
753 return inno->pixclock;
756 static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,
758 unsigned long *parent_rate)
760 const struct pre_pll_config *cfg = pre_pll_cfg_table;
762 rate = (rate / 1000) * 1000;
764 for (; cfg->pixclock != 0; cfg++)
765 if (cfg->pixclock == rate)
768 if (cfg->pixclock == 0)
771 return cfg->pixclock;
774 static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
776 unsigned long parent_rate)
778 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
779 const struct pre_pll_config *cfg = pre_pll_cfg_table;
780 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
784 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
785 __func__, rate, tmdsclock);
787 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
791 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
792 RK3328_PRE_PLL_POWER_DOWN);
794 /* Configure pre-pll */
795 inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
796 RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
797 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
799 val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE;
801 val |= RK3328_PRE_PLL_FRAC_DIV_DISABLE;
802 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);
803 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
804 inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) |
805 RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b));
806 inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
807 RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));
808 inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
809 RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
810 RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
811 inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));
812 inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));
813 inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));
815 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
817 /* Wait for Pre-PLL lock */
818 ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
821 dev_err(inno->dev, "Pre-PLL locking failed\n");
825 inno->pixclock = rate;
830 static const struct clk_ops inno_hdmi_phy_rk3328_clk_ops = {
831 .prepare = inno_hdmi_phy_rk3328_clk_prepare,
832 .unprepare = inno_hdmi_phy_rk3328_clk_unprepare,
833 .is_prepared = inno_hdmi_phy_rk3328_clk_is_prepared,
834 .recalc_rate = inno_hdmi_phy_rk3328_clk_recalc_rate,
835 .round_rate = inno_hdmi_phy_rk3328_clk_round_rate,
836 .set_rate = inno_hdmi_phy_rk3328_clk_set_rate,
839 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
841 struct device *dev = inno->dev;
842 struct device_node *np = dev->of_node;
843 struct clk_init_data init;
844 const char *parent_name;
847 parent_name = __clk_get_name(inno->refoclk);
849 init.parent_names = &parent_name;
850 init.num_parents = 1;
852 init.name = "pin_hd20_pclk";
853 init.ops = inno->plat_data->clk_ops;
855 /* optional override of the clock name */
856 of_property_read_string(np, "clock-output-names", &init.name);
858 inno->hw.init = &init;
860 inno->phyclk = devm_clk_register(dev, &inno->hw);
861 if (IS_ERR(inno->phyclk)) {
862 ret = PTR_ERR(inno->phyclk);
863 dev_err(dev, "failed to register clock: %d\n", ret);
867 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk);
869 dev_err(dev, "failed to register clock provider: %d\n", ret);
876 static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
879 * Use phy internal register control
880 * rxsense/poweron/pllpd/pdataen signal.
882 inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN |
883 RK3228_BYPASS_PWRON_EN |
884 RK3228_BYPASS_PLLPD_EN);
885 inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN,
886 RK3228_BYPASS_PDATA_EN);
888 /* manual power down post-PLL */
889 inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
890 RK3228_POST_PLL_CTRL_MANUAL);
892 inno->chip_version = 1;
898 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,
899 const struct post_pll_config *cfg,
900 const struct phy_config *phy_cfg)
905 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE,
906 RK3228_PDATAEN_DISABLE);
907 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
908 RK3228_POST_PLL_POWER_DOWN,
909 RK3228_PRE_PLL_POWER_DOWN |
910 RK3228_POST_PLL_POWER_DOWN);
912 /* Post-PLL update */
913 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK,
914 RK3228_POST_PLL_PRE_DIV(cfg->prediv));
915 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK,
916 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv));
917 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
919 if (cfg->postdiv == 1) {
920 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
923 int div = cfg->postdiv / 2 - 1;
925 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
926 RK3228_POST_PLL_POST_DIV_ENABLE);
927 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK,
928 RK3228_POST_PLL_POST_DIV(div));
931 for (v = 0; v < 4; v++)
932 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
934 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
935 RK3228_POST_PLL_POWER_DOWN, 0);
936 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE,
937 RK3228_BANDGAP_ENABLE);
938 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE,
939 RK3228_TMDS_DRIVER_ENABLE);
941 /* Wait for post PLL lock */
942 ret = inno_poll(inno, 0xeb, v, v & RK3228_POST_PLL_LOCK_STATUS,
945 dev_err(inno->dev, "Post-PLL locking failed\n");
949 if (cfg->tmdsclock > 340000000)
952 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, 0);
956 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
958 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0);
959 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0);
960 inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN,
961 RK3228_POST_PLL_POWER_DOWN);
964 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
965 .init = inno_hdmi_phy_rk3228_init,
966 .power_on = inno_hdmi_phy_rk3228_power_on,
967 .power_off = inno_hdmi_phy_rk3228_power_off,
970 static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
972 struct nvmem_cell *cell;
973 unsigned char *efuse_buf;
977 * Use phy internal register control
978 * rxsense/poweron/pllpd/pdataen signal.
980 inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN |
981 RK3328_BYPASS_POWERON_EN |
982 RK3328_BYPASS_PLLPD_EN);
983 inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN |
986 /* Disable phy irq */
987 inno_write(inno, 0x05, 0);
988 inno_write(inno, 0x07, 0);
990 /* try to read the chip-version */
991 inno->chip_version = 1;
992 cell = nvmem_cell_get(inno->dev, "cpu-version");
994 if (PTR_ERR(cell) == -EPROBE_DEFER)
995 return -EPROBE_DEFER;
1000 efuse_buf = nvmem_cell_read(cell, &len);
1001 nvmem_cell_put(cell);
1003 if (IS_ERR(efuse_buf))
1006 inno->chip_version = efuse_buf[0] + 1;
1013 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
1014 const struct post_pll_config *cfg,
1015 const struct phy_config *phy_cfg)
1020 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
1021 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1022 RK3328_POST_PLL_POWER_DOWN);
1024 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1025 if (cfg->postdiv == 1) {
1026 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1027 RK3328_POST_PLL_PRE_DIV(cfg->prediv));
1028 inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
1029 RK3328_POST_PLL_POWER_DOWN);
1031 v = (cfg->postdiv / 2) - 1;
1032 v &= RK3328_POST_PLL_POST_DIV_MASK;
1033 inno_write(inno, 0xad, v);
1034 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1035 RK3328_POST_PLL_PRE_DIV(cfg->prediv));
1036 inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
1037 RK3328_POST_PLL_REFCLK_SEL_TMDS |
1038 RK3328_POST_PLL_POWER_DOWN);
1041 for (v = 0; v < 14; v++)
1042 inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);
1044 /* set ESD detection threshold for TMDS CLK, D2, D1 and D0 */
1045 for (v = 0; v < 4; v++)
1046 inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK,
1047 RK3328_ESD_DETECT_340MV);
1049 if (phy_cfg->tmdsclock > 340000000) {
1050 /* Set termination resistor to 100ohm */
1051 v = clk_get_rate(inno->sysclk) / 100000;
1052 inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v)
1053 | RK3328_BYPASS_TERM_RESISTOR_CALIB);
1054 inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v));
1055 inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100);
1056 inno_update_bits(inno, 0xc5,
1057 RK3328_BYPASS_TERM_RESISTOR_CALIB, 0);
1059 inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB);
1061 /* clk termination resistor is 50ohm (parallel resistors) */
1062 if (phy_cfg->tmdsclock > 165000000)
1063 inno_update_bits(inno, 0xc8,
1064 RK3328_TMDS_TERM_RESIST_MASK,
1065 RK3328_TMDS_TERM_RESIST_75 |
1066 RK3328_TMDS_TERM_RESIST_150);
1068 /* data termination resistor for D2, D1 and D0 is 150ohm */
1069 for (v = 0; v < 3; v++)
1070 inno_update_bits(inno, 0xc9 + v,
1071 RK3328_TMDS_TERM_RESIST_MASK,
1072 RK3328_TMDS_TERM_RESIST_150);
1075 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0);
1076 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE,
1077 RK3328_BANDGAP_ENABLE);
1078 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE,
1079 RK3328_TMDS_DRIVER_ENABLE);
1081 /* Wait for post PLL lock */
1082 ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
1085 dev_err(inno->dev, "Post-PLL locking failed\n");
1089 if (phy_cfg->tmdsclock > 340000000)
1092 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
1094 /* Enable PHY IRQ */
1095 inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET)
1096 | RK3328_INT_TMDS_D2(RK3328_INT_VSS_AGND_ESD_DET));
1097 inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET)
1098 | RK3328_INT_TMDS_D0(RK3328_INT_VSS_AGND_ESD_DET));
1102 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
1104 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0);
1105 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0);
1106 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1107 RK3328_POST_PLL_POWER_DOWN);
1109 /* Disable PHY IRQ */
1110 inno_write(inno, 0x05, 0);
1111 inno_write(inno, 0x07, 0);
1114 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = {
1115 .init = inno_hdmi_phy_rk3328_init,
1116 .power_on = inno_hdmi_phy_rk3328_power_on,
1117 .power_off = inno_hdmi_phy_rk3328_power_off,
1120 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
1121 .ops = &rk3228_hdmi_phy_ops,
1122 .clk_ops = &inno_hdmi_phy_rk3228_clk_ops,
1123 .phy_cfg_table = rk3228_phy_cfg,
1126 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = {
1127 .ops = &rk3328_hdmi_phy_ops,
1128 .clk_ops = &inno_hdmi_phy_rk3328_clk_ops,
1129 .phy_cfg_table = rk3328_phy_cfg,
1132 static const struct regmap_config inno_hdmi_phy_regmap_config = {
1136 .max_register = 0x400,
1139 static void inno_hdmi_phy_action(void *data)
1141 struct inno_hdmi_phy *inno = data;
1143 clk_disable_unprepare(inno->refpclk);
1144 clk_disable_unprepare(inno->sysclk);
1147 static int inno_hdmi_phy_probe(struct platform_device *pdev)
1149 struct inno_hdmi_phy *inno;
1150 struct phy_provider *phy_provider;
1151 struct resource *res;
1155 inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL);
1159 inno->dev = &pdev->dev;
1161 inno->plat_data = of_device_get_match_data(inno->dev);
1162 if (!inno->plat_data || !inno->plat_data->ops)
1165 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1166 regs = devm_ioremap_resource(inno->dev, res);
1168 return PTR_ERR(regs);
1170 inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1171 if (IS_ERR(inno->sysclk)) {
1172 ret = PTR_ERR(inno->sysclk);
1173 dev_err(inno->dev, "failed to get sysclk: %d\n", ret);
1177 inno->refpclk = devm_clk_get(inno->dev, "refpclk");
1178 if (IS_ERR(inno->refpclk)) {
1179 ret = PTR_ERR(inno->refpclk);
1180 dev_err(inno->dev, "failed to get ref clock: %d\n", ret);
1184 inno->refoclk = devm_clk_get(inno->dev, "refoclk");
1185 if (IS_ERR(inno->refoclk)) {
1186 ret = PTR_ERR(inno->refoclk);
1187 dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n",
1192 ret = clk_prepare_enable(inno->sysclk);
1194 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1199 * Refpclk needs to be on, on at least the rk3328 for still
1202 ret = clk_prepare_enable(inno->refpclk);
1204 dev_err(inno->dev, "failed to enable refpclk\n");
1205 clk_disable_unprepare(inno->sysclk);
1209 ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action,
1214 inno->regmap = devm_regmap_init_mmio(inno->dev, regs,
1215 &inno_hdmi_phy_regmap_config);
1216 if (IS_ERR(inno->regmap))
1217 return PTR_ERR(inno->regmap);
1219 /* only the newer rk3328 hdmiphy has an interrupt */
1220 inno->irq = platform_get_irq(pdev, 0);
1221 if (inno->irq > 0) {
1222 ret = devm_request_threaded_irq(inno->dev, inno->irq,
1223 inno_hdmi_phy_rk3328_hardirq,
1224 inno_hdmi_phy_rk3328_irq,
1226 dev_name(inno->dev), inno);
1231 inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops);
1232 if (IS_ERR(inno->phy)) {
1233 dev_err(inno->dev, "failed to create HDMI PHY\n");
1234 return PTR_ERR(inno->phy);
1237 phy_set_drvdata(inno->phy, inno);
1238 phy_set_bus_width(inno->phy, 8);
1240 if (inno->plat_data->ops->init) {
1241 ret = inno->plat_data->ops->init(inno);
1246 ret = inno_hdmi_phy_clk_register(inno);
1250 phy_provider = devm_of_phy_provider_register(inno->dev,
1251 of_phy_simple_xlate);
1252 return PTR_ERR_OR_ZERO(phy_provider);
1255 static int inno_hdmi_phy_remove(struct platform_device *pdev)
1257 of_clk_del_provider(pdev->dev.of_node);
1262 static const struct of_device_id inno_hdmi_phy_of_match[] = {
1264 .compatible = "rockchip,rk3228-hdmi-phy",
1265 .data = &rk3228_hdmi_phy_drv_data
1267 .compatible = "rockchip,rk3328-hdmi-phy",
1268 .data = &rk3328_hdmi_phy_drv_data
1269 }, { /* sentinel */ }
1271 MODULE_DEVICE_TABLE(of, inno_hdmi_phy_of_match);
1273 static struct platform_driver inno_hdmi_phy_driver = {
1274 .probe = inno_hdmi_phy_probe,
1275 .remove = inno_hdmi_phy_remove,
1277 .name = "inno-hdmi-phy",
1278 .of_match_table = inno_hdmi_phy_of_match,
1281 module_platform_driver(inno_hdmi_phy_driver);
1283 MODULE_AUTHOR("Zheng Yang <zhengyang@rock-chips.com>");
1284 MODULE_DESCRIPTION("Innosilion HDMI 2.0 Transmitter PHY Driver");
1285 MODULE_LICENSE("GPL v2");