drivers/phy/rockchip/phy-rockchip-emmc.c

   1 /*
   2  * Rockchip emmc PHY driver
   3  *
   4  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
   5  * Copyright (C) 2016 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26
  27 /*
  28  * The higher 16-bit of this register is used for write protection
  29  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
  30  */
  31 #define HIWORD_UPDATE(val, mask, shift) \
  32                 ((val) << (shift) | (mask) << ((shift) + 16))
  33
  34 /* Register definition */
  35 #define GRF_EMMCPHY_CON0                0x0
  36 #define GRF_EMMCPHY_CON1                0x4
  37 #define GRF_EMMCPHY_CON2                0x8
  38 #define GRF_EMMCPHY_CON3                0xc
  39 #define GRF_EMMCPHY_CON4                0x10
  40 #define GRF_EMMCPHY_CON5                0x14
  41 #define GRF_EMMCPHY_CON6                0x18
  42 #define GRF_EMMCPHY_STATUS              0x20
  43
  44 #define PHYCTRL_PDB_MASK                0x1
  45 #define PHYCTRL_PDB_SHIFT               0x0
  46 #define PHYCTRL_PDB_PWR_ON              0x1
  47 #define PHYCTRL_PDB_PWR_OFF             0x0
  48 #define PHYCTRL_ENDLL_MASK              0x1
  49 #define PHYCTRL_ENDLL_SHIFT             0x1
  50 #define PHYCTRL_ENDLL_ENABLE            0x1
  51 #define PHYCTRL_ENDLL_DISABLE           0x0
  52 #define PHYCTRL_CALDONE_MASK            0x1
  53 #define PHYCTRL_CALDONE_SHIFT           0x6
  54 #define PHYCTRL_CALDONE_DONE            0x1
  55 #define PHYCTRL_CALDONE_GOING           0x0
  56 #define PHYCTRL_DLLRDY_MASK             0x1
  57 #define PHYCTRL_DLLRDY_SHIFT            0x5
  58 #define PHYCTRL_DLLRDY_DONE             0x1
  59 #define PHYCTRL_DLLRDY_GOING            0x0
  60 #define PHYCTRL_FREQSEL_200M            0x0
  61 #define PHYCTRL_FREQSEL_50M             0x1
  62 #define PHYCTRL_FREQSEL_100M            0x2
  63 #define PHYCTRL_FREQSEL_150M            0x3
  64 #define PHYCTRL_FREQSEL_MASK            0x3
  65 #define PHYCTRL_FREQSEL_SHIFT           0xc
  66 #define PHYCTRL_DR_MASK                 0x7
  67 #define PHYCTRL_DR_SHIFT                0x4
  68 #define PHYCTRL_DR_50OHM                0x0
  69 #define PHYCTRL_DR_33OHM                0x1
  70 #define PHYCTRL_DR_66OHM                0x2
  71 #define PHYCTRL_DR_100OHM               0x3
  72 #define PHYCTRL_DR_40OHM                0x4
  73 #define PHYCTRL_OTAPDLYENA              0x1
  74 #define PHYCTRL_OTAPDLYENA_MASK         0x1
  75 #define PHYCTRL_OTAPDLYENA_SHIFT        0xb
  76 #define PHYCTRL_OTAPDLYSEL_MASK         0xf
  77 #define PHYCTRL_OTAPDLYSEL_SHIFT        0x7
  78
  79 #define PHYCTRL_IS_CALDONE(x) \
  80         ((((x) >> PHYCTRL_CALDONE_SHIFT) & \
  81           PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
  82
  83 struct rockchip_emmc_phy {
  84         unsigned int    reg_offset;
  85         struct regmap   *reg_base;
  86         struct clk      *emmcclk;
  87 };
  88
  89 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
  90 {
  91         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
  92         unsigned int caldone;
  93         unsigned int dllrdy;
  94         unsigned int freqsel = PHYCTRL_FREQSEL_200M;
  95         unsigned long rate;
  96         unsigned long timeout;
  97         int ret;
  98
  99         /*
 100          * Keep phyctrl_pdb and phyctrl_endll low to allow
 101          * initialization of CALIO state M/C DFFs
 102          */
 103         regmap_write(rk_phy->reg_base,
 104                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 105                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
 106                                    PHYCTRL_PDB_MASK,
 107                                    PHYCTRL_PDB_SHIFT));
 108         regmap_write(rk_phy->reg_base,
 109                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 110                      HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
 111                                    PHYCTRL_ENDLL_MASK,
 112                                    PHYCTRL_ENDLL_SHIFT));
 113
 114         /* Already finish power_off above */
 115         if (on_off == PHYCTRL_PDB_PWR_OFF)
 116                 return 0;
 117
 118         rate = clk_get_rate(rk_phy->emmcclk);
 119
 120         if (rate != 0) {
 121                 unsigned long ideal_rate;
 122                 unsigned long diff;
 123
 124                 switch (rate) {
 125                 case 1 ... 74999999:
 126                         ideal_rate = 50000000;
 127                         freqsel = PHYCTRL_FREQSEL_50M;
 128                         break;
 129                 case 75000000 ... 124999999:
 130                         ideal_rate = 100000000;
 131                         freqsel = PHYCTRL_FREQSEL_100M;
 132                         break;
 133                 case 125000000 ... 174999999:
 134                         ideal_rate = 150000000;
 135                         freqsel = PHYCTRL_FREQSEL_150M;
 136                         break;
 137                 default:
 138                         ideal_rate = 200000000;
 139                         break;
 140                 }
 141
 142                 diff = (rate > ideal_rate) ?
 143                         rate - ideal_rate : ideal_rate - rate;
 144
 145                 /*
 146                  * In order for tuning delays to be accurate we need to be
 147                  * pretty spot on for the DLL range, so warn if we're too
 148                  * far off.  Also warn if we're above the 200 MHz max.  Don't
 149                  * warn for really slow rates since we won't be tuning then.
 150                  */
 151                 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
 152                         dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
 153         }
 154
 155         /*
 156          * According to the user manual, calpad calibration
 157          * cycle takes more than 2us without the minimal recommended
 158          * value, so we may need a little margin here
 159          */
 160         udelay(3);
 161         regmap_write(rk_phy->reg_base,
 162                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 163                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
 164                                    PHYCTRL_PDB_MASK,
 165                                    PHYCTRL_PDB_SHIFT));
 166
 167         /*
 168          * According to the user manual, it asks driver to wait 5us for
 169          * calpad busy trimming. However it is documented that this value is
 170          * PVT(A.K.A process,voltage and temperature) relevant, so some
 171          * failure cases are found which indicates we should be more tolerant
 172          * to calpad busy trimming.
 173          */
 174         ret = regmap_read_poll_timeout(rk_phy->reg_base,
 175                                        rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 176                                        caldone, PHYCTRL_IS_CALDONE(caldone),
 177                                        0, 50);
 178         if (ret) {
 179                 pr_err("%s: caldone failed, ret=%d\n", __func__, ret);
 180                 return ret;
 181         }
 182
 183         /* Set the frequency of the DLL operation */
 184         regmap_write(rk_phy->reg_base,
 185                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 186                      HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
 187                                    PHYCTRL_FREQSEL_SHIFT));
 188
 189         /* Turn on the DLL */
 190         regmap_write(rk_phy->reg_base,
 191                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 192                      HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
 193                                    PHYCTRL_ENDLL_MASK,
 194                                    PHYCTRL_ENDLL_SHIFT));
 195
 196         /*
 197          * We turned on the DLL even though the rate was 0 because we the
 198          * clock might be turned on later.  ...but we can't wait for the DLL
 199          * to lock when the rate is 0 because it will never lock with no
 200          * input clock.
 201          *
 202          * Technically we should be checking the lock later when the clock
 203          * is turned on, but for now we won't.
 204          */
 205         if (rate == 0)
 206                 return 0;
 207
 208         /*
 209          * After enabling analog DLL circuits docs say that we need 10.2 us if
 210          * our source clock is at 50 MHz and that lock time scales linearly
 211          * with clock speed.  If we are powering on the PHY and the card clock
 212          * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
 213          * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
 214          * Hopefully we won't be running at 100 kHz, but we should still make
 215          * sure we wait long enough.
 216          *
 217          * NOTE: There appear to be corner cases where the DLL seems to take
 218          * extra long to lock for reasons that aren't understood.  In some
 219          * extreme cases we've seen it take up to over 10ms (!).  We'll be
 220          * generous and give it 50ms.  We still busy wait here because:
 221          * - In most cases it should be super fast.
 222          * - This is not called lots during normal operation so it shouldn't
 223          *   be a power or performance problem to busy wait.  We expect it
 224          *   only at boot / resume.  In both cases, eMMC is probably on the
 225          *   critical path so busy waiting a little extra time should be OK.
 226          */
 227         timeout = jiffies + msecs_to_jiffies(50);
 228         do {
 229                 udelay(1);
 230
 231                 regmap_read(rk_phy->reg_base,
 232                         rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 233                         &dllrdy);
 234                 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
 235                 if (dllrdy == PHYCTRL_DLLRDY_DONE)
 236                         break;
 237         } while (!time_after(jiffies, timeout));
 238
 239         if (dllrdy != PHYCTRL_DLLRDY_DONE) {
 240                 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
 241                 return -ETIMEDOUT;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int rockchip_emmc_phy_init(struct phy *phy)
 248 {
 249         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 250         int ret = 0;
 251
 252         /*
 253          * We purposely get the clock here and not in probe to avoid the
 254          * circular dependency problem.  We expect:
 255          * - PHY driver to probe
 256          * - SDHCI driver to start probe
 257          * - SDHCI driver to register it's clock
 258          * - SDHCI driver to get the PHY
 259          * - SDHCI driver to init the PHY
 260          *
 261          * The clock is optional, so upon any error we just set to NULL.
 262          *
 263          * NOTE: we don't do anything special for EPROBE_DEFER here.  Given the
 264          * above expected use case, EPROBE_DEFER isn't sensible to expect, so
 265          * it's just like any other error.
 266          */
 267         rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
 268         if (IS_ERR(rk_phy->emmcclk)) {
 269                 dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);
 270                 rk_phy->emmcclk = NULL;
 271         }
 272
 273         return ret;
 274 }
 275
 276 static int rockchip_emmc_phy_exit(struct phy *phy)
 277 {
 278         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 279
 280         clk_put(rk_phy->emmcclk);
 281
 282         return 0;
 283 }
 284
 285 static int rockchip_emmc_phy_power_off(struct phy *phy)
 286 {
 287         /* Power down emmc phy analog blocks */
 288         return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
 289 }
 290
 291 static int rockchip_emmc_phy_power_on(struct phy *phy)
 292 {
 293         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 294
 295         /* Drive impedance: 50 Ohm */
 296         regmap_write(rk_phy->reg_base,
 297                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 298                      HIWORD_UPDATE(PHYCTRL_DR_50OHM,
 299                                    PHYCTRL_DR_MASK,
 300                                    PHYCTRL_DR_SHIFT));
 301
 302         /* Output tap delay: enable */
 303         regmap_write(rk_phy->reg_base,
 304                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 305                      HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
 306                                    PHYCTRL_OTAPDLYENA_MASK,
 307                                    PHYCTRL_OTAPDLYENA_SHIFT));
 308
 309         /* Output tap delay */
 310         regmap_write(rk_phy->reg_base,
 311                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 312                      HIWORD_UPDATE(4,
 313                                    PHYCTRL_OTAPDLYSEL_MASK,
 314                                    PHYCTRL_OTAPDLYSEL_SHIFT));
 315
 316         /* Power up emmc phy analog blocks */
 317         return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
 318 }
 319
 320 static const struct phy_ops ops = {
 321         .init           = rockchip_emmc_phy_init,
 322         .exit           = rockchip_emmc_phy_exit,
 323         .power_on       = rockchip_emmc_phy_power_on,
 324         .power_off      = rockchip_emmc_phy_power_off,
 325         .owner          = THIS_MODULE,
 326 };
 327
 328 static int rockchip_emmc_phy_probe(struct platform_device *pdev)
 329 {
 330         struct device *dev = &pdev->dev;
 331         struct rockchip_emmc_phy *rk_phy;
 332         struct phy *generic_phy;
 333         struct phy_provider *phy_provider;
 334         struct regmap *grf;
 335         unsigned int reg_offset;
 336
 337         if (!dev->parent || !dev->parent->of_node)
 338                 return -ENODEV;
 339
 340         grf = syscon_node_to_regmap(dev->parent->of_node);
 341         if (IS_ERR(grf)) {
 342                 dev_err(dev, "Missing rockchip,grf property\n");
 343                 return PTR_ERR(grf);
 344         }
 345
 346         rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
 347         if (!rk_phy)
 348                 return -ENOMEM;
 349
 350         if (of_property_read_u32(dev->of_node, "reg", &reg_offset)) {
 351                 dev_err(dev, "missing reg property in node %s\n",
 352                         dev->of_node->name);
 353                 return -EINVAL;
 354         }
 355
 356         rk_phy->reg_offset = reg_offset;
 357         rk_phy->reg_base = grf;
 358
 359         generic_phy = devm_phy_create(dev, dev->of_node, &ops);
 360         if (IS_ERR(generic_phy)) {
 361                 dev_err(dev, "failed to create PHY\n");
 362                 return PTR_ERR(generic_phy);
 363         }
 364
 365         phy_set_drvdata(generic_phy, rk_phy);
 366         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 367
 368         return PTR_ERR_OR_ZERO(phy_provider);
 369 }
 370
 371 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
 372         { .compatible = "rockchip,rk3399-emmc-phy" },
 373         {}
 374 };
 375
 376 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
 377
 378 static struct platform_driver rockchip_emmc_driver = {
 379         .probe          = rockchip_emmc_phy_probe,
 380         .driver         = {
 381                 .name   = "rockchip-emmc-phy",
 382                 .of_match_table = rockchip_emmc_phy_dt_ids,
 383         },
 384 };
 385
 386 module_platform_driver(rockchip_emmc_driver);
 387
 388 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
 389 MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
 390 MODULE_LICENSE("GPL v2");