1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19 #include <linux/slab.h>
21 #define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
23 #define OPMODE_MASK GENMASK(4, 3)
24 #define OPMODE_NORMAL (0x00)
25 #define OPMODE_NONDRIVING BIT(3)
26 #define TERMSEL BIT(5)
28 #define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40)
29 #define XCVRSEL BIT(0)
31 #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
34 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
35 #define RETENABLEN BIT(3)
36 #define FSEL_MASK GENMASK(6, 4)
37 #define FSEL_DEFAULT (0x3 << 4)
39 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
40 #define VBUSVLDEXTSEL0 BIT(4)
41 #define PLLBTUNE BIT(5)
43 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
44 #define VREGBYPASS BIT(0)
46 #define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
47 #define VBUSVLDEXT0 BIT(0)
49 #define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
50 #define USB2_AUTO_RESUME BIT(0)
51 #define USB2_SUSPEND_N BIT(2)
52 #define USB2_SUSPEND_N_SEL BIT(3)
54 #define USB2_PHY_USB_PHY_CFG0 (0x94)
55 #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
56 #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
58 #define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
59 #define REFCLK_SEL_MASK GENMASK(1, 0)
60 #define REFCLK_SEL_DEFAULT (0x2 << 0)
62 static const char * const qcom_snps_hsphy_vreg_names[] = {
63 "vdda-pll", "vdda33", "vdda18",
66 #define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names)
69 * struct qcom_snps_hsphy - snps hs phy attributes
71 * @dev: device structure
74 * @base: iomapped memory space for snps hs phy
76 * @num_clks: number of clocks
77 * @clks: array of clocks
78 * @phy_reset: phy reset control
79 * @vregs: regulator supplies bulk data
80 * @phy_initialized: if PHY has been initialized correctly
81 * @mode: contains the current mode the PHY is in
82 * @update_seq_cfg: tuning parameters for phy init
84 struct qcom_snps_hsphy {
91 struct clk_bulk_data *clks;
92 struct reset_control *phy_reset;
93 struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
99 static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy)
101 struct device *dev = hsphy->dev;
104 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL);
109 * TODO: Currently no device tree instantiation of the PHY is using the clock.
110 * This needs to be fixed in order for this code to be able to use devm_clk_bulk_get().
112 hsphy->clks[0].id = "cfg_ahb";
113 hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb");
114 if (IS_ERR(hsphy->clks[0].clk))
115 return dev_err_probe(dev, PTR_ERR(hsphy->clks[0].clk),
116 "failed to get cfg_ahb clk\n");
118 hsphy->clks[1].id = "ref";
119 hsphy->clks[1].clk = devm_clk_get(dev, "ref");
120 if (IS_ERR(hsphy->clks[1].clk))
121 return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk),
122 "failed to get ref clk\n");
127 static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
132 reg = readl_relaxed(base + offset);
135 writel_relaxed(reg, base + offset);
137 /* Ensure above write is completed */
138 readl_relaxed(base + offset);
141 static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy)
143 dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");
145 if (hsphy->mode == PHY_MODE_USB_HOST) {
146 /* Enable auto-resume to meet remote wakeup timing */
147 qcom_snps_hsphy_write_mask(hsphy->base,
148 USB2_PHY_USB_PHY_HS_PHY_CTRL2,
151 usleep_range(500, 1000);
152 qcom_snps_hsphy_write_mask(hsphy->base,
153 USB2_PHY_USB_PHY_HS_PHY_CTRL2,
154 0, USB2_AUTO_RESUME);
160 static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)
162 dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");
167 static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev)
169 struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
171 if (!hsphy->phy_initialized)
174 return qcom_snps_hsphy_suspend(hsphy);
177 static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev)
179 struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
181 if (!hsphy->phy_initialized)
184 return qcom_snps_hsphy_resume(hsphy);
187 static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
190 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
196 static int qcom_snps_hsphy_init(struct phy *phy)
198 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
201 dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);
203 ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
207 ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks);
209 dev_err(&phy->dev, "failed to enable clocks, %d\n", ret);
213 ret = reset_control_assert(hsphy->phy_reset);
215 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
219 usleep_range(100, 150);
221 ret = reset_control_deassert(hsphy->phy_reset);
223 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
227 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
228 UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
229 UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
230 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
232 qcom_snps_hsphy_write_mask(hsphy->base,
233 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
235 qcom_snps_hsphy_write_mask(hsphy->base,
236 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
238 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
239 REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
240 qcom_snps_hsphy_write_mask(hsphy->base,
241 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
242 VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
243 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
244 VBUSVLDEXT0, VBUSVLDEXT0);
246 qcom_snps_hsphy_write_mask(hsphy->base,
247 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
248 VREGBYPASS, VREGBYPASS);
250 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
251 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
252 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
254 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
257 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
260 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
261 USB2_SUSPEND_N_SEL, 0);
263 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
264 UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
266 hsphy->phy_initialized = true;
271 clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks);
273 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
278 static int qcom_snps_hsphy_exit(struct phy *phy)
280 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
282 reset_control_assert(hsphy->phy_reset);
283 clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks);
284 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
285 hsphy->phy_initialized = false;
290 static const struct phy_ops qcom_snps_hsphy_gen_ops = {
291 .init = qcom_snps_hsphy_init,
292 .exit = qcom_snps_hsphy_exit,
293 .set_mode = qcom_snps_hsphy_set_mode,
294 .owner = THIS_MODULE,
297 static const struct of_device_id qcom_snps_hsphy_of_match_table[] = {
298 { .compatible = "qcom,sm8150-usb-hs-phy", },
299 { .compatible = "qcom,usb-snps-hs-7nm-phy", },
300 { .compatible = "qcom,usb-snps-femto-v2-phy", },
303 MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table);
305 static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = {
306 SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend,
307 qcom_snps_hsphy_runtime_resume, NULL)
310 static int qcom_snps_hsphy_probe(struct platform_device *pdev)
312 struct device *dev = &pdev->dev;
313 struct qcom_snps_hsphy *hsphy;
314 struct phy_provider *phy_provider;
315 struct phy *generic_phy;
319 hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);
325 hsphy->base = devm_platform_ioremap_resource(pdev, 0);
326 if (IS_ERR(hsphy->base))
327 return PTR_ERR(hsphy->base);
329 ret = qcom_snps_hsphy_clk_init(hsphy);
331 return dev_err_probe(dev, ret, "failed to initialize clocks\n");
333 hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
334 if (IS_ERR(hsphy->phy_reset)) {
335 dev_err(dev, "failed to get phy core reset\n");
336 return PTR_ERR(hsphy->phy_reset);
339 num = ARRAY_SIZE(hsphy->vregs);
340 for (i = 0; i < num; i++)
341 hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];
343 ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);
345 return dev_err_probe(dev, ret,
346 "failed to get regulator supplies\n");
348 pm_runtime_set_active(dev);
349 pm_runtime_enable(dev);
351 * Prevent runtime pm from being ON by default. Users can enable
352 * it using power/control in sysfs.
354 pm_runtime_forbid(dev);
356 generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops);
357 if (IS_ERR(generic_phy)) {
358 ret = PTR_ERR(generic_phy);
359 dev_err(dev, "failed to create phy, %d\n", ret);
362 hsphy->phy = generic_phy;
364 dev_set_drvdata(dev, hsphy);
365 phy_set_drvdata(generic_phy, hsphy);
367 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
368 if (!IS_ERR(phy_provider))
369 dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");
371 pm_runtime_disable(dev);
373 return PTR_ERR_OR_ZERO(phy_provider);
376 static struct platform_driver qcom_snps_hsphy_driver = {
377 .probe = qcom_snps_hsphy_probe,
379 .name = "qcom-snps-hs-femto-v2-phy",
380 .pm = &qcom_snps_hsphy_pm_ops,
381 .of_match_table = qcom_snps_hsphy_of_match_table,
385 module_platform_driver(qcom_snps_hsphy_driver);
387 MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver");
388 MODULE_LICENSE("GPL v2");