1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
6 #ifndef QCOM_PHY_QMP_H_
7 #define QCOM_PHY_QMP_H_
9 /* Only for QMP V2 PHY - QSERDES COM registers */
10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
20 #define QSERDES_COM_SYS_CLK_CTRL 0x03c
21 #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
22 #define QSERDES_COM_PLL_IVCO 0x048
23 #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
24 #define QSERDES_COM_LOCK_CMP2_MODE0 0x050
25 #define QSERDES_COM_LOCK_CMP3_MODE0 0x054
26 #define QSERDES_COM_LOCK_CMP1_MODE1 0x058
27 #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
28 #define QSERDES_COM_LOCK_CMP3_MODE1 0x060
29 #define QSERDES_COM_BG_TRIM 0x070
30 #define QSERDES_COM_CLK_EP_DIV 0x074
31 #define QSERDES_COM_CP_CTRL_MODE0 0x078
32 #define QSERDES_COM_CP_CTRL_MODE1 0x07c
33 #define QSERDES_COM_PLL_RCTRL_MODE0 0x084
34 #define QSERDES_COM_PLL_RCTRL_MODE1 0x088
35 #define QSERDES_COM_PLL_CCTRL_MODE0 0x090
36 #define QSERDES_COM_PLL_CCTRL_MODE1 0x094
37 #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
38 #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
39 #define QSERDES_COM_RESETSM_CNTRL 0x0b4
40 #define QSERDES_COM_RESTRIM_CTRL 0x0bc
41 #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
42 #define QSERDES_COM_LOCK_CMP_EN 0x0c8
43 #define QSERDES_COM_LOCK_CMP_CFG 0x0cc
44 #define QSERDES_COM_DEC_START_MODE0 0x0d0
45 #define QSERDES_COM_DEC_START_MODE1 0x0d4
46 #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
47 #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
48 #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
49 #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
50 #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
51 #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
52 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
53 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
54 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
55 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
56 #define QSERDES_COM_VCO_TUNE_CTRL 0x124
57 #define QSERDES_COM_VCO_TUNE_MAP 0x128
58 #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
59 #define QSERDES_COM_VCO_TUNE2_MODE0 0x130
60 #define QSERDES_COM_VCO_TUNE1_MODE1 0x134
61 #define QSERDES_COM_VCO_TUNE2_MODE1 0x138
62 #define QSERDES_COM_VCO_TUNE_TIMER1 0x144
63 #define QSERDES_COM_VCO_TUNE_TIMER2 0x148
64 #define QSERDES_COM_BG_CTRL 0x170
65 #define QSERDES_COM_CLK_SELECT 0x174
66 #define QSERDES_COM_HSCLK_SEL 0x178
67 #define QSERDES_COM_CORECLK_DIV 0x184
68 #define QSERDES_COM_CORE_CLK_EN 0x18c
69 #define QSERDES_COM_C_READY_STATUS 0x190
70 #define QSERDES_COM_CMN_CONFIG 0x194
71 #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
72 #define QSERDES_COM_DEBUG_BUS0 0x1a0
73 #define QSERDES_COM_DEBUG_BUS1 0x1a4
74 #define QSERDES_COM_DEBUG_BUS2 0x1a8
75 #define QSERDES_COM_DEBUG_BUS3 0x1ac
76 #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
77 #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
79 /* Only for QMP V2 PHY - TX registers */
80 #define QSERDES_TX_EMP_POST1_LVL 0x018
81 #define QSERDES_TX_SLEW_CNTL 0x040
82 #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
83 #define QSERDES_TX_DEBUG_BUS_SEL 0x064
84 #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
85 #define QSERDES_TX_LANE_MODE 0x094
86 #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
88 /* Only for QMP V2 PHY - RX registers */
89 #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
90 #define QSERDES_RX_UCDR_SO_GAIN 0x01c
91 #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
92 #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
93 #define QSERDES_RX_RX_TERM_BW 0x090
94 #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
95 #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
96 #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
97 #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
98 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
99 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
100 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
101 #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
102 #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
103 #define QSERDES_RX_SIGDET_ENABLES 0x110
104 #define QSERDES_RX_SIGDET_CNTRL 0x114
105 #define QSERDES_RX_SIGDET_LVL 0x118
106 #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
107 #define QSERDES_RX_RX_BAND 0x120
108 #define QSERDES_RX_RX_INTERFACE_MODE 0x12c
110 /* Only for QMP V2 PHY - PCS registers */
111 #define QPHY_POWER_DOWN_CONTROL 0x04
112 #define QPHY_TXDEEMPH_M6DB_V0 0x24
113 #define QPHY_TXDEEMPH_M3P5DB_V0 0x28
114 #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
115 #define QPHY_RX_IDLE_DTCT_CNTRL 0x58
116 #define QPHY_POWER_STATE_CONFIG1 0x60
117 #define QPHY_POWER_STATE_CONFIG2 0x64
118 #define QPHY_POWER_STATE_CONFIG4 0x6c
119 #define QPHY_LOCK_DETECT_CONFIG1 0x80
120 #define QPHY_LOCK_DETECT_CONFIG2 0x84
121 #define QPHY_LOCK_DETECT_CONFIG3 0x88
122 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
123 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
124 #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
125 #define QPHY_OSC_DTCT_ACTIONS 0x1AC
126 #define QPHY_RX_SIGDET_LVL 0x1D8
127 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC
128 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0
130 /* Only for QMP V3 PHY - DP COM registers */
131 #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
132 #define QPHY_V3_DP_COM_SW_RESET 0x04
133 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
134 #define QPHY_V3_DP_COM_SWI_CTRL 0x0c
135 #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
136 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
137 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
139 /* Only for QMP V3 PHY - QSERDES COM registers */
140 #define QSERDES_V3_COM_BG_TIMER 0x00c
141 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
142 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
143 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
144 #define QSERDES_V3_COM_SSC_PER1 0x01c
145 #define QSERDES_V3_COM_SSC_PER2 0x020
146 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
147 #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
148 #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
149 #define QSERDES_V3_COM_CLK_ENABLE1 0x038
150 #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
151 #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
152 #define QSERDES_V3_COM_PLL_IVCO 0x048
153 #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
154 #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
155 #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
156 #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
157 #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
158 #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
159 #define QSERDES_V3_COM_CLK_EP_DIV 0x05c
160 #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
161 #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
162 #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
163 #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
164 #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
165 #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
166 #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
167 #define QSERDES_V3_COM_RESETSM_CNTRL 0x088
168 #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
169 #define QSERDES_V3_COM_LOCK_CMP_EN 0x090
170 #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
171 #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
172 #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
173 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
174 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
175 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
176 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
177 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
178 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
179 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
180 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
181 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
182 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
183 #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
184 #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
185 #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
186 #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
187 #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
188 #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
189 #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
190 #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
191 #define QSERDES_V3_COM_CLK_SELECT 0x138
192 #define QSERDES_V3_COM_HSCLK_SEL 0x13c
193 #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
194 #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
195 #define QSERDES_V3_COM_CORE_CLK_EN 0x154
196 #define QSERDES_V3_COM_C_READY_STATUS 0x158
197 #define QSERDES_V3_COM_CMN_CONFIG 0x15c
198 #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
199 #define QSERDES_V3_COM_DEBUG_BUS0 0x168
200 #define QSERDES_V3_COM_DEBUG_BUS1 0x16c
201 #define QSERDES_V3_COM_DEBUG_BUS2 0x170
202 #define QSERDES_V3_COM_DEBUG_BUS3 0x174
203 #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
205 /* Only for QMP V3 PHY - TX registers */
206 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
207 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
208 #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
209 #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
210 #define QSERDES_V3_TX_LANE_MODE_1 0x08c
211 #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
213 /* Only for QMP V3 PHY - RX registers */
214 #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
215 #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
216 #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
217 #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
218 #define QSERDES_V3_RX_RX_TERM_BW 0x07c
219 #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
220 #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
221 #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
222 #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
223 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
224 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
225 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
226 #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
227 #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
228 #define QSERDES_V3_RX_SIGDET_ENABLES 0x100
229 #define QSERDES_V3_RX_SIGDET_CNTRL 0x104
230 #define QSERDES_V3_RX_SIGDET_LVL 0x108
231 #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
232 #define QSERDES_V3_RX_RX_BAND 0x110
233 #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
234 #define QSERDES_V3_RX_RX_MODE_00 0x164
236 /* Only for QMP V3 PHY - PCS registers */
237 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
238 #define QPHY_V3_PCS_TXMGN_V0 0x00c
239 #define QPHY_V3_PCS_TXMGN_V1 0x010
240 #define QPHY_V3_PCS_TXMGN_V2 0x014
241 #define QPHY_V3_PCS_TXMGN_V3 0x018
242 #define QPHY_V3_PCS_TXMGN_V4 0x01c
243 #define QPHY_V3_PCS_TXMGN_LS 0x020
244 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
245 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
246 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
247 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
248 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
249 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
250 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
251 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
252 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
253 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
254 #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
255 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
256 #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
257 #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
258 #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
259 #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
260 #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
261 #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
262 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
263 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
264 #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
265 #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
266 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
267 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
268 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
269 #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
270 #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
271 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
272 #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
273 #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
274 #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
275 #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
276 #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
277 #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
278 #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
279 #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
280 #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
281 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
282 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
284 /* Only for QMP V3 PHY - PCS_MISC registers */
285 #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c