1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
6 #ifndef QCOM_PHY_QMP_H_
7 #define QCOM_PHY_QMP_H_
9 #include "phy-qcom-qmp-qserdes-com.h"
10 #include "phy-qcom-qmp-qserdes-txrx.h"
12 #include "phy-qcom-qmp-qserdes-com-v3.h"
13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
15 #include "phy-qcom-qmp-qserdes-com-v4.h"
16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
17 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
19 #include "phy-qcom-qmp-qserdes-com-v5.h"
20 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
21 #include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
22 #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
24 #include "phy-qcom-qmp-qserdes-com-v6.h"
25 #include "phy-qcom-qmp-qserdes-txrx-v6.h"
26 #include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
27 #include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
28 #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
30 #include "phy-qcom-qmp-qserdes-com-v7.h"
31 #include "phy-qcom-qmp-qserdes-txrx-v7.h"
33 #include "phy-qcom-qmp-qserdes-pll.h"
35 #include "phy-qcom-qmp-pcs-v2.h"
37 #include "phy-qcom-qmp-pcs-v3.h"
39 #include "phy-qcom-qmp-pcs-v4.h"
41 #include "phy-qcom-qmp-pcs-v4_20.h"
43 #include "phy-qcom-qmp-pcs-v5.h"
45 #include "phy-qcom-qmp-pcs-v5_20.h"
47 #include "phy-qcom-qmp-pcs-v6.h"
49 #include "phy-qcom-qmp-pcs-v6_20.h"
51 #include "phy-qcom-qmp-pcs-v7.h"
53 /* Only for QMP V3 & V4 PHY - DP COM registers */
54 #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
55 #define QPHY_V3_DP_COM_SW_RESET 0x04
56 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
57 #define QPHY_V3_DP_COM_SWI_CTRL 0x0c
58 #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
59 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
60 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
62 /* QSERDES V3 COM bits */
63 # define QSERDES_V3_COM_BIAS_EN 0x0001
64 # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
65 # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
66 # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
67 # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
68 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
69 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
71 /* QSERDES V3 TX bits */
72 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
73 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
74 # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
75 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
77 /* QMP PHY - DP PHY registers */
78 #define QSERDES_DP_PHY_REVISION_ID0 0x000
79 #define QSERDES_DP_PHY_REVISION_ID1 0x004
80 #define QSERDES_DP_PHY_REVISION_ID2 0x008
81 #define QSERDES_DP_PHY_REVISION_ID3 0x00c
82 #define QSERDES_DP_PHY_CFG 0x010
83 #define QSERDES_DP_PHY_PD_CTL 0x018
84 # define DP_PHY_PD_CTL_PWRDN 0x001
85 # define DP_PHY_PD_CTL_PSR_PWRDN 0x002
86 # define DP_PHY_PD_CTL_AUX_PWRDN 0x004
87 # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
88 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
89 # define DP_PHY_PD_CTL_PLL_PWRDN 0x020
90 # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
91 #define QSERDES_DP_PHY_MODE 0x01c
92 #define QSERDES_DP_PHY_AUX_CFG0 0x020
93 #define QSERDES_DP_PHY_AUX_CFG1 0x024
94 #define QSERDES_DP_PHY_AUX_CFG2 0x028
95 #define QSERDES_DP_PHY_AUX_CFG3 0x02c
96 #define QSERDES_DP_PHY_AUX_CFG4 0x030
97 #define QSERDES_DP_PHY_AUX_CFG5 0x034
98 #define QSERDES_DP_PHY_AUX_CFG6 0x038
99 #define QSERDES_DP_PHY_AUX_CFG7 0x03c
100 #define QSERDES_DP_PHY_AUX_CFG8 0x040
101 #define QSERDES_DP_PHY_AUX_CFG9 0x044
103 /* Only for QMP V3 PHY - DP PHY registers */
104 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
105 # define PHY_AUX_STOP_ERR_MASK 0x01
106 # define PHY_AUX_DEC_ERR_MASK 0x02
107 # define PHY_AUX_SYNC_ERR_MASK 0x04
108 # define PHY_AUX_ALIGN_ERR_MASK 0x08
109 # define PHY_AUX_REQ_ERR_MASK 0x10
111 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
112 #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
114 #define QSERDES_V3_DP_PHY_VCO_DIV 0x064
115 #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
116 #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
118 #define QSERDES_V3_DP_PHY_SPARE0 0x0ac
119 #define DP_PHY_SPARE0_MASK 0x0f
120 #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004)
122 #define QSERDES_V3_DP_PHY_STATUS 0x0c0
124 /* Only for QMP V4 PHY - DP PHY registers */
125 #define QSERDES_V4_DP_PHY_CFG_1 0x014
126 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
127 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
128 #define QSERDES_V4_DP_PHY_VCO_DIV 0x070
129 #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078
130 #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c
131 #define QSERDES_V4_DP_PHY_SPARE0 0x0c8
132 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
133 #define QSERDES_V4_DP_PHY_STATUS 0x0dc
135 #define QSERDES_V5_DP_PHY_VCO_DIV 0x070
136 #define QSERDES_V5_DP_PHY_STATUS 0x0dc
138 /* Only for QMP V6 PHY - DP PHY registers */
139 #define QSERDES_V6_DP_PHY_VCO_DIV 0x070
140 #define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
141 #define QSERDES_V6_DP_PHY_STATUS 0x0e4