drivers/phy/qualcomm/phy-qcom-qmp-usbc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/reset.h>
  22 #include <linux/slab.h>
  23 #include <linux/usb/typec.h>
  24 #include <linux/usb/typec_mux.h>
  25
  26 #include "phy-qcom-qmp.h"
  27 #include "phy-qcom-qmp-pcs-misc-v3.h"
  28
  29 /* QPHY_SW_RESET bit */
  30 #define SW_RESET                                BIT(0)
  31 /* QPHY_POWER_DOWN_CONTROL */
  32 #define SW_PWRDN                                BIT(0)
  33 /* QPHY_START_CONTROL bits */
  34 #define SERDES_START                            BIT(0)
  35 #define PCS_START                               BIT(1)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38
  39 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  40 /* DP PHY soft reset */
  41 #define SW_DPPHY_RESET                          BIT(0)
  42 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  43 #define SW_DPPHY_RESET_MUX                      BIT(1)
  44 /* USB3 PHY soft reset */
  45 #define SW_USB3PHY_RESET                        BIT(2)
  46 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  47 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  48
  49 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  50 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  51 #define DP_MODE                                 BIT(1) /* enables DP mode */
  52
  53 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  54 #define ARCVR_DTCT_EN                           BIT(0)
  55 #define ALFPS_DTCT_EN                           BIT(1)
  56 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  57
  58 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  59 #define IRQ_CLEAR                               BIT(0)
  60
  61 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  62
  63 struct qmp_phy_init_tbl {
  64         unsigned int offset;
  65         unsigned int val;
  66         /*
  67          * mask of lanes for which this register is written
  68          * for cases when second lane needs different values
  69          */
  70         u8 lane_mask;
  71 };
  72
  73 #define QMP_PHY_INIT_CFG(o, v)          \
  74         {                               \
  75                 .offset = o,            \
  76                 .val = v,               \
  77                 .lane_mask = 0xff,      \
  78         }
  79
  80 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  81         {                               \
  82                 .offset = o,            \
  83                 .val = v,               \
  84                 .lane_mask = l,         \
  85         }
  86
  87 /* set of registers with offsets different per-PHY */
  88 enum qphy_reg_layout {
  89         /* PCS registers */
  90         QPHY_SW_RESET,
  91         QPHY_START_CTRL,
  92         QPHY_PCS_STATUS,
  93         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
  94         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
  95         QPHY_PCS_POWER_DOWN_CONTROL,
  96         /* Keep last to ensure regs_layout arrays are properly initialized */
  97         QPHY_LAYOUT_SIZE
  98 };
  99
 100 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 101         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
 102         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
 103         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
 104         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
 105         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
 106         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 107 };
 108
 109 static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = {
 110         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
 111         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
 112         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
 113         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
 114         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
 115         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 116 };
 117
 118 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
 119         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 120         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 121         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 122         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
 123         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 124         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 125         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 126         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 127         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 128         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 129         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 130         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 131         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 132         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 133         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 134         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 135         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 136         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 137         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 138         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 139         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 140         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 141         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 142         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 143         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 144         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 145         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 146         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 147         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 148         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
 149         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 150         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 151         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 152         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 153         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 154         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 155         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 156         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 157 };
 158
 159 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
 160         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 161         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 162         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 163         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 164 };
 165
 166 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
 167         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 168         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 169         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 170         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 171         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
 172         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 173         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
 174         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 175         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 176         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 177         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 178         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 179         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 180         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 181         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
 182         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
 183         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 184 };
 185
 186 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
 187         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 188         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 189         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 190         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 191         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 192         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 193         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 194         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 195         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 196         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 197         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 198         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 199         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 200         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 201         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 202         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 203         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 204         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 205         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 206         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 207         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 208         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 209         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
 210         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 211         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 212         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 213         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 214         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 215         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 216         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 217         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 218         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 219         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 220         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 221         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
 222         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 223         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 224         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 225 };
 226
 227 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
 228         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 229         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 230         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 231         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 232         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
 233         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
 234         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 235         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 236         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 237         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 238         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 239         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 240         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 241         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 242         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 243         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 244         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 245         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 246         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 247         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 248         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 249         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 250         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
 251         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 252         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 253         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 254         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 255         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 256         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 257         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 258         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 259         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 260         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 261         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 262         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 263         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 264         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
 265         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
 266 };
 267
 268 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
 269         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 270         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 271         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 272         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 273         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
 274 };
 275
 276 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
 277         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 278         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 279         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 280         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 281         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 282         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 283         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 284         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 285         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 286         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 287         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 288         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 289         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
 290         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 291         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 292         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
 293         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
 294 };
 295
 296 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
 297         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 298         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 299         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 300         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 301         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 302         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 303         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 304         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 305         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 306         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 307         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 308         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 309         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 310         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 311         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 312         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 313         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 314         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 315         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 316         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 317         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 318 };
 319
 320 struct qmp_usbc_offsets {
 321         u16 serdes;
 322         u16 pcs;
 323         u16 pcs_misc;
 324         u16 tx;
 325         u16 rx;
 326         /* for PHYs with >= 2 lanes */
 327         u16 tx2;
 328         u16 rx2;
 329 };
 330
 331 /* struct qmp_phy_cfg - per-PHY initialization config */
 332 struct qmp_phy_cfg {
 333         const struct qmp_usbc_offsets *offsets;
 334
 335         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 336         const struct qmp_phy_init_tbl *serdes_tbl;
 337         int serdes_tbl_num;
 338         const struct qmp_phy_init_tbl *tx_tbl;
 339         int tx_tbl_num;
 340         const struct qmp_phy_init_tbl *rx_tbl;
 341         int rx_tbl_num;
 342         const struct qmp_phy_init_tbl *pcs_tbl;
 343         int pcs_tbl_num;
 344
 345         /* regulators to be requested */
 346         const char * const *vreg_list;
 347         int num_vregs;
 348
 349         /* array of registers with different offsets */
 350         const unsigned int *regs;
 351
 352         /* true, if PHY needs delay after POWER_DOWN */
 353         bool has_pwrdn_delay;
 354 };
 355
 356 struct qmp_usbc {
 357         struct device *dev;
 358
 359         const struct qmp_phy_cfg *cfg;
 360
 361         void __iomem *serdes;
 362         void __iomem *pcs;
 363         void __iomem *pcs_misc;
 364         void __iomem *tx;
 365         void __iomem *rx;
 366         void __iomem *tx2;
 367         void __iomem *rx2;
 368
 369         struct regmap *tcsr_map;
 370         u32 vls_clamp_reg;
 371
 372         struct clk *pipe_clk;
 373         struct clk_bulk_data *clks;
 374         int num_clks;
 375         int num_resets;
 376         struct reset_control_bulk_data *resets;
 377         struct regulator_bulk_data *vregs;
 378
 379         struct mutex phy_mutex;
 380
 381         enum phy_mode mode;
 382         unsigned int usb_init_count;
 383
 384         struct phy *phy;
 385
 386         struct clk_fixed_rate pipe_clk_fixed;
 387
 388         struct typec_switch_dev *sw;
 389         enum typec_orientation orientation;
 390 };
 391
 392 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
 393 {
 394         u32 reg;
 395
 396         reg = readl(base + offset);
 397         reg |= val;
 398         writel(reg, base + offset);
 399
 400         /* ensure that above write is through */
 401         readl(base + offset);
 402 }
 403
 404 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
 405 {
 406         u32 reg;
 407
 408         reg = readl(base + offset);
 409         reg &= ~val;
 410         writel(reg, base + offset);
 411
 412         /* ensure that above write is through */
 413         readl(base + offset);
 414 }
 415
 416 /* list of clocks required by phy */
 417 static const char * const qmp_usbc_phy_clk_l[] = {
 418         "aux", "cfg_ahb", "ref", "com_aux",
 419 };
 420
 421 /* list of resets */
 422 static const char * const usb3phy_legacy_reset_l[] = {
 423         "phy", "common",
 424 };
 425
 426 static const char * const usb3phy_reset_l[] = {
 427         "phy_phy", "phy",
 428 };
 429
 430 /* list of regulators */
 431 static const char * const qmp_phy_vreg_l[] = {
 432         "vdda-phy", "vdda-pll",
 433 };
 434
 435 static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 = {
 436         .serdes         = 0x0,
 437         .pcs            = 0xc00,
 438         .pcs_misc       = 0xa00,
 439         .tx             = 0x200,
 440         .rx             = 0x400,
 441         .tx2            = 0x600,
 442         .rx2            = 0x800,
 443 };
 444
 445 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
 446         .offsets                = &qmp_usbc_offsets_v3_qcm2290,
 447
 448         .serdes_tbl             = msm8998_usb3_serdes_tbl,
 449         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
 450         .tx_tbl                 = msm8998_usb3_tx_tbl,
 451         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
 452         .rx_tbl                 = msm8998_usb3_rx_tbl,
 453         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
 454         .pcs_tbl                = msm8998_usb3_pcs_tbl,
 455         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
 456         .vreg_list              = qmp_phy_vreg_l,
 457         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
 458         .regs                   = qmp_v3_usb3phy_regs_layout,
 459 };
 460
 461 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
 462         .offsets                = &qmp_usbc_offsets_v3_qcm2290,
 463
 464         .serdes_tbl             = qcm2290_usb3_serdes_tbl,
 465         .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
 466         .tx_tbl                 = qcm2290_usb3_tx_tbl,
 467         .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
 468         .rx_tbl                 = qcm2290_usb3_rx_tbl,
 469         .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
 470         .pcs_tbl                = qcm2290_usb3_pcs_tbl,
 471         .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
 472         .vreg_list              = qmp_phy_vreg_l,
 473         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
 474         .regs                   = qmp_v3_usb3phy_regs_layout_qcm2290,
 475 };
 476
 477 static void qmp_usbc_configure_lane(void __iomem *base,
 478                                         const struct qmp_phy_init_tbl tbl[],
 479                                         int num,
 480                                         u8 lane_mask)
 481 {
 482         int i;
 483         const struct qmp_phy_init_tbl *t = tbl;
 484
 485         if (!t)
 486                 return;
 487
 488         for (i = 0; i < num; i++, t++) {
 489                 if (!(t->lane_mask & lane_mask))
 490                         continue;
 491
 492                 writel(t->val, base + t->offset);
 493         }
 494 }
 495
 496 static void qmp_usbc_configure(void __iomem *base,
 497                                    const struct qmp_phy_init_tbl tbl[],
 498                                    int num)
 499 {
 500         qmp_usbc_configure_lane(base, tbl, num, 0xff);
 501 }
 502
 503 static int qmp_usbc_init(struct phy *phy)
 504 {
 505         struct qmp_usbc *qmp = phy_get_drvdata(phy);
 506         const struct qmp_phy_cfg *cfg = qmp->cfg;
 507         void __iomem *pcs = qmp->pcs;
 508         u32 val = 0;
 509         int ret;
 510
 511         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
 512         if (ret) {
 513                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
 514                 return ret;
 515         }
 516
 517         ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
 518         if (ret) {
 519                 dev_err(qmp->dev, "reset assert failed\n");
 520                 goto err_disable_regulators;
 521         }
 522
 523         ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);
 524         if (ret) {
 525                 dev_err(qmp->dev, "reset deassert failed\n");
 526                 goto err_disable_regulators;
 527         }
 528
 529         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
 530         if (ret)
 531                 goto err_assert_reset;
 532
 533         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
 534
 535 #define SW_PORTSELECT_VAL                       BIT(0)
 536 #define SW_PORTSELECT_MUX                       BIT(1)
 537         /* Use software based port select and switch on typec orientation */
 538         val = SW_PORTSELECT_MUX;
 539         if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
 540                 val |= SW_PORTSELECT_VAL;
 541         writel(val, qmp->pcs_misc);
 542
 543         return 0;
 544
 545 err_assert_reset:
 546         reset_control_bulk_assert(qmp->num_resets, qmp->resets);
 547 err_disable_regulators:
 548         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
 549
 550         return ret;
 551 }
 552
 553 static int qmp_usbc_exit(struct phy *phy)
 554 {
 555         struct qmp_usbc *qmp = phy_get_drvdata(phy);
 556         const struct qmp_phy_cfg *cfg = qmp->cfg;
 557
 558         reset_control_bulk_assert(qmp->num_resets, qmp->resets);
 559
 560         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
 561
 562         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
 563
 564         return 0;
 565 }
 566
 567 static int qmp_usbc_power_on(struct phy *phy)
 568 {
 569         struct qmp_usbc *qmp = phy_get_drvdata(phy);
 570         const struct qmp_phy_cfg *cfg = qmp->cfg;
 571         void __iomem *status;
 572         unsigned int val;
 573         int ret;
 574
 575         qmp_usbc_configure(qmp->serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
 576
 577         ret = clk_prepare_enable(qmp->pipe_clk);
 578         if (ret) {
 579                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
 580                 return ret;
 581         }
 582
 583         /* Tx, Rx, and PCS configurations */
 584         qmp_usbc_configure_lane(qmp->tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
 585         qmp_usbc_configure_lane(qmp->rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
 586
 587         qmp_usbc_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
 588         qmp_usbc_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
 589
 590         qmp_usbc_configure(qmp->pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
 591
 592         if (cfg->has_pwrdn_delay)
 593                 usleep_range(10, 20);
 594
 595         /* Pull PHY out of reset state */
 596         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
 597
 598         /* start SerDes and Phy-Coding-Sublayer */
 599         qphy_setbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
 600
 601         status = qmp->pcs + cfg->regs[QPHY_PCS_STATUS];
 602         ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
 603                                  PHY_INIT_COMPLETE_TIMEOUT);
 604         if (ret) {
 605                 dev_err(qmp->dev, "phy initialization timed-out\n");
 606                 goto err_disable_pipe_clk;
 607         }
 608
 609         return 0;
 610
 611 err_disable_pipe_clk:
 612         clk_disable_unprepare(qmp->pipe_clk);
 613
 614         return ret;
 615 }
 616
 617 static int qmp_usbc_power_off(struct phy *phy)
 618 {
 619         struct qmp_usbc *qmp = phy_get_drvdata(phy);
 620         const struct qmp_phy_cfg *cfg = qmp->cfg;
 621
 622         clk_disable_unprepare(qmp->pipe_clk);
 623
 624         /* PHY reset */
 625         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
 626
 627         /* stop SerDes and Phy-Coding-Sublayer */
 628         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
 629                         SERDES_START | PCS_START);
 630
 631         /* Put PHY into POWER DOWN state: active low */
 632         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
 633                         SW_PWRDN);
 634
 635         return 0;
 636 }
 637
 638 static int qmp_usbc_enable(struct phy *phy)
 639 {
 640         struct qmp_usbc *qmp = phy_get_drvdata(phy);
 641         int ret;
 642
 643         mutex_lock(&qmp->phy_mutex);
 644
 645         ret = qmp_usbc_init(phy);
 646         if (ret)
 647                 goto out_unlock;
 648
 649         ret = qmp_usbc_power_on(phy);
 650         if (ret) {
 651                 qmp_usbc_exit(phy);
 652                 goto out_unlock;
 653         }
 654
 655         qmp->usb_init_count++;
 656 out_unlock:
 657         mutex_unlock(&qmp->phy_mutex);
 658
 659         return ret;
 660 }
 661
 662 static int qmp_usbc_disable(struct phy *phy)
 663 {
 664         struct qmp_usbc *qmp = phy_get_drvdata(phy);
 665         int ret;
 666
 667         qmp->usb_init_count--;
 668         ret = qmp_usbc_power_off(phy);
 669         if (ret)
 670                 return ret;
 671         return qmp_usbc_exit(phy);
 672 }
 673
 674 static int qmp_usbc_set_mode(struct phy *phy, enum phy_mode mode, int submode)
 675 {
 676         struct qmp_usbc *qmp = phy_get_drvdata(phy);
 677
 678         qmp->mode = mode;
 679
 680         return 0;
 681 }
 682
 683 static const struct phy_ops qmp_usbc_phy_ops = {
 684         .init           = qmp_usbc_enable,
 685         .exit           = qmp_usbc_disable,
 686         .set_mode       = qmp_usbc_set_mode,
 687         .owner          = THIS_MODULE,
 688 };
 689
 690 static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp)
 691 {
 692         const struct qmp_phy_cfg *cfg = qmp->cfg;
 693         void __iomem *pcs = qmp->pcs;
 694         u32 intr_mask;
 695
 696         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
 697             qmp->mode == PHY_MODE_USB_DEVICE_SS)
 698                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
 699         else
 700                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
 701
 702         /* Clear any pending interrupts status */
 703         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
 704         /* Writing 1 followed by 0 clears the interrupt */
 705         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
 706
 707         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
 708                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
 709
 710         /* Enable required PHY autonomous mode interrupts */
 711         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
 712
 713         /* Enable i/o clamp_n for autonomous mode */
 714         if (qmp->tcsr_map && qmp->vls_clamp_reg)
 715                 regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 1);
 716 }
 717
 718 static void qmp_usbc_disable_autonomous_mode(struct qmp_usbc *qmp)
 719 {
 720         const struct qmp_phy_cfg *cfg = qmp->cfg;
 721         void __iomem *pcs = qmp->pcs;
 722
 723         /* Disable i/o clamp_n on resume for normal mode */
 724         if (qmp->tcsr_map && qmp->vls_clamp_reg)
 725                 regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 0);
 726
 727         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
 728                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
 729
 730         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
 731         /* Writing 1 followed by 0 clears the interrupt */
 732         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
 733 }
 734
 735 static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev)
 736 {
 737         struct qmp_usbc *qmp = dev_get_drvdata(dev);
 738
 739         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
 740
 741         if (!qmp->phy->init_count) {
 742                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 743                 return 0;
 744         }
 745
 746         qmp_usbc_enable_autonomous_mode(qmp);
 747
 748         clk_disable_unprepare(qmp->pipe_clk);
 749         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
 750
 751         return 0;
 752 }
 753
 754 static int __maybe_unused qmp_usbc_runtime_resume(struct device *dev)
 755 {
 756         struct qmp_usbc *qmp = dev_get_drvdata(dev);
 757         int ret = 0;
 758
 759         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
 760
 761         if (!qmp->phy->init_count) {
 762                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 763                 return 0;
 764         }
 765
 766         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
 767         if (ret)
 768                 return ret;
 769
 770         ret = clk_prepare_enable(qmp->pipe_clk);
 771         if (ret) {
 772                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
 773                 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
 774                 return ret;
 775         }
 776
 777         qmp_usbc_disable_autonomous_mode(qmp);
 778
 779         return 0;
 780 }
 781
 782 static const struct dev_pm_ops qmp_usbc_pm_ops = {
 783         SET_RUNTIME_PM_OPS(qmp_usbc_runtime_suspend,
 784                            qmp_usbc_runtime_resume, NULL)
 785 };
 786
 787 static int qmp_usbc_vreg_init(struct qmp_usbc *qmp)
 788 {
 789         const struct qmp_phy_cfg *cfg = qmp->cfg;
 790         struct device *dev = qmp->dev;
 791         int num = cfg->num_vregs;
 792         int i;
 793
 794         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
 795         if (!qmp->vregs)
 796                 return -ENOMEM;
 797
 798         for (i = 0; i < num; i++)
 799                 qmp->vregs[i].supply = cfg->vreg_list[i];
 800
 801         return devm_regulator_bulk_get(dev, num, qmp->vregs);
 802 }
 803
 804 static int qmp_usbc_reset_init(struct qmp_usbc *qmp,
 805                               const char *const *reset_list,
 806                               int num_resets)
 807 {
 808         struct device *dev = qmp->dev;
 809         int i;
 810         int ret;
 811
 812         qmp->resets = devm_kcalloc(dev, num_resets,
 813                                    sizeof(*qmp->resets), GFP_KERNEL);
 814         if (!qmp->resets)
 815                 return -ENOMEM;
 816
 817         for (i = 0; i < num_resets; i++)
 818                 qmp->resets[i].id = reset_list[i];
 819
 820         qmp->num_resets = num_resets;
 821
 822         ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);
 823         if (ret)
 824                 return dev_err_probe(dev, ret, "failed to get resets\n");
 825
 826         return 0;
 827 }
 828
 829 static int qmp_usbc_clk_init(struct qmp_usbc *qmp)
 830 {
 831         struct device *dev = qmp->dev;
 832         int num = ARRAY_SIZE(qmp_usbc_phy_clk_l);
 833         int i;
 834
 835         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
 836         if (!qmp->clks)
 837                 return -ENOMEM;
 838
 839         for (i = 0; i < num; i++)
 840                 qmp->clks[i].id = qmp_usbc_phy_clk_l[i];
 841
 842         qmp->num_clks = num;
 843
 844         return devm_clk_bulk_get_optional(dev, num, qmp->clks);
 845 }
 846
 847 static void phy_clk_release_provider(void *res)
 848 {
 849         of_clk_del_provider(res);
 850 }
 851
 852 /*
 853  * Register a fixed rate pipe clock.
 854  *
 855  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
 856  * controls it. The <s>_pipe_clk coming out of the GCC is requested
 857  * by the PHY driver for its operations.
 858  * We register the <s>_pipe_clksrc here. The gcc driver takes care
 859  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
 860  * Below picture shows this relationship.
 861  *
 862  *         +---------------+
 863  *         |   PHY block   |<<---------------------------------------+
 864  *         |               |                                         |
 865  *         |   +-------+   |                   +-----+               |
 866  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
 867  *    clk  |   +-------+   |                   +-----+
 868  *         +---------------+
 869  */
 870 static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node *np)
 871 {
 872         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
 873         struct clk_init_data init = { };
 874         int ret;
 875
 876         ret = of_property_read_string(np, "clock-output-names", &init.name);
 877         if (ret) {
 878                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
 879                 return ret;
 880         }
 881
 882         init.ops = &clk_fixed_rate_ops;
 883
 884         /* controllers using QMP phys use 125MHz pipe clock interface */
 885         fixed->fixed_rate = 125000000;
 886         fixed->hw.init = &init;
 887
 888         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
 889         if (ret)
 890                 return ret;
 891
 892         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
 893         if (ret)
 894                 return ret;
 895
 896         /*
 897          * Roll a devm action because the clock provider is the child node, but
 898          * the child node is not actually a device.
 899          */
 900         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
 901 }
 902
 903 #if IS_ENABLED(CONFIG_TYPEC)
 904 static int qmp_usbc_typec_switch_set(struct typec_switch_dev *sw,
 905                                       enum typec_orientation orientation)
 906 {
 907         struct qmp_usbc *qmp = typec_switch_get_drvdata(sw);
 908
 909         if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
 910                 return 0;
 911
 912         mutex_lock(&qmp->phy_mutex);
 913         qmp->orientation = orientation;
 914
 915         if (qmp->usb_init_count) {
 916                 qmp_usbc_power_off(qmp->phy);
 917                 qmp_usbc_exit(qmp->phy);
 918
 919                 qmp_usbc_init(qmp->phy);
 920                 qmp_usbc_power_on(qmp->phy);
 921         }
 922
 923         mutex_unlock(&qmp->phy_mutex);
 924
 925         return 0;
 926 }
 927
 928 static void qmp_usbc_typec_unregister(void *data)
 929 {
 930         struct qmp_usbc *qmp = data;
 931
 932         typec_switch_unregister(qmp->sw);
 933 }
 934
 935 static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp)
 936 {
 937         struct typec_switch_desc sw_desc = {};
 938         struct device *dev = qmp->dev;
 939
 940         sw_desc.drvdata = qmp;
 941         sw_desc.fwnode = dev->fwnode;
 942         sw_desc.set = qmp_usbc_typec_switch_set;
 943         qmp->sw = typec_switch_register(dev, &sw_desc);
 944         if (IS_ERR(qmp->sw)) {
 945                 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
 946                 return PTR_ERR(qmp->sw);
 947         }
 948
 949         return devm_add_action_or_reset(dev, qmp_usbc_typec_unregister, qmp);
 950 }
 951 #else
 952 static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp)
 953 {
 954         return 0;
 955 }
 956 #endif
 957
 958 static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_node *np)
 959 {
 960         struct platform_device *pdev = to_platform_device(qmp->dev);
 961         struct device *dev = qmp->dev;
 962         int ret;
 963
 964         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
 965         if (IS_ERR(qmp->serdes))
 966                 return PTR_ERR(qmp->serdes);
 967
 968         /*
 969          * Get memory resources for the PHY:
 970          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
 971          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
 972          * For single lane PHYs: pcs_misc (optional) -> 3.
 973          */
 974         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
 975         if (IS_ERR(qmp->tx))
 976                 return PTR_ERR(qmp->tx);
 977
 978         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
 979         if (IS_ERR(qmp->rx))
 980                 return PTR_ERR(qmp->rx);
 981
 982         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
 983         if (IS_ERR(qmp->pcs))
 984                 return PTR_ERR(qmp->pcs);
 985
 986         qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
 987         if (IS_ERR(qmp->tx2))
 988                 return PTR_ERR(qmp->tx2);
 989
 990         qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
 991         if (IS_ERR(qmp->rx2))
 992                 return PTR_ERR(qmp->rx2);
 993
 994         qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
 995         if (IS_ERR(qmp->pcs_misc)) {
 996                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
 997                 qmp->pcs_misc = NULL;
 998         }
 999
1000         qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
1001         if (IS_ERR(qmp->pipe_clk)) {
1002                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
1003                                      "failed to get pipe clock\n");
1004         }
1005
1006         ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
1007         if (ret < 0)
1008                 return ret;
1009
1010         qmp->num_clks = ret;
1011
1012         ret = qmp_usbc_reset_init(qmp, usb3phy_legacy_reset_l,
1013                                  ARRAY_SIZE(usb3phy_legacy_reset_l));
1014         if (ret)
1015                 return ret;
1016
1017         return 0;
1018 }
1019
1020 static int qmp_usbc_parse_dt(struct qmp_usbc *qmp)
1021 {
1022         struct platform_device *pdev = to_platform_device(qmp->dev);
1023         const struct qmp_phy_cfg *cfg = qmp->cfg;
1024         const struct qmp_usbc_offsets *offs = cfg->offsets;
1025         struct device *dev = qmp->dev;
1026         void __iomem *base;
1027         int ret;
1028
1029         if (!offs)
1030                 return -EINVAL;
1031
1032         base = devm_platform_ioremap_resource(pdev, 0);
1033         if (IS_ERR(base))
1034                 return PTR_ERR(base);
1035
1036         qmp->serdes = base + offs->serdes;
1037         qmp->pcs = base + offs->pcs;
1038         if (offs->pcs_misc)
1039                 qmp->pcs_misc = base + offs->pcs_misc;
1040         qmp->tx = base + offs->tx;
1041         qmp->rx = base + offs->rx;
1042
1043         qmp->tx2 = base + offs->tx2;
1044         qmp->rx2 = base + offs->rx2;
1045
1046         ret = qmp_usbc_clk_init(qmp);
1047         if (ret)
1048                 return ret;
1049
1050         qmp->pipe_clk = devm_clk_get(dev, "pipe");
1051         if (IS_ERR(qmp->pipe_clk)) {
1052                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
1053                                      "failed to get pipe clock\n");
1054         }
1055
1056         ret = qmp_usbc_reset_init(qmp, usb3phy_reset_l,
1057                                  ARRAY_SIZE(usb3phy_reset_l));
1058         if (ret)
1059                 return ret;
1060
1061         return 0;
1062 }
1063
1064 static int qmp_usbc_parse_vls_clamp(struct qmp_usbc *qmp)
1065 {
1066         struct of_phandle_args tcsr_args;
1067         struct device *dev = qmp->dev;
1068         int ret;
1069
1070         /*  for backwards compatibility ignore if there is no property */
1071         ret = of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1, 0,
1072                                                &tcsr_args);
1073         if (ret == -ENOENT)
1074                 return 0;
1075         else if (ret < 0)
1076                 return dev_err_probe(dev, ret, "Failed to parse qcom,tcsr-reg\n");
1077
1078         qmp->tcsr_map = syscon_node_to_regmap(tcsr_args.np);
1079         of_node_put(tcsr_args.np);
1080         if (IS_ERR(qmp->tcsr_map))
1081                 return PTR_ERR(qmp->tcsr_map);
1082
1083         qmp->vls_clamp_reg = tcsr_args.args[0];
1084
1085         return 0;
1086 }
1087
1088 static int qmp_usbc_probe(struct platform_device *pdev)
1089 {
1090         struct device *dev = &pdev->dev;
1091         struct phy_provider *phy_provider;
1092         struct device_node *np;
1093         struct qmp_usbc *qmp;
1094         int ret;
1095
1096         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1097         if (!qmp)
1098                 return -ENOMEM;
1099
1100         qmp->dev = dev;
1101
1102         qmp->orientation = TYPEC_ORIENTATION_NORMAL;
1103
1104         qmp->cfg = of_device_get_match_data(dev);
1105         if (!qmp->cfg)
1106                 return -EINVAL;
1107
1108         mutex_init(&qmp->phy_mutex);
1109
1110         ret = qmp_usbc_vreg_init(qmp);
1111         if (ret)
1112                 return ret;
1113
1114         ret = qmp_usbc_typec_switch_register(qmp);
1115         if (ret)
1116                 return ret;
1117
1118         ret = qmp_usbc_parse_vls_clamp(qmp);
1119         if (ret)
1120                 return ret;
1121
1122         /* Check for legacy binding with child node. */
1123         np = of_get_child_by_name(dev->of_node, "phy");
1124         if (np) {
1125                 ret = qmp_usbc_parse_dt_legacy(qmp, np);
1126         } else {
1127                 np = of_node_get(dev->of_node);
1128                 ret = qmp_usbc_parse_dt(qmp);
1129         }
1130         if (ret)
1131                 goto err_node_put;
1132
1133         pm_runtime_set_active(dev);
1134         ret = devm_pm_runtime_enable(dev);
1135         if (ret)
1136                 goto err_node_put;
1137         /*
1138          * Prevent runtime pm from being ON by default. Users can enable
1139          * it using power/control in sysfs.
1140          */
1141         pm_runtime_forbid(dev);
1142
1143         ret = phy_pipe_clk_register(qmp, np);
1144         if (ret)
1145                 goto err_node_put;
1146
1147         qmp->phy = devm_phy_create(dev, np, &qmp_usbc_phy_ops);
1148         if (IS_ERR(qmp->phy)) {
1149                 ret = PTR_ERR(qmp->phy);
1150                 dev_err(dev, "failed to create PHY: %d\n", ret);
1151                 goto err_node_put;
1152         }
1153
1154         phy_set_drvdata(qmp->phy, qmp);
1155
1156         of_node_put(np);
1157
1158         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1159
1160         return PTR_ERR_OR_ZERO(phy_provider);
1161
1162 err_node_put:
1163         of_node_put(np);
1164         return ret;
1165 }
1166
1167 static const struct of_device_id qmp_usbc_of_match_table[] = {
1168         {
1169                 .compatible = "qcom,msm8998-qmp-usb3-phy",
1170                 .data = &msm8998_usb3phy_cfg,
1171         }, {
1172                 .compatible = "qcom,qcm2290-qmp-usb3-phy",
1173                 .data = &qcm2290_usb3phy_cfg,
1174         }, {
1175                 .compatible = "qcom,sm6115-qmp-usb3-phy",
1176                 .data = &qcm2290_usb3phy_cfg,
1177         },
1178         { },
1179 };
1180 MODULE_DEVICE_TABLE(of, qmp_usbc_of_match_table);
1181
1182 static struct platform_driver qmp_usbc_driver = {
1183         .probe          = qmp_usbc_probe,
1184         .driver = {
1185                 .name   = "qcom-qmp-usbc-phy",
1186                 .pm     = &qmp_usbc_pm_ops,
1187                 .of_match_table = qmp_usbc_of_match_table,
1188         },
1189 };
1190
1191 module_platform_driver(qmp_usbc_driver);
1192
1193 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1194 MODULE_DESCRIPTION("Qualcomm QMP USB-C PHY driver");
1195 MODULE_LICENSE("GPL");