1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
22 #include "phy-qcom-qmp.h"
23 #include "phy-qcom-qmp-pcs-misc-v3.h"
24 #include "phy-qcom-qmp-pcs-misc-v4.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
27 #include "phy-qcom-qmp-pcs-usb-v6.h"
28 #include "phy-qcom-qmp-pcs-usb-v7.h"
30 /* QPHY_SW_RESET bit */
31 #define SW_RESET BIT(0)
32 /* QPHY_POWER_DOWN_CONTROL */
33 #define SW_PWRDN BIT(0)
34 /* QPHY_START_CONTROL bits */
35 #define SERDES_START BIT(0)
36 #define PCS_START BIT(1)
37 /* QPHY_PCS_STATUS bit */
38 #define PHYSTATUS BIT(6)
40 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
41 /* DP PHY soft reset */
42 #define SW_DPPHY_RESET BIT(0)
43 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
44 #define SW_DPPHY_RESET_MUX BIT(1)
45 /* USB3 PHY soft reset */
46 #define SW_USB3PHY_RESET BIT(2)
47 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
48 #define SW_USB3PHY_RESET_MUX BIT(3)
50 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
51 #define USB3_MODE BIT(0) /* enables USB3 mode */
52 #define DP_MODE BIT(1) /* enables DP mode */
54 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
55 #define ARCVR_DTCT_EN BIT(0)
56 #define ALFPS_DTCT_EN BIT(1)
57 #define ARCVR_DTCT_EVENT_SEL BIT(4)
59 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
60 #define IRQ_CLEAR BIT(0)
62 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
63 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */
65 #define PHY_INIT_COMPLETE_TIMEOUT 10000
67 struct qmp_phy_init_tbl {
71 * mask of lanes for which this register is written
72 * for cases when second lane needs different values
77 #define QMP_PHY_INIT_CFG(o, v) \
84 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \
91 /* set of registers with offsets different per-PHY */
92 enum qphy_reg_layout {
97 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
98 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
99 QPHY_PCS_POWER_DOWN_CONTROL,
100 QPHY_PCS_MISC_CLAMP_ENABLE,
101 /* Keep last to ensure regs_layout arrays are properly initialized */
105 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
106 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
107 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
108 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS,
109 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
110 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
111 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
114 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
115 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
116 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
117 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
118 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
119 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
120 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
121 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE,
124 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
125 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
126 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
127 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
128 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
131 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
132 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
133 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE,
136 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
137 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
138 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
139 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
140 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
143 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
144 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
147 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
148 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
149 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
150 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
151 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
154 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
155 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
158 static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
159 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET,
160 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL,
161 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1,
162 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL,
165 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL,
166 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
169 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
170 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
171 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
172 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
173 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
174 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
175 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
176 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
177 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
178 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
179 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
180 /* PLL and Loop filter settings */
181 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
182 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
183 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
184 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
185 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
186 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
187 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
188 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
189 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
190 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
191 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
192 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
193 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
194 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
195 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
197 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
198 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
199 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
200 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
201 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
202 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
203 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
206 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
207 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
208 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
209 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
212 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
213 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
214 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
215 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
216 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
217 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
218 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
219 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
220 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
221 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
222 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
225 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
226 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
227 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
228 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
229 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
230 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
231 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
232 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
233 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
234 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
235 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
236 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
237 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
238 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
239 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
240 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
241 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
242 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
243 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
244 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
245 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
246 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
247 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
248 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
251 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
252 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
253 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
254 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
255 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
256 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
257 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
258 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
259 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
260 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
261 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
262 /* PLL and Loop filter settings */
263 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
264 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
265 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
266 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
267 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
268 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
269 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
270 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
271 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
272 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
273 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
274 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
275 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
276 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
277 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
279 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
280 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
281 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
282 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
283 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
284 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
285 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
288 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
289 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
290 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
291 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
292 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
293 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
294 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
295 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
296 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
297 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
300 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
326 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
327 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
328 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
329 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
330 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
331 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
332 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
333 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
334 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
335 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
336 /* PLL and Loop filter settings */
337 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
338 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
339 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
340 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
341 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
342 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
343 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
344 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
345 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
346 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
347 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
348 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
349 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
350 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
351 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
352 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
354 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
355 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
356 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
357 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
358 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
359 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
360 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
363 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
364 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
365 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
366 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
369 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
370 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
371 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
372 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
373 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
374 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
375 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
376 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
377 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
378 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
379 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
382 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
384 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
385 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
386 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
387 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
388 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
390 /* Lock Det settings */
391 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
392 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
393 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
394 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
397 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
436 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
437 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
438 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
439 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
440 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
441 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
444 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
447 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
448 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
449 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
450 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
451 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
452 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
453 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
454 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
455 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
458 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
466 /* Lock Det settings */
467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
500 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
508 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
515 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
516 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
517 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
518 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
519 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
520 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
521 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
522 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
523 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
539 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
540 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
544 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
548 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
551 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
552 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
553 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
554 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
555 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
558 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
561 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
562 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
563 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
564 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
565 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
566 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
567 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
597 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
598 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
599 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
600 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
601 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
602 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
603 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
604 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
605 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
606 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
607 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
608 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
609 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
610 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
611 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
614 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
615 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
616 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
619 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
620 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
621 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
622 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
623 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
624 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
625 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
628 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
633 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
634 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
638 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
639 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
640 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
667 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
668 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
669 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
670 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
671 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
672 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
673 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
674 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
675 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
676 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
677 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
678 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
679 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
684 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
689 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
690 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
691 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
692 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
693 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
694 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
697 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
713 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
714 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
715 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
716 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
717 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
718 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
719 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
720 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
721 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
722 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
723 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
724 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
725 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
726 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
727 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
728 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
733 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
736 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
737 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
738 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
739 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
740 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
741 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
742 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
743 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
746 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
747 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
748 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
749 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
750 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
751 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
752 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
753 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
754 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
755 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
756 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
757 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
758 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
759 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
760 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
761 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
762 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
763 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
764 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
765 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
766 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
767 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
768 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
769 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
770 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
771 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
772 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
773 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
774 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
775 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
776 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
777 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
780 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = {
781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e),
782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),
783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
786 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
787 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e),
788 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82),
789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea),
792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
793 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
794 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
795 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
796 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7),
797 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
798 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7),
799 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
800 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e),
801 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),
802 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
803 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
804 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
805 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12),
806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34),
807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),
810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),
811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
829 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = {
830 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
831 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
832 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
833 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
834 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
835 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
836 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
837 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
838 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
839 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21),
842 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = {
843 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
844 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
845 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
846 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
847 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
848 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
849 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
850 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
851 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
852 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
853 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
854 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
855 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
856 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
857 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
858 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
859 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
860 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
861 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
862 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
863 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
864 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
865 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
866 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
867 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
868 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff),
869 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf),
870 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed),
871 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
872 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
873 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
874 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
875 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
876 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
877 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
878 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
879 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
880 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
881 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
884 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = {
885 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
886 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
887 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
888 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
889 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
890 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa),
891 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
892 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
893 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
894 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
895 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
896 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
897 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
898 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
901 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = {
902 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
903 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
904 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
905 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
908 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
909 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
910 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
911 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
912 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
913 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
914 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
915 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
918 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
919 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
920 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
921 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
922 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
923 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
924 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
925 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
926 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
927 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
928 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
929 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
930 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
931 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
932 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
933 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
934 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
935 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
936 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
937 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
938 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
939 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
940 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
941 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
942 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
943 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
944 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
945 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
946 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
947 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
948 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
949 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
952 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
953 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
954 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
956 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
957 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
958 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
959 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
960 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
962 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
963 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
964 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
965 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
966 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
969 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
970 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
971 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
974 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
975 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
976 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
977 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
978 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
979 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
980 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
981 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
982 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
983 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
984 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
985 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
986 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
987 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
988 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
989 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
990 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
991 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
992 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
993 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
994 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
995 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
996 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
997 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
998 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
999 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1000 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1001 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1002 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1003 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1004 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1005 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1006 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1007 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1008 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1009 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1010 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1011 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1012 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1013 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1016 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1017 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1018 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1019 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1020 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1021 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1022 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1023 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1026 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1027 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1028 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1029 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1030 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1031 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1032 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1033 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1034 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1035 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1036 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1060 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1061 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1062 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1063 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1064 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1065 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1066 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1067 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1068 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1069 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1070 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1071 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1072 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1073 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1074 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1077 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = {
1078 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1079 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1082 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {
1083 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1084 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),
1085 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1086 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1087 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1088 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1089 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1090 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1091 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1092 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1093 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1094 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1095 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1096 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1099 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = {
1100 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1101 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1102 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
1105 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = {
1106 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
1107 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1108 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),
1109 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),
1110 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),
1111 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),
1112 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16),
1113 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41),
1114 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41),
1115 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),
1116 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75),
1117 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),
1118 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),
1119 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25),
1120 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02),
1121 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
1122 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
1123 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
1124 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
1125 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
1126 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1127 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),
1128 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),
1129 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),
1130 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08),
1131 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a),
1132 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),
1133 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55),
1134 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75),
1135 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),
1136 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25),
1137 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02),
1138 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),
1139 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01),
1140 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),
1141 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),
1142 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a),
1143 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a),
1144 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14),
1145 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04),
1146 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20),
1147 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),
1148 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
1149 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
1150 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
1151 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c),
1154 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = {
1155 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00),
1156 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00),
1157 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1158 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1159 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5),
1160 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f),
1161 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f),
1162 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f),
1163 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12),
1164 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21),
1167 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = {
1168 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a),
1169 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06),
1170 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1171 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1172 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1173 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1174 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99),
1175 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),
1176 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),
1177 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00),
1178 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a),
1179 QMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1180 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54),
1181 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f),
1182 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13),
1183 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1184 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1185 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1186 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1187 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1188 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1189 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04),
1190 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1191 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f),
1192 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf),
1193 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff),
1194 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf),
1195 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed),
1196 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc),
1197 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c),
1198 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c),
1199 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d),
1200 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09),
1201 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04),
1202 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1203 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c),
1204 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10),
1205 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14),
1206 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),
1209 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = {
1210 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1211 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89),
1212 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20),
1213 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13),
1214 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21),
1215 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa),
1216 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1217 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1218 QMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a),
1219 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1220 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1221 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c),
1222 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b),
1223 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10),
1226 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = {
1227 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1228 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1229 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1230 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
1233 struct qmp_usb_offsets {
1240 /* for PHYs with >= 2 lanes */
1245 /* struct qmp_phy_cfg - per-PHY initialization config */
1246 struct qmp_phy_cfg {
1249 const struct qmp_usb_offsets *offsets;
1251 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1252 const struct qmp_phy_init_tbl *serdes_tbl;
1254 const struct qmp_phy_init_tbl *tx_tbl;
1256 const struct qmp_phy_init_tbl *rx_tbl;
1258 const struct qmp_phy_init_tbl *pcs_tbl;
1260 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1261 int pcs_usb_tbl_num;
1263 /* regulators to be requested */
1264 const char * const *vreg_list;
1267 /* array of registers with different offsets */
1268 const unsigned int *regs;
1270 /* true, if PHY needs delay after POWER_DOWN */
1271 bool has_pwrdn_delay;
1273 /* Offset from PCS to PCS_USB region */
1274 unsigned int pcs_usb_offset;
1280 const struct qmp_phy_cfg *cfg;
1282 void __iomem *serdes;
1284 void __iomem *pcs_misc;
1285 void __iomem *pcs_usb;
1291 struct clk *pipe_clk;
1292 struct clk_bulk_data *clks;
1295 struct reset_control_bulk_data *resets;
1296 struct regulator_bulk_data *vregs;
1302 struct clk_fixed_rate pipe_clk_fixed;
1305 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1309 reg = readl(base + offset);
1311 writel(reg, base + offset);
1313 /* ensure that above write is through */
1314 readl(base + offset);
1317 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1321 reg = readl(base + offset);
1323 writel(reg, base + offset);
1325 /* ensure that above write is through */
1326 readl(base + offset);
1329 /* list of clocks required by phy */
1330 static const char * const qmp_usb_phy_clk_l[] = {
1331 "aux", "cfg_ahb", "ref", "com_aux",
1334 /* list of resets */
1335 static const char * const usb3phy_legacy_reset_l[] = {
1339 static const char * const usb3phy_reset_l[] = {
1343 /* list of regulators */
1344 static const char * const qmp_phy_vreg_l[] = {
1345 "vdda-phy", "vdda-pll",
1348 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
1356 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
1364 static const struct qmp_usb_offsets qmp_usb_offsets_v3_msm8996 = {
1371 static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {
1379 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1387 static const struct qmp_usb_offsets qmp_usb_offsets_v6 = {
1395 static const struct qmp_usb_offsets qmp_usb_offsets_v7 = {
1403 static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
1406 .offsets = &qmp_usb_offsets_v3,
1408 .serdes_tbl = ipq9574_usb3_serdes_tbl,
1409 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1410 .tx_tbl = msm8996_usb3_tx_tbl,
1411 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1412 .rx_tbl = ipq8074_usb3_rx_tbl,
1413 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1414 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1415 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1416 .vreg_list = qmp_phy_vreg_l,
1417 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1418 .regs = qmp_v3_usb3phy_regs_layout,
1421 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1424 .offsets = &qmp_usb_offsets_v3,
1426 .serdes_tbl = ipq8074_usb3_serdes_tbl,
1427 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1428 .tx_tbl = msm8996_usb3_tx_tbl,
1429 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1430 .rx_tbl = ipq8074_usb3_rx_tbl,
1431 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1432 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1433 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1434 .vreg_list = qmp_phy_vreg_l,
1435 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1436 .regs = qmp_v3_usb3phy_regs_layout,
1439 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1442 .offsets = &qmp_usb_offsets_ipq9574,
1444 .serdes_tbl = ipq9574_usb3_serdes_tbl,
1445 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1446 .tx_tbl = ipq9574_usb3_tx_tbl,
1447 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
1448 .rx_tbl = ipq9574_usb3_rx_tbl,
1449 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
1450 .pcs_tbl = ipq9574_usb3_pcs_tbl,
1451 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
1452 .vreg_list = qmp_phy_vreg_l,
1453 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1454 .regs = qmp_v3_usb3phy_regs_layout,
1457 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1460 .offsets = &qmp_usb_offsets_v3_msm8996,
1462 .serdes_tbl = msm8996_usb3_serdes_tbl,
1463 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1464 .tx_tbl = msm8996_usb3_tx_tbl,
1465 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1466 .rx_tbl = msm8996_usb3_rx_tbl,
1467 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1468 .pcs_tbl = msm8996_usb3_pcs_tbl,
1469 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1470 .vreg_list = qmp_phy_vreg_l,
1471 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1472 .regs = qmp_v2_usb3phy_regs_layout,
1475 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1478 .offsets = &qmp_usb_offsets_v5,
1480 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1481 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1482 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1483 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1484 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1485 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1486 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl,
1487 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
1488 .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl,
1489 .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),
1490 .vreg_list = qmp_phy_vreg_l,
1491 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1492 .regs = qmp_v5_usb3phy_regs_layout,
1495 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1498 .offsets = &qmp_usb_offsets_v5,
1500 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1501 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1502 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1503 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1504 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1505 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1506 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,
1507 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1508 .pcs_usb_tbl = sc8280xp_usb3_uniphy_pcs_usb_tbl,
1509 .pcs_usb_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl),
1510 .vreg_list = qmp_phy_vreg_l,
1511 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1512 .regs = qmp_v5_usb3phy_regs_layout,
1515 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1518 .offsets = &qmp_usb_offsets_v3,
1520 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1521 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1522 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1523 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1524 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1525 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1526 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1527 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1528 .vreg_list = qmp_phy_vreg_l,
1529 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1530 .regs = qmp_v3_usb3phy_regs_layout,
1532 .has_pwrdn_delay = true,
1535 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1538 .offsets = &qmp_usb_offsets_v4,
1540 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1541 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1542 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
1543 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1544 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
1545 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1546 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
1547 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1548 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
1549 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1550 .vreg_list = qmp_phy_vreg_l,
1551 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1552 .regs = qmp_v4_usb3phy_regs_layout,
1553 .pcs_usb_offset = 0x600,
1555 .has_pwrdn_delay = true,
1558 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1561 .offsets = &qmp_usb_offsets_v4,
1563 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1564 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1565 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
1566 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1567 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
1568 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1569 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1570 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1571 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1572 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1573 .vreg_list = qmp_phy_vreg_l,
1574 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1575 .regs = qmp_v4_usb3phy_regs_layout,
1576 .pcs_usb_offset = 0x600,
1578 .has_pwrdn_delay = true,
1581 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1584 .offsets = &qmp_usb_offsets_v4,
1586 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1587 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1588 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
1589 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1590 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
1591 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1592 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1593 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1594 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1595 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1596 .vreg_list = qmp_phy_vreg_l,
1597 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1598 .regs = qmp_v4_usb3phy_regs_layout,
1599 .pcs_usb_offset = 0x600,
1601 .has_pwrdn_delay = true,
1604 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1607 .offsets = &qmp_usb_offsets_v5,
1609 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1610 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1611 .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
1612 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1613 .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
1614 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1615 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1616 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1617 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1618 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1619 .vreg_list = qmp_phy_vreg_l,
1620 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1621 .regs = qmp_v5_usb3phy_regs_layout,
1622 .pcs_usb_offset = 0x1000,
1624 .has_pwrdn_delay = true,
1627 static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = {
1629 .offsets = &qmp_usb_offsets_v6,
1631 .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl,
1632 .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl),
1633 .tx_tbl = sdx75_usb3_uniphy_tx_tbl,
1634 .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl),
1635 .rx_tbl = sdx75_usb3_uniphy_rx_tbl,
1636 .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl),
1637 .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl,
1638 .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl),
1639 .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl,
1640 .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl),
1641 .vreg_list = qmp_phy_vreg_l,
1642 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1643 .regs = qmp_v6_usb3phy_regs_layout,
1644 .pcs_usb_offset = 0x1000,
1646 .has_pwrdn_delay = true,
1649 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1652 .offsets = &qmp_usb_offsets_v5,
1654 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1655 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1656 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
1657 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1658 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
1659 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1660 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1661 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1662 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1663 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1664 .vreg_list = qmp_phy_vreg_l,
1665 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1666 .regs = qmp_v5_usb3phy_regs_layout,
1667 .pcs_usb_offset = 0x1000,
1669 .has_pwrdn_delay = true,
1672 static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = {
1675 .offsets = &qmp_usb_offsets_v7,
1677 .serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl,
1678 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl),
1679 .tx_tbl = x1e80100_usb3_uniphy_tx_tbl,
1680 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl),
1681 .rx_tbl = x1e80100_usb3_uniphy_rx_tbl,
1682 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl),
1683 .pcs_tbl = x1e80100_usb3_uniphy_pcs_tbl,
1684 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl),
1685 .pcs_usb_tbl = x1e80100_usb3_uniphy_pcs_usb_tbl,
1686 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl),
1687 .vreg_list = qmp_phy_vreg_l,
1688 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1689 .regs = qmp_v7_usb3phy_regs_layout,
1692 static void qmp_usb_configure_lane(void __iomem *base,
1693 const struct qmp_phy_init_tbl tbl[],
1698 const struct qmp_phy_init_tbl *t = tbl;
1703 for (i = 0; i < num; i++, t++) {
1704 if (!(t->lane_mask & lane_mask))
1707 writel(t->val, base + t->offset);
1711 static void qmp_usb_configure(void __iomem *base,
1712 const struct qmp_phy_init_tbl tbl[],
1715 qmp_usb_configure_lane(base, tbl, num, 0xff);
1718 static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1720 const struct qmp_phy_cfg *cfg = qmp->cfg;
1721 void __iomem *serdes = qmp->serdes;
1722 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1723 int serdes_tbl_num = cfg->serdes_tbl_num;
1725 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
1730 static int qmp_usb_init(struct phy *phy)
1732 struct qmp_usb *qmp = phy_get_drvdata(phy);
1733 const struct qmp_phy_cfg *cfg = qmp->cfg;
1734 void __iomem *pcs = qmp->pcs;
1737 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1739 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1743 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1745 dev_err(qmp->dev, "reset assert failed\n");
1746 goto err_disable_regulators;
1749 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);
1751 dev_err(qmp->dev, "reset deassert failed\n");
1752 goto err_disable_regulators;
1755 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1757 goto err_assert_reset;
1759 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1764 reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1765 err_disable_regulators:
1766 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1771 static int qmp_usb_exit(struct phy *phy)
1773 struct qmp_usb *qmp = phy_get_drvdata(phy);
1774 const struct qmp_phy_cfg *cfg = qmp->cfg;
1776 reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1778 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1780 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1785 static int qmp_usb_power_on(struct phy *phy)
1787 struct qmp_usb *qmp = phy_get_drvdata(phy);
1788 const struct qmp_phy_cfg *cfg = qmp->cfg;
1789 void __iomem *tx = qmp->tx;
1790 void __iomem *rx = qmp->rx;
1791 void __iomem *pcs = qmp->pcs;
1792 void __iomem *pcs_usb = qmp->pcs_usb;
1793 void __iomem *status;
1797 qmp_usb_serdes_init(qmp);
1799 ret = clk_prepare_enable(qmp->pipe_clk);
1801 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1805 /* Tx, Rx, and PCS configurations */
1806 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
1807 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
1809 if (cfg->lanes >= 2) {
1810 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
1811 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
1814 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1817 qmp_usb_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
1819 if (cfg->has_pwrdn_delay)
1820 usleep_range(10, 20);
1822 /* Pull PHY out of reset state */
1823 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1825 /* start SerDes and Phy-Coding-Sublayer */
1826 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
1828 status = pcs + cfg->regs[QPHY_PCS_STATUS];
1829 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
1830 PHY_INIT_COMPLETE_TIMEOUT);
1832 dev_err(qmp->dev, "phy initialization timed-out\n");
1833 goto err_disable_pipe_clk;
1838 err_disable_pipe_clk:
1839 clk_disable_unprepare(qmp->pipe_clk);
1844 static int qmp_usb_power_off(struct phy *phy)
1846 struct qmp_usb *qmp = phy_get_drvdata(phy);
1847 const struct qmp_phy_cfg *cfg = qmp->cfg;
1849 clk_disable_unprepare(qmp->pipe_clk);
1852 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1854 /* stop SerDes and Phy-Coding-Sublayer */
1855 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
1856 SERDES_START | PCS_START);
1858 /* Put PHY into POWER DOWN state: active low */
1859 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1865 static int qmp_usb_enable(struct phy *phy)
1869 ret = qmp_usb_init(phy);
1873 ret = qmp_usb_power_on(phy);
1880 static int qmp_usb_disable(struct phy *phy)
1884 ret = qmp_usb_power_off(phy);
1887 return qmp_usb_exit(phy);
1890 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1892 struct qmp_usb *qmp = phy_get_drvdata(phy);
1899 static const struct phy_ops qmp_usb_phy_ops = {
1900 .init = qmp_usb_enable,
1901 .exit = qmp_usb_disable,
1902 .set_mode = qmp_usb_set_mode,
1903 .owner = THIS_MODULE,
1906 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
1908 const struct qmp_phy_cfg *cfg = qmp->cfg;
1909 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1910 void __iomem *pcs_misc = qmp->pcs_misc;
1913 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1914 qmp->mode == PHY_MODE_USB_DEVICE_SS)
1915 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1917 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1919 /* Clear any pending interrupts status */
1920 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1921 /* Writing 1 followed by 0 clears the interrupt */
1922 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1924 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1925 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1927 /* Enable required PHY autonomous mode interrupts */
1928 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1930 /* Enable i/o clamp_n for autonomous mode */
1931 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
1932 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
1935 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
1937 const struct qmp_phy_cfg *cfg = qmp->cfg;
1938 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1939 void __iomem *pcs_misc = qmp->pcs_misc;
1941 /* Disable i/o clamp_n on resume for normal mode */
1942 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
1943 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
1945 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1946 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1948 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1949 /* Writing 1 followed by 0 clears the interrupt */
1950 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1953 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
1955 struct qmp_usb *qmp = dev_get_drvdata(dev);
1957 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1959 if (!qmp->phy->init_count) {
1960 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1964 qmp_usb_enable_autonomous_mode(qmp);
1966 clk_disable_unprepare(qmp->pipe_clk);
1967 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1972 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
1974 struct qmp_usb *qmp = dev_get_drvdata(dev);
1977 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1979 if (!qmp->phy->init_count) {
1980 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1984 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1988 ret = clk_prepare_enable(qmp->pipe_clk);
1990 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1991 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1995 qmp_usb_disable_autonomous_mode(qmp);
2000 static const struct dev_pm_ops qmp_usb_pm_ops = {
2001 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
2002 qmp_usb_runtime_resume, NULL)
2005 static int qmp_usb_vreg_init(struct qmp_usb *qmp)
2007 const struct qmp_phy_cfg *cfg = qmp->cfg;
2008 struct device *dev = qmp->dev;
2009 int num = cfg->num_vregs;
2012 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2016 for (i = 0; i < num; i++)
2017 qmp->vregs[i].supply = cfg->vreg_list[i];
2019 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2022 static int qmp_usb_reset_init(struct qmp_usb *qmp,
2023 const char *const *reset_list,
2026 struct device *dev = qmp->dev;
2030 qmp->resets = devm_kcalloc(dev, num_resets,
2031 sizeof(*qmp->resets), GFP_KERNEL);
2035 for (i = 0; i < num_resets; i++)
2036 qmp->resets[i].id = reset_list[i];
2038 qmp->num_resets = num_resets;
2040 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);
2042 return dev_err_probe(dev, ret, "failed to get resets\n");
2047 static int qmp_usb_clk_init(struct qmp_usb *qmp)
2049 struct device *dev = qmp->dev;
2050 int num = ARRAY_SIZE(qmp_usb_phy_clk_l);
2053 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2057 for (i = 0; i < num; i++)
2058 qmp->clks[i].id = qmp_usb_phy_clk_l[i];
2060 qmp->num_clks = num;
2062 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
2065 static void phy_clk_release_provider(void *res)
2067 of_clk_del_provider(res);
2071 * Register a fixed rate pipe clock.
2073 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2074 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2075 * by the PHY driver for its operations.
2076 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2077 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2078 * Below picture shows this relationship.
2081 * | PHY block |<<---------------------------------------+
2083 * | +-------+ | +-----+ |
2084 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2085 * clk | +-------+ | +-----+
2088 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
2090 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
2091 struct clk_init_data init = { };
2094 ret = of_property_read_string(np, "clock-output-names", &init.name);
2096 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2100 init.ops = &clk_fixed_rate_ops;
2102 /* controllers using QMP phys use 125MHz pipe clock interface */
2103 fixed->fixed_rate = 125000000;
2104 fixed->hw.init = &init;
2106 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2110 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2115 * Roll a devm action because the clock provider is the child node, but
2116 * the child node is not actually a device.
2118 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2121 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2122 int index, bool exclusive)
2124 struct resource res;
2127 if (of_address_to_resource(np, index, &res))
2128 return IOMEM_ERR_PTR(-EINVAL);
2130 return devm_ioremap(dev, res.start, resource_size(&res));
2133 return devm_of_iomap(dev, np, index, NULL);
2136 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
2138 struct platform_device *pdev = to_platform_device(qmp->dev);
2139 const struct qmp_phy_cfg *cfg = qmp->cfg;
2140 struct device *dev = qmp->dev;
2141 bool exclusive = true;
2144 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2145 if (IS_ERR(qmp->serdes))
2146 return PTR_ERR(qmp->serdes);
2149 * FIXME: These bindings should be fixed to not rely on overlapping
2152 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2154 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2158 * Get memory resources for the PHY:
2159 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2160 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2161 * For single lane PHYs: pcs_misc (optional) -> 3.
2163 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2164 if (IS_ERR(qmp->tx))
2165 return PTR_ERR(qmp->tx);
2167 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2168 if (IS_ERR(qmp->rx))
2169 return PTR_ERR(qmp->rx);
2171 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2172 if (IS_ERR(qmp->pcs))
2173 return PTR_ERR(qmp->pcs);
2175 if (cfg->pcs_usb_offset)
2176 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2178 if (cfg->lanes >= 2) {
2179 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2180 if (IS_ERR(qmp->tx2))
2181 return PTR_ERR(qmp->tx2);
2183 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2184 if (IS_ERR(qmp->rx2))
2185 return PTR_ERR(qmp->rx2);
2187 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2189 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2192 if (IS_ERR(qmp->pcs_misc)) {
2193 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2194 qmp->pcs_misc = NULL;
2197 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2198 if (IS_ERR(qmp->pipe_clk)) {
2199 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2200 "failed to get pipe clock\n");
2203 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
2207 qmp->num_clks = ret;
2209 ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l,
2210 ARRAY_SIZE(usb3phy_legacy_reset_l));
2217 static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2219 struct platform_device *pdev = to_platform_device(qmp->dev);
2220 const struct qmp_phy_cfg *cfg = qmp->cfg;
2221 const struct qmp_usb_offsets *offs = cfg->offsets;
2222 struct device *dev = qmp->dev;
2229 base = devm_platform_ioremap_resource(pdev, 0);
2231 return PTR_ERR(base);
2233 qmp->serdes = base + offs->serdes;
2234 qmp->pcs = base + offs->pcs;
2236 qmp->pcs_usb = base + offs->pcs_usb;
2238 qmp->pcs_misc = base + offs->pcs_misc;
2239 qmp->tx = base + offs->tx;
2240 qmp->rx = base + offs->rx;
2242 if (cfg->lanes >= 2) {
2243 qmp->tx2 = base + offs->tx2;
2244 qmp->rx2 = base + offs->rx2;
2247 ret = qmp_usb_clk_init(qmp);
2251 qmp->pipe_clk = devm_clk_get(dev, "pipe");
2252 if (IS_ERR(qmp->pipe_clk)) {
2253 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2254 "failed to get pipe clock\n");
2257 ret = qmp_usb_reset_init(qmp, usb3phy_reset_l,
2258 ARRAY_SIZE(usb3phy_reset_l));
2265 static int qmp_usb_probe(struct platform_device *pdev)
2267 struct device *dev = &pdev->dev;
2268 struct phy_provider *phy_provider;
2269 struct device_node *np;
2270 struct qmp_usb *qmp;
2273 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2279 qmp->cfg = of_device_get_match_data(dev);
2283 ret = qmp_usb_vreg_init(qmp);
2287 /* Check for legacy binding with child node. */
2288 np = of_get_next_available_child(dev->of_node, NULL);
2290 ret = qmp_usb_parse_dt_legacy(qmp, np);
2292 np = of_node_get(dev->of_node);
2293 ret = qmp_usb_parse_dt(qmp);
2298 pm_runtime_set_active(dev);
2299 ret = devm_pm_runtime_enable(dev);
2303 * Prevent runtime pm from being ON by default. Users can enable
2304 * it using power/control in sysfs.
2306 pm_runtime_forbid(dev);
2308 ret = phy_pipe_clk_register(qmp, np);
2312 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
2313 if (IS_ERR(qmp->phy)) {
2314 ret = PTR_ERR(qmp->phy);
2315 dev_err(dev, "failed to create PHY: %d\n", ret);
2319 phy_set_drvdata(qmp->phy, qmp);
2323 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2325 return PTR_ERR_OR_ZERO(phy_provider);
2332 static const struct of_device_id qmp_usb_of_match_table[] = {
2334 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2335 .data = &ipq6018_usb3phy_cfg,
2337 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2338 .data = &ipq8074_usb3phy_cfg,
2340 .compatible = "qcom,ipq9574-qmp-usb3-phy",
2341 .data = &ipq9574_usb3phy_cfg,
2343 .compatible = "qcom,msm8996-qmp-usb3-phy",
2344 .data = &msm8996_usb3phy_cfg,
2346 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2347 .data = &sa8775p_usb3_uniphy_cfg,
2349 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2350 .data = &sc8280xp_usb3_uniphy_cfg,
2352 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2353 .data = &qmp_v3_usb3_uniphy_cfg,
2355 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2356 .data = &sdx55_usb3_uniphy_cfg,
2358 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2359 .data = &sdx65_usb3_uniphy_cfg,
2361 .compatible = "qcom,sdx75-qmp-usb3-uni-phy",
2362 .data = &sdx75_usb3_uniphy_cfg,
2364 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2365 .data = &sm8150_usb3_uniphy_cfg,
2367 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2368 .data = &sm8250_usb3_uniphy_cfg,
2370 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2371 .data = &sm8350_usb3_uniphy_cfg,
2373 .compatible = "qcom,x1e80100-qmp-usb3-uni-phy",
2374 .data = &x1e80100_usb3_uniphy_cfg,
2378 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2380 static struct platform_driver qmp_usb_driver = {
2381 .probe = qmp_usb_probe,
2383 .name = "qcom-qmp-usb-phy",
2384 .pm = &qmp_usb_pm_ops,
2385 .of_match_table = qmp_usb_of_match_table,
2389 module_platform_driver(qmp_usb_driver);
2391 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2392 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2393 MODULE_LICENSE("GPL v2");