drivers/phy/qualcomm/phy-qcom-qmp-combo.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21 #include <linux/usb/typec.h>
  22 #include <linux/usb/typec_mux.h>
  23
  24 #include <drm/bridge/aux-bridge.h>
  25
  26 #include <dt-bindings/phy/phy-qcom-qmp.h>
  27
  28 #include "phy-qcom-qmp.h"
  29 #include "phy-qcom-qmp-pcs-misc-v3.h"
  30 #include "phy-qcom-qmp-pcs-usb-v4.h"
  31 #include "phy-qcom-qmp-pcs-usb-v5.h"
  32 #include "phy-qcom-qmp-pcs-usb-v6.h"
  33
  34 /* QPHY_SW_RESET bit */
  35 #define SW_RESET                                BIT(0)
  36 /* QPHY_POWER_DOWN_CONTROL */
  37 #define SW_PWRDN                                BIT(0)
  38 /* QPHY_START_CONTROL bits */
  39 #define SERDES_START                            BIT(0)
  40 #define PCS_START                               BIT(1)
  41 /* QPHY_PCS_STATUS bit */
  42 #define PHYSTATUS                               BIT(6)
  43
  44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  45 /* DP PHY soft reset */
  46 #define SW_DPPHY_RESET                          BIT(0)
  47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  48 #define SW_DPPHY_RESET_MUX                      BIT(1)
  49 /* USB3 PHY soft reset */
  50 #define SW_USB3PHY_RESET                        BIT(2)
  51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  52 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  53
  54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  55 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  56 #define DP_MODE                                 BIT(1) /* enables DP mode */
  57
  58 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  59 #define ARCVR_DTCT_EN                           BIT(0)
  60 #define ALFPS_DTCT_EN                           BIT(1)
  61 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  62
  63 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  64 #define IRQ_CLEAR                               BIT(0)
  65
  66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  67 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  68
  69 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
  70 #define SW_PORTSELECT_VAL                       BIT(0)
  71 #define SW_PORTSELECT_MUX                       BIT(1)
  72
  73 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  74
  75 struct qmp_phy_init_tbl {
  76         unsigned int offset;
  77         unsigned int val;
  78         /*
  79          * mask of lanes for which this register is written
  80          * for cases when second lane needs different values
  81          */
  82         u8 lane_mask;
  83 };
  84
  85 #define QMP_PHY_INIT_CFG(o, v)          \
  86         {                               \
  87                 .offset = o,            \
  88                 .val = v,               \
  89                 .lane_mask = 0xff,      \
  90         }
  91
  92 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  93         {                               \
  94                 .offset = o,            \
  95                 .val = v,               \
  96                 .lane_mask = l,         \
  97         }
  98
  99 /* set of registers with offsets different per-PHY */
 100 enum qphy_reg_layout {
 101         /* PCS registers */
 102         QPHY_SW_RESET,
 103         QPHY_START_CTRL,
 104         QPHY_PCS_STATUS,
 105         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 106         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 107         QPHY_PCS_POWER_DOWN_CONTROL,
 108
 109         QPHY_COM_RESETSM_CNTRL,
 110         QPHY_COM_C_READY_STATUS,
 111         QPHY_COM_CMN_STATUS,
 112         QPHY_COM_BIAS_EN_CLKBUFLR_EN,
 113
 114         QPHY_DP_PHY_STATUS,
 115         QPHY_DP_PHY_VCO_DIV,
 116
 117         QPHY_TX_TX_POL_INV,
 118         QPHY_TX_TX_DRV_LVL,
 119         QPHY_TX_TX_EMP_POST1_LVL,
 120         QPHY_TX_HIGHZ_DRVR_EN,
 121         QPHY_TX_TRANSCEIVER_BIAS_EN,
 122
 123         /* Keep last to ensure regs_layout arrays are properly initialized */
 124         QPHY_LAYOUT_SIZE
 125 };
 126
 127 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 128         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
 129         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
 130         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
 131         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 132         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
 133         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
 134
 135         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V3_COM_RESETSM_CNTRL,
 136         [QPHY_COM_C_READY_STATUS]       = QSERDES_V3_COM_C_READY_STATUS,
 137         [QPHY_COM_CMN_STATUS]           = QSERDES_V3_COM_CMN_STATUS,
 138         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN,
 139
 140         [QPHY_DP_PHY_STATUS]            = QSERDES_V3_DP_PHY_STATUS,
 141         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V3_DP_PHY_VCO_DIV,
 142
 143         [QPHY_TX_TX_POL_INV]            = QSERDES_V3_TX_TX_POL_INV,
 144         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V3_TX_TX_DRV_LVL,
 145         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V3_TX_TX_EMP_POST1_LVL,
 146         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V3_TX_HIGHZ_DRVR_EN,
 147         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN,
 148 };
 149
 150 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 151         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
 152         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
 153         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
 154         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 155
 156         /* In PCS_USB */
 157         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 158         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 159
 160         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V4_COM_RESETSM_CNTRL,
 161         [QPHY_COM_C_READY_STATUS]       = QSERDES_V4_COM_C_READY_STATUS,
 162         [QPHY_COM_CMN_STATUS]           = QSERDES_V4_COM_CMN_STATUS,
 163         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN,
 164
 165         [QPHY_DP_PHY_STATUS]            = QSERDES_V4_DP_PHY_STATUS,
 166         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V4_DP_PHY_VCO_DIV,
 167
 168         [QPHY_TX_TX_POL_INV]            = QSERDES_V4_TX_TX_POL_INV,
 169         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V4_TX_TX_DRV_LVL,
 170         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V4_TX_TX_EMP_POST1_LVL,
 171         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V4_TX_HIGHZ_DRVR_EN,
 172         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN,
 173 };
 174
 175 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 176         [QPHY_SW_RESET]                 = QPHY_V5_PCS_SW_RESET,
 177         [QPHY_START_CTRL]               = QPHY_V5_PCS_START_CONTROL,
 178         [QPHY_PCS_STATUS]               = QPHY_V5_PCS_PCS_STATUS1,
 179         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_POWER_DOWN_CONTROL,
 180
 181         /* In PCS_USB */
 182         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 183         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 184
 185         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V5_COM_RESETSM_CNTRL,
 186         [QPHY_COM_C_READY_STATUS]       = QSERDES_V5_COM_C_READY_STATUS,
 187         [QPHY_COM_CMN_STATUS]           = QSERDES_V5_COM_CMN_STATUS,
 188         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN,
 189
 190         [QPHY_DP_PHY_STATUS]            = QSERDES_V5_DP_PHY_STATUS,
 191         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V5_DP_PHY_VCO_DIV,
 192
 193         [QPHY_TX_TX_POL_INV]            = QSERDES_V5_5NM_TX_TX_POL_INV,
 194         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V5_5NM_TX_TX_DRV_LVL,
 195         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,
 196         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN,
 197         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN,
 198 };
 199
 200 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 201         [QPHY_SW_RESET]                 = QPHY_V6_PCS_SW_RESET,
 202         [QPHY_START_CTRL]               = QPHY_V6_PCS_START_CONTROL,
 203         [QPHY_PCS_STATUS]               = QPHY_V6_PCS_PCS_STATUS1,
 204         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_PCS_POWER_DOWN_CONTROL,
 205
 206         /* In PCS_USB */
 207         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 208         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 209
 210         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V6_COM_RESETSM_CNTRL,
 211         [QPHY_COM_C_READY_STATUS]       = QSERDES_V6_COM_C_READY_STATUS,
 212         [QPHY_COM_CMN_STATUS]           = QSERDES_V6_COM_CMN_STATUS,
 213         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
 214
 215         [QPHY_DP_PHY_STATUS]            = QSERDES_V6_DP_PHY_STATUS,
 216         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V6_DP_PHY_VCO_DIV,
 217
 218         [QPHY_TX_TX_POL_INV]            = QSERDES_V6_TX_TX_POL_INV,
 219         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V6_TX_TX_DRV_LVL,
 220         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V6_TX_TX_EMP_POST1_LVL,
 221         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V6_TX_HIGHZ_DRVR_EN,
 222         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN,
 223 };
 224
 225 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 226         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 227         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 228         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 229         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 230         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 231         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 232         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 233         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 234         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 235         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 236         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 237         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 238         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 239         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 240         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 241         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 242         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 243         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 244         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 245         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 246         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 247         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 248         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 249         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 250         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 251         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 252         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 253         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 254         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 255         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 256         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 257         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 258         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 259         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 260         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 261         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 262 };
 263
 264 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 265         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 266         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 267         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 268         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 269         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 270 };
 271
 272 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
 273         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 274         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
 275         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 276         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
 277         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 278         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 279         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
 280         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
 281         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 282         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 283         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 284         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 285         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 286         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 287         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 288         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
 289         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
 290         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 291         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 292         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 293         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 294 };
 295
 296 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
 297         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
 298         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 299         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 300         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 301         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
 302         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
 303         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 304 };
 305
 306 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
 307         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
 308         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 309         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 310         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 311         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
 312         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
 313         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 314 };
 315
 316 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
 317         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 318         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
 319         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
 320         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
 321         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
 322         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
 323         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 324 };
 325
 326 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
 327         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
 328         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 329         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 330         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 331         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
 332         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
 333         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
 334 };
 335
 336 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
 337         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
 338         QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
 339         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 340         QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
 341         QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
 342         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
 343         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
 344         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 345         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
 346         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
 347         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
 348         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
 349         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
 350         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 351         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 352 };
 353
 354 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 355         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 356         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 357         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 358         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 359         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 360         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 361         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 362         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 363         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 364 };
 365
 366 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 367         /* FLL settings */
 368         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 369         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 370         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 371         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 372         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 373
 374         /* Lock Det settings */
 375         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 376         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 377         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 378         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 379
 380         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 381         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 382         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 383         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 384         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 385         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 386         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 387         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 388         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 389         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 390         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 391         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 392         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 393         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 394         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 395         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 396         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 397         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 398         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 399
 400         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 401         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 402         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 403         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 404         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 405         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 406         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 407         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 408         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 409         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 410         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 411 };
 412
 413 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
 414         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 415         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 416         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 417         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 418         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 419         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 420         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 421         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 422         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 423         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 424 };
 425
 426 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
 427         /* FLL settings */
 428         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 429         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 430         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 431         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 432         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 433
 434         /* Lock Det settings */
 435         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 436         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 437         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 438         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 439
 440         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
 441         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 442         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 443         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 444         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 445         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 446         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 447         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 448         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 449         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 450         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 451         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 452         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 453         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 454         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 455         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 456         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 457         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 458         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 459
 460         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 461         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 462         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 463         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 464         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 465         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 466         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 467         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 468         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 469         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 470         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 471         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
 472
 473         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 474         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 475 };
 476
 477 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
 478         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 479         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 480         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 481         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 482         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 483         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 484         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 485         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 486         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 487         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 488         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 489         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 490         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 491         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 492         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 493         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 494         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 495         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 496         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 497         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 498         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 499         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 500         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 501         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 502         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 503         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 504         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 505         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 506         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 507         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 508         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 509         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 510         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 511         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 512         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 513         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 514         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 515         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 516         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 517         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 518 };
 519
 520 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
 521         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
 522         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
 523         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 524         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 525         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
 526 };
 527
 528 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
 529         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
 530         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 531         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 532         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 533         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 534         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 535         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 536         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 537         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 538         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 539         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 540         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
 541         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 542         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 543         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 544         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 545         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 546         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 547         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 548         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 549         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
 550         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
 551         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
 552         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 553         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
 554         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 555         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 556         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 557         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 558         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 559         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 560         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 561         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 562         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 563         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 564         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 565 };
 566
 567 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
 568         /* Lock Det settings */
 569         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 570         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 571         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 572
 573         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 574         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 575         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 576         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 577         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 578         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 579         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 580         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 581 };
 582
 583 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
 584         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 585         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 586 };
 587
 588 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
 589         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
 590         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
 591         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 592         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 593         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 594         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 595         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
 596         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
 597 };
 598
 599 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
 600         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 601         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 602         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 603         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 604         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 605         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 606         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 607         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 608         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 609         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 610         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 611         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 612         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 613         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 614         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 615         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 616         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 617         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 618         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 619         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 620         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
 621         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
 622         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
 623         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
 624         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
 625         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 626         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
 627         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 628         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 629         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 630         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 631         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 632         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 633         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 634         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 635         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 636         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 637         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 638 };
 639
 640 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
 641         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 642         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 643         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 644         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 645         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 646         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 647         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 648         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 649         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 650         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 651         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 652         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 653 };
 654
 655 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
 656         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 657         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 658 };
 659
 660 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
 661         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
 662         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
 663         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
 664         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
 665         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
 666         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 667         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
 668         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
 669         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
 670         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 671 };
 672
 673 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
 674         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 675         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 676         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 677         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 678         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 679         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 680         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 681         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 682         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 683         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 684         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 685         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 686         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 687         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 688         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 689         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 690         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 691         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 692         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 693         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 694         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 695         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
 696         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
 697         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
 698         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
 699         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
 700         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
 701         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 702         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 703         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
 704         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
 705         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 706         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
 707         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 708         QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 709         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
 710         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 711         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
 712 };
 713
 714 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
 715         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 716         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 717         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 718         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 719         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 720         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 721         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 722         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 723         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 724         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 725         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 726         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 727         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 728         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 729 };
 730
 731 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
 732         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 733         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 734         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 735         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 736 };
 737
 738 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
 739         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
 740         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
 741         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
 742         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
 743         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
 744         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
 745         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
 746         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
 747         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
 748         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
 749         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
 750         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
 751         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
 752         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
 753         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
 754         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
 755         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
 756         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
 757         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
 758         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
 759         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
 760         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
 761         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
 762         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
 763         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
 764         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
 765         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
 766         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 767         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
 768         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
 769         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
 770         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
 771         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
 772         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
 773         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
 774         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
 775         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
 776         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
 777         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
 778         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
 779         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
 780         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
 781         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
 782         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 783         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
 784         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
 785         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
 786         QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
 787 };
 788
 789 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
 790         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
 791         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
 792         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
 793         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 794         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
 795         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
 796         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
 797         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
 798         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
 799         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
 800         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
 801 };
 802
 803 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
 804         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
 805         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
 806         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 807         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 808         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 809         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 810         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
 811         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
 812         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
 813         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
 814         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
 815         QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 816         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
 817         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
 818         QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
 819         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 820         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 821         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 822         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
 823         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 824         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 825         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
 826         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 827         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
 828         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
 829         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
 830         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
 831         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
 832         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
 833         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 834         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
 835         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
 836         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
 837         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
 838
 839         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
 840         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
 841         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
 842         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
 843         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
 844
 845         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
 846         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
 847         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
 848         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
 849         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
 850 };
 851
 852 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
 853         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
 854         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
 855         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
 856         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
 857         QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
 858         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99),
 859         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 860         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 861         QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
 862         QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 863         QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 864         QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
 865         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
 866         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
 867 };
 868
 869 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
 870         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 871         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 872         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 873         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 874         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
 875 };
 876
 877 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
 878         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
 879         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
 880         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
 881         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
 882         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
 883         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
 884         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 885         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 886         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 887         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 888         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
 889         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 890         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 891         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
 892         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
 893         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
 894         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
 895         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
 896         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
 897         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
 898 };
 899
 900 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
 901         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
 902         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 903         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 904         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 905         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
 906         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
 907         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 908 };
 909
 910 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
 911         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
 912         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 913         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 914         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 915         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
 916         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
 917         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 918 };
 919
 920 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
 921         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 922         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
 923         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
 924         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
 925         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
 926         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
 927         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 928 };
 929
 930 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
 931         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
 932         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 933         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 934         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 935         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
 936         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
 937         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 938 };
 939
 940 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
 941         QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
 942         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 943         QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
 944         QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
 945         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
 946         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
 947         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 948         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
 949         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 950         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 951         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
 952         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
 953         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
 954         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
 955 };
 956
 957 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = {
 958         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
 959         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
 960         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
 961         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
 962         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
 963         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
 964         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 965         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 966         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 967         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 968         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 969         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 970         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 971         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
 972         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 973         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 974         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 975         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
 976         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
 977         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
 978         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
 979         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
 980         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
 981 };
 982
 983 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
 984         QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
 985         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 986         QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
 987         QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
 988         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
 989         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
 990         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 991         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
 992         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 993         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 994         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
 995 };
 996
 997 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
 998         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
 999         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1000         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40),
1001         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0),
1002         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff),
1003         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f),
1004         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03),
1005         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf),
1006         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1007         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1008         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
1009         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
1010 };
1011
1012 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
1013         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
1014         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
1015         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
1016         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
1017         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
1018         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
1019         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1020         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1021         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1022         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1023         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
1024         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
1025         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1026         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1027         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
1028         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1029         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
1030         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
1031         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
1032         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
1033 };
1034
1035 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
1036         QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
1037         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1038         QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
1039         QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
1040         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
1041         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
1042         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1043         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
1044         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
1045         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1046         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
1047 };
1048
1049 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
1050         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
1051         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1052         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1053         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1054         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
1055         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
1056         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1057         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1058         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1059 };
1060
1061 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
1062         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
1063         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1064         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1065         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1066         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
1067         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
1068         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1069         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1070         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1071 };
1072
1073 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
1074         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1075         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
1076         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
1077         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
1078         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
1079         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
1080         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1081         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
1082         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
1083 };
1084
1085 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
1086         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
1087         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1088         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1089         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1090         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
1091         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1092         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1093         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1094         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1095 };
1096
1097 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
1098         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1099         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1100         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1101         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd),
1102         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d),
1103         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd),
1104         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d),
1105         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1106         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02),
1107         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02),
1108         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1109         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1110         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1111         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1112         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1113         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1114         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1115         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1116         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1117         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1118         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04),
1119         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01),
1120         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04),
1121         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01),
1122         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1123         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5),
1124         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05),
1125         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1126         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5),
1127         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1128         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1129         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4),
1130         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00),
1131         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4),
1132         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00),
1133         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13),
1134         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1135         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1136         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1137         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1138         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76),
1139         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff),
1140         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1141         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1142         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
1143         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01),
1144         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a),
1145 };
1146
1147 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {
1148         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05),
1149         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2),
1150         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10),
1151         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1152         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1153 };
1154
1155 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {
1156         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04),
1157         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1158         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00),
1159         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2),
1160         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2),
1161         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb),
1162         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21),
1163         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f),
1164         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80),
1165         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45),
1166         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00),
1167         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b),
1168         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63),
1169         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6),
1170         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23),
1171         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35),
1172         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30),
1173         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e),
1174         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00),
1175         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1176         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80),
1177         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b),
1178         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1179         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15),
1180         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1181         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1182         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00),
1183         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d),
1184         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00),
1185         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45),
1186         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09),
1187         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09),
1188         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05),
1189         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),
1190 };
1191
1192 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {
1193         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1194         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1195         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1196         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1197         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1198         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1199         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1200         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1201         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a),
1202         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1203         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1204         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1205         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1206         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1207         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1208         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1209 };
1210
1211 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = {
1212         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1213         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1214         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1215         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2),
1216         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03),
1217         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2),
1218         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1219         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
1220         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1221         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1222         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1223         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1224         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1225         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1226         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
1227         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1228         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1229         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
1230         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
1231         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
1232         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
1233         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
1234         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
1235         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
1236         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
1237         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
1238         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55),
1239         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03),
1240         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1241         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1242         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03),
1243         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1244         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba),
1245         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00),
1246         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba),
1247         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00),
1248         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13),
1249         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1250         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1251         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1252         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1253         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76),
1254         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1255         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f),
1256         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1257         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1258         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
1259         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01),
1260         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a),
1261         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1262 };
1263
1264 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = {
1265         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05),
1266         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50),
1267         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50),
1268         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1269         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1270 };
1271
1272 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = {
1273         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04),
1274         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1275         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00),
1276         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3),
1277         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3),
1278         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8),
1279         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e),
1280         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36),
1281         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6),
1282         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64),
1283         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6),
1284         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee),
1285         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18),
1286         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a),
1287         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04),
1288         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36),
1289         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3),
1290         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1291         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80),
1292         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f),
1293         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08),
1294         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15),
1295         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0),
1296         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48),
1297         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1298         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1299         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00),
1300         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04),
1301         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88),
1302         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45),
1303         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d),
1304         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09),
1305         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05),
1306         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f),
1307         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14),
1308 };
1309
1310 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
1311         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1312         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1313         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1314         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
1315         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
1316         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
1317         QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
1318         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x55),
1319         QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
1320         QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0xd4),
1321         QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x30),
1322         QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
1323         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
1324         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
1325 };
1326
1327 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
1328         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1329         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1330 };
1331
1332 /* list of regulators */
1333 struct qmp_regulator_data {
1334         const char *name;
1335         unsigned int enable_load;
1336 };
1337
1338 static struct qmp_regulator_data qmp_phy_vreg_l[] = {
1339         { .name = "vdda-phy", .enable_load = 21800 },
1340         { .name = "vdda-pll", .enable_load = 36000 },
1341 };
1342
1343 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
1344         { 0x00, 0x0c, 0x15, 0x1a },
1345         { 0x02, 0x0e, 0x16, 0xff },
1346         { 0x02, 0x11, 0xff, 0xff },
1347         { 0x04, 0xff, 0xff, 0xff }
1348 };
1349
1350 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
1351         { 0x02, 0x12, 0x16, 0x1a },
1352         { 0x09, 0x19, 0x1f, 0xff },
1353         { 0x10, 0x1f, 0xff, 0xff },
1354         { 0x1f, 0xff, 0xff, 0xff }
1355 };
1356
1357 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
1358         { 0x00, 0x0c, 0x14, 0x19 },
1359         { 0x00, 0x0b, 0x12, 0xff },
1360         { 0x00, 0x0b, 0xff, 0xff },
1361         { 0x04, 0xff, 0xff, 0xff }
1362 };
1363
1364 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
1365         { 0x08, 0x0f, 0x16, 0x1f },
1366         { 0x11, 0x1e, 0x1f, 0xff },
1367         { 0x19, 0x1f, 0xff, 0xff },
1368         { 0x1f, 0xff, 0xff, 0xff }
1369 };
1370
1371 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
1372         { 0x00, 0x0c, 0x15, 0x1b },
1373         { 0x02, 0x0e, 0x16, 0xff },
1374         { 0x02, 0x11, 0xff, 0xff },
1375         { 0x04, 0xff, 0xff, 0xff }
1376 };
1377
1378 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
1379         { 0x00, 0x0d, 0x14, 0x1a },
1380         { 0x00, 0x0e, 0x15, 0xff },
1381         { 0x00, 0x0d, 0xff, 0xff },
1382         { 0x03, 0xff, 0xff, 0xff }
1383 };
1384
1385 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
1386         { 0x08, 0x0f, 0x16, 0x1f },
1387         { 0x11, 0x1e, 0x1f, 0xff },
1388         { 0x16, 0x1f, 0xff, 0xff },
1389         { 0x1f, 0xff, 0xff, 0xff }
1390 };
1391
1392 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
1393         { 0x20, 0x2c, 0x35, 0x3b },
1394         { 0x22, 0x2e, 0x36, 0xff },
1395         { 0x22, 0x31, 0xff, 0xff },
1396         { 0x24, 0xff, 0xff, 0xff }
1397 };
1398
1399 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = {
1400         { 0x22, 0x32, 0x36, 0x3a },
1401         { 0x29, 0x39, 0x3f, 0xff },
1402         { 0x30, 0x3f, 0xff, 0xff },
1403         { 0x3f, 0xff, 0xff, 0xff }
1404 };
1405
1406 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = {
1407         { 0x20, 0x2d, 0x34, 0x3a },
1408         { 0x20, 0x2e, 0x35, 0xff },
1409         { 0x20, 0x2e, 0xff, 0xff },
1410         { 0x24, 0xff, 0xff, 0xff }
1411 };
1412
1413 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {
1414         { 0x28, 0x2f, 0x36, 0x3f },
1415         { 0x31, 0x3e, 0x3f, 0xff },
1416         { 0x36, 0x3f, 0xff, 0xff },
1417         { 0x3f, 0xff, 0xff, 0xff }
1418 };
1419
1420 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
1421         { 0x20, 0x2d, 0x34, 0x3a },
1422         { 0x20, 0x2e, 0x35, 0xff },
1423         { 0x20, 0x2e, 0xff, 0xff },
1424         { 0x22, 0xff, 0xff, 0xff }
1425 };
1426
1427 struct qmp_combo;
1428
1429 struct qmp_combo_offsets {
1430         u16 com;
1431         u16 txa;
1432         u16 rxa;
1433         u16 txb;
1434         u16 rxb;
1435         u16 usb3_serdes;
1436         u16 usb3_pcs_misc;
1437         u16 usb3_pcs;
1438         u16 usb3_pcs_usb;
1439         u16 dp_serdes;
1440         u16 dp_txa;
1441         u16 dp_txb;
1442         u16 dp_dp_phy;
1443 };
1444
1445 struct qmp_phy_cfg {
1446         const struct qmp_combo_offsets *offsets;
1447
1448         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1449         const struct qmp_phy_init_tbl *serdes_tbl;
1450         int serdes_tbl_num;
1451         const struct qmp_phy_init_tbl *tx_tbl;
1452         int tx_tbl_num;
1453         const struct qmp_phy_init_tbl *rx_tbl;
1454         int rx_tbl_num;
1455         const struct qmp_phy_init_tbl *pcs_tbl;
1456         int pcs_tbl_num;
1457         const struct qmp_phy_init_tbl *pcs_usb_tbl;
1458         int pcs_usb_tbl_num;
1459
1460         const struct qmp_phy_init_tbl *dp_serdes_tbl;
1461         int dp_serdes_tbl_num;
1462         const struct qmp_phy_init_tbl *dp_tx_tbl;
1463         int dp_tx_tbl_num;
1464
1465         /* Init sequence for DP PHY block link rates */
1466         const struct qmp_phy_init_tbl *serdes_tbl_rbr;
1467         int serdes_tbl_rbr_num;
1468         const struct qmp_phy_init_tbl *serdes_tbl_hbr;
1469         int serdes_tbl_hbr_num;
1470         const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
1471         int serdes_tbl_hbr2_num;
1472         const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
1473         int serdes_tbl_hbr3_num;
1474
1475         /* DP PHY swing and pre_emphasis tables */
1476         const u8 (*swing_hbr_rbr)[4][4];
1477         const u8 (*swing_hbr3_hbr2)[4][4];
1478         const u8 (*pre_emphasis_hbr_rbr)[4][4];
1479         const u8 (*pre_emphasis_hbr3_hbr2)[4][4];
1480
1481         /* DP PHY callbacks */
1482         int (*configure_dp_phy)(struct qmp_combo *qmp);
1483         void (*configure_dp_tx)(struct qmp_combo *qmp);
1484         int (*calibrate_dp_phy)(struct qmp_combo *qmp);
1485         void (*dp_aux_init)(struct qmp_combo *qmp);
1486
1487         /* resets to be requested */
1488         const char * const *reset_list;
1489         int num_resets;
1490         /* regulators to be requested */
1491         const struct qmp_regulator_data *vreg_list;
1492         int num_vregs;
1493
1494         /* array of registers with different offsets */
1495         const unsigned int *regs;
1496
1497         /* true, if PHY needs delay after POWER_DOWN */
1498         bool has_pwrdn_delay;
1499
1500         /* Offset from PCS to PCS_USB region */
1501         unsigned int pcs_usb_offset;
1502
1503 };
1504
1505 struct qmp_combo {
1506         struct device *dev;
1507
1508         const struct qmp_phy_cfg *cfg;
1509
1510         void __iomem *com;
1511
1512         void __iomem *serdes;
1513         void __iomem *tx;
1514         void __iomem *rx;
1515         void __iomem *pcs;
1516         void __iomem *tx2;
1517         void __iomem *rx2;
1518         void __iomem *pcs_misc;
1519         void __iomem *pcs_usb;
1520
1521         void __iomem *dp_serdes;
1522         void __iomem *dp_tx;
1523         void __iomem *dp_tx2;
1524         void __iomem *dp_dp_phy;
1525
1526         struct clk *pipe_clk;
1527         struct clk_bulk_data *clks;
1528         int num_clks;
1529         struct reset_control_bulk_data *resets;
1530         struct regulator_bulk_data *vregs;
1531
1532         struct mutex phy_mutex;
1533         int init_count;
1534
1535         struct phy *usb_phy;
1536         enum phy_mode mode;
1537         unsigned int usb_init_count;
1538
1539         struct phy *dp_phy;
1540         unsigned int dp_aux_cfg;
1541         struct phy_configure_opts_dp dp_opts;
1542         unsigned int dp_init_count;
1543
1544         struct clk_fixed_rate pipe_clk_fixed;
1545         struct clk_hw dp_link_hw;
1546         struct clk_hw dp_pixel_hw;
1547
1548         struct typec_switch_dev *sw;
1549         enum typec_orientation orientation;
1550 };
1551
1552 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp);
1553 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp);
1554 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp);
1555 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp);
1556
1557 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp);
1558 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp);
1559 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp);
1560 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp);
1561
1562 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1563 {
1564         u32 reg;
1565
1566         reg = readl(base + offset);
1567         reg |= val;
1568         writel(reg, base + offset);
1569
1570         /* ensure that above write is through */
1571         readl(base + offset);
1572 }
1573
1574 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1575 {
1576         u32 reg;
1577
1578         reg = readl(base + offset);
1579         reg &= ~val;
1580         writel(reg, base + offset);
1581
1582         /* ensure that above write is through */
1583         readl(base + offset);
1584 }
1585
1586 /* list of clocks required by phy */
1587 static const char * const qmp_combo_phy_clk_l[] = {
1588         "aux", "cfg_ahb", "ref", "com_aux",
1589 };
1590
1591 /* list of resets */
1592 static const char * const msm8996_usb3phy_reset_l[] = {
1593         "phy", "common",
1594 };
1595
1596 static const char * const sc7180_usb3phy_reset_l[] = {
1597         "phy",
1598 };
1599
1600 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1601         .com            = 0x0000,
1602         .txa            = 0x1200,
1603         .rxa            = 0x1400,
1604         .txb            = 0x1600,
1605         .rxb            = 0x1800,
1606         .usb3_serdes    = 0x1000,
1607         .usb3_pcs_misc  = 0x1a00,
1608         .usb3_pcs       = 0x1c00,
1609         .usb3_pcs_usb   = 0x1f00,
1610         .dp_serdes      = 0x2000,
1611         .dp_txa         = 0x2200,
1612         .dp_txb         = 0x2600,
1613         .dp_dp_phy      = 0x2a00,
1614 };
1615
1616 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
1617         .com            = 0x0000,
1618         .txa            = 0x0400,
1619         .rxa            = 0x0600,
1620         .txb            = 0x0a00,
1621         .rxb            = 0x0c00,
1622         .usb3_serdes    = 0x1000,
1623         .usb3_pcs_misc  = 0x1200,
1624         .usb3_pcs       = 0x1400,
1625         .usb3_pcs_usb   = 0x1700,
1626         .dp_serdes      = 0x2000,
1627         .dp_dp_phy      = 0x2200,
1628 };
1629
1630 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
1631         .offsets                = &qmp_combo_offsets_v3,
1632
1633         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1634         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1635         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1636         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1637         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1638         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1639         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1640         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1641
1642         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1643         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1644         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1645         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1646
1647         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1648         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1649         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1650         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1651         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1652         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1653         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1654         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1655
1656         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1657         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1658         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1659         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1660
1661         .dp_aux_init            = qmp_v3_dp_aux_init,
1662         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1663         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1664         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1665
1666         .reset_list             = sc7180_usb3phy_reset_l,
1667         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1668         .vreg_list              = qmp_phy_vreg_l,
1669         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1670         .regs                   = qmp_v3_usb3phy_regs_layout,
1671
1672         .has_pwrdn_delay        = true,
1673 };
1674
1675 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = {
1676         .offsets                = &qmp_combo_offsets_v3,
1677
1678         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1679         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1680         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1681         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1682         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1683         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1684         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1685         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1686
1687         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1688         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1689         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1690         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1691
1692         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1693         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1694         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1695         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1696         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1697         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1698         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1699         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1700
1701         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1702         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1703         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1704         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1705
1706         .dp_aux_init            = qmp_v3_dp_aux_init,
1707         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1708         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1709         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1710
1711         .reset_list             = msm8996_usb3phy_reset_l,
1712         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1713         .vreg_list              = qmp_phy_vreg_l,
1714         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1715         .regs                   = qmp_v3_usb3phy_regs_layout,
1716
1717         .has_pwrdn_delay        = true,
1718 };
1719
1720 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = {
1721         .offsets                = &qmp_combo_offsets_v3,
1722
1723         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1724         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1725         .tx_tbl                 = sm8150_usb3_tx_tbl,
1726         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1727         .rx_tbl                 = sm8150_usb3_rx_tbl,
1728         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1729         .pcs_tbl                = sm8150_usb3_pcs_tbl,
1730         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
1731         .pcs_usb_tbl            = sm8150_usb3_pcs_usb_tbl,
1732         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
1733
1734         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1735         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1736         .dp_tx_tbl              = qmp_v4_dp_tx_tbl,
1737         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1738
1739         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1740         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1741         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1742         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1743         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1744         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1745         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1746         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1747
1748         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1749         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1750         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1751         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1752
1753         .dp_aux_init            = qmp_v4_dp_aux_init,
1754         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1755         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1756         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1757
1758         .reset_list             = msm8996_usb3phy_reset_l,
1759         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1760         .vreg_list              = qmp_phy_vreg_l,
1761         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1762         .regs                   = qmp_v45_usb3phy_regs_layout,
1763         .pcs_usb_offset         = 0x300,
1764
1765         .has_pwrdn_delay        = true,
1766 };
1767
1768 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
1769         .offsets                = &qmp_combo_offsets_v5,
1770
1771         .serdes_tbl             = sc8280xp_usb43dp_serdes_tbl,
1772         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
1773         .tx_tbl                 = sc8280xp_usb43dp_tx_tbl,
1774         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),
1775         .rx_tbl                 = sc8280xp_usb43dp_rx_tbl,
1776         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),
1777         .pcs_tbl                = sc8280xp_usb43dp_pcs_tbl,
1778         .pcs_tbl_num            = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),
1779
1780         .dp_serdes_tbl          = qmp_v5_dp_serdes_tbl,
1781         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v5_dp_serdes_tbl),
1782         .dp_tx_tbl              = qmp_v5_5nm_dp_tx_tbl,
1783         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl),
1784
1785         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1786         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1787         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1788         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1789         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1790         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1791         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1792         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1793
1794         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
1795         .pre_emphasis_hbr_rbr   = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1796         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1797         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1798
1799         .dp_aux_init            = qmp_v4_dp_aux_init,
1800         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1801         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1802         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1803
1804         .reset_list             = msm8996_usb3phy_reset_l,
1805         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1806         .vreg_list              = qmp_phy_vreg_l,
1807         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1808         .regs                   = qmp_v5_5nm_usb3phy_regs_layout,
1809 };
1810
1811 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
1812         .offsets                = &qmp_combo_offsets_v5,
1813
1814         .serdes_tbl             = x1e80100_usb43dp_serdes_tbl,
1815         .serdes_tbl_num         = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl),
1816         .tx_tbl                 = x1e80100_usb43dp_tx_tbl,
1817         .tx_tbl_num             = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl),
1818         .rx_tbl                 = x1e80100_usb43dp_rx_tbl,
1819         .rx_tbl_num             = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl),
1820         .pcs_tbl                = x1e80100_usb43dp_pcs_tbl,
1821         .pcs_tbl_num            = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl),
1822         .pcs_usb_tbl            = x1e80100_usb43dp_pcs_usb_tbl,
1823         .pcs_usb_tbl_num        = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl),
1824
1825         .dp_serdes_tbl          = qmp_v6_dp_serdes_tbl,
1826         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1827         .dp_tx_tbl              = qmp_v6_dp_tx_tbl,
1828         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1829
1830         .serdes_tbl_rbr         = qmp_v6_dp_serdes_tbl_rbr,
1831         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1832         .serdes_tbl_hbr         = qmp_v6_dp_serdes_tbl_hbr,
1833         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1834         .serdes_tbl_hbr2        = qmp_v6_dp_serdes_tbl_hbr2,
1835         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1836         .serdes_tbl_hbr3        = qmp_v6_dp_serdes_tbl_hbr3,
1837         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1838
1839         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
1840         .pre_emphasis_hbr_rbr   = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1841         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1842         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1843
1844         .dp_aux_init            = qmp_v4_dp_aux_init,
1845         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1846         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1847         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1848
1849         .reset_list             = msm8996_usb3phy_reset_l,
1850         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1851         .vreg_list              = qmp_phy_vreg_l,
1852         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1853         .regs                   = qmp_v45_usb3phy_regs_layout,
1854 };
1855
1856 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1857         .offsets                = &qmp_combo_offsets_v3,
1858
1859         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1860         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1861         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1862         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1863         .rx_tbl                 = sm6350_usb3_rx_tbl,
1864         .rx_tbl_num             = ARRAY_SIZE(sm6350_usb3_rx_tbl),
1865         .pcs_tbl                = sm6350_usb3_pcs_tbl,
1866         .pcs_tbl_num            = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
1867
1868         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1869         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1870         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1871         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1872
1873         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1874         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1875         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1876         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1877         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1878         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1879         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1880         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1881
1882         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1883         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1884         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1885         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1886
1887         .dp_aux_init            = qmp_v3_dp_aux_init,
1888         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1889         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1890         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1891
1892         .reset_list             = msm8996_usb3phy_reset_l,
1893         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1894         .vreg_list              = qmp_phy_vreg_l,
1895         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1896         .regs                   = qmp_v3_usb3phy_regs_layout,
1897 };
1898
1899 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
1900         .offsets                = &qmp_combo_offsets_v3,
1901
1902         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1903         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1904         .tx_tbl                 = sm8250_usb3_tx_tbl,
1905         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1906         .rx_tbl                 = sm8250_usb3_rx_tbl,
1907         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1908         .pcs_tbl                = sm8250_usb3_pcs_tbl,
1909         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
1910         .pcs_usb_tbl            = sm8250_usb3_pcs_usb_tbl,
1911         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
1912
1913         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1914         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1915         .dp_tx_tbl              = qmp_v4_dp_tx_tbl,
1916         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1917
1918         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1919         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1920         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1921         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1922         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1923         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1924         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1925         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1926
1927         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1928         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1929         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1930         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1931
1932         .dp_aux_init            = qmp_v4_dp_aux_init,
1933         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1934         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1935         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1936
1937         .reset_list             = msm8996_usb3phy_reset_l,
1938         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1939         .vreg_list              = qmp_phy_vreg_l,
1940         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1941         .regs                   = qmp_v45_usb3phy_regs_layout,
1942         .pcs_usb_offset         = 0x300,
1943
1944         .has_pwrdn_delay        = true,
1945 };
1946
1947 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
1948         .offsets                = &qmp_combo_offsets_v3,
1949
1950         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1951         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1952         .tx_tbl                 = sm8350_usb3_tx_tbl,
1953         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1954         .rx_tbl                 = sm8350_usb3_rx_tbl,
1955         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1956         .pcs_tbl                = sm8350_usb3_pcs_tbl,
1957         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1958         .pcs_usb_tbl            = sm8350_usb3_pcs_usb_tbl,
1959         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1960
1961         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1962         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1963         .dp_tx_tbl              = qmp_v5_dp_tx_tbl,
1964         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
1965
1966         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1967         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1968         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1969         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1970         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1971         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1972         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1973         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1974
1975         .swing_hbr_rbr          = &qmp_dp_v4_voltage_swing_hbr_rbr,
1976         .pre_emphasis_hbr_rbr   = &qmp_dp_v4_pre_emphasis_hbr_rbr,
1977         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1978         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
1979
1980         .dp_aux_init            = qmp_v4_dp_aux_init,
1981         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1982         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1983         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1984
1985         .reset_list             = msm8996_usb3phy_reset_l,
1986         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1987         .vreg_list              = qmp_phy_vreg_l,
1988         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1989         .regs                   = qmp_v45_usb3phy_regs_layout,
1990
1991         .has_pwrdn_delay        = true,
1992 };
1993
1994 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
1995         .offsets                = &qmp_combo_offsets_v3,
1996
1997         .serdes_tbl             = sm8550_usb3_serdes_tbl,
1998         .serdes_tbl_num         = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
1999         .tx_tbl                 = sm8550_usb3_tx_tbl,
2000         .tx_tbl_num             = ARRAY_SIZE(sm8550_usb3_tx_tbl),
2001         .rx_tbl                 = sm8550_usb3_rx_tbl,
2002         .rx_tbl_num             = ARRAY_SIZE(sm8550_usb3_rx_tbl),
2003         .pcs_tbl                = sm8550_usb3_pcs_tbl,
2004         .pcs_tbl_num            = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
2005         .pcs_usb_tbl            = sm8550_usb3_pcs_usb_tbl,
2006         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
2007
2008         .dp_serdes_tbl          = qmp_v6_dp_serdes_tbl,
2009         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2010         .dp_tx_tbl              = qmp_v6_dp_tx_tbl,
2011         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2012
2013         .serdes_tbl_rbr         = qmp_v6_dp_serdes_tbl_rbr,
2014         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2015         .serdes_tbl_hbr         = qmp_v6_dp_serdes_tbl_hbr,
2016         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2017         .serdes_tbl_hbr2        = qmp_v6_dp_serdes_tbl_hbr2,
2018         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2019         .serdes_tbl_hbr3        = qmp_v6_dp_serdes_tbl_hbr3,
2020         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2021
2022         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
2023         .pre_emphasis_hbr_rbr   = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2024         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2025         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2026
2027         .dp_aux_init            = qmp_v4_dp_aux_init,
2028         .configure_dp_tx        = qmp_v4_configure_dp_tx,
2029         .configure_dp_phy       = qmp_v4_configure_dp_phy,
2030         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
2031
2032         .regs                   = qmp_v6_usb3phy_regs_layout,
2033         .reset_list             = msm8996_usb3phy_reset_l,
2034         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2035         .vreg_list              = qmp_phy_vreg_l,
2036         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2037 };
2038
2039 static void qmp_combo_configure_lane(void __iomem *base,
2040                                         const struct qmp_phy_init_tbl tbl[],
2041                                         int num,
2042                                         u8 lane_mask)
2043 {
2044         int i;
2045         const struct qmp_phy_init_tbl *t = tbl;
2046
2047         if (!t)
2048                 return;
2049
2050         for (i = 0; i < num; i++, t++) {
2051                 if (!(t->lane_mask & lane_mask))
2052                         continue;
2053
2054                 writel(t->val, base + t->offset);
2055         }
2056 }
2057
2058 static void qmp_combo_configure(void __iomem *base,
2059                                    const struct qmp_phy_init_tbl tbl[],
2060                                    int num)
2061 {
2062         qmp_combo_configure_lane(base, tbl, num, 0xff);
2063 }
2064
2065 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
2066 {
2067         const struct qmp_phy_cfg *cfg = qmp->cfg;
2068         void __iomem *serdes = qmp->dp_serdes;
2069         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2070
2071         qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
2072
2073         switch (dp_opts->link_rate) {
2074         case 1620:
2075                 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr,
2076                                 cfg->serdes_tbl_rbr_num);
2077                 break;
2078         case 2700:
2079                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr,
2080                                 cfg->serdes_tbl_hbr_num);
2081                 break;
2082         case 5400:
2083                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2,
2084                                 cfg->serdes_tbl_hbr2_num);
2085                 break;
2086         case 8100:
2087                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3,
2088                                 cfg->serdes_tbl_hbr3_num);
2089                 break;
2090         default:
2091                 /* Other link rates aren't supported */
2092                 return -EINVAL;
2093         }
2094
2095         return 0;
2096 }
2097
2098 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
2099 {
2100         const struct qmp_phy_cfg *cfg = qmp->cfg;
2101
2102         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2103                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2104                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2105
2106         /* Turn on BIAS current for PHY/PLL */
2107         writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
2108                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
2109                qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2110
2111         writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2112
2113         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2114                DP_PHY_PD_CTL_LANE_0_1_PWRDN |
2115                DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
2116                DP_PHY_PD_CTL_DP_CLAMP_EN,
2117                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2118
2119         writel(QSERDES_V3_COM_BIAS_EN |
2120                QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
2121                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
2122                QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
2123                qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2124
2125         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2126         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2127         writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2128         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2129         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2130         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2131         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2132         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2133         writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2134         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2135         qmp->dp_aux_cfg = 0;
2136
2137         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2138                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2139                PHY_AUX_REQ_ERR_MASK,
2140                qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
2141 }
2142
2143 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)
2144 {
2145         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2146         const struct qmp_phy_cfg *cfg = qmp->cfg;
2147         unsigned int v_level = 0, p_level = 0;
2148         u8 voltage_swing_cfg, pre_emphasis_cfg;
2149         int i;
2150
2151         for (i = 0; i < dp_opts->lanes; i++) {
2152                 v_level = max(v_level, dp_opts->voltage[i]);
2153                 p_level = max(p_level, dp_opts->pre[i]);
2154         }
2155
2156         if (dp_opts->link_rate <= 2700) {
2157                 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level];
2158                 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level];
2159         } else {
2160                 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level];
2161                 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level];
2162         }
2163
2164         /* TODO: Move check to config check */
2165         if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
2166                 return -EINVAL;
2167
2168         /* Enable MUX to use Cursor values from these registers */
2169         voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
2170         pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
2171
2172         writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2173         writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2174         writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2175         writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2176
2177         return 0;
2178 }
2179
2180 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
2181 {
2182         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2183         u32 bias_en, drvr_en;
2184
2185         if (qmp_combo_configure_dp_swing(qmp) < 0)
2186                 return;
2187
2188         if (dp_opts->lanes == 1) {
2189                 bias_en = 0x3e;
2190                 drvr_en = 0x13;
2191         } else {
2192                 bias_en = 0x3f;
2193                 drvr_en = 0x10;
2194         }
2195
2196         writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2197         writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2198         writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2199         writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2200 }
2201
2202 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
2203 {
2204         bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2205         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2206         u32 val;
2207
2208         val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2209               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
2210
2211         if (dp_opts->lanes == 4 || reverse)
2212                 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
2213         if (dp_opts->lanes == 4 || !reverse)
2214                 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
2215
2216         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2217
2218         if (reverse)
2219                 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
2220         else
2221                 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
2222
2223         return reverse;
2224 }
2225
2226 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp)
2227 {
2228         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2229         u32 phy_vco_div;
2230         unsigned long pixel_freq;
2231         const struct qmp_phy_cfg *cfg = qmp->cfg;
2232
2233         switch (dp_opts->link_rate) {
2234         case 1620:
2235                 phy_vco_div = 0x1;
2236                 pixel_freq = 1620000000UL / 2;
2237                 break;
2238         case 2700:
2239                 phy_vco_div = 0x1;
2240                 pixel_freq = 2700000000UL / 2;
2241                 break;
2242         case 5400:
2243                 phy_vco_div = 0x2;
2244                 pixel_freq = 5400000000UL / 4;
2245                 break;
2246         case 8100:
2247                 phy_vco_div = 0x0;
2248                 pixel_freq = 8100000000UL / 6;
2249                 break;
2250         default:
2251                 /* Other link rates aren't supported */
2252                 return -EINVAL;
2253         }
2254         writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]);
2255
2256         clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2257         clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
2258
2259         return 0;
2260 }
2261
2262 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
2263 {
2264         const struct qmp_phy_cfg *cfg = qmp->cfg;
2265         u32 status;
2266         int ret;
2267
2268         qmp_combo_configure_dp_mode(qmp);
2269
2270         writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2271         writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2272
2273         ret = qmp_combo_configure_dp_clocks(qmp);
2274         if (ret)
2275                 return ret;
2276
2277         writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2278         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2279         writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2280         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2281         writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2282
2283         writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
2284
2285         if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
2286                         status,
2287                         ((status & BIT(0)) > 0),
2288                         500,
2289                         10000))
2290                 return -ETIMEDOUT;
2291
2292         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2293
2294         if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2295                         status,
2296                         ((status & BIT(1)) > 0),
2297                         500,
2298                         10000))
2299                 return -ETIMEDOUT;
2300
2301         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2302         udelay(2000);
2303         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2304
2305         return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2306                         status,
2307                         ((status & BIT(1)) > 0),
2308                         500,
2309                         10000);
2310 }
2311
2312 /*
2313  * We need to calibrate the aux setting here as many times
2314  * as the caller tries
2315  */
2316 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
2317 {
2318         static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
2319         u8 val;
2320
2321         qmp->dp_aux_cfg++;
2322         qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2323         val = cfg1_settings[qmp->dp_aux_cfg];
2324
2325         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2326
2327         return 0;
2328 }
2329
2330 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
2331 {
2332         const struct qmp_phy_cfg *cfg = qmp->cfg;
2333
2334         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2335                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2336                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2337
2338         /* Turn on BIAS current for PHY/PLL */
2339         writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2340
2341         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2342         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2343         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2344         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2345         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2346         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2347         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2348         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2349         writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2350         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2351         qmp->dp_aux_cfg = 0;
2352
2353         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2354                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2355                PHY_AUX_REQ_ERR_MASK,
2356                qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2357 }
2358
2359 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
2360 {
2361         const struct qmp_phy_cfg *cfg = qmp->cfg;
2362
2363         /* Program default values before writing proper values */
2364         writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2365         writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2366
2367         writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2368         writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2369
2370         qmp_combo_configure_dp_swing(qmp);
2371 }
2372
2373 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
2374 {
2375         const struct qmp_phy_cfg *cfg = qmp->cfg;
2376         u32 status;
2377         int ret;
2378
2379         writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
2380
2381         qmp_combo_configure_dp_mode(qmp);
2382
2383         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2384         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2385
2386         writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
2387         writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
2388
2389         ret = qmp_combo_configure_dp_clocks(qmp);
2390         if (ret)
2391                 return ret;
2392
2393         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2394         writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2395         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2396         writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2397
2398         writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
2399
2400         if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
2401                         status,
2402                         ((status & BIT(0)) > 0),
2403                         500,
2404                         10000))
2405                 return -ETIMEDOUT;
2406
2407         if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
2408                         status,
2409                         ((status & BIT(0)) > 0),
2410                         500,
2411                         10000))
2412                 return -ETIMEDOUT;
2413
2414         if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
2415                         status,
2416                         ((status & BIT(1)) > 0),
2417                         500,
2418                         10000))
2419                 return -ETIMEDOUT;
2420
2421         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2422
2423         if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2424                         status,
2425                         ((status & BIT(0)) > 0),
2426                         500,
2427                         10000))
2428                 return -ETIMEDOUT;
2429
2430         if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2431                         status,
2432                         ((status & BIT(1)) > 0),
2433                         500,
2434                         10000))
2435                 return -ETIMEDOUT;
2436
2437         return 0;
2438 }
2439
2440 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
2441 {
2442         const struct qmp_phy_cfg *cfg = qmp->cfg;
2443         bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2444         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2445         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2446         u32 status;
2447         int ret;
2448
2449         ret = qmp_v456_configure_dp_phy(qmp);
2450         if (ret < 0)
2451                 return ret;
2452
2453         /*
2454          * At least for 7nm DP PHY this has to be done after enabling link
2455          * clock.
2456          */
2457
2458         if (dp_opts->lanes == 1) {
2459                 bias0_en = reverse ? 0x3e : 0x15;
2460                 bias1_en = reverse ? 0x15 : 0x3e;
2461                 drvr0_en = reverse ? 0x13 : 0x10;
2462                 drvr1_en = reverse ? 0x10 : 0x13;
2463         } else if (dp_opts->lanes == 2) {
2464                 bias0_en = reverse ? 0x3f : 0x15;
2465                 bias1_en = reverse ? 0x15 : 0x3f;
2466                 drvr0_en = 0x10;
2467                 drvr1_en = 0x10;
2468         } else {
2469                 bias0_en = 0x3f;
2470                 bias1_en = 0x3f;
2471                 drvr0_en = 0x10;
2472                 drvr1_en = 0x10;
2473         }
2474
2475         writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2476         writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2477         writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2478         writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2479
2480         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2481         udelay(2000);
2482         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2483
2484         if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2485                         status,
2486                         ((status & BIT(1)) > 0),
2487                         500,
2488                         10000))
2489                 return -ETIMEDOUT;
2490
2491         writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
2492         writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
2493
2494         writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2495         writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2496
2497         writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2498         writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2499
2500         return 0;
2501
2502         return 0;
2503 }
2504
2505 /*
2506  * We need to calibrate the aux setting here as many times
2507  * as the caller tries
2508  */
2509 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
2510 {
2511         static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
2512         u8 val;
2513
2514         qmp->dp_aux_cfg++;
2515         qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2516         val = cfg1_settings[qmp->dp_aux_cfg];
2517
2518         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2519
2520         return 0;
2521 }
2522
2523 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts)
2524 {
2525         const struct phy_configure_opts_dp *dp_opts = &opts->dp;
2526         struct qmp_combo *qmp = phy_get_drvdata(phy);
2527         const struct qmp_phy_cfg *cfg = qmp->cfg;
2528
2529         mutex_lock(&qmp->phy_mutex);
2530
2531         memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts));
2532         if (qmp->dp_opts.set_voltages) {
2533                 cfg->configure_dp_tx(qmp);
2534                 qmp->dp_opts.set_voltages = 0;
2535         }
2536
2537         mutex_unlock(&qmp->phy_mutex);
2538
2539         return 0;
2540 }
2541
2542 static int qmp_combo_dp_calibrate(struct phy *phy)
2543 {
2544         struct qmp_combo *qmp = phy_get_drvdata(phy);
2545         const struct qmp_phy_cfg *cfg = qmp->cfg;
2546         int ret = 0;
2547
2548         mutex_lock(&qmp->phy_mutex);
2549
2550         if (cfg->calibrate_dp_phy)
2551                 ret = cfg->calibrate_dp_phy(qmp);
2552
2553         mutex_unlock(&qmp->phy_mutex);
2554
2555         return ret;
2556 }
2557
2558 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
2559 {
2560         const struct qmp_phy_cfg *cfg = qmp->cfg;
2561         void __iomem *com = qmp->com;
2562         int ret;
2563         u32 val;
2564
2565         if (!force && qmp->init_count++)
2566                 return 0;
2567
2568         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2569         if (ret) {
2570                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2571                 goto err_decrement_count;
2572         }
2573
2574         ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2575         if (ret) {
2576                 dev_err(qmp->dev, "reset assert failed\n");
2577                 goto err_disable_regulators;
2578         }
2579
2580         ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2581         if (ret) {
2582                 dev_err(qmp->dev, "reset deassert failed\n");
2583                 goto err_disable_regulators;
2584         }
2585
2586         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
2587         if (ret)
2588                 goto err_assert_reset;
2589
2590         qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN);
2591
2592         /* override hardware control for reset of qmp phy */
2593         qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2594                         SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2595                         SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2596
2597         /* Use software based port select and switch on typec orientation */
2598         val = SW_PORTSELECT_MUX;
2599         if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
2600                 val |= SW_PORTSELECT_VAL;
2601         writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL);
2602         writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
2603
2604         /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2605         qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2606                         SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2607                         SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2608
2609         qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2610         qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2611
2612         qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2613                         SW_PWRDN);
2614
2615         return 0;
2616
2617 err_assert_reset:
2618         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2619 err_disable_regulators:
2620         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2621 err_decrement_count:
2622         qmp->init_count--;
2623
2624         return ret;
2625 }
2626
2627 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force)
2628 {
2629         const struct qmp_phy_cfg *cfg = qmp->cfg;
2630
2631         if (!force && --qmp->init_count)
2632                 return 0;
2633
2634         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2635
2636         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2637
2638         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2639
2640         return 0;
2641 }
2642
2643 static int qmp_combo_dp_init(struct phy *phy)
2644 {
2645         struct qmp_combo *qmp = phy_get_drvdata(phy);
2646         const struct qmp_phy_cfg *cfg = qmp->cfg;
2647         int ret;
2648
2649         mutex_lock(&qmp->phy_mutex);
2650
2651         ret = qmp_combo_com_init(qmp, false);
2652         if (ret)
2653                 goto out_unlock;
2654
2655         cfg->dp_aux_init(qmp);
2656
2657         qmp->dp_init_count++;
2658
2659 out_unlock:
2660         mutex_unlock(&qmp->phy_mutex);
2661         return ret;
2662 }
2663
2664 static int qmp_combo_dp_exit(struct phy *phy)
2665 {
2666         struct qmp_combo *qmp = phy_get_drvdata(phy);
2667
2668         mutex_lock(&qmp->phy_mutex);
2669
2670         qmp_combo_com_exit(qmp, false);
2671
2672         qmp->dp_init_count--;
2673
2674         mutex_unlock(&qmp->phy_mutex);
2675
2676         return 0;
2677 }
2678
2679 static int qmp_combo_dp_power_on(struct phy *phy)
2680 {
2681         struct qmp_combo *qmp = phy_get_drvdata(phy);
2682         const struct qmp_phy_cfg *cfg = qmp->cfg;
2683         void __iomem *tx = qmp->dp_tx;
2684         void __iomem *tx2 = qmp->dp_tx2;
2685
2686         mutex_lock(&qmp->phy_mutex);
2687
2688         qmp_combo_dp_serdes_init(qmp);
2689
2690         qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2691         qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
2692
2693         /* Configure special DP tx tunings */
2694         cfg->configure_dp_tx(qmp);
2695
2696         /* Configure link rate, swing, etc. */
2697         cfg->configure_dp_phy(qmp);
2698
2699         mutex_unlock(&qmp->phy_mutex);
2700
2701         return 0;
2702 }
2703
2704 static int qmp_combo_dp_power_off(struct phy *phy)
2705 {
2706         struct qmp_combo *qmp = phy_get_drvdata(phy);
2707
2708         mutex_lock(&qmp->phy_mutex);
2709
2710         /* Assert DP PHY power down */
2711         writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2712
2713         mutex_unlock(&qmp->phy_mutex);
2714
2715         return 0;
2716 }
2717
2718 static int qmp_combo_usb_power_on(struct phy *phy)
2719 {
2720         struct qmp_combo *qmp = phy_get_drvdata(phy);
2721         const struct qmp_phy_cfg *cfg = qmp->cfg;
2722         void __iomem *serdes = qmp->serdes;
2723         void __iomem *tx = qmp->tx;
2724         void __iomem *rx = qmp->rx;
2725         void __iomem *tx2 = qmp->tx2;
2726         void __iomem *rx2 = qmp->rx2;
2727         void __iomem *pcs = qmp->pcs;
2728         void __iomem *pcs_usb = qmp->pcs_usb;
2729         void __iomem *status;
2730         unsigned int val;
2731         int ret;
2732
2733         qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
2734
2735         ret = clk_prepare_enable(qmp->pipe_clk);
2736         if (ret) {
2737                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2738                 return ret;
2739         }
2740
2741         /* Tx, Rx, and PCS configurations */
2742         qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2743         qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2744
2745         qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2746         qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2747
2748         qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2749
2750         if (pcs_usb)
2751                 qmp_combo_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
2752
2753         if (cfg->has_pwrdn_delay)
2754                 usleep_range(10, 20);
2755
2756         /* Pull PHY out of reset state */
2757         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2758
2759         /* start SerDes and Phy-Coding-Sublayer */
2760         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2761
2762         status = pcs + cfg->regs[QPHY_PCS_STATUS];
2763         ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
2764                         PHY_INIT_COMPLETE_TIMEOUT);
2765         if (ret) {
2766                 dev_err(qmp->dev, "phy initialization timed-out\n");
2767                 goto err_disable_pipe_clk;
2768         }
2769
2770         return 0;
2771
2772 err_disable_pipe_clk:
2773         clk_disable_unprepare(qmp->pipe_clk);
2774
2775         return ret;
2776 }
2777
2778 static int qmp_combo_usb_power_off(struct phy *phy)
2779 {
2780         struct qmp_combo *qmp = phy_get_drvdata(phy);
2781         const struct qmp_phy_cfg *cfg = qmp->cfg;
2782
2783         clk_disable_unprepare(qmp->pipe_clk);
2784
2785         /* PHY reset */
2786         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2787
2788         /* stop SerDes and Phy-Coding-Sublayer */
2789         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
2790                         SERDES_START | PCS_START);
2791
2792         /* Put PHY into POWER DOWN state: active low */
2793         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2794                         SW_PWRDN);
2795
2796         return 0;
2797 }
2798
2799 static int qmp_combo_usb_init(struct phy *phy)
2800 {
2801         struct qmp_combo *qmp = phy_get_drvdata(phy);
2802         int ret;
2803
2804         mutex_lock(&qmp->phy_mutex);
2805         ret = qmp_combo_com_init(qmp, false);
2806         if (ret)
2807                 goto out_unlock;
2808
2809         ret = qmp_combo_usb_power_on(phy);
2810         if (ret) {
2811                 qmp_combo_com_exit(qmp, false);
2812                 goto out_unlock;
2813         }
2814
2815         qmp->usb_init_count++;
2816
2817 out_unlock:
2818         mutex_unlock(&qmp->phy_mutex);
2819         return ret;
2820 }
2821
2822 static int qmp_combo_usb_exit(struct phy *phy)
2823 {
2824         struct qmp_combo *qmp = phy_get_drvdata(phy);
2825         int ret;
2826
2827         mutex_lock(&qmp->phy_mutex);
2828         ret = qmp_combo_usb_power_off(phy);
2829         if (ret)
2830                 goto out_unlock;
2831
2832         ret = qmp_combo_com_exit(qmp, false);
2833         if (ret)
2834                 goto out_unlock;
2835
2836         qmp->usb_init_count--;
2837
2838 out_unlock:
2839         mutex_unlock(&qmp->phy_mutex);
2840         return ret;
2841 }
2842
2843 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2844 {
2845         struct qmp_combo *qmp = phy_get_drvdata(phy);
2846
2847         qmp->mode = mode;
2848
2849         return 0;
2850 }
2851
2852 static const struct phy_ops qmp_combo_usb_phy_ops = {
2853         .init           = qmp_combo_usb_init,
2854         .exit           = qmp_combo_usb_exit,
2855         .set_mode       = qmp_combo_usb_set_mode,
2856         .owner          = THIS_MODULE,
2857 };
2858
2859 static const struct phy_ops qmp_combo_dp_phy_ops = {
2860         .init           = qmp_combo_dp_init,
2861         .configure      = qmp_combo_dp_configure,
2862         .power_on       = qmp_combo_dp_power_on,
2863         .calibrate      = qmp_combo_dp_calibrate,
2864         .power_off      = qmp_combo_dp_power_off,
2865         .exit           = qmp_combo_dp_exit,
2866         .owner          = THIS_MODULE,
2867 };
2868
2869 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp)
2870 {
2871         const struct qmp_phy_cfg *cfg = qmp->cfg;
2872         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2873         void __iomem *pcs_misc = qmp->pcs_misc;
2874         u32 intr_mask;
2875
2876         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2877             qmp->mode == PHY_MODE_USB_DEVICE_SS)
2878                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2879         else
2880                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2881
2882         /* Clear any pending interrupts status */
2883         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2884         /* Writing 1 followed by 0 clears the interrupt */
2885         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2886
2887         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2888                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2889
2890         /* Enable required PHY autonomous mode interrupts */
2891         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2892
2893         /* Enable i/o clamp_n for autonomous mode */
2894         if (pcs_misc)
2895                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2896 }
2897
2898 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
2899 {
2900         const struct qmp_phy_cfg *cfg = qmp->cfg;
2901         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2902         void __iomem *pcs_misc = qmp->pcs_misc;
2903
2904         /* Disable i/o clamp_n on resume for normal mode */
2905         if (pcs_misc)
2906                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2907
2908         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2909                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2910
2911         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2912         /* Writing 1 followed by 0 clears the interrupt */
2913         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2914 }
2915
2916 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev)
2917 {
2918         struct qmp_combo *qmp = dev_get_drvdata(dev);
2919
2920         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2921
2922         if (!qmp->init_count) {
2923                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2924                 return 0;
2925         }
2926
2927         qmp_combo_enable_autonomous_mode(qmp);
2928
2929         clk_disable_unprepare(qmp->pipe_clk);
2930         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2931
2932         return 0;
2933 }
2934
2935 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev)
2936 {
2937         struct qmp_combo *qmp = dev_get_drvdata(dev);
2938         int ret = 0;
2939
2940         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2941
2942         if (!qmp->init_count) {
2943                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2944                 return 0;
2945         }
2946
2947         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
2948         if (ret)
2949                 return ret;
2950
2951         ret = clk_prepare_enable(qmp->pipe_clk);
2952         if (ret) {
2953                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2954                 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2955                 return ret;
2956         }
2957
2958         qmp_combo_disable_autonomous_mode(qmp);
2959
2960         return 0;
2961 }
2962
2963 static const struct dev_pm_ops qmp_combo_pm_ops = {
2964         SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend,
2965                            qmp_combo_runtime_resume, NULL)
2966 };
2967
2968 static int qmp_combo_vreg_init(struct qmp_combo *qmp)
2969 {
2970         const struct qmp_phy_cfg *cfg = qmp->cfg;
2971         struct device *dev = qmp->dev;
2972         int num = cfg->num_vregs;
2973         int ret, i;
2974
2975         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2976         if (!qmp->vregs)
2977                 return -ENOMEM;
2978
2979         for (i = 0; i < num; i++)
2980                 qmp->vregs[i].supply = cfg->vreg_list[i].name;
2981
2982         ret = devm_regulator_bulk_get(dev, num, qmp->vregs);
2983         if (ret) {
2984                 dev_err(dev, "failed at devm_regulator_bulk_get\n");
2985                 return ret;
2986         }
2987
2988         for (i = 0; i < num; i++) {
2989                 ret = regulator_set_load(qmp->vregs[i].consumer,
2990                                         cfg->vreg_list[i].enable_load);
2991                 if (ret) {
2992                         dev_err(dev, "failed to set load at %s\n",
2993                                 qmp->vregs[i].supply);
2994                         return ret;
2995                 }
2996         }
2997
2998         return 0;
2999 }
3000
3001 static int qmp_combo_reset_init(struct qmp_combo *qmp)
3002 {
3003         const struct qmp_phy_cfg *cfg = qmp->cfg;
3004         struct device *dev = qmp->dev;
3005         int i;
3006         int ret;
3007
3008         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
3009                                    sizeof(*qmp->resets), GFP_KERNEL);
3010         if (!qmp->resets)
3011                 return -ENOMEM;
3012
3013         for (i = 0; i < cfg->num_resets; i++)
3014                 qmp->resets[i].id = cfg->reset_list[i];
3015
3016         ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
3017         if (ret)
3018                 return dev_err_probe(dev, ret, "failed to get resets\n");
3019
3020         return 0;
3021 }
3022
3023 static int qmp_combo_clk_init(struct qmp_combo *qmp)
3024 {
3025         struct device *dev = qmp->dev;
3026         int num = ARRAY_SIZE(qmp_combo_phy_clk_l);
3027         int i;
3028
3029         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
3030         if (!qmp->clks)
3031                 return -ENOMEM;
3032
3033         for (i = 0; i < num; i++)
3034                 qmp->clks[i].id = qmp_combo_phy_clk_l[i];
3035
3036         qmp->num_clks = num;
3037
3038         return devm_clk_bulk_get_optional(dev, num, qmp->clks);
3039 }
3040
3041 static void phy_clk_release_provider(void *res)
3042 {
3043         of_clk_del_provider(res);
3044 }
3045
3046 /*
3047  * Register a fixed rate pipe clock.
3048  *
3049  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
3050  * controls it. The <s>_pipe_clk coming out of the GCC is requested
3051  * by the PHY driver for its operations.
3052  * We register the <s>_pipe_clksrc here. The gcc driver takes care
3053  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
3054  * Below picture shows this relationship.
3055  *
3056  *         +---------------+
3057  *         |   PHY block   |<<---------------------------------------+
3058  *         |               |                                         |
3059  *         |   +-------+   |                   +-----+               |
3060  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3061  *    clk  |   +-------+   |                   +-----+
3062  *         +---------------+
3063  */
3064 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np)
3065 {
3066         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
3067         struct clk_init_data init = { };
3068         char name[64];
3069
3070         snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev));
3071         init.name = name;
3072         init.ops = &clk_fixed_rate_ops;
3073
3074         /* controllers using QMP phys use 125MHz pipe clock interface */
3075         fixed->fixed_rate = 125000000;
3076         fixed->hw.init = &init;
3077
3078         return devm_clk_hw_register(qmp->dev, &fixed->hw);
3079 }
3080
3081 /*
3082  * Display Port PLL driver block diagram for branch clocks
3083  *
3084  *              +------------------------------+
3085  *              |         DP_VCO_CLK           |
3086  *              |                              |
3087  *              |    +-------------------+     |
3088  *              |    |   (DP PLL/VCO)    |     |
3089  *              |    +---------+---------+     |
3090  *              |              v               |
3091  *              |   +----------+-----------+   |
3092  *              |   | hsclk_divsel_clk_src |   |
3093  *              |   +----------+-----------+   |
3094  *              +------------------------------+
3095  *                              |
3096  *          +---------<---------v------------>----------+
3097  *          |                                           |
3098  * +--------v----------------+                          |
3099  * |    dp_phy_pll_link_clk  |                          |
3100  * |     link_clk            |                          |
3101  * +--------+----------------+                          |
3102  *          |                                           |
3103  *          |                                           |
3104  *          v                                           v
3105  * Input to DISPCC block                                |
3106  * for link clk, crypto clk                             |
3107  * and interface clock                                  |
3108  *                                                      |
3109  *                                                      |
3110  *      +--------<------------+-----------------+---<---+
3111  *      |                     |                 |
3112  * +----v---------+  +--------v-----+  +--------v------+
3113  * | vco_divided  |  | vco_divided  |  | vco_divided   |
3114  * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
3115  * |              |  |              |  |               |
3116  * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
3117  * +-------+------+  +-----+--------+  +--------+------+
3118  *         |                 |                  |
3119  *         v---->----------v-------------<------v
3120  *                         |
3121  *              +----------+-----------------+
3122  *              |   dp_phy_pll_vco_div_clk   |
3123  *              +---------+------------------+
3124  *                        |
3125  *                        v
3126  *              Input to DISPCC block
3127  *              for DP pixel clock
3128  *
3129  */
3130 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3131 {
3132         switch (req->rate) {
3133         case 1620000000UL / 2:
3134         case 2700000000UL / 2:
3135         /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3136                 return 0;
3137         default:
3138                 return -EINVAL;
3139         }
3140 }
3141
3142 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3143 {
3144         const struct qmp_combo *qmp;
3145         const struct phy_configure_opts_dp *dp_opts;
3146
3147         qmp = container_of(hw, struct qmp_combo, dp_pixel_hw);
3148         dp_opts = &qmp->dp_opts;
3149
3150         switch (dp_opts->link_rate) {
3151         case 1620:
3152                 return 1620000000UL / 2;
3153         case 2700:
3154                 return 2700000000UL / 2;
3155         case 5400:
3156                 return 5400000000UL / 4;
3157         case 8100:
3158                 return 8100000000UL / 6;
3159         default:
3160                 return 0;
3161         }
3162 }
3163
3164 static const struct clk_ops qmp_dp_pixel_clk_ops = {
3165         .determine_rate = qmp_dp_pixel_clk_determine_rate,
3166         .recalc_rate    = qmp_dp_pixel_clk_recalc_rate,
3167 };
3168
3169 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3170 {
3171         switch (req->rate) {
3172         case 162000000:
3173         case 270000000:
3174         case 540000000:
3175         case 810000000:
3176                 return 0;
3177         default:
3178                 return -EINVAL;
3179         }
3180 }
3181
3182 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3183 {
3184         const struct qmp_combo *qmp;
3185         const struct phy_configure_opts_dp *dp_opts;
3186
3187         qmp = container_of(hw, struct qmp_combo, dp_link_hw);
3188         dp_opts = &qmp->dp_opts;
3189
3190         switch (dp_opts->link_rate) {
3191         case 1620:
3192         case 2700:
3193         case 5400:
3194         case 8100:
3195                 return dp_opts->link_rate * 100000;
3196         default:
3197                 return 0;
3198         }
3199 }
3200
3201 static const struct clk_ops qmp_dp_link_clk_ops = {
3202         .determine_rate = qmp_dp_link_clk_determine_rate,
3203         .recalc_rate    = qmp_dp_link_clk_recalc_rate,
3204 };
3205
3206 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
3207 {
3208         struct qmp_combo *qmp = data;
3209         unsigned int idx = clkspec->args[0];
3210
3211         if (idx >= 2) {
3212                 pr_err("%s: invalid index %u\n", __func__, idx);
3213                 return ERR_PTR(-EINVAL);
3214         }
3215
3216         if (idx == 0)
3217                 return &qmp->dp_link_hw;
3218
3219         return &qmp->dp_pixel_hw;
3220 }
3221
3222 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np)
3223 {
3224         struct clk_init_data init = { };
3225         char name[64];
3226         int ret;
3227
3228         snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
3229         init.ops = &qmp_dp_link_clk_ops;
3230         init.name = name;
3231         qmp->dp_link_hw.init = &init;
3232         ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw);
3233         if (ret)
3234                 return ret;
3235
3236         snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
3237         init.ops = &qmp_dp_pixel_clk_ops;
3238         init.name = name;
3239         qmp->dp_pixel_hw.init = &init;
3240         ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw);
3241         if (ret)
3242                 return ret;
3243
3244         return 0;
3245 }
3246
3247 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data)
3248 {
3249         struct qmp_combo *qmp = data;
3250
3251         switch (clkspec->args[0]) {
3252         case QMP_USB43DP_USB3_PIPE_CLK:
3253                 return &qmp->pipe_clk_fixed.hw;
3254         case QMP_USB43DP_DP_LINK_CLK:
3255                 return &qmp->dp_link_hw;
3256         case QMP_USB43DP_DP_VCO_DIV_CLK:
3257                 return &qmp->dp_pixel_hw;
3258         }
3259
3260         return ERR_PTR(-EINVAL);
3261 }
3262
3263 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np,
3264                                         struct device_node *dp_np)
3265 {
3266         int ret;
3267
3268         ret = phy_pipe_clk_register(qmp, usb_np);
3269         if (ret)
3270                 return ret;
3271
3272         ret = phy_dp_clks_register(qmp, dp_np);
3273         if (ret)
3274                 return ret;
3275
3276         /*
3277          * Register a single provider for bindings without child nodes.
3278          */
3279         if (usb_np == qmp->dev->of_node)
3280                 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp);
3281
3282         /*
3283          * Register multiple providers for legacy bindings with child nodes.
3284          */
3285         ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get,
3286                                         &qmp->pipe_clk_fixed.hw);
3287         if (ret)
3288                 return ret;
3289
3290         /*
3291          * Roll a devm action because the clock provider is the child node, but
3292          * the child node is not actually a device.
3293          */
3294         ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np);
3295         if (ret)
3296                 return ret;
3297
3298         ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp);
3299         if (ret)
3300                 return ret;
3301
3302         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np);
3303 }
3304
3305 #if IS_ENABLED(CONFIG_TYPEC)
3306 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw,
3307                                       enum typec_orientation orientation)
3308 {
3309         struct qmp_combo *qmp = typec_switch_get_drvdata(sw);
3310         const struct qmp_phy_cfg *cfg = qmp->cfg;
3311
3312         if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
3313                 return 0;
3314
3315         mutex_lock(&qmp->phy_mutex);
3316         qmp->orientation = orientation;
3317
3318         if (qmp->init_count) {
3319                 if (qmp->usb_init_count)
3320                         qmp_combo_usb_power_off(qmp->usb_phy);
3321                 qmp_combo_com_exit(qmp, true);
3322
3323                 qmp_combo_com_init(qmp, true);
3324                 if (qmp->usb_init_count)
3325                         qmp_combo_usb_power_on(qmp->usb_phy);
3326                 if (qmp->dp_init_count)
3327                         cfg->dp_aux_init(qmp);
3328         }
3329         mutex_unlock(&qmp->phy_mutex);
3330
3331         return 0;
3332 }
3333
3334 static void qmp_combo_typec_unregister(void *data)
3335 {
3336         struct qmp_combo *qmp = data;
3337
3338         typec_switch_unregister(qmp->sw);
3339 }
3340
3341 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3342 {
3343         struct typec_switch_desc sw_desc = {};
3344         struct device *dev = qmp->dev;
3345
3346         sw_desc.drvdata = qmp;
3347         sw_desc.fwnode = dev->fwnode;
3348         sw_desc.set = qmp_combo_typec_switch_set;
3349         qmp->sw = typec_switch_register(dev, &sw_desc);
3350         if (IS_ERR(qmp->sw)) {
3351                 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
3352                 return PTR_ERR(qmp->sw);
3353         }
3354
3355         return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp);
3356 }
3357 #else
3358 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3359 {
3360         return 0;
3361 }
3362 #endif
3363
3364 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np)
3365 {
3366         struct device *dev = qmp->dev;
3367
3368         /*
3369          * Get memory resources from the DP child node:
3370          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3371          * tx2 -> 3; rx2 -> 4
3372          *
3373          * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
3374          * implementation.
3375          */
3376         qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
3377         if (IS_ERR(qmp->dp_tx))
3378                 return PTR_ERR(qmp->dp_tx);
3379
3380         qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
3381         if (IS_ERR(qmp->dp_dp_phy))
3382                 return PTR_ERR(qmp->dp_dp_phy);
3383
3384         qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
3385         if (IS_ERR(qmp->dp_tx2))
3386                 return PTR_ERR(qmp->dp_tx2);
3387
3388         return 0;
3389 }
3390
3391 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np)
3392 {
3393         const struct qmp_phy_cfg *cfg = qmp->cfg;
3394         struct device *dev = qmp->dev;
3395
3396         /*
3397          * Get memory resources from the USB child node:
3398          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3399          * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5
3400          */
3401         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3402         if (IS_ERR(qmp->tx))
3403                 return PTR_ERR(qmp->tx);
3404
3405         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3406         if (IS_ERR(qmp->rx))
3407                 return PTR_ERR(qmp->rx);
3408
3409         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3410         if (IS_ERR(qmp->pcs))
3411                 return PTR_ERR(qmp->pcs);
3412
3413         if (cfg->pcs_usb_offset)
3414                 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
3415
3416         qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3417         if (IS_ERR(qmp->tx2))
3418                 return PTR_ERR(qmp->tx2);
3419
3420         qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
3421         if (IS_ERR(qmp->rx2))
3422                 return PTR_ERR(qmp->rx2);
3423
3424         qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
3425         if (IS_ERR(qmp->pcs_misc)) {
3426                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
3427                 qmp->pcs_misc = NULL;
3428         }
3429
3430         qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
3431         if (IS_ERR(qmp->pipe_clk)) {
3432                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3433                                      "failed to get pipe clock\n");
3434         }
3435
3436         return 0;
3437 }
3438
3439 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np,
3440                                         struct device_node *dp_np)
3441 {
3442         struct platform_device *pdev = to_platform_device(qmp->dev);
3443         int ret;
3444
3445         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
3446         if (IS_ERR(qmp->serdes))
3447                 return PTR_ERR(qmp->serdes);
3448
3449         qmp->com = devm_platform_ioremap_resource(pdev, 1);
3450         if (IS_ERR(qmp->com))
3451                 return PTR_ERR(qmp->com);
3452
3453         qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2);
3454         if (IS_ERR(qmp->dp_serdes))
3455                 return PTR_ERR(qmp->dp_serdes);
3456
3457         ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np);
3458         if (ret)
3459                 return ret;
3460
3461         ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np);
3462         if (ret)
3463                 return ret;
3464
3465         ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
3466         if (ret < 0)
3467                 return ret;
3468
3469         qmp->num_clks = ret;
3470
3471         return 0;
3472 }
3473
3474 static int qmp_combo_parse_dt(struct qmp_combo *qmp)
3475 {
3476         struct platform_device *pdev = to_platform_device(qmp->dev);
3477         const struct qmp_phy_cfg *cfg = qmp->cfg;
3478         const struct qmp_combo_offsets *offs = cfg->offsets;
3479         struct device *dev = qmp->dev;
3480         void __iomem *base;
3481         int ret;
3482
3483         if (!offs)
3484                 return -EINVAL;
3485
3486         base = devm_platform_ioremap_resource(pdev, 0);
3487         if (IS_ERR(base))
3488                 return PTR_ERR(base);
3489
3490         qmp->com = base + offs->com;
3491         qmp->tx = base + offs->txa;
3492         qmp->rx = base + offs->rxa;
3493         qmp->tx2 = base + offs->txb;
3494         qmp->rx2 = base + offs->rxb;
3495
3496         qmp->serdes = base + offs->usb3_serdes;
3497         qmp->pcs_misc = base + offs->usb3_pcs_misc;
3498         qmp->pcs = base + offs->usb3_pcs;
3499         qmp->pcs_usb = base + offs->usb3_pcs_usb;
3500
3501         qmp->dp_serdes = base + offs->dp_serdes;
3502         if (offs->dp_txa) {
3503                 qmp->dp_tx = base + offs->dp_txa;
3504                 qmp->dp_tx2 = base + offs->dp_txb;
3505         } else {
3506                 qmp->dp_tx = base + offs->txa;
3507                 qmp->dp_tx2 = base + offs->txb;
3508         }
3509         qmp->dp_dp_phy = base + offs->dp_dp_phy;
3510
3511         ret = qmp_combo_clk_init(qmp);
3512         if (ret)
3513                 return ret;
3514
3515         qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
3516         if (IS_ERR(qmp->pipe_clk)) {
3517                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3518                                 "failed to get usb3_pipe clock\n");
3519         }
3520
3521         return 0;
3522 }
3523
3524 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args)
3525 {
3526         struct qmp_combo *qmp = dev_get_drvdata(dev);
3527
3528         if (args->args_count == 0)
3529                 return ERR_PTR(-EINVAL);
3530
3531         switch (args->args[0]) {
3532         case QMP_USB43DP_USB3_PHY:
3533                 return qmp->usb_phy;
3534         case QMP_USB43DP_DP_PHY:
3535                 return qmp->dp_phy;
3536         }
3537
3538         return ERR_PTR(-EINVAL);
3539 }
3540
3541 static int qmp_combo_probe(struct platform_device *pdev)
3542 {
3543         struct qmp_combo *qmp;
3544         struct device *dev = &pdev->dev;
3545         struct device_node *dp_np, *usb_np;
3546         struct phy_provider *phy_provider;
3547         int ret;
3548
3549         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3550         if (!qmp)
3551                 return -ENOMEM;
3552
3553         qmp->dev = dev;
3554
3555         qmp->orientation = TYPEC_ORIENTATION_NORMAL;
3556
3557         qmp->cfg = of_device_get_match_data(dev);
3558         if (!qmp->cfg)
3559                 return -EINVAL;
3560
3561         mutex_init(&qmp->phy_mutex);
3562
3563         ret = qmp_combo_reset_init(qmp);
3564         if (ret)
3565                 return ret;
3566
3567         ret = qmp_combo_vreg_init(qmp);
3568         if (ret)
3569                 return ret;
3570
3571         /* Check for legacy binding with child nodes. */
3572         usb_np = of_get_child_by_name(dev->of_node, "usb3-phy");
3573         if (usb_np) {
3574                 dp_np = of_get_child_by_name(dev->of_node, "dp-phy");
3575                 if (!dp_np) {
3576                         of_node_put(usb_np);
3577                         return -EINVAL;
3578                 }
3579
3580                 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np);
3581         } else {
3582                 usb_np = of_node_get(dev->of_node);
3583                 dp_np = of_node_get(dev->of_node);
3584
3585                 ret = qmp_combo_parse_dt(qmp);
3586         }
3587         if (ret)
3588                 goto err_node_put;
3589
3590         ret = qmp_combo_typec_switch_register(qmp);
3591         if (ret)
3592                 goto err_node_put;
3593
3594         ret = drm_aux_bridge_register(dev);
3595         if (ret)
3596                 goto err_node_put;
3597
3598         pm_runtime_set_active(dev);
3599         ret = devm_pm_runtime_enable(dev);
3600         if (ret)
3601                 goto err_node_put;
3602         /*
3603          * Prevent runtime pm from being ON by default. Users can enable
3604          * it using power/control in sysfs.
3605          */
3606         pm_runtime_forbid(dev);
3607
3608         ret = qmp_combo_register_clocks(qmp, usb_np, dp_np);
3609         if (ret)
3610                 goto err_node_put;
3611
3612         qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops);
3613         if (IS_ERR(qmp->usb_phy)) {
3614                 ret = PTR_ERR(qmp->usb_phy);
3615                 dev_err(dev, "failed to create USB PHY: %d\n", ret);
3616                 goto err_node_put;
3617         }
3618
3619         phy_set_drvdata(qmp->usb_phy, qmp);
3620
3621         qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops);
3622         if (IS_ERR(qmp->dp_phy)) {
3623                 ret = PTR_ERR(qmp->dp_phy);
3624                 dev_err(dev, "failed to create DP PHY: %d\n", ret);
3625                 goto err_node_put;
3626         }
3627
3628         phy_set_drvdata(qmp->dp_phy, qmp);
3629
3630         dev_set_drvdata(dev, qmp);
3631
3632         if (usb_np == dev->of_node)
3633                 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate);
3634         else
3635                 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3636
3637         of_node_put(usb_np);
3638         of_node_put(dp_np);
3639
3640         return PTR_ERR_OR_ZERO(phy_provider);
3641
3642 err_node_put:
3643         of_node_put(usb_np);
3644         of_node_put(dp_np);
3645         return ret;
3646 }
3647
3648 static const struct of_device_id qmp_combo_of_match_table[] = {
3649         {
3650                 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3651                 .data = &sc7180_usb3dpphy_cfg,
3652         },
3653         {
3654                 .compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3655                 .data = &sm8250_usb3dpphy_cfg,
3656         },
3657         {
3658                 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
3659                 .data = &sc8180x_usb3dpphy_cfg,
3660         },
3661         {
3662                 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
3663                 .data = &sc8280xp_usb43dpphy_cfg,
3664         },
3665         {
3666                 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
3667                 .data = &sdm845_usb3dpphy_cfg,
3668         },
3669         {
3670                 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
3671                 .data = &sm6350_usb3dpphy_cfg,
3672         },
3673         {
3674                 .compatible = "qcom,sm8150-qmp-usb3-dp-phy",
3675                 .data = &sc8180x_usb3dpphy_cfg,
3676         },
3677         {
3678                 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
3679                 .data = &sm8250_usb3dpphy_cfg,
3680         },
3681         {
3682                 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
3683                 .data = &sm8350_usb3dpphy_cfg,
3684         },
3685         {
3686                 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
3687                 .data = &sm8350_usb3dpphy_cfg,
3688         },
3689         {
3690                 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
3691                 .data = &sm8550_usb3dpphy_cfg,
3692         },
3693         {
3694                 .compatible = "qcom,sm8650-qmp-usb3-dp-phy",
3695                 .data = &sm8550_usb3dpphy_cfg,
3696         },
3697         {
3698                 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
3699                 .data = &x1e80100_usb3dpphy_cfg,
3700         },
3701         { }
3702 };
3703 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);
3704
3705 static struct platform_driver qmp_combo_driver = {
3706         .probe          = qmp_combo_probe,
3707         .driver = {
3708                 .name   = "qcom-qmp-combo-phy",
3709                 .pm     = &qmp_combo_pm_ops,
3710                 .of_match_table = qmp_combo_of_match_table,
3711         },
3712 };
3713
3714 module_platform_driver(qmp_combo_driver);
3715
3716 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
3717 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");
3718 MODULE_LICENSE("GPL v2");