drivers/phy/phy-omap-control.c

   1 /*
   2  * omap-control-phy.c - The PHY part of control module.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/clk.h>
  27 #include <linux/phy/omap_control_phy.h>
  28
  29 /**
  30  * omap_control_pcie_pcs - set the PCS delay count
  31  * @dev: the control module device
  32  * @delay: 8 bit delay value
  33  */
  34 void omap_control_pcie_pcs(struct device *dev, u8 delay)
  35 {
  36         u32 val;
  37         struct omap_control_phy *control_phy;
  38
  39         if (IS_ERR(dev) || !dev) {
  40                 pr_err("%s: invalid device\n", __func__);
  41                 return;
  42         }
  43
  44         control_phy = dev_get_drvdata(dev);
  45         if (!control_phy) {
  46                 dev_err(dev, "%s: invalid control phy device\n", __func__);
  47                 return;
  48         }
  49
  50         if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
  51                 dev_err(dev, "%s: unsupported operation\n", __func__);
  52                 return;
  53         }
  54
  55         val = readl(control_phy->pcie_pcs);
  56         val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
  57                 OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
  58         val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
  59         writel(val, control_phy->pcie_pcs);
  60 }
  61 EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
  62
  63 /**
  64  * omap_control_phy_power - power on/off the phy using control module reg
  65  * @dev: the control module device
  66  * @on: 0 or 1, based on powering on or off the PHY
  67  */
  68 void omap_control_phy_power(struct device *dev, int on)
  69 {
  70         u32 val;
  71         unsigned long rate;
  72         struct omap_control_phy *control_phy;
  73
  74         if (IS_ERR(dev) || !dev) {
  75                 pr_err("%s: invalid device\n", __func__);
  76                 return;
  77         }
  78
  79         control_phy = dev_get_drvdata(dev);
  80         if (!control_phy) {
  81                 dev_err(dev, "%s: invalid control phy device\n", __func__);
  82                 return;
  83         }
  84
  85         if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
  86                 return;
  87
  88         val = readl(control_phy->power);
  89
  90         switch (control_phy->type) {
  91         case OMAP_CTRL_TYPE_USB2:
  92                 if (on)
  93                         val &= ~OMAP_CTRL_DEV_PHY_PD;
  94                 else
  95                         val |= OMAP_CTRL_DEV_PHY_PD;
  96                 break;
  97
  98         case OMAP_CTRL_TYPE_PCIE:
  99         case OMAP_CTRL_TYPE_PIPE3:
 100                 rate = clk_get_rate(control_phy->sys_clk);
 101                 rate = rate/1000000;
 102
 103                 if (on) {
 104                         val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
 105                                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
 106                         val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
 107                                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 108                         val |= rate <<
 109                                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 110                 } else {
 111                         val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
 112                         val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
 113                                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 114                 }
 115                 break;
 116
 117         case OMAP_CTRL_TYPE_DRA7USB2:
 118                 if (on)
 119                         val &= ~OMAP_CTRL_USB2_PHY_PD;
 120                 else
 121                         val |= OMAP_CTRL_USB2_PHY_PD;
 122                 break;
 123
 124         case OMAP_CTRL_TYPE_AM437USB2:
 125                 if (on) {
 126                         val &= ~(AM437X_CTRL_USB2_PHY_PD |
 127                                         AM437X_CTRL_USB2_OTG_PD);
 128                         val |= (AM437X_CTRL_USB2_OTGVDET_EN |
 129                                         AM437X_CTRL_USB2_OTGSESSEND_EN);
 130                 } else {
 131                         val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
 132                                         AM437X_CTRL_USB2_OTGSESSEND_EN);
 133                         val |= (AM437X_CTRL_USB2_PHY_PD |
 134                                          AM437X_CTRL_USB2_OTG_PD);
 135                 }
 136                 break;
 137         default:
 138                 dev_err(dev, "%s: type %d not recognized\n",
 139                         __func__, control_phy->type);
 140                 break;
 141         }
 142
 143         writel(val, control_phy->power);
 144 }
 145 EXPORT_SYMBOL_GPL(omap_control_phy_power);
 146
 147 /**
 148  * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
 149  * @ctrl_phy: struct omap_control_phy *
 150  *
 151  * Writes to the mailbox register to notify the usb core that a usb
 152  * device has been connected.
 153  */
 154 static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
 155 {
 156         u32 val;
 157
 158         val = readl(ctrl_phy->otghs_control);
 159         val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
 160         val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
 161         writel(val, ctrl_phy->otghs_control);
 162 }
 163
 164 /**
 165  * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
 166  * impedance
 167  * @ctrl_phy: struct omap_control_phy *
 168  *
 169  * Writes to the mailbox register to notify the usb core that it has been
 170  * connected to a usb host.
 171  */
 172 static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
 173 {
 174         u32 val;
 175
 176         val = readl(ctrl_phy->otghs_control);
 177         val &= ~OMAP_CTRL_DEV_SESSEND;
 178         val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
 179                 OMAP_CTRL_DEV_VBUSVALID;
 180         writel(val, ctrl_phy->otghs_control);
 181 }
 182
 183 /**
 184  * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
 185  * impedance
 186  * @ctrl_phy: struct omap_control_phy *
 187  *
 188  * Writes to the mailbox register to notify the usb core it's now in
 189  * disconnected state.
 190  */
 191 static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
 192 {
 193         u32 val;
 194
 195         val = readl(ctrl_phy->otghs_control);
 196         val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
 197         val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
 198         writel(val, ctrl_phy->otghs_control);
 199 }
 200
 201 /**
 202  * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
 203  * or device mode or to denote disconnected state
 204  * @dev: the control module device
 205  * @mode: The mode to which usb should be configured
 206  *
 207  * This is an API to write to the mailbox register to notify the usb core that
 208  * a usb device has been connected.
 209  */
 210 void omap_control_usb_set_mode(struct device *dev,
 211         enum omap_control_usb_mode mode)
 212 {
 213         struct omap_control_phy *ctrl_phy;
 214
 215         if (IS_ERR(dev) || !dev)
 216                 return;
 217
 218         ctrl_phy = dev_get_drvdata(dev);
 219         if (!ctrl_phy) {
 220                 dev_err(dev, "Invalid control phy device\n");
 221                 return;
 222         }
 223
 224         if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
 225                 return;
 226
 227         switch (mode) {
 228         case USB_MODE_HOST:
 229                 omap_control_usb_host_mode(ctrl_phy);
 230                 break;
 231         case USB_MODE_DEVICE:
 232                 omap_control_usb_device_mode(ctrl_phy);
 233                 break;
 234         case USB_MODE_DISCONNECT:
 235                 omap_control_usb_set_sessionend(ctrl_phy);
 236                 break;
 237         default:
 238                 dev_vdbg(dev, "invalid omap control usb mode\n");
 239         }
 240 }
 241 EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
 242
 243 static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
 244 static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
 245 static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
 246 static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
 247 static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
 248 static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
 249
 250 static const struct of_device_id omap_control_phy_id_table[] = {
 251         {
 252                 .compatible = "ti,control-phy-otghs",
 253                 .data = &otghs_data,
 254         },
 255         {
 256                 .compatible = "ti,control-phy-usb2",
 257                 .data = &usb2_data,
 258         },
 259         {
 260                 .compatible = "ti,control-phy-pipe3",
 261                 .data = &pipe3_data,
 262         },
 263         {
 264                 .compatible = "ti,control-phy-pcie",
 265                 .data = &pcie_data,
 266         },
 267         {
 268                 .compatible = "ti,control-phy-usb2-dra7",
 269                 .data = &dra7usb2_data,
 270         },
 271         {
 272                 .compatible = "ti,control-phy-usb2-am437",
 273                 .data = &am437usb2_data,
 274         },
 275         {},
 276 };
 277 MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
 278
 279 static int omap_control_phy_probe(struct platform_device *pdev)
 280 {
 281         struct resource *res;
 282         const struct of_device_id *of_id;
 283         struct omap_control_phy *control_phy;
 284
 285         of_id = of_match_device(omap_control_phy_id_table, &pdev->dev);
 286         if (!of_id)
 287                 return -EINVAL;
 288
 289         control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
 290                 GFP_KERNEL);
 291         if (!control_phy)
 292                 return -ENOMEM;
 293
 294         control_phy->dev = &pdev->dev;
 295         control_phy->type = *(enum omap_control_phy_type *)of_id->data;
 296
 297         if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
 298                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 299                         "otghs_control");
 300                 control_phy->otghs_control = devm_ioremap_resource(
 301                         &pdev->dev, res);
 302                 if (IS_ERR(control_phy->otghs_control))
 303                         return PTR_ERR(control_phy->otghs_control);
 304         } else {
 305                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 306                                 "power");
 307                 control_phy->power = devm_ioremap_resource(&pdev->dev, res);
 308                 if (IS_ERR(control_phy->power)) {
 309                         dev_err(&pdev->dev, "Couldn't get power register\n");
 310                         return PTR_ERR(control_phy->power);
 311                 }
 312         }
 313
 314         if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
 315             control_phy->type == OMAP_CTRL_TYPE_PCIE) {
 316                 control_phy->sys_clk = devm_clk_get(control_phy->dev,
 317                         "sys_clkin");
 318                 if (IS_ERR(control_phy->sys_clk)) {
 319                         pr_err("%s: unable to get sys_clkin\n", __func__);
 320                         return -EINVAL;
 321                 }
 322         }
 323
 324         if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
 325                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 326                                                    "pcie_pcs");
 327                 control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
 328                 if (IS_ERR(control_phy->pcie_pcs))
 329                         return PTR_ERR(control_phy->pcie_pcs);
 330         }
 331
 332         dev_set_drvdata(control_phy->dev, control_phy);
 333
 334         return 0;
 335 }
 336
 337 static struct platform_driver omap_control_phy_driver = {
 338         .probe          = omap_control_phy_probe,
 339         .driver         = {
 340                 .name   = "omap-control-phy",
 341                 .of_match_table = omap_control_phy_id_table,
 342         },
 343 };
 344
 345 static int __init omap_control_phy_init(void)
 346 {
 347         return platform_driver_register(&omap_control_phy_driver);
 348 }
 349 subsys_initcall(omap_control_phy_init);
 350
 351 static void __exit omap_control_phy_exit(void)
 352 {
 353         platform_driver_unregister(&omap_control_phy_driver);
 354 }
 355 module_exit(omap_control_phy_exit);
 356
 357 MODULE_ALIAS("platform:omap_control_phy");
 358 MODULE_AUTHOR("Texas Instruments Inc.");
 359 MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
 360 MODULE_LICENSE("GPL v2");