1 /* SPDX-License-Identifier: GPL-2.0+
2 * Microchip Sparx5 SerDes driver
4 * Copyright (c) 2020 Microchip Technology Inc.
7 #ifndef _SPARX5_SERDES_H_
8 #define _SPARX5_SERDES_H_
10 #include "sparx5_serdes_regs.h"
12 #define SPX5_SERDES_MAX 33
14 enum sparx5_serdes_type {
20 enum sparx5_serdes_mode {
25 SPX5_SD_MODE_1000BASEX,
29 struct sparx5_serdes_private {
31 void __iomem *regs[NUM_TARGETS];
32 struct phy *phys[SPX5_SERDES_MAX];
34 unsigned long coreclock;
37 struct sparx5_serdes_macro {
38 struct sparx5_serdes_private *priv;
41 enum sparx5_serdes_type serdestype;
42 enum sparx5_serdes_mode serdesmode;
43 phy_interface_t portmode;
48 /* Read, Write and modify registers content.
49 * The register definition macros start at the id
51 static inline void __iomem *sdx5_addr(void __iomem *base[],
52 int id, int tinst, int tcnt,
58 WARN_ON((tinst) >= tcnt);
59 WARN_ON((ginst) >= gcnt);
60 WARN_ON((rinst) >= rcnt);
61 return base[id + (tinst)] +
62 gbase + ((ginst) * gwidth) +
63 raddr + ((rinst) * rwidth);
66 static inline void __iomem *sdx5_inst_baseaddr(void __iomem *base,
72 WARN_ON((ginst) >= gcnt);
73 WARN_ON((rinst) >= rcnt);
75 gbase + ((ginst) * gwidth) +
76 raddr + ((rinst) * rwidth);
79 static inline void sdx5_rmw(u32 val, u32 mask, struct sparx5_serdes_private *priv,
80 int id, int tinst, int tcnt,
81 int gbase, int ginst, int gcnt, int gwidth,
82 int raddr, int rinst, int rcnt, int rwidth)
86 sdx5_addr(priv->regs, id, tinst, tcnt,
87 gbase, ginst, gcnt, gwidth,
88 raddr, rinst, rcnt, rwidth);
90 nval = (nval & ~mask) | (val & mask);
94 static inline void sdx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
95 int id, int tinst, int tcnt,
96 int gbase, int ginst, int gcnt, int gwidth,
97 int raddr, int rinst, int rcnt, int rwidth)
101 sdx5_inst_baseaddr(iomem,
102 gbase, ginst, gcnt, gwidth,
103 raddr, rinst, rcnt, rwidth);
105 nval = (nval & ~mask) | (val & mask);
109 static inline void sdx5_rmw_addr(u32 val, u32 mask, void __iomem *addr)
114 nval = (nval & ~mask) | (val & mask);
118 static inline void __iomem *sdx5_inst_get(struct sparx5_serdes_private *priv,
121 return priv->regs[id + tinst];
124 static inline void __iomem *sdx5_inst_addr(void __iomem *iomem,
125 int id, int tinst, int tcnt,
127 int ginst, int gcnt, int gwidth,
129 int rinst, int rcnt, int rwidth)
131 return sdx5_inst_baseaddr(iomem, gbase, ginst, gcnt, gwidth,
132 raddr, rinst, rcnt, rwidth);
136 #endif /* _SPARX5_SERDES_REGS_H_ */