1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
5 * Copyright 2018 Cadence Design Systems, Inc.
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/reset.h>
25 #include <linux/regmap.h>
27 #define REF_CLK_19_2MHz 19200000
28 #define REF_CLK_25MHz 25000000
30 #define MAX_NUM_LANES 4
31 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
33 #define NUM_SSC_MODE 3
34 #define NUM_PHY_TYPE 6
36 #define POLL_TIMEOUT_US 5000
37 #define PLL_LOCK_TIMEOUT 100000
39 #define TORRENT_COMMON_CDB_OFFSET 0x0
41 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
42 ((0x4000 << (block_offset)) + \
43 (((ln) << 9) << (reg_offset)))
45 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
46 ((0x8000 << (block_offset)) + \
47 (((ln) << 9) << (reg_offset)))
49 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
50 (0xC000 << (block_offset))
52 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
53 (0xE000 << (block_offset))
55 #define TORRENT_DPTX_PHY_OFFSET 0x0
58 * register offsets from DPTX PHY register block base (i.e MHDP
59 * register base + 0x30a00)
61 #define PHY_AUX_CTRL 0x04
62 #define PHY_RESET 0x20
63 #define PMA_TX_ELEC_IDLE_MASK 0xF0U
64 #define PMA_TX_ELEC_IDLE_SHIFT 4
65 #define PHY_L00_RESET_N_MASK 0x01U
66 #define PHY_PMA_XCVR_PLLCLK_EN 0x24
67 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
68 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
69 #define PHY_POWER_STATE_LN_0 0x0000
70 #define PHY_POWER_STATE_LN_1 0x0008
71 #define PHY_POWER_STATE_LN_2 0x0010
72 #define PHY_POWER_STATE_LN_3 0x0018
73 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
74 #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
75 #define PHY_PMA_CMN_READY 0x34
78 * register offsets from SD0801 PHY register block base (i.e MHDP
79 * register base + 0x500000)
81 #define CMN_SSM_BANDGAP_TMR 0x0021U
82 #define CMN_SSM_BIAS_TMR 0x0022U
83 #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
84 #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
85 #define CMN_PLLSM1_PLLPRE_TMR 0x0032U
86 #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
87 #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
88 #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
89 #define CMN_CDIAG_REFCLK_OVRD 0x004CU
90 #define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
91 #define CMN_BGCAL_INIT_TMR 0x0064U
92 #define CMN_BGCAL_ITER_TMR 0x0065U
93 #define CMN_IBCAL_INIT_TMR 0x0074U
94 #define CMN_PLL0_VCOCAL_TCTRL 0x0082U
95 #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
96 #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
97 #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
98 #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
99 #define CMN_PLL0_INTDIV_M0 0x0090U
100 #define CMN_PLL0_FRACDIVL_M0 0x0091U
101 #define CMN_PLL0_FRACDIVH_M0 0x0092U
102 #define CMN_PLL0_HIGH_THR_M0 0x0093U
103 #define CMN_PLL0_DSM_DIAG_M0 0x0094U
104 #define CMN_PLL0_SS_CTRL1_M0 0x0098U
105 #define CMN_PLL0_SS_CTRL2_M0 0x0099U
106 #define CMN_PLL0_SS_CTRL3_M0 0x009AU
107 #define CMN_PLL0_SS_CTRL4_M0 0x009BU
108 #define CMN_PLL0_LOCK_REFCNT_START 0x009CU
109 #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
110 #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
111 #define CMN_PLL0_INTDIV_M1 0x00A0U
112 #define CMN_PLL0_FRACDIVH_M1 0x00A2U
113 #define CMN_PLL0_HIGH_THR_M1 0x00A3U
114 #define CMN_PLL0_DSM_DIAG_M1 0x00A4U
115 #define CMN_PLL0_SS_CTRL1_M1 0x00A8U
116 #define CMN_PLL0_SS_CTRL2_M1 0x00A9U
117 #define CMN_PLL0_SS_CTRL3_M1 0x00AAU
118 #define CMN_PLL0_SS_CTRL4_M1 0x00ABU
119 #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
120 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
121 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
122 #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
123 #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
124 #define CMN_PLL1_INTDIV_M0 0x00D0U
125 #define CMN_PLL1_FRACDIVL_M0 0x00D1U
126 #define CMN_PLL1_FRACDIVH_M0 0x00D2U
127 #define CMN_PLL1_HIGH_THR_M0 0x00D3U
128 #define CMN_PLL1_DSM_DIAG_M0 0x00D4U
129 #define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U
130 #define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U
131 #define CMN_PLL1_SS_CTRL1_M0 0x00D8U
132 #define CMN_PLL1_SS_CTRL2_M0 0x00D9U
133 #define CMN_PLL1_SS_CTRL3_M0 0x00DAU
134 #define CMN_PLL1_SS_CTRL4_M0 0x00DBU
135 #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
136 #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
137 #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
138 #define CMN_TXPUCAL_TUNE 0x0103U
139 #define CMN_TXPUCAL_INIT_TMR 0x0104U
140 #define CMN_TXPUCAL_ITER_TMR 0x0105U
141 #define CMN_TXPDCAL_TUNE 0x010BU
142 #define CMN_TXPDCAL_INIT_TMR 0x010CU
143 #define CMN_TXPDCAL_ITER_TMR 0x010DU
144 #define CMN_RXCAL_INIT_TMR 0x0114U
145 #define CMN_RXCAL_ITER_TMR 0x0115U
146 #define CMN_SD_CAL_INIT_TMR 0x0124U
147 #define CMN_SD_CAL_ITER_TMR 0x0125U
148 #define CMN_SD_CAL_REFTIM_START 0x0126U
149 #define CMN_SD_CAL_PLLCNT_START 0x0128U
150 #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
151 #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
152 #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
153 #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
154 #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
155 #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
156 #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
157 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
158 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
159 #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
160 #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
161 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
162 #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
163 #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
164 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
165 #define CMN_DIAG_BIAS_OVRD1 0x01E1U
167 /* PMA TX Lane registers */
168 #define TX_TXCC_CTRL 0x0040U
169 #define TX_TXCC_CPOST_MULT_00 0x004CU
170 #define TX_TXCC_CPOST_MULT_01 0x004DU
171 #define TX_TXCC_MGNFS_MULT_000 0x0050U
172 #define TX_TXCC_MGNFS_MULT_100 0x0054U
173 #define DRV_DIAG_TX_DRV 0x00C6U
174 #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
175 #define XCVR_DIAG_HSCLK_SEL 0x00E6U
176 #define XCVR_DIAG_HSCLK_DIV 0x00E7U
177 #define XCVR_DIAG_RXCLK_CTRL 0x00E9U
178 #define XCVR_DIAG_BIDI_CTRL 0x00EAU
179 #define XCVR_DIAG_PSC_OVRD 0x00EBU
180 #define TX_PSC_A0 0x0100U
181 #define TX_PSC_A1 0x0101U
182 #define TX_PSC_A2 0x0102U
183 #define TX_PSC_A3 0x0103U
184 #define TX_RCVDET_ST_TMR 0x0123U
185 #define TX_DIAG_ACYA 0x01E7U
186 #define TX_DIAG_ACYA_HBDC_MASK 0x0001U
188 /* PMA RX Lane registers */
189 #define RX_PSC_A0 0x0000U
190 #define RX_PSC_A1 0x0001U
191 #define RX_PSC_A2 0x0002U
192 #define RX_PSC_A3 0x0003U
193 #define RX_PSC_CAL 0x0006U
194 #define RX_CDRLF_CNFG 0x0080U
195 #define RX_CDRLF_CNFG3 0x0082U
196 #define RX_SIGDET_HL_FILT_TMR 0x0090U
197 #define RX_REE_GCSM1_CTRL 0x0108U
198 #define RX_REE_GCSM1_EQENM_PH1 0x0109U
199 #define RX_REE_GCSM1_EQENM_PH2 0x010AU
200 #define RX_REE_GCSM2_CTRL 0x0110U
201 #define RX_REE_PERGCSM_CTRL 0x0118U
202 #define RX_REE_ATTEN_THR 0x0149U
203 #define RX_REE_TAP1_CLIP 0x0171U
204 #define RX_REE_TAP2TON_CLIP 0x0172U
205 #define RX_REE_SMGM_CTRL1 0x0177U
206 #define RX_REE_SMGM_CTRL2 0x0178U
207 #define RX_DIAG_DFE_CTRL 0x01E0U
208 #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
209 #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
210 #define RX_DIAG_NQST_CTRL 0x01E5U
211 #define RX_DIAG_SIGDET_TUNE 0x01E8U
212 #define RX_DIAG_PI_RATE 0x01F4U
213 #define RX_DIAG_PI_CAP 0x01F5U
214 #define RX_DIAG_ACYA 0x01FFU
216 /* PHY PCS common registers */
217 #define PHY_PIPE_CMN_CTRL1 0x0000U
218 #define PHY_PLL_CFG 0x000EU
219 #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
220 #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
221 #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
223 /* PHY PMA common registers */
224 #define PHY_PMA_CMN_CTRL1 0x0000U
225 #define PHY_PMA_CMN_CTRL2 0x0001U
226 #define PHY_PMA_PLL_RAW_CTRL 0x0003U
228 static const char * const clk_names[] = {
229 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
232 static const struct reg_field phy_pll_cfg =
233 REG_FIELD(PHY_PLL_CFG, 0, 1);
235 static const struct reg_field phy_pma_cmn_ctrl_1 =
236 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
238 static const struct reg_field phy_pma_cmn_ctrl_2 =
239 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
241 static const struct reg_field phy_pma_pll_raw_ctrl =
242 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
244 static const struct reg_field phy_reset_ctrl =
245 REG_FIELD(PHY_RESET, 8, 8);
247 static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
249 #define REFCLK_OUT_NUM_CMN_CONFIG 5
251 enum cdns_torrent_refclk_out_cmn {
252 CMN_CDIAG_REFCLK_OVRD_4,
253 CMN_CDIAG_REFCLK_DRV0_CTRL_1,
254 CMN_CDIAG_REFCLK_DRV0_CTRL_4,
255 CMN_CDIAG_REFCLK_DRV0_CTRL_5,
256 CMN_CDIAG_REFCLK_DRV0_CTRL_6,
259 static const struct reg_field refclk_out_cmn_cfg[] = {
260 [CMN_CDIAG_REFCLK_OVRD_4] = REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4),
261 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
262 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
263 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
264 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
267 enum cdns_torrent_phy_type {
276 enum cdns_torrent_ssc_mode {
282 struct cdns_torrent_inst {
285 enum cdns_torrent_phy_type phy_type;
287 struct reset_control *lnk_rst;
288 enum cdns_torrent_ssc_mode ssc_mode;
291 struct cdns_torrent_phy {
292 void __iomem *base; /* DPTX registers base */
293 void __iomem *sd_base; /* SD0801 registers base */
294 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
295 struct reset_control *phy_rst;
296 struct reset_control *apb_rst;
299 unsigned long ref_clk_rate;
300 struct cdns_torrent_inst phys[MAX_NUM_LANES];
302 const struct cdns_torrent_data *init_data;
303 struct regmap *regmap;
304 struct regmap *regmap_common_cdb;
305 struct regmap *regmap_phy_pcs_common_cdb;
306 struct regmap *regmap_phy_pma_common_cdb;
307 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
308 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
309 struct regmap *regmap_dptx_phy_reg;
310 struct regmap_field *phy_pll_cfg;
311 struct regmap_field *phy_pma_cmn_ctrl_1;
312 struct regmap_field *phy_pma_cmn_ctrl_2;
313 struct regmap_field *phy_pma_pll_raw_ctrl;
314 struct regmap_field *phy_reset_ctrl;
315 struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1];
316 struct clk_onecell_data clk_data;
319 enum phy_powerstate {
321 /* Powerstate A1 is unused */
326 struct cdns_torrent_derived_refclk {
328 struct regmap_field *phy_pipe_cmn_ctrl1_0;
329 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG];
330 struct clk_init_data clk_data;
333 #define to_cdns_torrent_derived_refclk(_hw) \
334 container_of(_hw, struct cdns_torrent_derived_refclk, hw)
336 static int cdns_torrent_phy_init(struct phy *phy);
337 static int cdns_torrent_dp_init(struct phy *phy);
338 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
341 int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
342 static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
343 struct cdns_torrent_inst *inst);
345 void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
347 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
350 void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
352 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
354 static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
356 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
357 u32 rate, u32 num_lanes);
358 static int cdns_torrent_dp_configure(struct phy *phy,
359 union phy_configure_opts *opts);
360 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
362 enum phy_powerstate powerstate);
363 static int cdns_torrent_phy_on(struct phy *phy);
364 static int cdns_torrent_phy_off(struct phy *phy);
366 static const struct phy_ops cdns_torrent_phy_ops = {
367 .init = cdns_torrent_phy_init,
368 .configure = cdns_torrent_dp_configure,
369 .power_on = cdns_torrent_phy_on,
370 .power_off = cdns_torrent_phy_off,
371 .owner = THIS_MODULE,
374 static int cdns_torrent_noop_phy_on(struct phy *phy)
376 /* Give 5ms to 10ms delay for the PIPE clock to be stable */
377 usleep_range(5000, 10000);
382 static const struct phy_ops noop_ops = {
383 .power_on = cdns_torrent_noop_phy_on,
384 .owner = THIS_MODULE,
387 struct cdns_reg_pairs {
392 struct cdns_torrent_vals {
393 struct cdns_reg_pairs *reg_pairs;
397 struct cdns_torrent_data {
398 u8 block_offset_shift;
400 struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
402 struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
404 struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
406 struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
408 struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
410 struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
414 struct cdns_regmap_cdb_context {
420 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
422 struct cdns_regmap_cdb_context *ctx = context;
423 u32 offset = reg << ctx->reg_offset_shift;
425 writew(val, ctx->base + offset);
430 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
432 struct cdns_regmap_cdb_context *ctx = context;
433 u32 offset = reg << ctx->reg_offset_shift;
435 *val = readw(ctx->base + offset);
439 static int cdns_regmap_dptx_write(void *context, unsigned int reg,
442 struct cdns_regmap_cdb_context *ctx = context;
445 writel(val, ctx->base + offset);
450 static int cdns_regmap_dptx_read(void *context, unsigned int reg,
453 struct cdns_regmap_cdb_context *ctx = context;
456 *val = readl(ctx->base + offset);
460 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
462 .name = "torrent_tx_lane" n "_cdb", \
465 .reg_write = cdns_regmap_write, \
466 .reg_read = cdns_regmap_read, \
469 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
471 .name = "torrent_rx_lane" n "_cdb", \
474 .reg_write = cdns_regmap_write, \
475 .reg_read = cdns_regmap_read, \
478 static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
479 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
480 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
481 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
482 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
485 static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
486 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
487 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
488 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
489 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
492 static const struct regmap_config cdns_torrent_common_cdb_config = {
493 .name = "torrent_common_cdb",
496 .reg_write = cdns_regmap_write,
497 .reg_read = cdns_regmap_read,
500 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
501 .name = "torrent_phy_pcs_cmn_cdb",
504 .reg_write = cdns_regmap_write,
505 .reg_read = cdns_regmap_read,
508 static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
509 .name = "torrent_phy_pma_cmn_cdb",
512 .reg_write = cdns_regmap_write,
513 .reg_read = cdns_regmap_read,
516 static const struct regmap_config cdns_torrent_dptx_phy_config = {
517 .name = "torrent_dptx_phy",
520 .reg_write = cdns_regmap_dptx_write,
521 .reg_read = cdns_regmap_dptx_read,
524 /* PHY mmr access functions */
526 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
528 regmap_write(regmap, offset, val);
531 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
535 regmap_read(regmap, offset, &val);
539 /* DPTX mmr access functions */
541 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
543 regmap_write(regmap, offset, val);
546 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
550 regmap_read(regmap, offset, &val);
555 * Structure used to store values of PHY registers for voltage-related
556 * coefficients, for particular voltage swing and pre-emphasis level. Values
557 * are shared across all physical lanes.
559 struct coefficients {
560 /* Value of DRV_DIAG_TX_DRV register to use */
562 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
564 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
569 * Array consists of values of voltage-related registers for sd0801 PHY. A value
570 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
572 static const struct coefficients vltg_coeff[4][4] = {
573 /* voltage swing 0, pre-emphasis 0->3 */
574 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
575 .cpost_mult = 0x0000},
576 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
577 .cpost_mult = 0x0014},
578 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
579 .cpost_mult = 0x0020},
580 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
581 .cpost_mult = 0x002A}
584 /* voltage swing 1, pre-emphasis 0->3 */
585 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
586 .cpost_mult = 0x0000},
587 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
588 .cpost_mult = 0x0012},
589 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
590 .cpost_mult = 0x001F},
591 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
592 .cpost_mult = 0xFFFF}
595 /* voltage swing 2, pre-emphasis 0->3 */
596 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
597 .cpost_mult = 0x0000},
598 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
599 .cpost_mult = 0x0013},
600 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
601 .cpost_mult = 0xFFFF},
602 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
603 .cpost_mult = 0xFFFF}
606 /* voltage swing 3, pre-emphasis 0->3 */
607 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
608 .cpost_mult = 0x0000},
609 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
610 .cpost_mult = 0xFFFF},
611 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
612 .cpost_mult = 0xFFFF},
613 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
614 .cpost_mult = 0xFFFF}
619 * Enable or disable PLL for selected lanes.
621 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
622 struct phy_configure_opts_dp *dp,
627 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
630 * Used to determine, which bits to check for or enable in
631 * PHY_PMA_XCVR_PLLCLK_EN register.
634 /* Used to enable or disable lanes. */
637 /* Select values of registers and mask, depending on enabled lane
643 pll_bits = 0x00000001;
647 pll_bits = 0x00000003;
651 pll_bits = 0x0000000F;
658 pll_val = 0x00000000;
660 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
662 /* Wait for acknowledgment from PHY. */
663 ret = regmap_read_poll_timeout(regmap,
664 PHY_PMA_XCVR_PLLCLK_EN_ACK,
666 (rd_val & pll_bits) == pll_val,
673 * Perform register operations related to setting link rate, once powerstate is
674 * set and PLL disable request was processed.
676 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
677 struct phy_configure_opts_dp *dp)
682 /* Disable the cmn_pll0_en before re-programming the new data rate. */
683 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
686 * Wait for PLL ready de-assertion.
687 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
689 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
691 ((read_val >> 2) & 0x01) != 0,
697 /* DP Rate Change - VCO Output settings. */
698 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) {
699 /* PMA common configuration 19.2MHz */
700 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
702 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
703 } else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) {
704 /* PMA common configuration 25MHz */
705 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
707 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
709 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
711 /* Enable the cmn_pll0_en. */
712 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
715 * Wait for PLL ready assertion.
716 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
718 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
720 (read_val & 0x01) != 0,
726 * Verify, that parameters to configure PHY with are correct.
728 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
729 struct phy_configure_opts_dp *dp)
733 /* If changing link rate was required, verify it's supported. */
735 switch (dp->link_rate) {
751 /* Verify lane count. */
756 /* valid lane count. */
762 /* Check against actual number of PHY's lanes. */
763 if (dp->lanes > inst->num_lanes)
767 * If changing voltages is required, check swing and pre-emphasis
770 if (dp->set_voltages) {
771 /* Lane count verified previously. */
772 for (i = 0; i < dp->lanes; i++) {
773 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
776 /* Sum of voltage swing and pre-emphasis levels cannot
779 if (dp->voltage[i] + dp->pre[i] > 3)
787 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
788 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
791 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
792 u32 pwr_state = cdns_torrent_dp_read(regmap,
793 PHY_PMA_XCVR_POWER_STATE_REQ);
794 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
795 PHY_PMA_XCVR_PLLCLK_EN);
797 /* Lane 0 is always enabled. */
798 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
799 PHY_POWER_STATE_LN_0);
800 pll_clk_en &= ~0x01U;
804 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
805 PHY_POWER_STATE_LN_1);
806 pll_clk_en &= ~(0x01U << 1);
811 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
812 PHY_POWER_STATE_LN_2);
813 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
814 PHY_POWER_STATE_LN_3);
815 pll_clk_en &= ~(0x01U << 2);
816 pll_clk_en &= ~(0x01U << 3);
819 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
820 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
823 /* Configure lane count as required. */
824 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
825 struct phy_configure_opts_dp *dp)
829 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
830 u8 lane_mask = (1 << dp->lanes) - 1;
832 value = cdns_torrent_dp_read(regmap, PHY_RESET);
833 /* clear pma_tx_elec_idle_ln_* bits. */
834 value &= ~PMA_TX_ELEC_IDLE_MASK;
835 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
836 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
837 PMA_TX_ELEC_IDLE_MASK;
838 cdns_torrent_dp_write(regmap, PHY_RESET, value);
840 /* reset the link by asserting phy_l00_reset_n low */
841 cdns_torrent_dp_write(regmap, PHY_RESET,
842 value & (~PHY_L00_RESET_N_MASK));
845 * Assert lane reset on unused lanes and lane 0 so they remain in reset
846 * and powered down when re-enabling the link
848 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
849 cdns_torrent_dp_write(regmap, PHY_RESET, value);
851 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
853 /* release phy_l0*_reset_n based on used laneCount */
854 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
855 cdns_torrent_dp_write(regmap, PHY_RESET, value);
857 /* Wait, until PHY gets ready after releasing PHY reset signal. */
858 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
864 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
865 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
867 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
872 /* Configure link rate as required. */
873 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
874 struct phy_configure_opts_dp *dp)
878 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
882 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
887 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
892 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
895 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
899 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
908 /* Configure voltage swing and pre-emphasis for all enabled lanes. */
909 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
910 struct phy_configure_opts_dp *dp)
915 for (lane = 0; lane < dp->lanes; lane++) {
916 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
919 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
920 * current state of the analog TX driver.
922 val |= TX_DIAG_ACYA_HBDC_MASK;
923 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
926 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
927 TX_TXCC_CTRL, 0x08A4);
928 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
929 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
930 DRV_DIAG_TX_DRV, val);
931 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
932 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
933 TX_TXCC_MGNFS_MULT_000,
935 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
936 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
937 TX_TXCC_CPOST_MULT_00,
940 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
943 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
944 * analog TX driver to reflect the new programmed one.
946 val &= ~TX_DIAG_ACYA_HBDC_MASK;
947 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
952 static int cdns_torrent_dp_configure(struct phy *phy,
953 union phy_configure_opts *opts)
955 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
956 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
959 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
961 dev_err(&phy->dev, "invalid params for phy configure\n");
965 if (opts->dp.set_lanes) {
966 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
968 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
973 if (opts->dp.set_rate) {
974 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
976 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
981 if (opts->dp.set_voltages)
982 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
987 static int cdns_torrent_dp_init(struct phy *phy)
989 unsigned char lane_bits;
991 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
992 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
993 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
995 switch (cdns_phy->ref_clk_rate) {
996 case REF_CLK_19_2MHz:
998 /* Valid Ref Clock Rate */
1001 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1005 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
1007 /* PHY PMA registers configuration function */
1008 cdns_torrent_dp_pma_cfg(cdns_phy, inst);
1011 * Set lines power state to A0
1012 * Set lines pll clk enable to 0
1014 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
1017 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
1020 lane_bits = (1 << inst->num_lanes) - 1;
1021 cdns_torrent_dp_write(regmap, PHY_RESET,
1022 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
1024 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1025 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
1027 /* PHY PMA registers configuration functions */
1028 /* Initialize PHY with max supported link rate, without SSC. */
1029 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
1030 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
1031 cdns_phy->max_bit_rate,
1033 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
1034 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
1035 cdns_phy->max_bit_rate,
1037 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
1040 /* take out of reset */
1041 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
1043 cdns_torrent_phy_on(phy);
1045 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1049 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
1055 int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
1059 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1061 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
1062 reg & 1, 0, POLL_TIMEOUT_US);
1063 if (ret == -ETIMEDOUT) {
1064 dev_err(cdns_phy->dev,
1065 "timeout waiting for PMA common ready\n");
1072 static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
1073 struct cdns_torrent_inst *inst)
1077 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
1078 /* PMA common configuration 19.2MHz */
1079 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
1080 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
1081 /* PMA common configuration 25MHz */
1082 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
1084 /* PMA lane configuration to deal with multi-link operation */
1085 for (i = 0; i < inst->num_lanes; i++)
1086 cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
1090 void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
1092 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1094 /* refclock registers - assumes 19.2 MHz refclock */
1095 cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
1096 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
1097 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
1098 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
1099 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
1100 cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
1101 cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
1102 cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
1103 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
1104 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
1105 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
1106 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
1107 cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
1108 cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
1109 cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
1110 cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
1111 cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
1112 cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
1115 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1116 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1117 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1118 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1119 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1120 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1121 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1122 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1123 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
1124 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
1125 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
1126 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
1127 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
1128 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
1129 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
1130 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
1134 * Set registers responsible for enabling and configuring SSC, with second and
1135 * third register values provided by parameters.
1138 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
1139 u32 ctrl2_val, u32 ctrl3_val)
1141 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1143 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
1144 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
1145 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
1146 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
1147 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
1148 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
1149 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
1150 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
1154 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
1157 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1159 /* Assumes 19.2 MHz refclock */
1161 /* Setting VCO for 10.8GHz */
1164 cdns_torrent_phy_write(regmap,
1165 CMN_PLL0_INTDIV_M0, 0x0119);
1166 cdns_torrent_phy_write(regmap,
1167 CMN_PLL0_FRACDIVL_M0, 0x4000);
1168 cdns_torrent_phy_write(regmap,
1169 CMN_PLL0_FRACDIVH_M0, 0x0002);
1170 cdns_torrent_phy_write(regmap,
1171 CMN_PLL0_HIGH_THR_M0, 0x00BC);
1172 cdns_torrent_phy_write(regmap,
1173 CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
1174 cdns_torrent_phy_write(regmap,
1175 CMN_PLL1_INTDIV_M0, 0x0119);
1176 cdns_torrent_phy_write(regmap,
1177 CMN_PLL1_FRACDIVL_M0, 0x4000);
1178 cdns_torrent_phy_write(regmap,
1179 CMN_PLL1_FRACDIVH_M0, 0x0002);
1180 cdns_torrent_phy_write(regmap,
1181 CMN_PLL1_HIGH_THR_M0, 0x00BC);
1182 cdns_torrent_phy_write(regmap,
1183 CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
1185 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A,
1188 /* Setting VCO for 9.72GHz */
1192 cdns_torrent_phy_write(regmap,
1193 CMN_PLL0_INTDIV_M0, 0x01FA);
1194 cdns_torrent_phy_write(regmap,
1195 CMN_PLL0_FRACDIVL_M0, 0x4000);
1196 cdns_torrent_phy_write(regmap,
1197 CMN_PLL0_FRACDIVH_M0, 0x0002);
1198 cdns_torrent_phy_write(regmap,
1199 CMN_PLL0_HIGH_THR_M0, 0x0152);
1200 cdns_torrent_phy_write(regmap,
1201 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1202 cdns_torrent_phy_write(regmap,
1203 CMN_PLL1_INTDIV_M0, 0x01FA);
1204 cdns_torrent_phy_write(regmap,
1205 CMN_PLL1_FRACDIVL_M0, 0x4000);
1206 cdns_torrent_phy_write(regmap,
1207 CMN_PLL1_FRACDIVH_M0, 0x0002);
1208 cdns_torrent_phy_write(regmap,
1209 CMN_PLL1_HIGH_THR_M0, 0x0152);
1210 cdns_torrent_phy_write(regmap,
1211 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1213 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD,
1216 /* Setting VCO for 8.64GHz */
1219 cdns_torrent_phy_write(regmap,
1220 CMN_PLL0_INTDIV_M0, 0x01C2);
1221 cdns_torrent_phy_write(regmap,
1222 CMN_PLL0_FRACDIVL_M0, 0x0000);
1223 cdns_torrent_phy_write(regmap,
1224 CMN_PLL0_FRACDIVH_M0, 0x0002);
1225 cdns_torrent_phy_write(regmap,
1226 CMN_PLL0_HIGH_THR_M0, 0x012C);
1227 cdns_torrent_phy_write(regmap,
1228 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1229 cdns_torrent_phy_write(regmap,
1230 CMN_PLL1_INTDIV_M0, 0x01C2);
1231 cdns_torrent_phy_write(regmap,
1232 CMN_PLL1_FRACDIVL_M0, 0x0000);
1233 cdns_torrent_phy_write(regmap,
1234 CMN_PLL1_FRACDIVH_M0, 0x0002);
1235 cdns_torrent_phy_write(regmap,
1236 CMN_PLL1_HIGH_THR_M0, 0x012C);
1237 cdns_torrent_phy_write(regmap,
1238 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1240 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536,
1243 /* Setting VCO for 8.1GHz */
1245 cdns_torrent_phy_write(regmap,
1246 CMN_PLL0_INTDIV_M0, 0x01A5);
1247 cdns_torrent_phy_write(regmap,
1248 CMN_PLL0_FRACDIVL_M0, 0xE000);
1249 cdns_torrent_phy_write(regmap,
1250 CMN_PLL0_FRACDIVH_M0, 0x0002);
1251 cdns_torrent_phy_write(regmap,
1252 CMN_PLL0_HIGH_THR_M0, 0x011A);
1253 cdns_torrent_phy_write(regmap,
1254 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1255 cdns_torrent_phy_write(regmap,
1256 CMN_PLL1_INTDIV_M0, 0x01A5);
1257 cdns_torrent_phy_write(regmap,
1258 CMN_PLL1_FRACDIVL_M0, 0xE000);
1259 cdns_torrent_phy_write(regmap,
1260 CMN_PLL1_FRACDIVH_M0, 0x0002);
1261 cdns_torrent_phy_write(regmap,
1262 CMN_PLL1_HIGH_THR_M0, 0x011A);
1263 cdns_torrent_phy_write(regmap,
1264 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1266 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7,
1272 cdns_torrent_phy_write(regmap,
1273 CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
1274 cdns_torrent_phy_write(regmap,
1275 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
1276 cdns_torrent_phy_write(regmap,
1277 CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
1278 cdns_torrent_phy_write(regmap,
1279 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
1281 cdns_torrent_phy_write(regmap,
1282 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
1283 cdns_torrent_phy_write(regmap,
1284 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
1285 /* Set reset register values to disable SSC */
1286 cdns_torrent_phy_write(regmap,
1287 CMN_PLL0_SS_CTRL1_M0, 0x0002);
1288 cdns_torrent_phy_write(regmap,
1289 CMN_PLL0_SS_CTRL2_M0, 0x0000);
1290 cdns_torrent_phy_write(regmap,
1291 CMN_PLL0_SS_CTRL3_M0, 0x0000);
1292 cdns_torrent_phy_write(regmap,
1293 CMN_PLL0_SS_CTRL4_M0, 0x0000);
1294 cdns_torrent_phy_write(regmap,
1295 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
1296 cdns_torrent_phy_write(regmap,
1297 CMN_PLL1_SS_CTRL1_M0, 0x0002);
1298 cdns_torrent_phy_write(regmap,
1299 CMN_PLL1_SS_CTRL2_M0, 0x0000);
1300 cdns_torrent_phy_write(regmap,
1301 CMN_PLL1_SS_CTRL3_M0, 0x0000);
1302 cdns_torrent_phy_write(regmap,
1303 CMN_PLL1_SS_CTRL4_M0, 0x0000);
1304 cdns_torrent_phy_write(regmap,
1305 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
1308 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
1309 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
1310 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
1311 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
1315 void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
1317 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1319 /* refclock registers - assumes 25 MHz refclock */
1320 cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
1321 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
1322 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
1323 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
1324 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
1325 cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
1326 cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
1327 cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
1328 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
1329 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
1330 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
1331 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
1332 cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
1333 cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
1334 cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
1335 cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
1336 cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
1337 cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
1340 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1341 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1342 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1343 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1344 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1345 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1346 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1347 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1348 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
1349 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
1350 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
1351 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
1352 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
1353 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
1354 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
1355 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
1359 * Set registers responsible for enabling and configuring SSC, with second
1360 * register value provided by a parameter.
1362 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
1365 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1367 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
1368 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
1369 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
1370 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
1371 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
1372 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
1373 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
1374 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
1378 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
1381 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1383 /* Assumes 25 MHz refclock */
1385 /* Setting VCO for 10.8GHz */
1388 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
1389 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
1390 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1391 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
1392 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
1393 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
1394 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1395 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
1397 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
1399 /* Setting VCO for 9.72GHz */
1403 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
1404 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
1405 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1406 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
1407 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
1408 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
1409 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1410 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
1412 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
1414 /* Setting VCO for 8.64GHz */
1417 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
1418 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
1419 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1420 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
1421 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
1422 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
1423 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1424 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
1426 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
1428 /* Setting VCO for 8.1GHz */
1430 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
1431 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
1432 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1433 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
1434 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
1435 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
1436 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1437 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
1439 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
1443 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1444 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1447 cdns_torrent_phy_write(regmap,
1448 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
1449 cdns_torrent_phy_write(regmap,
1450 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
1451 cdns_torrent_phy_write(regmap,
1452 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
1453 cdns_torrent_phy_write(regmap,
1454 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
1456 cdns_torrent_phy_write(regmap,
1457 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
1458 cdns_torrent_phy_write(regmap,
1459 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
1460 /* Set reset register values to disable SSC */
1461 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
1462 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
1463 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
1464 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
1465 cdns_torrent_phy_write(regmap,
1466 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
1467 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
1468 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
1469 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
1470 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
1471 cdns_torrent_phy_write(regmap,
1472 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
1475 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
1476 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
1477 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
1478 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
1481 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1482 u32 rate, u32 num_lanes)
1484 unsigned int clk_sel_val = 0;
1485 unsigned int hsclk_div_val = 0;
1488 /* 16'h0000 for single DP link configuration */
1489 regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
1493 clk_sel_val = 0x0f01;
1499 clk_sel_val = 0x0701;
1503 clk_sel_val = 0x0b00;
1508 clk_sel_val = 0x0301;
1512 clk_sel_val = 0x0200;
1517 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1518 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1519 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1520 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1522 /* PMA lane configuration to deal with multi-link operation */
1523 for (i = 0; i < num_lanes; i++)
1524 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
1525 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1528 static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
1531 /* Per lane, refclock-dependent receiver detection setting */
1532 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
1533 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1534 TX_RCVDET_ST_TMR, 0x0780);
1535 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
1536 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1537 TX_RCVDET_ST_TMR, 0x09C4);
1539 /* Writing Tx/Rx Power State Controllers registers */
1540 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1542 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1544 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1546 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1548 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1550 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1553 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1554 RX_PSC_CAL, 0x0000);
1556 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1557 RX_REE_GCSM1_CTRL, 0x0000);
1558 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1559 RX_REE_GCSM2_CTRL, 0x0000);
1560 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1561 RX_REE_PERGCSM_CTRL, 0x0000);
1563 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1564 XCVR_DIAG_BIDI_CTRL, 0x000F);
1565 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1566 XCVR_DIAG_PLLDRC_CTRL, 0x0001);
1567 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1568 XCVR_DIAG_HSCLK_SEL, 0x0000);
1571 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1573 enum phy_powerstate powerstate)
1575 /* Register value for power state for a single byte. */
1581 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1583 switch (powerstate) {
1584 case (POWERSTATE_A0):
1587 case (POWERSTATE_A2):
1596 /* Select values of registers and mask, depending on enabled
1599 switch (num_lanes) {
1608 | (value_part << 8));
1611 /* lanes 0-3, all */
1615 | (value_part << 16)
1616 | (value_part << 24));
1621 /* Set power state A<n>. */
1622 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1623 /* Wait, until PHY acknowledges power state completion. */
1624 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1625 read_val, (read_val & mask) == value, 0,
1627 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1633 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
1635 unsigned int read_val;
1637 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1640 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1643 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1644 read_val, read_val & 1,
1645 0, POLL_TIMEOUT_US);
1646 if (ret == -ETIMEDOUT) {
1647 dev_err(cdns_phy->dev,
1648 "timeout waiting for link PLL clock enable ack\n");
1654 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1659 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1665 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
1667 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1669 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
1670 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
1671 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
1672 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
1673 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1);
1674 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1);
1679 static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
1681 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1683 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0);
1686 static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
1688 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1691 regmap_field_read(derived_refclk->phy_pipe_cmn_ctrl1_0, &val);
1696 static const struct clk_ops cdns_torrent_derived_refclk_ops = {
1697 .enable = cdns_torrent_derived_refclk_enable,
1698 .disable = cdns_torrent_derived_refclk_disable,
1699 .is_enabled = cdns_torrent_derived_refclk_is_enabled,
1702 static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)
1704 struct cdns_torrent_derived_refclk *derived_refclk;
1705 struct device *dev = cdns_phy->dev;
1706 struct regmap_field *field;
1707 struct clk_init_data *init;
1708 const char *parent_name;
1709 struct regmap *regmap;
1714 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
1715 if (!derived_refclk)
1718 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1719 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
1721 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1723 dev_err(dev, "No parent clock for derived_refclk\n");
1724 return PTR_ERR(clk);
1727 init = &derived_refclk->clk_data;
1730 parent_name = __clk_get_name(clk);
1731 init->parent_names = &parent_name;
1732 init->num_parents = 1;
1734 init->ops = &cdns_torrent_derived_refclk_ops;
1736 init->name = clk_name;
1738 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1739 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0);
1740 if (IS_ERR(field)) {
1741 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n");
1742 return PTR_ERR(field);
1744 derived_refclk->phy_pipe_cmn_ctrl1_0 = field;
1746 regmap = cdns_phy->regmap_common_cdb;
1747 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) {
1748 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
1749 if (IS_ERR(field)) {
1750 dev_err(dev, "CMN reg field init failed\n");
1751 return PTR_ERR(field);
1753 derived_refclk->cmn_fields[i] = field;
1756 derived_refclk->hw.init = init;
1758 clk = devm_clk_register(dev, &derived_refclk->hw);
1760 return PTR_ERR(clk);
1762 cdns_phy->clks[CDNS_TORRENT_REFCLK_DRIVER] = clk;
1767 static int cdns_torrent_phy_on(struct phy *phy)
1769 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1770 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1774 if (cdns_phy->nsubnodes == 1) {
1775 /* Take the PHY lane group out of reset */
1776 reset_control_deassert(inst->lnk_rst);
1778 /* Take the PHY out of reset */
1779 ret = reset_control_deassert(cdns_phy->phy_rst);
1785 * Wait for cmn_ready assertion
1786 * PHY_PMA_CMN_CTRL1[0] == 1
1788 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
1789 read_val, read_val, 1000,
1792 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
1801 static int cdns_torrent_phy_off(struct phy *phy)
1803 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1804 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1807 if (cdns_phy->nsubnodes != 1)
1810 ret = reset_control_assert(cdns_phy->phy_rst);
1814 return reset_control_assert(inst->lnk_rst);
1817 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
1819 u8 reg_offset_shift,
1820 const struct regmap_config *config)
1822 struct cdns_regmap_cdb_context *ctx;
1824 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1826 return ERR_PTR(-ENOMEM);
1829 ctx->base = base + block_offset;
1830 ctx->reg_offset_shift = reg_offset_shift;
1832 return devm_regmap_init(dev, NULL, ctx, config);
1835 static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
1837 struct device *dev = cdns_phy->dev;
1838 struct regmap_field *field;
1839 struct regmap *regmap;
1841 regmap = cdns_phy->regmap_dptx_phy_reg;
1842 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
1843 if (IS_ERR(field)) {
1844 dev_err(dev, "PHY_RESET reg field init failed\n");
1845 return PTR_ERR(field);
1847 cdns_phy->phy_reset_ctrl = field;
1852 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
1854 struct device *dev = cdns_phy->dev;
1855 struct regmap_field *field;
1856 struct regmap *regmap;
1858 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1859 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
1860 if (IS_ERR(field)) {
1861 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
1862 return PTR_ERR(field);
1864 cdns_phy->phy_pll_cfg = field;
1866 regmap = cdns_phy->regmap_phy_pma_common_cdb;
1867 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
1868 if (IS_ERR(field)) {
1869 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
1870 return PTR_ERR(field);
1872 cdns_phy->phy_pma_cmn_ctrl_1 = field;
1874 regmap = cdns_phy->regmap_phy_pma_common_cdb;
1875 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
1876 if (IS_ERR(field)) {
1877 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
1878 return PTR_ERR(field);
1880 cdns_phy->phy_pma_cmn_ctrl_2 = field;
1882 regmap = cdns_phy->regmap_phy_pma_common_cdb;
1883 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
1884 if (IS_ERR(field)) {
1885 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
1886 return PTR_ERR(field);
1888 cdns_phy->phy_pma_pll_raw_ctrl = field;
1893 static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
1895 void __iomem *base = cdns_phy->base;
1896 struct device *dev = cdns_phy->dev;
1897 struct regmap *regmap;
1898 u8 reg_offset_shift;
1901 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
1903 block_offset = TORRENT_DPTX_PHY_OFFSET;
1904 regmap = cdns_regmap_init(dev, base, block_offset,
1906 &cdns_torrent_dptx_phy_config);
1907 if (IS_ERR(regmap)) {
1908 dev_err(dev, "Failed to init DPTX PHY regmap\n");
1909 return PTR_ERR(regmap);
1911 cdns_phy->regmap_dptx_phy_reg = regmap;
1916 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
1918 void __iomem *sd_base = cdns_phy->sd_base;
1919 u8 block_offset_shift, reg_offset_shift;
1920 struct device *dev = cdns_phy->dev;
1921 struct regmap *regmap;
1925 block_offset_shift = cdns_phy->init_data->block_offset_shift;
1926 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
1928 for (i = 0; i < MAX_NUM_LANES; i++) {
1929 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
1931 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1933 &cdns_torrent_tx_lane_cdb_config[i]);
1934 if (IS_ERR(regmap)) {
1935 dev_err(dev, "Failed to init tx lane CDB regmap\n");
1936 return PTR_ERR(regmap);
1938 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
1940 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
1942 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1944 &cdns_torrent_rx_lane_cdb_config[i]);
1945 if (IS_ERR(regmap)) {
1946 dev_err(dev, "Failed to init rx lane CDB regmap\n");
1947 return PTR_ERR(regmap);
1949 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
1952 block_offset = TORRENT_COMMON_CDB_OFFSET;
1953 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1955 &cdns_torrent_common_cdb_config);
1956 if (IS_ERR(regmap)) {
1957 dev_err(dev, "Failed to init common CDB regmap\n");
1958 return PTR_ERR(regmap);
1960 cdns_phy->regmap_common_cdb = regmap;
1962 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
1963 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1965 &cdns_torrent_phy_pcs_cmn_cdb_config);
1966 if (IS_ERR(regmap)) {
1967 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
1968 return PTR_ERR(regmap);
1970 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
1972 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
1973 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1975 &cdns_torrent_phy_pma_cmn_cdb_config);
1976 if (IS_ERR(regmap)) {
1977 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
1978 return PTR_ERR(regmap);
1980 cdns_phy->regmap_phy_pma_common_cdb = regmap;
1985 static int cdns_torrent_phy_init(struct phy *phy)
1987 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1988 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
1989 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
1990 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
1991 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1992 enum cdns_torrent_phy_type phy_type = inst->phy_type;
1993 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
1994 struct cdns_torrent_vals *pcs_cmn_vals;
1995 struct cdns_reg_pairs *reg_pairs;
1996 struct regmap *regmap;
2000 if (cdns_phy->nsubnodes > 1)
2003 if (phy_type == TYPE_DP)
2004 return cdns_torrent_dp_init(phy);
2007 * Spread spectrum generation is not required or supported
2010 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
2013 /* PHY configuration specific registers for single link */
2014 link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
2015 if (link_cmn_vals) {
2016 reg_pairs = link_cmn_vals->reg_pairs;
2017 num_regs = link_cmn_vals->num_regs;
2018 regmap = cdns_phy->regmap_common_cdb;
2021 * First array value in link_cmn_vals must be of
2022 * PHY_PLL_CFG register
2024 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
2026 for (i = 1; i < num_regs; i++)
2027 regmap_write(regmap, reg_pairs[i].off,
2031 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
2032 if (xcvr_diag_vals) {
2033 reg_pairs = xcvr_diag_vals->reg_pairs;
2034 num_regs = xcvr_diag_vals->num_regs;
2035 for (i = 0; i < inst->num_lanes; i++) {
2036 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2037 for (j = 0; j < num_regs; j++)
2038 regmap_write(regmap, reg_pairs[j].off,
2043 /* PHY PCS common registers configurations */
2044 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
2046 reg_pairs = pcs_cmn_vals->reg_pairs;
2047 num_regs = pcs_cmn_vals->num_regs;
2048 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2049 for (i = 0; i < num_regs; i++)
2050 regmap_write(regmap, reg_pairs[i].off,
2054 /* PMA common registers configurations */
2055 cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
2057 reg_pairs = cmn_vals->reg_pairs;
2058 num_regs = cmn_vals->num_regs;
2059 regmap = cdns_phy->regmap_common_cdb;
2060 for (i = 0; i < num_regs; i++)
2061 regmap_write(regmap, reg_pairs[i].off,
2065 /* PMA TX lane registers configurations */
2066 tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc];
2068 reg_pairs = tx_ln_vals->reg_pairs;
2069 num_regs = tx_ln_vals->num_regs;
2070 for (i = 0; i < inst->num_lanes; i++) {
2071 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2072 for (j = 0; j < num_regs; j++)
2073 regmap_write(regmap, reg_pairs[j].off,
2078 /* PMA RX lane registers configurations */
2079 rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc];
2081 reg_pairs = rx_ln_vals->reg_pairs;
2082 num_regs = rx_ln_vals->num_regs;
2083 for (i = 0; i < inst->num_lanes; i++) {
2084 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
2085 for (j = 0; j < num_regs; j++)
2086 regmap_write(regmap, reg_pairs[j].off,
2095 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
2097 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2098 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2099 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2100 enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
2101 struct cdns_torrent_vals *pcs_cmn_vals;
2102 int i, j, node, mlane, num_lanes, ret;
2103 struct cdns_reg_pairs *reg_pairs;
2104 enum cdns_torrent_ssc_mode ssc;
2105 struct regmap *regmap;
2108 /* Maximum 2 links (subnodes) are supported */
2109 if (cdns_phy->nsubnodes != 2)
2112 phy_t1 = cdns_phy->phys[0].phy_type;
2113 phy_t2 = cdns_phy->phys[1].phy_type;
2116 * First configure the PHY for first link with phy_t1. Get the array
2117 * values as [phy_t1][phy_t2][ssc].
2119 for (node = 0; node < cdns_phy->nsubnodes; node++) {
2122 * If first link with phy_t1 is configured, then
2123 * configure the PHY for second link with phy_t2.
2124 * Get the array values as [phy_t2][phy_t1][ssc].
2126 tmp_phy_type = phy_t1;
2128 phy_t2 = tmp_phy_type;
2131 mlane = cdns_phy->phys[node].mlane;
2132 ssc = cdns_phy->phys[node].ssc_mode;
2133 num_lanes = cdns_phy->phys[node].num_lanes;
2136 * PHY configuration specific registers:
2137 * link_cmn_vals depend on combination of PHY types being
2138 * configured and are common for both PHY types, so array
2139 * values should be same for [phy_t1][phy_t2][ssc] and
2140 * [phy_t2][phy_t1][ssc].
2141 * xcvr_diag_vals also depend on combination of PHY types
2142 * being configured, but these can be different for particular
2143 * PHY type and are per lane.
2145 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
2146 if (link_cmn_vals) {
2147 reg_pairs = link_cmn_vals->reg_pairs;
2148 num_regs = link_cmn_vals->num_regs;
2149 regmap = cdns_phy->regmap_common_cdb;
2152 * First array value in link_cmn_vals must be of
2153 * PHY_PLL_CFG register
2155 regmap_field_write(cdns_phy->phy_pll_cfg,
2158 for (i = 1; i < num_regs; i++)
2159 regmap_write(regmap, reg_pairs[i].off,
2163 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
2164 if (xcvr_diag_vals) {
2165 reg_pairs = xcvr_diag_vals->reg_pairs;
2166 num_regs = xcvr_diag_vals->num_regs;
2167 for (i = 0; i < num_lanes; i++) {
2168 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2169 for (j = 0; j < num_regs; j++)
2170 regmap_write(regmap, reg_pairs[j].off,
2175 /* PHY PCS common registers configurations */
2176 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
2178 reg_pairs = pcs_cmn_vals->reg_pairs;
2179 num_regs = pcs_cmn_vals->num_regs;
2180 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2181 for (i = 0; i < num_regs; i++)
2182 regmap_write(regmap, reg_pairs[i].off,
2186 /* PMA common registers configurations */
2187 cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc];
2189 reg_pairs = cmn_vals->reg_pairs;
2190 num_regs = cmn_vals->num_regs;
2191 regmap = cdns_phy->regmap_common_cdb;
2192 for (i = 0; i < num_regs; i++)
2193 regmap_write(regmap, reg_pairs[i].off,
2197 /* PMA TX lane registers configurations */
2198 tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc];
2200 reg_pairs = tx_ln_vals->reg_pairs;
2201 num_regs = tx_ln_vals->num_regs;
2202 for (i = 0; i < num_lanes; i++) {
2203 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2204 for (j = 0; j < num_regs; j++)
2205 regmap_write(regmap, reg_pairs[j].off,
2210 /* PMA RX lane registers configurations */
2211 rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc];
2213 reg_pairs = rx_ln_vals->reg_pairs;
2214 num_regs = rx_ln_vals->num_regs;
2215 for (i = 0; i < num_lanes; i++) {
2216 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
2217 for (j = 0; j < num_regs; j++)
2218 regmap_write(regmap, reg_pairs[j].off,
2223 reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2226 /* Take the PHY out of reset */
2227 ret = reset_control_deassert(cdns_phy->phy_rst);
2234 static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
2236 struct device *dev = cdns_phy->dev;
2238 of_clk_del_provider(dev->of_node);
2241 static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
2243 struct device *dev = cdns_phy->dev;
2244 struct device_node *node = dev->of_node;
2247 ret = cdns_torrent_derived_refclk_register(cdns_phy);
2249 dev_err(dev, "failed to register derived refclk\n");
2253 cdns_phy->clk_data.clks = cdns_phy->clks;
2254 cdns_phy->clk_data.clk_num = CDNS_TORRENT_REFCLK_DRIVER + 1;
2256 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &cdns_phy->clk_data);
2258 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
2265 static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
2267 struct device *dev = cdns_phy->dev;
2269 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
2270 if (IS_ERR(cdns_phy->phy_rst)) {
2271 dev_err(dev, "%s: failed to get reset\n",
2272 dev->of_node->full_name);
2273 return PTR_ERR(cdns_phy->phy_rst);
2276 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");
2277 if (IS_ERR(cdns_phy->apb_rst)) {
2278 dev_err(dev, "%s: failed to get apb reset\n",
2279 dev->of_node->full_name);
2280 return PTR_ERR(cdns_phy->apb_rst);
2286 static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2288 struct device *dev = cdns_phy->dev;
2291 cdns_phy->clk = devm_clk_get(dev, "refclk");
2292 if (IS_ERR(cdns_phy->clk)) {
2293 dev_err(dev, "phy ref clock not found\n");
2294 return PTR_ERR(cdns_phy->clk);
2297 ret = clk_prepare_enable(cdns_phy->clk);
2299 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2303 cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
2304 if (!(cdns_phy->ref_clk_rate)) {
2305 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2306 clk_disable_unprepare(cdns_phy->clk);
2313 static int cdns_torrent_phy_probe(struct platform_device *pdev)
2315 struct cdns_torrent_phy *cdns_phy;
2316 struct device *dev = &pdev->dev;
2317 struct phy_provider *phy_provider;
2318 const struct cdns_torrent_data *data;
2319 struct device_node *child;
2320 int ret, subnodes, node = 0, i;
2321 u32 total_num_lanes = 0;
2322 int already_configured;
2323 u8 init_dp_regmap = 0;
2326 /* Get init data for this PHY */
2327 data = of_device_get_match_data(dev);
2331 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
2335 dev_set_drvdata(dev, cdns_phy);
2336 cdns_phy->dev = dev;
2337 cdns_phy->init_data = data;
2339 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
2340 if (IS_ERR(cdns_phy->sd_base))
2341 return PTR_ERR(cdns_phy->sd_base);
2343 subnodes = of_get_available_child_count(dev->of_node);
2344 if (subnodes == 0) {
2345 dev_err(dev, "No available link subnodes found\n");
2349 ret = cdns_torrent_regmap_init(cdns_phy);
2353 ret = cdns_torrent_regfield_init(cdns_phy);
2357 ret = cdns_torrent_clk_register(cdns_phy);
2361 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured);
2363 if (!already_configured) {
2364 ret = cdns_torrent_reset(cdns_phy);
2368 ret = cdns_torrent_clk(cdns_phy);
2373 reset_control_deassert(cdns_phy->apb_rst);
2376 for_each_available_child_of_node(dev->of_node, child) {
2379 /* PHY subnode name must be 'phy'. */
2380 if (!(of_node_name_eq(child, "phy")))
2383 cdns_phy->phys[node].lnk_rst =
2384 of_reset_control_array_get_exclusive(child);
2385 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
2386 dev_err(dev, "%s: failed to get reset\n",
2388 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
2392 if (of_property_read_u32(child, "reg",
2393 &cdns_phy->phys[node].mlane)) {
2394 dev_err(dev, "%s: No \"reg\"-property.\n",
2400 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
2401 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
2409 cdns_phy->phys[node].phy_type = TYPE_PCIE;
2412 cdns_phy->phys[node].phy_type = TYPE_DP;
2414 case PHY_TYPE_SGMII:
2415 cdns_phy->phys[node].phy_type = TYPE_SGMII;
2417 case PHY_TYPE_QSGMII:
2418 cdns_phy->phys[node].phy_type = TYPE_QSGMII;
2421 cdns_phy->phys[node].phy_type = TYPE_USB;
2424 dev_err(dev, "Unsupported protocol\n");
2429 if (of_property_read_u32(child, "cdns,num-lanes",
2430 &cdns_phy->phys[node].num_lanes)) {
2431 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
2437 total_num_lanes += cdns_phy->phys[node].num_lanes;
2440 cdns_phy->phys[node].ssc_mode = NO_SSC;
2441 of_property_read_u32(child, "cdns,ssc-mode",
2442 &cdns_phy->phys[node].ssc_mode);
2444 if (!already_configured)
2445 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
2447 gphy = devm_phy_create(dev, child, &noop_ops);
2449 ret = PTR_ERR(gphy);
2453 if (cdns_phy->phys[node].phy_type == TYPE_DP) {
2454 switch (cdns_phy->phys[node].num_lanes) {
2458 /* valid number of lanes */
2461 dev_err(dev, "unsupported number of lanes: %d\n",
2462 cdns_phy->phys[node].num_lanes);
2467 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
2468 of_property_read_u32(child, "cdns,max-bit-rate",
2469 &cdns_phy->max_bit_rate);
2471 switch (cdns_phy->max_bit_rate) {
2480 /* valid bit rate */
2483 dev_err(dev, "unsupported max bit rate: %dMbps\n",
2484 cdns_phy->max_bit_rate);
2489 /* DPTX registers */
2490 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
2491 if (IS_ERR(cdns_phy->base)) {
2492 ret = PTR_ERR(cdns_phy->base);
2496 if (!init_dp_regmap) {
2497 ret = cdns_torrent_dp_regmap_init(cdns_phy);
2501 ret = cdns_torrent_dp_regfield_init(cdns_phy);
2508 dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
2509 cdns_phy->phys[node].num_lanes,
2510 cdns_phy->max_bit_rate / 1000,
2511 cdns_phy->max_bit_rate % 1000);
2513 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
2514 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
2515 gphy->attrs.mode = PHY_MODE_DP;
2518 cdns_phy->phys[node].phy = gphy;
2519 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
2523 cdns_phy->nsubnodes = node;
2525 if (total_num_lanes > MAX_NUM_LANES) {
2526 dev_err(dev, "Invalid lane configuration\n");
2531 if (cdns_phy->nsubnodes > 1 && !already_configured) {
2532 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
2537 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2538 if (IS_ERR(phy_provider)) {
2539 ret = PTR_ERR(phy_provider);
2548 for (i = 0; i < node; i++)
2549 reset_control_put(cdns_phy->phys[i].lnk_rst);
2551 reset_control_assert(cdns_phy->apb_rst);
2552 clk_disable_unprepare(cdns_phy->clk);
2554 cdns_torrent_clk_cleanup(cdns_phy);
2558 static int cdns_torrent_phy_remove(struct platform_device *pdev)
2560 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
2563 reset_control_assert(cdns_phy->phy_rst);
2564 reset_control_assert(cdns_phy->apb_rst);
2565 for (i = 0; i < cdns_phy->nsubnodes; i++) {
2566 reset_control_assert(cdns_phy->phys[i].lnk_rst);
2567 reset_control_put(cdns_phy->phys[i].lnk_rst);
2570 clk_disable_unprepare(cdns_phy->clk);
2571 cdns_torrent_clk_cleanup(cdns_phy);
2576 /* USB and SGMII/QSGMII link configuration */
2577 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
2578 {0x0002, PHY_PLL_CFG},
2579 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
2580 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
2583 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
2584 {0x0000, XCVR_DIAG_HSCLK_SEL},
2585 {0x0001, XCVR_DIAG_HSCLK_DIV},
2586 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
2589 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
2590 {0x0011, XCVR_DIAG_HSCLK_SEL},
2591 {0x0003, XCVR_DIAG_HSCLK_DIV},
2592 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
2595 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
2596 .reg_pairs = usb_sgmii_link_cmn_regs,
2597 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
2600 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
2601 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
2602 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
2605 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
2606 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
2607 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
2610 /* PCIe and USB Unique SSC link configuration */
2611 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
2612 {0x0003, PHY_PLL_CFG},
2613 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
2614 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
2615 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
2618 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
2619 {0x0000, XCVR_DIAG_HSCLK_SEL},
2620 {0x0001, XCVR_DIAG_HSCLK_DIV},
2621 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
2624 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
2625 {0x0011, XCVR_DIAG_HSCLK_SEL},
2626 {0x0001, XCVR_DIAG_HSCLK_DIV},
2627 {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
2630 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
2631 .reg_pairs = pcie_usb_link_cmn_regs,
2632 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
2635 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
2636 .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
2637 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
2640 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
2641 .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
2642 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
2645 /* USB 100 MHz Ref clk, internal SSC */
2646 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
2647 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2648 {0x0004, CMN_PLL0_DSM_DIAG_M1},
2649 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2650 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2651 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
2652 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2653 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2654 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
2655 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2656 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2657 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
2658 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2659 {0x0064, CMN_PLL0_INTDIV_M0},
2660 {0x0050, CMN_PLL0_INTDIV_M1},
2661 {0x0064, CMN_PLL1_INTDIV_M0},
2662 {0x0002, CMN_PLL0_FRACDIVH_M0},
2663 {0x0002, CMN_PLL0_FRACDIVH_M1},
2664 {0x0002, CMN_PLL1_FRACDIVH_M0},
2665 {0x0044, CMN_PLL0_HIGH_THR_M0},
2666 {0x0036, CMN_PLL0_HIGH_THR_M1},
2667 {0x0044, CMN_PLL1_HIGH_THR_M0},
2668 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2669 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
2670 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2671 {0x0001, CMN_PLL0_SS_CTRL1_M0},
2672 {0x0001, CMN_PLL0_SS_CTRL1_M1},
2673 {0x0001, CMN_PLL1_SS_CTRL1_M0},
2674 {0x011B, CMN_PLL0_SS_CTRL2_M0},
2675 {0x011B, CMN_PLL0_SS_CTRL2_M1},
2676 {0x011B, CMN_PLL1_SS_CTRL2_M0},
2677 {0x006E, CMN_PLL0_SS_CTRL3_M0},
2678 {0x0058, CMN_PLL0_SS_CTRL3_M1},
2679 {0x006E, CMN_PLL1_SS_CTRL3_M0},
2680 {0x000E, CMN_PLL0_SS_CTRL4_M0},
2681 {0x0012, CMN_PLL0_SS_CTRL4_M1},
2682 {0x000E, CMN_PLL1_SS_CTRL4_M0},
2683 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
2684 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
2685 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
2686 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
2687 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
2688 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
2689 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
2690 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
2691 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
2692 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
2693 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
2694 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
2695 {0x007F, CMN_TXPUCAL_TUNE},
2696 {0x007F, CMN_TXPDCAL_TUNE}
2699 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
2700 .reg_pairs = usb_100_int_ssc_cmn_regs,
2701 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
2704 /* Single USB link configuration */
2705 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
2706 {0x0000, PHY_PLL_CFG},
2707 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
2710 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
2711 {0x0000, XCVR_DIAG_HSCLK_SEL},
2712 {0x0001, XCVR_DIAG_HSCLK_DIV},
2713 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
2716 static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
2717 .reg_pairs = sl_usb_link_cmn_regs,
2718 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
2721 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
2722 .reg_pairs = sl_usb_xcvr_diag_ln_regs,
2723 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
2726 /* USB PHY PCS common configuration */
2727 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
2728 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
2729 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
2730 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
2733 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
2734 .reg_pairs = usb_phy_pcs_cmn_regs,
2735 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
2738 /* USB 100 MHz Ref clk, no SSC */
2739 static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
2740 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
2741 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
2742 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
2743 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2744 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2745 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
2746 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
2749 static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
2750 .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
2751 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
2754 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
2755 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
2756 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
2757 {0x007F, CMN_TXPUCAL_TUNE},
2758 {0x007F, CMN_TXPDCAL_TUNE}
2761 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
2762 {0x02FF, TX_PSC_A0},
2763 {0x06AF, TX_PSC_A1},
2764 {0x06AE, TX_PSC_A2},
2765 {0x06AE, TX_PSC_A3},
2766 {0x2A82, TX_TXCC_CTRL},
2767 {0x0014, TX_TXCC_CPOST_MULT_01},
2768 {0x0003, XCVR_DIAG_PSC_OVRD}
2771 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
2772 {0x0D1D, RX_PSC_A0},
2773 {0x0D1D, RX_PSC_A1},
2774 {0x0D00, RX_PSC_A2},
2775 {0x0500, RX_PSC_A3},
2776 {0x0013, RX_SIGDET_HL_FILT_TMR},
2777 {0x0000, RX_REE_GCSM1_CTRL},
2778 {0x0C02, RX_REE_ATTEN_THR},
2779 {0x0330, RX_REE_SMGM_CTRL1},
2780 {0x0300, RX_REE_SMGM_CTRL2},
2781 {0x0019, RX_REE_TAP1_CLIP},
2782 {0x0019, RX_REE_TAP2TON_CLIP},
2783 {0x1004, RX_DIAG_SIGDET_TUNE},
2784 {0x00F9, RX_DIAG_NQST_CTRL},
2785 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
2786 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
2787 {0x0000, RX_DIAG_PI_CAP},
2788 {0x0031, RX_DIAG_PI_RATE},
2789 {0x0001, RX_DIAG_ACYA},
2790 {0x018C, RX_CDRLF_CNFG},
2791 {0x0003, RX_CDRLF_CNFG3}
2794 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
2795 .reg_pairs = usb_100_no_ssc_cmn_regs,
2796 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
2799 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
2800 .reg_pairs = usb_100_no_ssc_tx_ln_regs,
2801 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
2804 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
2805 .reg_pairs = usb_100_no_ssc_rx_ln_regs,
2806 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
2809 /* Single link USB, 100 MHz Ref clk, internal SSC */
2810 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
2811 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2812 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2813 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2814 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2815 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2816 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2817 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2818 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2819 {0x0064, CMN_PLL0_INTDIV_M0},
2820 {0x0064, CMN_PLL1_INTDIV_M0},
2821 {0x0002, CMN_PLL0_FRACDIVH_M0},
2822 {0x0002, CMN_PLL1_FRACDIVH_M0},
2823 {0x0044, CMN_PLL0_HIGH_THR_M0},
2824 {0x0044, CMN_PLL1_HIGH_THR_M0},
2825 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2826 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2827 {0x0001, CMN_PLL0_SS_CTRL1_M0},
2828 {0x0001, CMN_PLL1_SS_CTRL1_M0},
2829 {0x011B, CMN_PLL0_SS_CTRL2_M0},
2830 {0x011B, CMN_PLL1_SS_CTRL2_M0},
2831 {0x006E, CMN_PLL0_SS_CTRL3_M0},
2832 {0x006E, CMN_PLL1_SS_CTRL3_M0},
2833 {0x000E, CMN_PLL0_SS_CTRL4_M0},
2834 {0x000E, CMN_PLL1_SS_CTRL4_M0},
2835 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
2836 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
2837 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
2838 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
2839 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2840 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2841 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
2842 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
2843 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
2844 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
2845 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
2846 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
2847 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
2848 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
2851 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
2852 .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
2853 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
2856 /* PCIe and SGMII/QSGMII Unique SSC link configuration */
2857 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
2858 {0x0003, PHY_PLL_CFG},
2859 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
2860 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
2861 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
2864 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
2865 {0x0000, XCVR_DIAG_HSCLK_SEL},
2866 {0x0001, XCVR_DIAG_HSCLK_DIV},
2867 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
2870 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
2871 {0x0011, XCVR_DIAG_HSCLK_SEL},
2872 {0x0003, XCVR_DIAG_HSCLK_DIV},
2873 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
2876 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
2877 .reg_pairs = pcie_sgmii_link_cmn_regs,
2878 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
2881 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
2882 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
2883 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
2886 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
2887 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
2888 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
2891 /* SGMII 100 MHz Ref clk, no SSC */
2892 static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
2893 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
2894 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
2895 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
2896 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2897 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2900 static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
2901 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
2902 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
2905 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
2906 {0x007F, CMN_TXPUCAL_TUNE},
2907 {0x007F, CMN_TXPDCAL_TUNE}
2910 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
2911 {0x00F3, TX_PSC_A0},
2912 {0x04A2, TX_PSC_A2},
2913 {0x04A2, TX_PSC_A3},
2914 {0x0000, TX_TXCC_CPOST_MULT_00},
2915 {0x00B3, DRV_DIAG_TX_DRV}
2918 static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
2919 {0x00F3, TX_PSC_A0},
2920 {0x04A2, TX_PSC_A2},
2921 {0x04A2, TX_PSC_A3},
2922 {0x0000, TX_TXCC_CPOST_MULT_00},
2923 {0x00B3, DRV_DIAG_TX_DRV},
2924 {0x4000, XCVR_DIAG_RXCLK_CTRL},
2927 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
2928 {0x091D, RX_PSC_A0},
2929 {0x0900, RX_PSC_A2},
2930 {0x0100, RX_PSC_A3},
2931 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
2932 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
2933 {0x0000, RX_DIAG_DFE_CTRL},
2934 {0x0019, RX_REE_TAP1_CLIP},
2935 {0x0019, RX_REE_TAP2TON_CLIP},
2936 {0x0098, RX_DIAG_NQST_CTRL},
2937 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
2938 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
2939 {0x0000, RX_DIAG_PI_CAP},
2940 {0x0010, RX_DIAG_PI_RATE},
2941 {0x0001, RX_DIAG_ACYA},
2942 {0x018C, RX_CDRLF_CNFG},
2945 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
2946 .reg_pairs = sgmii_100_no_ssc_cmn_regs,
2947 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
2950 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
2951 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
2952 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
2955 static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
2956 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
2957 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
2960 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
2961 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
2962 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
2965 /* SGMII 100 MHz Ref clk, internal SSC */
2966 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
2967 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2968 {0x0004, CMN_PLL0_DSM_DIAG_M1},
2969 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2970 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2971 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
2972 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2973 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2974 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
2975 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2976 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2977 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
2978 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2979 {0x0064, CMN_PLL0_INTDIV_M0},
2980 {0x0050, CMN_PLL0_INTDIV_M1},
2981 {0x0064, CMN_PLL1_INTDIV_M0},
2982 {0x0002, CMN_PLL0_FRACDIVH_M0},
2983 {0x0002, CMN_PLL0_FRACDIVH_M1},
2984 {0x0002, CMN_PLL1_FRACDIVH_M0},
2985 {0x0044, CMN_PLL0_HIGH_THR_M0},
2986 {0x0036, CMN_PLL0_HIGH_THR_M1},
2987 {0x0044, CMN_PLL1_HIGH_THR_M0},
2988 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2989 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
2990 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2991 {0x0001, CMN_PLL0_SS_CTRL1_M0},
2992 {0x0001, CMN_PLL0_SS_CTRL1_M1},
2993 {0x0001, CMN_PLL1_SS_CTRL1_M0},
2994 {0x011B, CMN_PLL0_SS_CTRL2_M0},
2995 {0x011B, CMN_PLL0_SS_CTRL2_M1},
2996 {0x011B, CMN_PLL1_SS_CTRL2_M0},
2997 {0x006E, CMN_PLL0_SS_CTRL3_M0},
2998 {0x0058, CMN_PLL0_SS_CTRL3_M1},
2999 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3000 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3001 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3002 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3003 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3004 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3005 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3006 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3007 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3008 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3009 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3010 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3011 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3012 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3013 {0x007F, CMN_TXPUCAL_TUNE},
3014 {0x007F, CMN_TXPDCAL_TUNE}
3017 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
3018 .reg_pairs = sgmii_100_int_ssc_cmn_regs,
3019 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
3022 /* QSGMII 100 MHz Ref clk, no SSC */
3023 static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
3024 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3025 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3026 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3027 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3028 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3031 static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
3032 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
3033 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
3036 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
3037 {0x007F, CMN_TXPUCAL_TUNE},
3038 {0x007F, CMN_TXPDCAL_TUNE}
3041 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
3042 {0x00F3, TX_PSC_A0},
3043 {0x04A2, TX_PSC_A2},
3044 {0x04A2, TX_PSC_A3},
3045 {0x0000, TX_TXCC_CPOST_MULT_00},
3046 {0x0011, TX_TXCC_MGNFS_MULT_100},
3047 {0x0003, DRV_DIAG_TX_DRV}
3050 static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
3051 {0x00F3, TX_PSC_A0},
3052 {0x04A2, TX_PSC_A2},
3053 {0x04A2, TX_PSC_A3},
3054 {0x0000, TX_TXCC_CPOST_MULT_00},
3055 {0x0011, TX_TXCC_MGNFS_MULT_100},
3056 {0x0003, DRV_DIAG_TX_DRV},
3057 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3060 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
3061 {0x091D, RX_PSC_A0},
3062 {0x0900, RX_PSC_A2},
3063 {0x0100, RX_PSC_A3},
3064 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3065 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3066 {0x0000, RX_DIAG_DFE_CTRL},
3067 {0x0019, RX_REE_TAP1_CLIP},
3068 {0x0019, RX_REE_TAP2TON_CLIP},
3069 {0x0098, RX_DIAG_NQST_CTRL},
3070 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3071 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3072 {0x0000, RX_DIAG_PI_CAP},
3073 {0x0010, RX_DIAG_PI_RATE},
3074 {0x0001, RX_DIAG_ACYA},
3075 {0x018C, RX_CDRLF_CNFG},
3078 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
3079 .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
3080 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
3083 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
3084 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
3085 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
3088 static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
3089 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
3090 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
3093 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
3094 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
3095 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
3098 /* QSGMII 100 MHz Ref clk, internal SSC */
3099 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
3100 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3101 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3102 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3103 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3104 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3105 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3106 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3107 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3108 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3109 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3110 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3111 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3112 {0x0064, CMN_PLL0_INTDIV_M0},
3113 {0x0050, CMN_PLL0_INTDIV_M1},
3114 {0x0064, CMN_PLL1_INTDIV_M0},
3115 {0x0002, CMN_PLL0_FRACDIVH_M0},
3116 {0x0002, CMN_PLL0_FRACDIVH_M1},
3117 {0x0002, CMN_PLL1_FRACDIVH_M0},
3118 {0x0044, CMN_PLL0_HIGH_THR_M0},
3119 {0x0036, CMN_PLL0_HIGH_THR_M1},
3120 {0x0044, CMN_PLL1_HIGH_THR_M0},
3121 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3122 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3123 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3124 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3125 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3126 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3127 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3128 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3129 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3130 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3131 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3132 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3133 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3134 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3135 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3136 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3137 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3138 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3139 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3140 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3141 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3142 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3143 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3144 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3145 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3146 {0x007F, CMN_TXPUCAL_TUNE},
3147 {0x007F, CMN_TXPDCAL_TUNE}
3150 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
3151 .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
3152 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
3155 /* Single SGMII/QSGMII link configuration */
3156 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
3157 {0x0000, PHY_PLL_CFG},
3158 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
3161 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
3162 {0x0000, XCVR_DIAG_HSCLK_SEL},
3163 {0x0003, XCVR_DIAG_HSCLK_DIV},
3164 {0x0013, XCVR_DIAG_PLLDRC_CTRL}
3167 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
3168 .reg_pairs = sl_sgmii_link_cmn_regs,
3169 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
3172 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
3173 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
3174 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
3177 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */
3178 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
3179 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3180 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3181 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3182 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3183 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3184 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3185 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3186 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3187 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3188 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3189 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3190 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3191 {0x0064, CMN_PLL0_INTDIV_M0},
3192 {0x0050, CMN_PLL0_INTDIV_M1},
3193 {0x0064, CMN_PLL1_INTDIV_M0},
3194 {0x0002, CMN_PLL0_FRACDIVH_M0},
3195 {0x0002, CMN_PLL0_FRACDIVH_M1},
3196 {0x0002, CMN_PLL1_FRACDIVH_M0},
3197 {0x0044, CMN_PLL0_HIGH_THR_M0},
3198 {0x0036, CMN_PLL0_HIGH_THR_M1},
3199 {0x0044, CMN_PLL1_HIGH_THR_M0},
3200 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3201 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3202 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3203 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3204 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3205 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3206 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3207 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3208 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3209 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3210 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3211 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3212 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3213 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3214 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3215 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3216 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3217 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3218 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3219 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3220 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3221 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3222 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3223 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3224 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3227 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
3228 .reg_pairs = pcie_100_int_ssc_cmn_regs,
3229 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
3232 /* Single link PCIe, 100 MHz Ref clk, internal SSC */
3233 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
3234 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3235 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3236 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3237 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3238 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3239 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3240 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3241 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3242 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3243 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3244 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3245 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3246 {0x0064, CMN_PLL0_INTDIV_M0},
3247 {0x0050, CMN_PLL0_INTDIV_M1},
3248 {0x0050, CMN_PLL1_INTDIV_M0},
3249 {0x0002, CMN_PLL0_FRACDIVH_M0},
3250 {0x0002, CMN_PLL0_FRACDIVH_M1},
3251 {0x0002, CMN_PLL1_FRACDIVH_M0},
3252 {0x0044, CMN_PLL0_HIGH_THR_M0},
3253 {0x0036, CMN_PLL0_HIGH_THR_M1},
3254 {0x0036, CMN_PLL1_HIGH_THR_M0},
3255 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3256 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3257 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3258 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3259 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3260 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3261 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3262 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3263 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3264 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3265 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3266 {0x0058, CMN_PLL1_SS_CTRL3_M0},
3267 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3268 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3269 {0x0012, CMN_PLL1_SS_CTRL4_M0},
3270 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3271 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3272 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3273 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3274 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3275 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3276 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3277 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3278 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3279 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3282 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
3283 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
3284 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
3287 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */
3288 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
3289 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3290 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3291 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
3294 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
3295 {0x0019, RX_REE_TAP1_CLIP},
3296 {0x0019, RX_REE_TAP2TON_CLIP},
3297 {0x0001, RX_DIAG_ACYA}
3300 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
3301 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
3302 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
3305 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
3306 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
3307 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
3310 static const struct cdns_torrent_data cdns_map_torrent = {
3311 .block_offset_shift = 0x2,
3312 .reg_offset_shift = 0x2,
3317 [EXTERNAL_SSC] = NULL,
3318 [INTERNAL_SSC] = NULL,
3321 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3322 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3323 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3326 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3327 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3328 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3331 [NO_SSC] = &pcie_usb_link_cmn_vals,
3332 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3333 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3338 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3341 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3342 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3343 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3346 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3347 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3348 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3353 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3356 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3357 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3358 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3361 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3362 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3363 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3368 [NO_SSC] = &sl_usb_link_cmn_vals,
3369 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
3370 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
3373 [NO_SSC] = &pcie_usb_link_cmn_vals,
3374 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3375 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3378 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3379 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3380 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3383 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3384 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3385 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3393 [EXTERNAL_SSC] = NULL,
3394 [INTERNAL_SSC] = NULL,
3397 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3398 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3399 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3402 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3403 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3404 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3407 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3408 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3409 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3414 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3417 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3418 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3419 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3422 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3423 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3424 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3429 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3432 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3433 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3434 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3437 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3438 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3439 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3444 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
3445 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3446 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3449 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3450 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3451 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3454 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3455 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3456 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3459 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3460 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3461 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3468 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3469 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3470 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3473 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3474 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3475 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3478 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3479 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3480 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3483 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3484 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3485 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3493 [EXTERNAL_SSC] = NULL,
3494 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
3497 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3498 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3499 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3502 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3503 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3504 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3507 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3508 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3509 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3514 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
3517 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3518 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3519 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
3522 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3523 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3524 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3529 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
3532 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3533 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3534 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
3537 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3538 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3539 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3544 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3545 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3546 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3549 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3550 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3551 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
3554 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3555 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3556 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3559 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3560 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3561 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3569 [EXTERNAL_SSC] = NULL,
3570 [INTERNAL_SSC] = NULL,
3574 [EXTERNAL_SSC] = NULL,
3575 [INTERNAL_SSC] = NULL,
3579 [EXTERNAL_SSC] = NULL,
3580 [INTERNAL_SSC] = NULL,
3584 [EXTERNAL_SSC] = NULL,
3585 [INTERNAL_SSC] = NULL,
3590 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3593 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3594 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3595 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3598 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3599 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3600 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3605 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3608 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3609 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3610 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3613 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3614 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3615 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3620 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3621 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3622 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3625 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3626 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3627 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3630 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3631 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3632 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3635 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3636 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3637 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3644 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3645 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3646 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3649 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3650 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3651 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3654 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3655 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3656 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3659 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3660 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3661 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3666 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3669 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3670 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3671 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3674 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3675 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3676 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3681 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3684 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3685 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3686 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3689 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3690 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3691 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3696 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3697 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3698 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3701 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3702 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3703 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3706 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3707 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3708 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3711 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3712 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3713 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3719 static const struct cdns_torrent_data ti_j721e_map_torrent = {
3720 .block_offset_shift = 0x0,
3721 .reg_offset_shift = 0x1,
3726 [EXTERNAL_SSC] = NULL,
3727 [INTERNAL_SSC] = NULL,
3730 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3731 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3732 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3735 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3736 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3737 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3740 [NO_SSC] = &pcie_usb_link_cmn_vals,
3741 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3742 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3747 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3750 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3751 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3752 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3755 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3756 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3757 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3762 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3765 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3766 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3767 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3770 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3771 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3772 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3777 [NO_SSC] = &sl_usb_link_cmn_vals,
3778 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
3779 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
3782 [NO_SSC] = &pcie_usb_link_cmn_vals,
3783 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3784 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3787 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3788 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3789 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3792 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3793 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3794 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3802 [EXTERNAL_SSC] = NULL,
3803 [INTERNAL_SSC] = NULL,
3806 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3807 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3808 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3811 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3812 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3813 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3816 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3817 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3818 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3823 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3826 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3827 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3828 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3831 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3832 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3833 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3838 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3841 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3842 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3843 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3846 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3847 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3848 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3853 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
3854 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3855 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3858 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3859 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3860 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3863 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3864 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3865 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3868 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3869 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3870 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3877 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3878 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3879 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3882 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3883 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3884 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3887 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3888 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3889 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3892 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3893 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3894 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3902 [EXTERNAL_SSC] = NULL,
3903 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
3906 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3907 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3908 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3911 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3912 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3913 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3916 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3917 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3918 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3923 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
3926 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3927 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3928 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
3931 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3932 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3933 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3938 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
3941 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3942 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3943 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
3946 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3947 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3948 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3953 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3954 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3955 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3958 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3959 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3960 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
3963 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3964 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3965 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3968 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3969 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3970 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3978 [EXTERNAL_SSC] = NULL,
3979 [INTERNAL_SSC] = NULL,
3983 [EXTERNAL_SSC] = NULL,
3984 [INTERNAL_SSC] = NULL,
3988 [EXTERNAL_SSC] = NULL,
3989 [INTERNAL_SSC] = NULL,
3993 [EXTERNAL_SSC] = NULL,
3994 [INTERNAL_SSC] = NULL,
3999 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4002 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4003 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4004 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4007 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4008 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4009 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4014 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4017 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4018 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4019 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4022 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4023 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4024 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4029 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4030 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4031 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4034 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4035 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4036 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4039 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4040 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4041 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4044 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4045 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4046 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4053 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4054 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4055 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4058 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4059 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4060 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4063 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4064 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4065 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4068 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4069 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4070 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4075 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4078 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4079 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4080 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4083 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4084 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4085 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4090 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4093 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4094 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4095 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4098 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4099 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4100 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4105 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4106 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4107 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4110 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4111 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4112 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4115 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4116 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4117 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4120 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4121 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4122 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4128 static const struct of_device_id cdns_torrent_phy_of_match[] = {
4130 .compatible = "cdns,torrent-phy",
4131 .data = &cdns_map_torrent,
4134 .compatible = "ti,j721e-serdes-10g",
4135 .data = &ti_j721e_map_torrent,
4139 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
4141 static struct platform_driver cdns_torrent_phy_driver = {
4142 .probe = cdns_torrent_phy_probe,
4143 .remove = cdns_torrent_phy_remove,
4145 .name = "cdns-torrent-phy",
4146 .of_match_table = cdns_torrent_phy_of_match,
4149 module_platform_driver(cdns_torrent_phy_driver);
4151 MODULE_AUTHOR("Cadence Design Systems, Inc.");
4152 MODULE_DESCRIPTION("Cadence Torrent PHY driver");
4153 MODULE_LICENSE("GPL v2");