drivers/phy/broadcom/phy-brcm-usb-init.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
   4  *
   5  * Copyright (C) 2014-2017 Broadcom
   6  */
   7
   8 /*
   9  * This module contains USB PHY initialization for power up and S3 resume
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/io.h>
  14
  15 #include <linux/soc/brcmstb/brcmstb.h>
  16 #include "phy-brcm-usb-init.h"
  17
  18 #define PHY_PORTS 2
  19 #define PHY_PORT_SELECT_0 0
  20 #define PHY_PORT_SELECT_1 0x1000
  21
  22 /* Register definitions for the USB CTRL block */
  23 #define USB_CTRL_SETUP                  0x00
  24 #define   USB_CTRL_SETUP_IOC_MASK                       0x00000010
  25 #define   USB_CTRL_SETUP_IPP_MASK                       0x00000020
  26 #define   USB_CTRL_SETUP_BABO_MASK                      0x00000001
  27 #define   USB_CTRL_SETUP_FNHW_MASK                      0x00000002
  28 #define   USB_CTRL_SETUP_FNBO_MASK                      0x00000004
  29 #define   USB_CTRL_SETUP_WABO_MASK                      0x00000008
  30 #define   USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK           0x00002000 /* option */
  31 #define   USB_CTRL_SETUP_SCB1_EN_MASK                   0x00004000 /* option */
  32 #define   USB_CTRL_SETUP_SCB2_EN_MASK                   0x00008000 /* option */
  33 #define   USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK           0X00020000 /* option */
  34 #define   USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK       0x00010000 /* option */
  35 #define   USB_CTRL_SETUP_STRAP_IPP_SEL_MASK             0x02000000 /* option */
  36 #define   USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK        0x04000000 /* option */
  37 #define   USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK 0x08000000 /* opt */
  38 #define   USB_CTRL_SETUP_OC3_DISABLE_MASK               0xc0000000 /* option */
  39 #define USB_CTRL_PLL_CTL                0x04
  40 #define   USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK          0x08000000
  41 #define   USB_CTRL_PLL_CTL_PLL_RESETB_MASK              0x40000000
  42 #define   USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK          0x80000000 /* option */
  43 #define USB_CTRL_EBRIDGE                0x0c
  44 #define   USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK           0x00020000 /* option */
  45 #define   USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK            0x00000f80 /* option */
  46 #define USB_CTRL_OBRIDGE                0x10
  47 #define   USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK           0x08000000
  48 #define USB_CTRL_MDIO                   0x14
  49 #define USB_CTRL_MDIO2                  0x18
  50 #define USB_CTRL_UTMI_CTL_1             0x2c
  51 #define   USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK      0x00000800
  52 #define   USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK   0x08000000
  53 #define USB_CTRL_USB_PM                 0x34
  54 #define   USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK          0x00800000 /* option */
  55 #define   USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK          0x00400000 /* option */
  56 #define   USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK      0x40000000 /* option */
  57 #define   USB_CTRL_USB_PM_USB_PWRDN_MASK                0x80000000 /* option */
  58 #define   USB_CTRL_USB_PM_SOFT_RESET_MASK               0x40000000 /* option */
  59 #define   USB_CTRL_USB_PM_USB20_HC_RESETB_MASK          0x30000000 /* option */
  60 #define   USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK      0x00300000 /* option */
  61 #define   USB_CTRL_USB_PM_RMTWKUP_EN_MASK               0x00000001
  62 #define USB_CTRL_USB_PM_STATUS          0x38
  63 #define USB_CTRL_USB30_CTL1             0x60
  64 #define   USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK   0x00000010
  65 #define   USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK          0x00010000
  66 #define   USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK      0x00020000 /* option */
  67 #define   USB_CTRL_USB30_CTL1_USB3_IOC_MASK             0x10000000 /* option */
  68 #define   USB_CTRL_USB30_CTL1_USB3_IPP_MASK             0x20000000 /* option */
  69 #define USB_CTRL_USB30_PCTL             0x70
  70 #define   USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK     0x00000002
  71 #define   USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK   0x00008000
  72 #define   USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK  0x00020000
  73 #define USB_CTRL_USB_DEVICE_CTL1        0x90
  74 #define   USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK       0x00000003 /* option */
  75
  76 /* Register definitions for the XHCI EC block */
  77 #define USB_XHCI_EC_IRAADR 0x658
  78 #define USB_XHCI_EC_IRADAT 0x65c
  79
  80 enum brcm_family_type {
  81         BRCM_FAMILY_3390A0,
  82         BRCM_FAMILY_4908,
  83         BRCM_FAMILY_7250B0,
  84         BRCM_FAMILY_7271A0,
  85         BRCM_FAMILY_7364A0,
  86         BRCM_FAMILY_7366C0,
  87         BRCM_FAMILY_74371A0,
  88         BRCM_FAMILY_7439B0,
  89         BRCM_FAMILY_7445D0,
  90         BRCM_FAMILY_7260A0,
  91         BRCM_FAMILY_7278A0,
  92         BRCM_FAMILY_COUNT,
  93 };
  94
  95 #define USB_BRCM_FAMILY(chip) \
  96         [BRCM_FAMILY_##chip] = __stringify(chip)
  97
  98 static const char *family_names[BRCM_FAMILY_COUNT] = {
  99         USB_BRCM_FAMILY(3390A0),
 100         USB_BRCM_FAMILY(4908),
 101         USB_BRCM_FAMILY(7250B0),
 102         USB_BRCM_FAMILY(7271A0),
 103         USB_BRCM_FAMILY(7364A0),
 104         USB_BRCM_FAMILY(7366C0),
 105         USB_BRCM_FAMILY(74371A0),
 106         USB_BRCM_FAMILY(7439B0),
 107         USB_BRCM_FAMILY(7445D0),
 108         USB_BRCM_FAMILY(7260A0),
 109         USB_BRCM_FAMILY(7278A0),
 110 };
 111
 112 enum {
 113         USB_CTRL_SETUP_SCB1_EN_SELECTOR,
 114         USB_CTRL_SETUP_SCB2_EN_SELECTOR,
 115         USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR,
 116         USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR,
 117         USB_CTRL_SETUP_OC3_DISABLE_SELECTOR,
 118         USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR,
 119         USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR,
 120         USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR,
 121         USB_CTRL_USB_PM_USB_PWRDN_SELECTOR,
 122         USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR,
 123         USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR,
 124         USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR,
 125         USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR,
 126         USB_CTRL_USB_PM_SOFT_RESET_SELECTOR,
 127         USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR,
 128         USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR,
 129         USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR,
 130         USB_CTRL_SETUP_ENDIAN_SELECTOR,
 131         USB_CTRL_SELECTOR_COUNT,
 132 };
 133
 134 #define USB_CTRL_MASK_FAMILY(params, reg, field)                        \
 135         (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
 136
 137 #define USB_CTRL_SET_FAMILY(params, reg, field) \
 138         usb_ctrl_set_family(params, USB_CTRL_##reg,     \
 139                         USB_CTRL_##reg##_##field##_SELECTOR)
 140 #define USB_CTRL_UNSET_FAMILY(params, reg, field)       \
 141         usb_ctrl_unset_family(params, USB_CTRL_##reg,   \
 142                 USB_CTRL_##reg##_##field##_SELECTOR)
 143
 144 #define MDIO_USB2       0
 145 #define MDIO_USB3       BIT(31)
 146
 147 #define USB_CTRL_SETUP_ENDIAN_BITS (    \
 148                 USB_CTRL_MASK(SETUP, BABO) |    \
 149                 USB_CTRL_MASK(SETUP, FNHW) |    \
 150                 USB_CTRL_MASK(SETUP, FNBO) |    \
 151                 USB_CTRL_MASK(SETUP, WABO))
 152
 153 #ifdef __LITTLE_ENDIAN
 154 #define ENDIAN_SETTINGS (                       \
 155                 USB_CTRL_MASK(SETUP, BABO) |    \
 156                 USB_CTRL_MASK(SETUP, FNHW))
 157 #else
 158 #define ENDIAN_SETTINGS (                       \
 159                 USB_CTRL_MASK(SETUP, FNHW) |    \
 160                 USB_CTRL_MASK(SETUP, FNBO) |    \
 161                 USB_CTRL_MASK(SETUP, WABO))
 162 #endif
 163
 164 struct id_to_type {
 165         u32 id;
 166         int type;
 167 };
 168
 169 static const struct id_to_type id_to_type_table[] = {
 170         { 0x33900000, BRCM_FAMILY_3390A0 },
 171         { 0x72500010, BRCM_FAMILY_7250B0 },
 172         { 0x72600000, BRCM_FAMILY_7260A0 },
 173         { 0x72550000, BRCM_FAMILY_7260A0 },
 174         { 0x72680000, BRCM_FAMILY_7271A0 },
 175         { 0x72710000, BRCM_FAMILY_7271A0 },
 176         { 0x73640000, BRCM_FAMILY_7364A0 },
 177         { 0x73660020, BRCM_FAMILY_7366C0 },
 178         { 0x07437100, BRCM_FAMILY_74371A0 },
 179         { 0x74390010, BRCM_FAMILY_7439B0 },
 180         { 0x74450030, BRCM_FAMILY_7445D0 },
 181         { 0x72780000, BRCM_FAMILY_7278A0 },
 182         { 0, BRCM_FAMILY_7271A0 }, /* default */
 183 };
 184
 185 static const u32
 186 usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
 187         /* 3390B0 */
 188         [BRCM_FAMILY_3390A0] = {
 189                 USB_CTRL_SETUP_SCB1_EN_MASK,
 190                 USB_CTRL_SETUP_SCB2_EN_MASK,
 191                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 192                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 193                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 194                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 195                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 196                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 197                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 198                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 199                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 200                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 201                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 202                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 203                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 204                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 205                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 206                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 207         },
 208         /* 4908 */
 209         [BRCM_FAMILY_4908] = {
 210                 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
 211                 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
 212                 0, /* USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
 213                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 214                 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
 215                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 216                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 217                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 218                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 219                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 220                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 221                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 222                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 223                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 224                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 225                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 226                 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK */
 227                 0, /* USB_CTRL_SETUP ENDIAN bits */
 228         },
 229         /* 7250b0 */
 230         [BRCM_FAMILY_7250B0] = {
 231                 USB_CTRL_SETUP_SCB1_EN_MASK,
 232                 USB_CTRL_SETUP_SCB2_EN_MASK,
 233                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 234                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 235                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 236                 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 237                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 238                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 239                 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
 240                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 241                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 242                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 243                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 244                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 245                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 246                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 247                 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 248                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 249         },
 250         /* 7271a0 */
 251         [BRCM_FAMILY_7271A0] = {
 252                 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
 253                 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
 254                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 255                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 256                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 257                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 258                 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 259                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 260                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 261                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 262                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 263                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 264                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 265                 USB_CTRL_USB_PM_SOFT_RESET_MASK,
 266                 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
 267                 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
 268                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 269                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 270         },
 271         /* 7364a0 */
 272         [BRCM_FAMILY_7364A0] = {
 273                 USB_CTRL_SETUP_SCB1_EN_MASK,
 274                 USB_CTRL_SETUP_SCB2_EN_MASK,
 275                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 276                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 277                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 278                 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 279                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 280                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 281                 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
 282                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 283                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 284                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 285                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 286                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 287                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 288                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 289                 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 290                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 291         },
 292         /* 7366c0 */
 293         [BRCM_FAMILY_7366C0] = {
 294                 USB_CTRL_SETUP_SCB1_EN_MASK,
 295                 USB_CTRL_SETUP_SCB2_EN_MASK,
 296                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 297                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 298                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 299                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 300                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 301                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 302                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 303                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 304                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 305                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 306                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 307                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 308                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 309                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 310                 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 311                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 312         },
 313         /* 74371A0 */
 314         [BRCM_FAMILY_74371A0] = {
 315                 USB_CTRL_SETUP_SCB1_EN_MASK,
 316                 USB_CTRL_SETUP_SCB2_EN_MASK,
 317                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
 318                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 319                 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
 320                 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 321                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 322                 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
 323                 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
 324                 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
 325                 USB_CTRL_USB30_CTL1_USB3_IOC_MASK,
 326                 USB_CTRL_USB30_CTL1_USB3_IPP_MASK,
 327                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 328                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 329                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 330                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 331                 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
 332                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 333         },
 334         /* 7439B0 */
 335         [BRCM_FAMILY_7439B0] = {
 336                 USB_CTRL_SETUP_SCB1_EN_MASK,
 337                 USB_CTRL_SETUP_SCB2_EN_MASK,
 338                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 339                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 340                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 341                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 342                 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 343                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 344                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 345                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 346                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 347                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 348                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 349                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 350                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 351                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 352                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 353                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 354         },
 355         /* 7445d0 */
 356         [BRCM_FAMILY_7445D0] = {
 357                 USB_CTRL_SETUP_SCB1_EN_MASK,
 358                 USB_CTRL_SETUP_SCB2_EN_MASK,
 359                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
 360                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 361                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 362                 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 363                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 364                 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
 365                 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
 366                 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
 367                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 368                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 369                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 370                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 371                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 372                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 373                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 374                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 375         },
 376         /* 7260a0 */
 377         [BRCM_FAMILY_7260A0] = {
 378                 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
 379                 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
 380                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 381                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 382                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 383                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 384                 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 385                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 386                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 387                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 388                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 389                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 390                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 391                 USB_CTRL_USB_PM_SOFT_RESET_MASK,
 392                 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
 393                 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
 394                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 395                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 396         },
 397         /* 7278a0 */
 398         [BRCM_FAMILY_7278A0] = {
 399                 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
 400                 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
 401                 0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
 402                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 403                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 404                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 405                 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 406                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 407                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 408                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 409                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 410                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 411                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 412                 USB_CTRL_USB_PM_SOFT_RESET_MASK,
 413                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 414                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 415                 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
 416                 0, /* USB_CTRL_SETUP ENDIAN bits */
 417         },
 418 };
 419
 420 static inline
 421 void usb_ctrl_unset_family(struct brcm_usb_init_params *params,
 422                            u32 reg_offset, u32 field)
 423 {
 424         u32 mask;
 425
 426         mask = params->usb_reg_bits_map[field];
 427         brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);
 428 };
 429
 430 static inline
 431 void usb_ctrl_set_family(struct brcm_usb_init_params *params,
 432                          u32 reg_offset, u32 field)
 433 {
 434         u32 mask;
 435
 436         mask = params->usb_reg_bits_map[field];
 437         brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);
 438 };
 439
 440 static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode)
 441 {
 442         u32 data;
 443
 444         data = (reg << 16) | mode;
 445         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 446         data |= (1 << 24);
 447         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 448         data &= ~(1 << 24);
 449         /* wait for the 60MHz parallel to serial shifter */
 450         usleep_range(10, 20);
 451         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 452         /* wait for the 60MHz parallel to serial shifter */
 453         usleep_range(10, 20);
 454
 455         return brcm_usb_readl(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff;
 456 }
 457
 458 static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg,
 459                                    u32 val, int mode)
 460 {
 461         u32 data;
 462
 463         data = (reg << 16) | val | mode;
 464         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 465         data |= (1 << 25);
 466         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 467         data &= ~(1 << 25);
 468
 469         /* wait for the 60MHz parallel to serial shifter */
 470         usleep_range(10, 20);
 471         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 472         /* wait for the 60MHz parallel to serial shifter */
 473         usleep_range(10, 20);
 474 }
 475
 476 static void brcmusb_usb_phy_ldo_fix(void __iomem *ctrl_base)
 477 {
 478         /* first disable FSM but also leave it that way */
 479         /* to allow normal suspend/resume */
 480         USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN);
 481         USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN_P1);
 482
 483         /* reset USB 2.0 PLL */
 484         USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB);
 485         /* PLL reset period */
 486         udelay(1);
 487         USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB);
 488         /* Give PLL enough time to lock */
 489         usleep_range(1000, 2000);
 490 }
 491
 492 static void brcmusb_usb2_eye_fix(void __iomem *ctrl_base)
 493 {
 494         /* Increase USB 2.0 TX level to meet spec requirement */
 495         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x80a0, MDIO_USB2);
 496         brcmusb_usb_mdio_write(ctrl_base, 0x0a, 0xc6a0, MDIO_USB2);
 497 }
 498
 499 static void brcmusb_usb3_pll_fix(void __iomem *ctrl_base)
 500 {
 501         /* Set correct window for PLL lock detect */
 502         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 503         brcmusb_usb_mdio_write(ctrl_base, 0x07, 0x1503, MDIO_USB3);
 504 }
 505
 506 static void brcmusb_usb3_enable_pipe_reset(void __iomem *ctrl_base)
 507 {
 508         u32 val;
 509
 510         /* Re-enable USB 3.0 pipe reset */
 511         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 512         val = brcmusb_usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200;
 513         brcmusb_usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3);
 514 }
 515
 516 static void brcmusb_usb3_enable_sigdet(void __iomem *ctrl_base)
 517 {
 518         u32 val, ofs;
 519         int ii;
 520
 521         ofs = 0;
 522         for (ii = 0; ii < PHY_PORTS; ++ii) {
 523                 /* Set correct default for sigdet */
 524                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8080 + ofs),
 525                                        MDIO_USB3);
 526                 val = brcmusb_usb_mdio_read(ctrl_base, 0x05, MDIO_USB3);
 527                 val = (val & ~0x800f) | 0x800d;
 528                 brcmusb_usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3);
 529                 ofs = PHY_PORT_SELECT_1;
 530         }
 531 }
 532
 533 static void brcmusb_usb3_enable_skip_align(void __iomem *ctrl_base)
 534 {
 535         u32 val, ofs;
 536         int ii;
 537
 538         ofs = 0;
 539         for (ii = 0; ii < PHY_PORTS; ++ii) {
 540                 /* Set correct default for SKIP align */
 541                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8060 + ofs),
 542                                        MDIO_USB3);
 543                 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200;
 544                 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 545                 ofs = PHY_PORT_SELECT_1;
 546         }
 547 }
 548
 549 static void brcmusb_usb3_unfreeze_aeq(void __iomem *ctrl_base)
 550 {
 551         u32 val, ofs;
 552         int ii;
 553
 554         ofs = 0;
 555         for (ii = 0; ii < PHY_PORTS; ++ii) {
 556                 /* Let EQ freeze after TSEQ */
 557                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x80e0 + ofs),
 558                                        MDIO_USB3);
 559                 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3);
 560                 val &= ~0x0008;
 561                 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 562                 ofs = PHY_PORT_SELECT_1;
 563         }
 564 }
 565
 566 static void brcmusb_usb3_pll_54mhz(struct brcm_usb_init_params *params)
 567 {
 568         u32 ofs;
 569         int ii;
 570         void __iomem *ctrl_base = params->regs[BRCM_REGS_CTRL];
 571
 572         /*
 573          * On newer B53 based SoC's, the reference clock for the
 574          * 3.0 PLL has been changed from 50MHz to 54MHz so the
 575          * PLL needs to be reprogrammed.
 576          * See SWLINUX-4006.
 577          *
 578          * On the 7364C0, the reference clock for the
 579          * 3.0 PLL has been changed from 50MHz to 54MHz to
 580          * work around a MOCA issue.
 581          * See SWLINUX-4169.
 582          */
 583         switch (params->selected_family) {
 584         case BRCM_FAMILY_3390A0:
 585         case BRCM_FAMILY_4908:
 586         case BRCM_FAMILY_7250B0:
 587         case BRCM_FAMILY_7366C0:
 588         case BRCM_FAMILY_74371A0:
 589         case BRCM_FAMILY_7439B0:
 590         case BRCM_FAMILY_7445D0:
 591         case BRCM_FAMILY_7260A0:
 592                 return;
 593         case BRCM_FAMILY_7364A0:
 594                 if (BRCM_REV(params->family_id) < 0x20)
 595                         return;
 596                 break;
 597         }
 598
 599         /* set USB 3.0 PLL to accept 54Mhz reference clock */
 600         USB_CTRL_UNSET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
 601
 602         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 603         brcmusb_usb_mdio_write(ctrl_base, 0x10, 0x5784, MDIO_USB3);
 604         brcmusb_usb_mdio_write(ctrl_base, 0x11, 0x01d0, MDIO_USB3);
 605         brcmusb_usb_mdio_write(ctrl_base, 0x12, 0x1DE8, MDIO_USB3);
 606         brcmusb_usb_mdio_write(ctrl_base, 0x13, 0xAA80, MDIO_USB3);
 607         brcmusb_usb_mdio_write(ctrl_base, 0x14, 0x8826, MDIO_USB3);
 608         brcmusb_usb_mdio_write(ctrl_base, 0x15, 0x0044, MDIO_USB3);
 609         brcmusb_usb_mdio_write(ctrl_base, 0x16, 0x8000, MDIO_USB3);
 610         brcmusb_usb_mdio_write(ctrl_base, 0x17, 0x0851, MDIO_USB3);
 611         brcmusb_usb_mdio_write(ctrl_base, 0x18, 0x0000, MDIO_USB3);
 612
 613         /* both ports */
 614         ofs = 0;
 615         for (ii = 0; ii < PHY_PORTS; ++ii) {
 616                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8040 + ofs),
 617                                        MDIO_USB3);
 618                 brcmusb_usb_mdio_write(ctrl_base, 0x03, 0x0090, MDIO_USB3);
 619                 brcmusb_usb_mdio_write(ctrl_base, 0x04, 0x0134, MDIO_USB3);
 620                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8020 + ofs),
 621                                        MDIO_USB3);
 622                 brcmusb_usb_mdio_write(ctrl_base, 0x01, 0x00e2, MDIO_USB3);
 623                 ofs = PHY_PORT_SELECT_1;
 624         }
 625
 626         /* restart PLL sequence */
 627         USB_CTRL_SET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
 628         /* Give PLL enough time to lock */
 629         usleep_range(1000, 2000);
 630 }
 631
 632 static void brcmusb_usb3_ssc_enable(void __iomem *ctrl_base)
 633 {
 634         u32 val;
 635
 636         /* Enable USB 3.0 TX spread spectrum */
 637         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3);
 638         val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
 639         brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 640
 641         /* Currently, USB 3.0 SSC is enabled via port 0 MDIO registers,
 642          * which should have been adequate. However, due to a bug in the
 643          * USB 3.0 PHY, it must be enabled via both ports (HWUSB3DVT-26).
 644          */
 645         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x9040, MDIO_USB3);
 646         val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
 647         brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 648 }
 649
 650 static void brcmusb_usb3_phy_workarounds(struct brcm_usb_init_params *params)
 651 {
 652         void __iomem *ctrl_base = params->regs[BRCM_REGS_CTRL];
 653
 654         brcmusb_usb3_pll_fix(ctrl_base);
 655         brcmusb_usb3_pll_54mhz(params);
 656         brcmusb_usb3_ssc_enable(ctrl_base);
 657         brcmusb_usb3_enable_pipe_reset(ctrl_base);
 658         brcmusb_usb3_enable_sigdet(ctrl_base);
 659         brcmusb_usb3_enable_skip_align(ctrl_base);
 660         brcmusb_usb3_unfreeze_aeq(ctrl_base);
 661 }
 662
 663 static void brcmusb_memc_fix(struct brcm_usb_init_params *params)
 664 {
 665         u32 prid;
 666
 667         if (params->selected_family != BRCM_FAMILY_7445D0)
 668                 return;
 669         /*
 670          * This is a workaround for HW7445-1869 where a DMA write ends up
 671          * doing a read pre-fetch after the end of the DMA buffer. This
 672          * causes a problem when the DMA buffer is at the end of physical
 673          * memory, causing the pre-fetch read to access non-existent memory,
 674          * and the chip bondout has MEMC2 disabled. When the pre-fetch read
 675          * tries to use the disabled MEMC2, it hangs the bus. The workaround
 676          * is to disable MEMC2 access in the usb controller which avoids
 677          * the hang.
 678          */
 679
 680         prid = params->product_id & 0xfffff000;
 681         switch (prid) {
 682         case 0x72520000:
 683         case 0x74480000:
 684         case 0x74490000:
 685         case 0x07252000:
 686         case 0x07448000:
 687         case 0x07449000:
 688                 USB_CTRL_UNSET_FAMILY(params, SETUP, SCB2_EN);
 689         }
 690 }
 691
 692 static void brcmusb_usb3_otp_fix(struct brcm_usb_init_params *params)
 693 {
 694         void __iomem *xhci_ec_base = params->regs[BRCM_REGS_XHCI_EC];
 695         u32 val;
 696
 697         if (params->family_id != 0x74371000 || !xhci_ec_base)
 698                 return;
 699         brcm_usb_writel(0xa20c, USB_XHCI_EC_REG(xhci_ec_base, IRAADR));
 700         val = brcm_usb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
 701
 702         /* set cfg_pick_ss_lock */
 703         val |= (1 << 27);
 704         brcm_usb_writel(val, USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
 705
 706         /* Reset USB 3.0 PHY for workaround to take effect */
 707         USB_CTRL_UNSET(params->regs[BRCM_REGS_CTRL], USB30_CTL1, PHY3_RESETB);
 708         USB_CTRL_SET(params->regs[BRCM_REGS_CTRL], USB30_CTL1, PHY3_RESETB);
 709 }
 710
 711 static void brcmusb_xhci_soft_reset(struct brcm_usb_init_params *params,
 712                                     int on_off)
 713 {
 714         /* Assert reset */
 715         if (on_off) {
 716                 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
 717                         USB_CTRL_UNSET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
 718                 else
 719                         USB_CTRL_UNSET_FAMILY(params,
 720                                               USB30_CTL1, XHC_SOFT_RESETB);
 721         } else { /* De-assert reset */
 722                 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
 723                         USB_CTRL_SET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
 724                 else
 725                         USB_CTRL_SET_FAMILY(params, USB30_CTL1,
 726                                             XHC_SOFT_RESETB);
 727         }
 728 }
 729
 730 /*
 731  * Return the best map table family. The order is:
 732  *   - exact match of chip and major rev
 733  *   - exact match of chip and closest older major rev
 734  *   - default chip/rev.
 735  * NOTE: The minor rev is always ignored.
 736  */
 737 static enum brcm_family_type get_family_type(
 738         struct brcm_usb_init_params *params)
 739 {
 740         int last_type = -1;
 741         u32 last_family = 0;
 742         u32 family_no_major;
 743         unsigned int x;
 744         u32 family;
 745
 746         family = params->family_id & 0xfffffff0;
 747         family_no_major = params->family_id & 0xffffff00;
 748         for (x = 0; id_to_type_table[x].id; x++) {
 749                 if (family == id_to_type_table[x].id)
 750                         return id_to_type_table[x].type;
 751                 if (family_no_major == (id_to_type_table[x].id & 0xffffff00))
 752                         if (family > id_to_type_table[x].id &&
 753                             last_family < id_to_type_table[x].id) {
 754                                 last_family = id_to_type_table[x].id;
 755                                 last_type = id_to_type_table[x].type;
 756                         }
 757         }
 758
 759         /* If no match, return the default family */
 760         if (last_type == -1)
 761                 return id_to_type_table[x].type;
 762         return last_type;
 763 }
 764
 765 static void usb_init_ipp(struct brcm_usb_init_params *params)
 766 {
 767         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 768         u32 reg;
 769         u32 orig_reg;
 770
 771         /* Starting with the 7445d0, there are no longer separate 3.0
 772          * versions of IOC and IPP.
 773          */
 774         if (USB_CTRL_MASK_FAMILY(params, USB30_CTL1, USB3_IOC)) {
 775                 if (params->ioc)
 776                         USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IOC);
 777                 if (params->ipp == 1)
 778                         USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IPP);
 779         }
 780
 781         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 782         orig_reg = reg;
 783         if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_CC_DRD_MODE_ENABLE_SEL))
 784                 /* Never use the strap, it's going away. */
 785                 reg &= ~(USB_CTRL_MASK_FAMILY(params,
 786                                               SETUP,
 787                                               STRAP_CC_DRD_MODE_ENABLE_SEL));
 788         if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_IPP_SEL))
 789                 /* override ipp strap pin (if it exits) */
 790                 if (params->ipp != 2)
 791                         reg &= ~(USB_CTRL_MASK_FAMILY(params, SETUP,
 792                                                       STRAP_IPP_SEL));
 793
 794         /* Override the default OC and PP polarity */
 795         reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC));
 796         if (params->ioc)
 797                 reg |= USB_CTRL_MASK(SETUP, IOC);
 798         if (params->ipp == 1)
 799                 reg |= USB_CTRL_MASK(SETUP, IPP);
 800         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 801
 802         /*
 803          * If we're changing IPP, make sure power is off long enough
 804          * to turn off any connected devices.
 805          */
 806         if ((reg ^ orig_reg) & USB_CTRL_MASK(SETUP, IPP))
 807                 msleep(50);
 808 }
 809
 810 static void usb_wake_enable(struct brcm_usb_init_params *params,
 811                           bool enable)
 812 {
 813         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 814
 815         if (enable)
 816                 USB_CTRL_SET(ctrl, USB_PM, RMTWKUP_EN);
 817         else
 818                 USB_CTRL_UNSET(ctrl, USB_PM, RMTWKUP_EN);
 819 }
 820
 821 static void usb_init_common(struct brcm_usb_init_params *params)
 822 {
 823         u32 reg;
 824         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 825
 826         /* Clear any pending wake conditions */
 827         usb_wake_enable(params, false);
 828         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_PM_STATUS));
 829         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_PM_STATUS));
 830
 831         /* Take USB out of power down */
 832         if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) {
 833                 USB_CTRL_UNSET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
 834                 /* 1 millisecond - for USB clocks to settle down */
 835                 usleep_range(1000, 2000);
 836         }
 837
 838         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) {
 839                 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB_PWRDN);
 840                 /* 1 millisecond - for USB clocks to settle down */
 841                 usleep_range(1000, 2000);
 842         }
 843
 844         if (params->selected_family != BRCM_FAMILY_74371A0 &&
 845             (BRCM_ID(params->family_id) != 0x7364))
 846                 /*
 847                  * HW7439-637: 7439a0 and its derivatives do not have large
 848                  * enough descriptor storage for this.
 849                  */
 850                 USB_CTRL_SET_FAMILY(params, SETUP, SS_EHCI64BIT_EN);
 851
 852         /* Block auto PLL suspend by USB2 PHY (Sasi) */
 853         USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN);
 854
 855         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 856         if (params->selected_family == BRCM_FAMILY_7364A0)
 857                 /* Suppress overcurrent indication from USB30 ports for A0 */
 858                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, OC3_DISABLE);
 859
 860         brcmusb_usb_phy_ldo_fix(ctrl);
 861         brcmusb_usb2_eye_fix(ctrl);
 862
 863         /*
 864          * Make sure the the second and third memory controller
 865          * interfaces are enabled if they exist.
 866          */
 867         if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN))
 868                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN);
 869         if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN))
 870                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN);
 871         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 872
 873         brcmusb_memc_fix(params);
 874
 875         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
 876                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 877                 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
 878                                         PORT_MODE);
 879                 reg |= params->mode;
 880                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 881         }
 882         if (USB_CTRL_MASK_FAMILY(params, USB_PM, BDC_SOFT_RESETB)) {
 883                 switch (params->mode) {
 884                 case USB_CTLR_MODE_HOST:
 885                         USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 886                         break;
 887                 default:
 888                         USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 889                         USB_CTRL_SET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 890                 break;
 891                 }
 892         }
 893         if (USB_CTRL_MASK_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE)) {
 894                 if (params->mode == USB_CTLR_MODE_TYPEC_PD)
 895                         USB_CTRL_SET_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE);
 896                 else
 897                         USB_CTRL_UNSET_FAMILY(params, SETUP,
 898                                               CC_DRD_MODE_ENABLE);
 899         }
 900 }
 901
 902 static void usb_init_eohci(struct brcm_usb_init_params *params)
 903 {
 904         u32 reg;
 905         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 906
 907         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB))
 908                 USB_CTRL_SET_FAMILY(params, USB_PM, USB20_HC_RESETB);
 909
 910         if (params->selected_family == BRCM_FAMILY_7366C0)
 911                 /*
 912                  * Don't enable this so the memory controller doesn't read
 913                  * into memory holes. NOTE: This bit is low true on 7366C0.
 914                  */
 915                 USB_CTRL_SET(ctrl, EBRIDGE, ESTOP_SCB_REQ);
 916
 917         /* Setup the endian bits */
 918         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 919         reg &= ~USB_CTRL_SETUP_ENDIAN_BITS;
 920         reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN);
 921         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 922
 923         if (params->selected_family == BRCM_FAMILY_7271A0)
 924                 /* Enable LS keep alive fix for certain keyboards */
 925                 USB_CTRL_SET(ctrl, OBRIDGE, LS_KEEP_ALIVE);
 926
 927         if (params->family_id == 0x72550000) {
 928                 /*
 929                  * Make the burst size 512 bytes to fix a hardware bug
 930                  * on the 7255a0. See HW7255-24.
 931                  */
 932                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, EBRIDGE));
 933                 reg &= ~USB_CTRL_MASK(EBRIDGE, EBR_SCB_SIZE);
 934                 reg |= 0x800;
 935                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, EBRIDGE));
 936         }
 937 }
 938
 939 static void usb_init_xhci(struct brcm_usb_init_params *params)
 940 {
 941         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 942
 943         USB_CTRL_UNSET(ctrl, USB30_PCTL, PHY3_IDDQ_OVERRIDE);
 944         /* 1 millisecond - for USB clocks to settle down */
 945         usleep_range(1000, 2000);
 946
 947         if (BRCM_ID(params->family_id) == 0x7366) {
 948                 /*
 949                  * The PHY3_SOFT_RESETB bits default to the wrong state.
 950                  */
 951                 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB);
 952                 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB_P1);
 953         }
 954
 955         /*
 956          * Kick start USB3 PHY
 957          * Make sure it's low to insure a rising edge.
 958          */
 959         USB_CTRL_UNSET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
 960         USB_CTRL_SET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
 961
 962         brcmusb_usb3_phy_workarounds(params);
 963         brcmusb_xhci_soft_reset(params, 0);
 964         brcmusb_usb3_otp_fix(params);
 965 }
 966
 967 static void usb_uninit_common(struct brcm_usb_init_params *params)
 968 {
 969         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN))
 970                 USB_CTRL_SET_FAMILY(params, USB_PM, USB_PWRDN);
 971
 972         if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN))
 973                 USB_CTRL_SET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
 974         if (params->wake_enabled)
 975                 usb_wake_enable(params, true);
 976 }
 977
 978 static void usb_uninit_eohci(struct brcm_usb_init_params *params)
 979 {
 980 }
 981
 982 static void usb_uninit_xhci(struct brcm_usb_init_params *params)
 983 {
 984         brcmusb_xhci_soft_reset(params, 1);
 985         USB_CTRL_SET(params->regs[BRCM_REGS_CTRL], USB30_PCTL,
 986                      PHY3_IDDQ_OVERRIDE);
 987 }
 988
 989 static int usb_get_dual_select(struct brcm_usb_init_params *params)
 990 {
 991         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 992         u32 reg = 0;
 993
 994         pr_debug("%s\n", __func__);
 995         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
 996                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 997                 reg &= USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
 998                                         PORT_MODE);
 999         }
1000         return reg;
1001 }
1002
1003 static void usb_set_dual_select(struct brcm_usb_init_params *params, int mode)
1004 {
1005         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
1006         u32 reg;
1007
1008         pr_debug("%s\n", __func__);
1009
1010         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
1011                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
1012                 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
1013                                         PORT_MODE);
1014                 reg |= mode;
1015                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
1016         }
1017 }
1018
1019 static const struct brcm_usb_init_ops bcm7445_ops = {
1020         .init_ipp = usb_init_ipp,
1021         .init_common = usb_init_common,
1022         .init_eohci = usb_init_eohci,
1023         .init_xhci = usb_init_xhci,
1024         .uninit_common = usb_uninit_common,
1025         .uninit_eohci = usb_uninit_eohci,
1026         .uninit_xhci = usb_uninit_xhci,
1027         .get_dual_select = usb_get_dual_select,
1028         .set_dual_select = usb_set_dual_select,
1029 };
1030
1031 void brcm_usb_dvr_init_4908(struct brcm_usb_init_params *params)
1032 {
1033         int fam;
1034
1035         fam = BRCM_FAMILY_4908;
1036         params->selected_family = fam;
1037         params->usb_reg_bits_map =
1038                 &usb_reg_bits_map_table[fam][0];
1039         params->family_name = family_names[fam];
1040         params->ops = &bcm7445_ops;
1041 }
1042
1043 void brcm_usb_dvr_init_7445(struct brcm_usb_init_params *params)
1044 {
1045         int fam;
1046
1047         pr_debug("%s\n", __func__);
1048
1049         fam = get_family_type(params);
1050         params->selected_family = fam;
1051         params->usb_reg_bits_map =
1052                 &usb_reg_bits_map_table[fam][0];
1053         params->family_name = family_names[fam];
1054         params->ops = &bcm7445_ops;
1055 }