drivers/phy/broadcom/phy-brcm-sata.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Broadcom SATA3 AHCI Controller PHY Driver
   4  *
   5  * Copyright (C) 2016 Broadcom
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/device.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18
  19 #define SATA_PCB_BANK_OFFSET                            0x23c
  20 #define SATA_PCB_REG_OFFSET(ofs)                        ((ofs) * 4)
  21
  22 #define MAX_PORTS                                       2
  23
  24 /* Register offset between PHYs in PCB space */
  25 #define SATA_PCB_REG_28NM_SPACE_SIZE                    0x1000
  26
  27 /* The older SATA PHY registers duplicated per port registers within the map,
  28  * rather than having a separate map per port.
  29  */
  30 #define SATA_PCB_REG_40NM_SPACE_SIZE                    0x10
  31
  32 /* Register offset between PHYs in PHY control space */
  33 #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE               0x8
  34
  35 enum brcm_sata_phy_version {
  36         BRCM_SATA_PHY_STB_16NM,
  37         BRCM_SATA_PHY_STB_28NM,
  38         BRCM_SATA_PHY_STB_40NM,
  39         BRCM_SATA_PHY_IPROC_NS2,
  40         BRCM_SATA_PHY_IPROC_NSP,
  41         BRCM_SATA_PHY_IPROC_SR,
  42         BRCM_SATA_PHY_DSL_28NM,
  43 };
  44
  45 enum brcm_sata_phy_rxaeq_mode {
  46         RXAEQ_MODE_OFF = 0,
  47         RXAEQ_MODE_AUTO,
  48         RXAEQ_MODE_MANUAL,
  49 };
  50
  51 static enum brcm_sata_phy_rxaeq_mode rxaeq_to_val(const char *m)
  52 {
  53         if (!strcmp(m, "auto"))
  54                 return RXAEQ_MODE_AUTO;
  55         else if (!strcmp(m, "manual"))
  56                 return RXAEQ_MODE_MANUAL;
  57         else
  58                 return RXAEQ_MODE_OFF;
  59 }
  60
  61 struct brcm_sata_port {
  62         int portnum;
  63         struct phy *phy;
  64         struct brcm_sata_phy *phy_priv;
  65         bool ssc_en;
  66         enum brcm_sata_phy_rxaeq_mode rxaeq_mode;
  67         u32 rxaeq_val;
  68 };
  69
  70 struct brcm_sata_phy {
  71         struct device *dev;
  72         void __iomem *phy_base;
  73         void __iomem *ctrl_base;
  74         enum brcm_sata_phy_version version;
  75
  76         struct brcm_sata_port phys[MAX_PORTS];
  77 };
  78
  79 enum sata_phy_regs {
  80         BLOCK0_REG_BANK                         = 0x000,
  81         BLOCK0_XGXSSTATUS                       = 0x81,
  82         BLOCK0_XGXSSTATUS_PLL_LOCK              = BIT(12),
  83         BLOCK0_SPARE                            = 0x8d,
  84         BLOCK0_SPARE_OOB_CLK_SEL_MASK           = 0x3,
  85         BLOCK0_SPARE_OOB_CLK_SEL_REFBY2         = 0x1,
  86
  87         PLL_REG_BANK_0                          = 0x050,
  88         PLL_REG_BANK_0_PLLCONTROL_0             = 0x81,
  89         PLLCONTROL_0_FREQ_DET_RESTART           = BIT(13),
  90         PLLCONTROL_0_FREQ_MONITOR               = BIT(12),
  91         PLLCONTROL_0_SEQ_START                  = BIT(15),
  92         PLL_CAP_CHARGE_TIME                     = 0x83,
  93         PLL_VCO_CAL_THRESH                      = 0x84,
  94         PLL_CAP_CONTROL                         = 0x85,
  95         PLL_FREQ_DET_TIME                       = 0x86,
  96         PLL_ACTRL2                              = 0x8b,
  97         PLL_ACTRL2_SELDIV_MASK                  = 0x1f,
  98         PLL_ACTRL2_SELDIV_SHIFT                 = 9,
  99         PLL_ACTRL6                              = 0x86,
 100
 101         PLL1_REG_BANK                           = 0x060,
 102         PLL1_ACTRL2                             = 0x82,
 103         PLL1_ACTRL3                             = 0x83,
 104         PLL1_ACTRL4                             = 0x84,
 105         PLL1_ACTRL5                             = 0x85,
 106         PLL1_ACTRL6                             = 0x86,
 107         PLL1_ACTRL7                             = 0x87,
 108         PLL1_ACTRL8                             = 0x88,
 109
 110         TX_REG_BANK                             = 0x070,
 111         TX_ACTRL0                               = 0x80,
 112         TX_ACTRL0_TXPOL_FLIP                    = BIT(6),
 113         TX_ACTRL5                               = 0x85,
 114         TX_ACTRL5_SSC_EN                        = BIT(11),
 115
 116         AEQRX_REG_BANK_0                        = 0xd0,
 117         AEQ_CONTROL1                            = 0x81,
 118         AEQ_CONTROL1_ENABLE                     = BIT(2),
 119         AEQ_CONTROL1_FREEZE                     = BIT(3),
 120         AEQ_FRC_EQ                              = 0x83,
 121         AEQ_FRC_EQ_FORCE                        = BIT(0),
 122         AEQ_FRC_EQ_FORCE_VAL                    = BIT(1),
 123         AEQ_RFZ_FRC_VAL                         = BIT(8),
 124         AEQRX_REG_BANK_1                        = 0xe0,
 125         AEQRX_SLCAL0_CTRL0                      = 0x82,
 126         AEQRX_SLCAL1_CTRL0                      = 0x86,
 127
 128         OOB_REG_BANK                            = 0x150,
 129         OOB1_REG_BANK                           = 0x160,
 130         OOB_CTRL1                               = 0x80,
 131         OOB_CTRL1_BURST_MAX_MASK                = 0xf,
 132         OOB_CTRL1_BURST_MAX_SHIFT               = 12,
 133         OOB_CTRL1_BURST_MIN_MASK                = 0xf,
 134         OOB_CTRL1_BURST_MIN_SHIFT               = 8,
 135         OOB_CTRL1_WAKE_IDLE_MAX_MASK            = 0xf,
 136         OOB_CTRL1_WAKE_IDLE_MAX_SHIFT           = 4,
 137         OOB_CTRL1_WAKE_IDLE_MIN_MASK            = 0xf,
 138         OOB_CTRL1_WAKE_IDLE_MIN_SHIFT           = 0,
 139         OOB_CTRL2                               = 0x81,
 140         OOB_CTRL2_SEL_ENA_SHIFT                 = 15,
 141         OOB_CTRL2_SEL_ENA_RC_SHIFT              = 14,
 142         OOB_CTRL2_RESET_IDLE_MAX_MASK           = 0x3f,
 143         OOB_CTRL2_RESET_IDLE_MAX_SHIFT          = 8,
 144         OOB_CTRL2_BURST_CNT_MASK                = 0x3,
 145         OOB_CTRL2_BURST_CNT_SHIFT               = 6,
 146         OOB_CTRL2_RESET_IDLE_MIN_MASK           = 0x3f,
 147         OOB_CTRL2_RESET_IDLE_MIN_SHIFT          = 0,
 148
 149         TXPMD_REG_BANK                          = 0x1a0,
 150         TXPMD_CONTROL1                          = 0x81,
 151         TXPMD_CONTROL1_TX_SSC_EN_FRC            = BIT(0),
 152         TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL        = BIT(1),
 153         TXPMD_TX_FREQ_CTRL_CONTROL1             = 0x82,
 154         TXPMD_TX_FREQ_CTRL_CONTROL2             = 0x83,
 155         TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK   = 0x3ff,
 156         TXPMD_TX_FREQ_CTRL_CONTROL3             = 0x84,
 157         TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK   = 0x3ff,
 158
 159         RXPMD_REG_BANK                          = 0x1c0,
 160         RXPMD_RX_CDR_CONTROL1                   = 0x81,
 161         RXPMD_RX_PPM_VAL_MASK                   = 0x1ff,
 162         RXPMD_RXPMD_EN_FRC                      = BIT(12),
 163         RXPMD_RXPMD_EN_FRC_VAL                  = BIT(13),
 164         RXPMD_RX_CDR_CDR_PROP_BW                = 0x82,
 165         RXPMD_G_CDR_PROP_BW_MASK                = 0x7,
 166         RXPMD_G1_CDR_PROP_BW_SHIFT              = 0,
 167         RXPMD_G2_CDR_PROP_BW_SHIFT              = 3,
 168         RXPMD_G3_CDR_PROB_BW_SHIFT              = 6,
 169         RXPMD_RX_CDR_CDR_ACQ_INTEG_BW           = 0x83,
 170         RXPMD_G_CDR_ACQ_INT_BW_MASK             = 0x7,
 171         RXPMD_G1_CDR_ACQ_INT_BW_SHIFT           = 0,
 172         RXPMD_G2_CDR_ACQ_INT_BW_SHIFT           = 3,
 173         RXPMD_G3_CDR_ACQ_INT_BW_SHIFT           = 6,
 174         RXPMD_RX_CDR_CDR_LOCK_INTEG_BW          = 0x84,
 175         RXPMD_G_CDR_LOCK_INT_BW_MASK            = 0x7,
 176         RXPMD_G1_CDR_LOCK_INT_BW_SHIFT          = 0,
 177         RXPMD_G2_CDR_LOCK_INT_BW_SHIFT          = 3,
 178         RXPMD_G3_CDR_LOCK_INT_BW_SHIFT          = 6,
 179         RXPMD_RX_FREQ_MON_CONTROL1              = 0x87,
 180         RXPMD_MON_CORRECT_EN                    = BIT(8),
 181         RXPMD_MON_MARGIN_VAL_MASK               = 0xff,
 182 };
 183
 184 enum sata_phy_ctrl_regs {
 185         PHY_CTRL_1                              = 0x0,
 186         PHY_CTRL_1_RESET                        = BIT(0),
 187 };
 188
 189 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
 190 {
 191         struct brcm_sata_phy *priv = port->phy_priv;
 192         u32 size = 0;
 193
 194         switch (priv->version) {
 195         case BRCM_SATA_PHY_IPROC_NS2:
 196                 size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE;
 197                 break;
 198         default:
 199                 dev_err(priv->dev, "invalid phy version\n");
 200                 break;
 201         }
 202
 203         return priv->ctrl_base + (port->portnum * size);
 204 }
 205
 206 static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
 207                              u32 ofs, u32 msk, u32 value)
 208 {
 209         struct brcm_sata_phy *priv = port->phy_priv;
 210         void __iomem *pcb_base = priv->phy_base;
 211         u32 tmp;
 212
 213         if (priv->version == BRCM_SATA_PHY_STB_40NM)
 214                 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
 215         else
 216                 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
 217
 218         writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
 219         tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
 220         tmp = (tmp & msk) | value;
 221         writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
 222 }
 223
 224 static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
 225 {
 226         struct brcm_sata_phy *priv = port->phy_priv;
 227         void __iomem *pcb_base = priv->phy_base;
 228
 229         if (priv->version == BRCM_SATA_PHY_STB_40NM)
 230                 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
 231         else
 232                 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
 233
 234         writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
 235         return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
 236 }
 237
 238 /* These defaults were characterized by H/W group */
 239 #define STB_FMIN_VAL_DEFAULT    0x3df
 240 #define STB_FMAX_VAL_DEFAULT    0x3df
 241 #define STB_FMAX_VAL_SSC        0x83
 242
 243 static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
 244 {
 245         struct brcm_sata_phy *priv = port->phy_priv;
 246         u32 tmp;
 247
 248         /* override the TX spread spectrum setting */
 249         tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
 250         brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
 251
 252         /* set fixed min freq */
 253         brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
 254                          ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
 255                          STB_FMIN_VAL_DEFAULT);
 256
 257         /* set fixed max freq depending on SSC config */
 258         if (port->ssc_en) {
 259                 dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum);
 260                 tmp = STB_FMAX_VAL_SSC;
 261         } else {
 262                 tmp = STB_FMAX_VAL_DEFAULT;
 263         }
 264
 265         brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
 266                           ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
 267 }
 268
 269 #define AEQ_FRC_EQ_VAL_SHIFT    2
 270 #define AEQ_FRC_EQ_VAL_MASK     0x3f
 271
 272 static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
 273 {
 274         u32 tmp = 0, reg = 0;
 275
 276         switch (port->rxaeq_mode) {
 277         case RXAEQ_MODE_OFF:
 278                 return 0;
 279
 280         case RXAEQ_MODE_AUTO:
 281                 reg = AEQ_CONTROL1;
 282                 tmp = AEQ_CONTROL1_ENABLE | AEQ_CONTROL1_FREEZE;
 283                 break;
 284
 285         case RXAEQ_MODE_MANUAL:
 286                 reg = AEQ_FRC_EQ;
 287                 tmp = AEQ_FRC_EQ_FORCE | AEQ_FRC_EQ_FORCE_VAL;
 288                 if (port->rxaeq_val > AEQ_FRC_EQ_VAL_MASK)
 289                         return -EINVAL;
 290                 tmp |= port->rxaeq_val << AEQ_FRC_EQ_VAL_SHIFT;
 291                 break;
 292         }
 293
 294         brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
 295         brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
 296
 297         return 0;
 298 }
 299
 300 static int brcm_stb_sata_init(struct brcm_sata_port *port)
 301 {
 302         brcm_stb_sata_ssc_init(port);
 303
 304         return brcm_stb_sata_rxaeq_init(port);
 305 }
 306
 307 static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
 308 {
 309         u32 tmp, value;
 310
 311         /* Reduce CP tail current to 1/16th of its default value */
 312         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
 313
 314         /* Turn off CP tail current boost */
 315         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
 316
 317         /* Set a specific AEQ equalizer value */
 318         tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
 319         brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
 320                          ~(tmp | AEQ_RFZ_FRC_VAL |
 321                            AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
 322                          tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
 323
 324         /* Set RX PPM val center frequency */
 325         if (port->ssc_en)
 326                 value = 0x52;
 327         else
 328                 value = 0;
 329         brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
 330                          ~RXPMD_RX_PPM_VAL_MASK, value);
 331
 332         /* Set proportional loop bandwith Gen1/2/3 */
 333         tmp = RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G1_CDR_PROP_BW_SHIFT |
 334               RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G2_CDR_PROP_BW_SHIFT |
 335               RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G3_CDR_PROB_BW_SHIFT;
 336         if (port->ssc_en)
 337                 value = 2 << RXPMD_G1_CDR_PROP_BW_SHIFT |
 338                         2 << RXPMD_G2_CDR_PROP_BW_SHIFT |
 339                         2 << RXPMD_G3_CDR_PROB_BW_SHIFT;
 340         else
 341                 value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
 342                         1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
 343                         1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
 344         brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
 345                          value);
 346
 347         /* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
 348         tmp = RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
 349               RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
 350               RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
 351         if (port->ssc_en)
 352                 value = 1 << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
 353                         1 << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
 354                         1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
 355         else
 356                 value = 0;
 357         brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
 358                          ~tmp, value);
 359
 360         /* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
 361         tmp = RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
 362               RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
 363               RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
 364         if (port->ssc_en)
 365                 value = 1 << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
 366                         1 << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
 367                         1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
 368         else
 369                 value = 0;
 370         brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
 371                          ~tmp, value);
 372
 373         /* Set no guard band and clamp CDR */
 374         tmp = RXPMD_MON_CORRECT_EN | RXPMD_MON_MARGIN_VAL_MASK;
 375         if (port->ssc_en)
 376                 value = 0x51;
 377         else
 378                 value = 0;
 379         brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
 380                          ~tmp, RXPMD_MON_CORRECT_EN | value);
 381
 382         /* Turn on/off SSC */
 383         brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
 384                          port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
 385
 386         return 0;
 387 }
 388
 389 static int brcm_stb_sata_16nm_init(struct brcm_sata_port *port)
 390 {
 391         return brcm_stb_sata_16nm_ssc_init(port);
 392 }
 393
 394 /* NS2 SATA PLL1 defaults were characterized by H/W group */
 395 #define NS2_PLL1_ACTRL2_MAGIC   0x1df8
 396 #define NS2_PLL1_ACTRL3_MAGIC   0x2b00
 397 #define NS2_PLL1_ACTRL4_MAGIC   0x8824
 398
 399 static int brcm_ns2_sata_init(struct brcm_sata_port *port)
 400 {
 401         int try;
 402         unsigned int val;
 403         void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
 404         struct device *dev = port->phy_priv->dev;
 405
 406         /* Configure OOB control */
 407         val = 0x0;
 408         val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
 409         val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
 410         val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
 411         val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
 412         brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
 413         val = 0x0;
 414         val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
 415         val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
 416         val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
 417         brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
 418
 419         /* Configure PHY PLL register bank 1 */
 420         val = NS2_PLL1_ACTRL2_MAGIC;
 421         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
 422         val = NS2_PLL1_ACTRL3_MAGIC;
 423         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
 424         val = NS2_PLL1_ACTRL4_MAGIC;
 425         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
 426
 427         /* Configure PHY BLOCK0 register bank */
 428         /* Set oob_clk_sel to refclk/2 */
 429         brcm_sata_phy_wr(port, BLOCK0_REG_BANK, BLOCK0_SPARE,
 430                          ~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
 431                          BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
 432
 433         /* Strobe PHY reset using PHY control register */
 434         writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1);
 435         mdelay(1);
 436         writel(0x0, ctrl_base + PHY_CTRL_1);
 437         mdelay(1);
 438
 439         /* Wait for PHY PLL lock by polling pll_lock bit */
 440         try = 50;
 441         while (try) {
 442                 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 443                                         BLOCK0_XGXSSTATUS);
 444                 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 445                         break;
 446                 msleep(20);
 447                 try--;
 448         }
 449         if (!try) {
 450                 /* PLL did not lock; give up */
 451                 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
 452                 return -ETIMEDOUT;
 453         }
 454
 455         dev_dbg(dev, "port%d initialized\n", port->portnum);
 456
 457         return 0;
 458 }
 459
 460 static int brcm_nsp_sata_init(struct brcm_sata_port *port)
 461 {
 462         struct device *dev = port->phy_priv->dev;
 463         unsigned int oob_bank;
 464         unsigned int val, try;
 465
 466         /* Configure OOB control */
 467         if (port->portnum == 0)
 468                 oob_bank = OOB_REG_BANK;
 469         else if (port->portnum == 1)
 470                 oob_bank = OOB1_REG_BANK;
 471         else
 472                 return -EINVAL;
 473
 474         val = 0x0;
 475         val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
 476         val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
 477         val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
 478         val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
 479         brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
 480
 481         val = 0x0;
 482         val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
 483         val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
 484         val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
 485         brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
 486
 487
 488         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL2,
 489                 ~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
 490                 0x0c << PLL_ACTRL2_SELDIV_SHIFT);
 491
 492         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CONTROL,
 493                                                 0xff0, 0x4f0);
 494
 495         val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
 496         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 497                                                                 ~val, val);
 498         val = PLLCONTROL_0_SEQ_START;
 499         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 500                                                                 ~val, 0);
 501         mdelay(10);
 502         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 503                                                                 ~val, val);
 504
 505         /* Wait for pll_seq_done bit */
 506         try = 50;
 507         while (--try) {
 508                 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 509                                         BLOCK0_XGXSSTATUS);
 510                 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 511                         break;
 512                 msleep(20);
 513         }
 514         if (!try) {
 515                 /* PLL did not lock; give up */
 516                 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
 517                 return -ETIMEDOUT;
 518         }
 519
 520         dev_dbg(dev, "port%d initialized\n", port->portnum);
 521
 522         return 0;
 523 }
 524
 525 /* SR PHY PLL0 registers */
 526 #define SR_PLL0_ACTRL6_MAGIC                    0xa
 527
 528 /* SR PHY PLL1 registers */
 529 #define SR_PLL1_ACTRL2_MAGIC                    0x32
 530 #define SR_PLL1_ACTRL3_MAGIC                    0x2
 531 #define SR_PLL1_ACTRL4_MAGIC                    0x3e8
 532
 533 static int brcm_sr_sata_init(struct brcm_sata_port *port)
 534 {
 535         struct device *dev = port->phy_priv->dev;
 536         unsigned int val, try;
 537
 538         /* Configure PHY PLL register bank 1 */
 539         val = SR_PLL1_ACTRL2_MAGIC;
 540         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
 541         val = SR_PLL1_ACTRL3_MAGIC;
 542         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
 543         val = SR_PLL1_ACTRL4_MAGIC;
 544         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
 545
 546         /* Configure PHY PLL register bank 0 */
 547         val = SR_PLL0_ACTRL6_MAGIC;
 548         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
 549
 550         /* Wait for PHY PLL lock by polling pll_lock bit */
 551         try = 50;
 552         do {
 553                 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 554                                         BLOCK0_XGXSSTATUS);
 555                 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 556                         break;
 557                 msleep(20);
 558                 try--;
 559         } while (try);
 560
 561         if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) {
 562                 /* PLL did not lock; give up */
 563                 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
 564                 return -ETIMEDOUT;
 565         }
 566
 567         /* Invert Tx polarity */
 568         brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL0,
 569                          ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
 570
 571         /* Configure OOB control to handle 100MHz reference clock */
 572         val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) |
 573                 (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
 574                 (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
 575                 (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
 576         brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
 577         val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
 578                 (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
 579                 (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
 580         brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
 581
 582         return 0;
 583 }
 584
 585 static int brcm_dsl_sata_init(struct brcm_sata_port *port)
 586 {
 587         struct device *dev = port->phy_priv->dev;
 588         unsigned int try;
 589         u32 tmp;
 590
 591         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
 592
 593         brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
 594
 595         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 596                          0, 0x3089);
 597         usleep_range(1000, 2000);
 598
 599         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 600                          0, 0x3088);
 601         usleep_range(1000, 2000);
 602
 603         brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
 604                          0, 0x3000);
 605
 606         brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
 607                          0, 0x3000);
 608         usleep_range(1000, 2000);
 609
 610         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
 611
 612         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
 613
 614         brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
 615         usleep_range(1000, 2000);
 616
 617         /* Acquire PLL lock */
 618         try = 50;
 619         while (try) {
 620                 tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 621                                        BLOCK0_XGXSSTATUS);
 622                 if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
 623                         break;
 624                 msleep(20);
 625                 try--;
 626         };
 627
 628         if (!try) {
 629                 /* PLL did not lock; give up */
 630                 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
 631                 return -ETIMEDOUT;
 632         }
 633
 634         dev_dbg(dev, "port%d initialized\n", port->portnum);
 635
 636         return 0;
 637 }
 638
 639 static int brcm_sata_phy_init(struct phy *phy)
 640 {
 641         int rc;
 642         struct brcm_sata_port *port = phy_get_drvdata(phy);
 643
 644         switch (port->phy_priv->version) {
 645         case BRCM_SATA_PHY_STB_16NM:
 646                 rc = brcm_stb_sata_16nm_init(port);
 647                 break;
 648         case BRCM_SATA_PHY_STB_28NM:
 649         case BRCM_SATA_PHY_STB_40NM:
 650                 rc = brcm_stb_sata_init(port);
 651                 break;
 652         case BRCM_SATA_PHY_IPROC_NS2:
 653                 rc = brcm_ns2_sata_init(port);
 654                 break;
 655         case BRCM_SATA_PHY_IPROC_NSP:
 656                 rc = brcm_nsp_sata_init(port);
 657                 break;
 658         case BRCM_SATA_PHY_IPROC_SR:
 659                 rc = brcm_sr_sata_init(port);
 660                 break;
 661         case BRCM_SATA_PHY_DSL_28NM:
 662                 rc = brcm_dsl_sata_init(port);
 663                 break;
 664         default:
 665                 rc = -ENODEV;
 666         }
 667
 668         return rc;
 669 }
 670
 671 static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
 672 {
 673         u32 tmp = BIT(8);
 674
 675         brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
 676                          ~tmp, tmp);
 677 }
 678
 679 static int brcm_sata_phy_calibrate(struct phy *phy)
 680 {
 681         struct brcm_sata_port *port = phy_get_drvdata(phy);
 682         int rc = -EOPNOTSUPP;
 683
 684         switch (port->phy_priv->version) {
 685         case BRCM_SATA_PHY_STB_28NM:
 686         case BRCM_SATA_PHY_STB_40NM:
 687                 brcm_stb_sata_calibrate(port);
 688                 rc = 0;
 689                 break;
 690         default:
 691                 break;
 692         }
 693
 694         return rc;
 695 }
 696
 697 static const struct phy_ops phy_ops = {
 698         .init           = brcm_sata_phy_init,
 699         .calibrate      = brcm_sata_phy_calibrate,
 700         .owner          = THIS_MODULE,
 701 };
 702
 703 static const struct of_device_id brcm_sata_phy_of_match[] = {
 704         { .compatible   = "brcm,bcm7216-sata-phy",
 705           .data = (void *)BRCM_SATA_PHY_STB_16NM },
 706         { .compatible   = "brcm,bcm7445-sata-phy",
 707           .data = (void *)BRCM_SATA_PHY_STB_28NM },
 708         { .compatible   = "brcm,bcm7425-sata-phy",
 709           .data = (void *)BRCM_SATA_PHY_STB_40NM },
 710         { .compatible   = "brcm,iproc-ns2-sata-phy",
 711           .data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
 712         { .compatible = "brcm,iproc-nsp-sata-phy",
 713           .data = (void *)BRCM_SATA_PHY_IPROC_NSP },
 714         { .compatible   = "brcm,iproc-sr-sata-phy",
 715           .data = (void *)BRCM_SATA_PHY_IPROC_SR },
 716         { .compatible   = "brcm,bcm63138-sata-phy",
 717           .data = (void *)BRCM_SATA_PHY_DSL_28NM },
 718         {},
 719 };
 720 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
 721
 722 static int brcm_sata_phy_probe(struct platform_device *pdev)
 723 {
 724         const char *rxaeq_mode;
 725         struct device *dev = &pdev->dev;
 726         struct device_node *dn = dev->of_node, *child;
 727         const struct of_device_id *of_id;
 728         struct brcm_sata_phy *priv;
 729         struct resource *res;
 730         struct phy_provider *provider;
 731         int ret, count = 0;
 732
 733         if (of_get_child_count(dn) == 0)
 734                 return -ENODEV;
 735
 736         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 737         if (!priv)
 738                 return -ENOMEM;
 739         dev_set_drvdata(dev, priv);
 740         priv->dev = dev;
 741
 742         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
 743         priv->phy_base = devm_ioremap_resource(dev, res);
 744         if (IS_ERR(priv->phy_base))
 745                 return PTR_ERR(priv->phy_base);
 746
 747         of_id = of_match_node(brcm_sata_phy_of_match, dn);
 748         if (of_id)
 749                 priv->version = (enum brcm_sata_phy_version)of_id->data;
 750         else
 751                 priv->version = BRCM_SATA_PHY_STB_28NM;
 752
 753         if (priv->version == BRCM_SATA_PHY_IPROC_NS2) {
 754                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 755                                                    "phy-ctrl");
 756                 priv->ctrl_base = devm_ioremap_resource(dev, res);
 757                 if (IS_ERR(priv->ctrl_base))
 758                         return PTR_ERR(priv->ctrl_base);
 759         }
 760
 761         for_each_available_child_of_node(dn, child) {
 762                 unsigned int id;
 763                 struct brcm_sata_port *port;
 764
 765                 if (of_property_read_u32(child, "reg", &id)) {
 766                         dev_err(dev, "missing reg property in node %pOFn\n",
 767                                         child);
 768                         ret = -EINVAL;
 769                         goto put_child;
 770                 }
 771
 772                 if (id >= MAX_PORTS) {
 773                         dev_err(dev, "invalid reg: %u\n", id);
 774                         ret = -EINVAL;
 775                         goto put_child;
 776                 }
 777                 if (priv->phys[id].phy) {
 778                         dev_err(dev, "already registered port %u\n", id);
 779                         ret = -EINVAL;
 780                         goto put_child;
 781                 }
 782
 783                 port = &priv->phys[id];
 784                 port->portnum = id;
 785                 port->phy_priv = priv;
 786                 port->phy = devm_phy_create(dev, child, &phy_ops);
 787                 port->rxaeq_mode = RXAEQ_MODE_OFF;
 788                 if (!of_property_read_string(child, "brcm,rxaeq-mode",
 789                                              &rxaeq_mode))
 790                         port->rxaeq_mode = rxaeq_to_val(rxaeq_mode);
 791                 if (port->rxaeq_mode == RXAEQ_MODE_MANUAL)
 792                         of_property_read_u32(child, "brcm,rxaeq-value",
 793                                              &port->rxaeq_val);
 794                 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
 795                 if (IS_ERR(port->phy)) {
 796                         dev_err(dev, "failed to create PHY\n");
 797                         ret = PTR_ERR(port->phy);
 798                         goto put_child;
 799                 }
 800
 801                 phy_set_drvdata(port->phy, port);
 802                 count++;
 803         }
 804
 805         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 806         if (IS_ERR(provider)) {
 807                 dev_err(dev, "could not register PHY provider\n");
 808                 return PTR_ERR(provider);
 809         }
 810
 811         dev_info(dev, "registered %d port(s)\n", count);
 812
 813         return 0;
 814 put_child:
 815         of_node_put(child);
 816         return ret;
 817 }
 818
 819 static struct platform_driver brcm_sata_phy_driver = {
 820         .probe  = brcm_sata_phy_probe,
 821         .driver = {
 822                 .of_match_table = brcm_sata_phy_of_match,
 823                 .name           = "brcm-sata-phy",
 824         }
 825 };
 826 module_platform_driver(brcm_sata_phy_driver);
 827
 828 MODULE_DESCRIPTION("Broadcom SATA PHY driver");
 829 MODULE_LICENSE("GPL");
 830 MODULE_AUTHOR("Marc Carino");
 831 MODULE_AUTHOR("Brian Norris");
 832 MODULE_ALIAS("platform:phy-brcm-sata");