1 // SPDX-License-Identifier: GPL-2.0-only
3 * HiSilicon SoC Hardware event counters support
5 * Copyright (C) 2017 Hisilicon Limited
6 * Author: Anurup M <anurup.m@huawei.com>
7 * Shaokun Zhang <zhangshaokun@hisilicon.com>
9 * This code is based on the uncore PMUs like arm-cci and arm-ccn.
11 #include <linux/bitmap.h>
12 #include <linux/bitops.h>
13 #include <linux/bug.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <asm/cputype.h>
19 #include <asm/local64.h>
21 #include "hisi_uncore_pmu.h"
23 #define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
24 #define HISI_MAX_PERIOD(nr) (BIT_ULL(nr) - 1)
27 * PMU format attributes
29 ssize_t hisi_format_sysfs_show(struct device *dev,
30 struct device_attribute *attr, char *buf)
32 struct dev_ext_attribute *eattr;
34 eattr = container_of(attr, struct dev_ext_attribute, attr);
36 return sprintf(buf, "%s\n", (char *)eattr->var);
38 EXPORT_SYMBOL_GPL(hisi_format_sysfs_show);
41 * PMU event attributes
43 ssize_t hisi_event_sysfs_show(struct device *dev,
44 struct device_attribute *attr, char *page)
46 struct dev_ext_attribute *eattr;
48 eattr = container_of(attr, struct dev_ext_attribute, attr);
50 return sprintf(page, "config=0x%lx\n", (unsigned long)eattr->var);
52 EXPORT_SYMBOL_GPL(hisi_event_sysfs_show);
55 * sysfs cpumask attributes. For uncore PMU, we only have a single CPU to show
57 ssize_t hisi_cpumask_sysfs_show(struct device *dev,
58 struct device_attribute *attr, char *buf)
60 struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
62 return sprintf(buf, "%d\n", hisi_pmu->on_cpu);
64 EXPORT_SYMBOL_GPL(hisi_cpumask_sysfs_show);
66 static bool hisi_validate_event_group(struct perf_event *event)
68 struct perf_event *sibling, *leader = event->group_leader;
69 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
70 /* Include count for the event */
73 if (!is_software_event(leader)) {
75 * We must NOT create groups containing mixed PMUs, although
76 * software events are acceptable
78 if (leader->pmu != event->pmu)
81 /* Increment counter for the leader */
86 for_each_sibling_event(sibling, event->group_leader) {
87 if (is_software_event(sibling))
89 if (sibling->pmu != event->pmu)
91 /* Increment counter for each sibling */
95 /* The group can not count events more than the counters in the HW */
96 return counters <= hisi_pmu->num_counters;
99 int hisi_uncore_pmu_counter_valid(struct hisi_pmu *hisi_pmu, int idx)
101 return idx >= 0 && idx < hisi_pmu->num_counters;
103 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_counter_valid);
105 int hisi_uncore_pmu_get_event_idx(struct perf_event *event)
107 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
108 unsigned long *used_mask = hisi_pmu->pmu_events.used_mask;
109 u32 num_counters = hisi_pmu->num_counters;
112 idx = find_first_zero_bit(used_mask, num_counters);
113 if (idx == num_counters)
116 set_bit(idx, used_mask);
120 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_get_event_idx);
122 static void hisi_uncore_pmu_clear_event_idx(struct hisi_pmu *hisi_pmu, int idx)
124 if (!hisi_uncore_pmu_counter_valid(hisi_pmu, idx)) {
125 dev_err(hisi_pmu->dev, "Unsupported event index:%d!\n", idx);
129 clear_bit(idx, hisi_pmu->pmu_events.used_mask);
132 int hisi_uncore_pmu_event_init(struct perf_event *event)
134 struct hw_perf_event *hwc = &event->hw;
135 struct hisi_pmu *hisi_pmu;
137 if (event->attr.type != event->pmu->type)
141 * We do not support sampling as the counters are all
142 * shared by all CPU cores in a CPU die(SCCL). Also we
143 * do not support attach to a task(per-process mode)
145 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
149 * The uncore counters not specific to any CPU, so cannot
156 * Validate if the events in group does not exceed the
157 * available counters in hardware.
159 if (!hisi_validate_event_group(event))
162 hisi_pmu = to_hisi_pmu(event->pmu);
163 if (event->attr.config > hisi_pmu->check_event)
166 if (hisi_pmu->on_cpu == -1)
169 * We don't assign an index until we actually place the event onto
170 * hardware. Use -1 to signify that we haven't decided where to put it
174 hwc->config_base = event->attr.config;
176 /* Enforce to use the same CPU for all events in this PMU */
177 event->cpu = hisi_pmu->on_cpu;
181 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_event_init);
184 * Set the counter to count the event that we're interested in,
185 * and enable interrupt and counter.
187 static void hisi_uncore_pmu_enable_event(struct perf_event *event)
189 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
190 struct hw_perf_event *hwc = &event->hw;
192 hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
193 HISI_GET_EVENTID(event));
195 hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc);
196 hisi_pmu->ops->enable_counter(hisi_pmu, hwc);
200 * Disable counter and interrupt.
202 static void hisi_uncore_pmu_disable_event(struct perf_event *event)
204 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
205 struct hw_perf_event *hwc = &event->hw;
207 hisi_pmu->ops->disable_counter(hisi_pmu, hwc);
208 hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc);
211 void hisi_uncore_pmu_set_event_period(struct perf_event *event)
213 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
214 struct hw_perf_event *hwc = &event->hw;
217 * The HiSilicon PMU counters support 32 bits or 48 bits, depending on
218 * the PMU. We reduce it to 2^(counter_bits - 1) to account for the
219 * extreme interrupt latency. So we could hopefully handle the overflow
220 * interrupt before another 2^(counter_bits - 1) events occur and the
221 * counter overtakes its previous value.
223 u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
225 local64_set(&hwc->prev_count, val);
226 /* Write start value to the hardware event counter */
227 hisi_pmu->ops->write_counter(hisi_pmu, hwc, val);
229 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_set_event_period);
231 void hisi_uncore_pmu_event_update(struct perf_event *event)
233 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
234 struct hw_perf_event *hwc = &event->hw;
235 u64 delta, prev_raw_count, new_raw_count;
238 /* Read the count from the counter register */
239 new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
240 prev_raw_count = local64_read(&hwc->prev_count);
241 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
242 new_raw_count) != prev_raw_count);
246 delta = (new_raw_count - prev_raw_count) &
247 HISI_MAX_PERIOD(hisi_pmu->counter_bits);
248 local64_add(delta, &event->count);
250 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_event_update);
252 void hisi_uncore_pmu_start(struct perf_event *event, int flags)
254 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
255 struct hw_perf_event *hwc = &event->hw;
257 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
260 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
262 hisi_uncore_pmu_set_event_period(event);
264 if (flags & PERF_EF_RELOAD) {
265 u64 prev_raw_count = local64_read(&hwc->prev_count);
267 hisi_pmu->ops->write_counter(hisi_pmu, hwc, prev_raw_count);
270 hisi_uncore_pmu_enable_event(event);
271 perf_event_update_userpage(event);
273 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_start);
275 void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
277 struct hw_perf_event *hwc = &event->hw;
279 hisi_uncore_pmu_disable_event(event);
280 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
281 hwc->state |= PERF_HES_STOPPED;
283 if (hwc->state & PERF_HES_UPTODATE)
286 /* Read hardware counter and update the perf counter statistics */
287 hisi_uncore_pmu_event_update(event);
288 hwc->state |= PERF_HES_UPTODATE;
290 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_stop);
292 int hisi_uncore_pmu_add(struct perf_event *event, int flags)
294 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
295 struct hw_perf_event *hwc = &event->hw;
298 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
300 /* Get an available counter index for counting */
301 idx = hisi_pmu->ops->get_event_idx(event);
306 hisi_pmu->pmu_events.hw_events[idx] = event;
308 if (flags & PERF_EF_START)
309 hisi_uncore_pmu_start(event, PERF_EF_RELOAD);
313 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_add);
315 void hisi_uncore_pmu_del(struct perf_event *event, int flags)
317 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
318 struct hw_perf_event *hwc = &event->hw;
320 hisi_uncore_pmu_stop(event, PERF_EF_UPDATE);
321 hisi_uncore_pmu_clear_event_idx(hisi_pmu, hwc->idx);
322 perf_event_update_userpage(event);
323 hisi_pmu->pmu_events.hw_events[hwc->idx] = NULL;
325 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_del);
327 void hisi_uncore_pmu_read(struct perf_event *event)
329 /* Read hardware counter and update the perf counter statistics */
330 hisi_uncore_pmu_event_update(event);
332 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_read);
334 void hisi_uncore_pmu_enable(struct pmu *pmu)
336 struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
337 int enabled = bitmap_weight(hisi_pmu->pmu_events.used_mask,
338 hisi_pmu->num_counters);
343 hisi_pmu->ops->start_counters(hisi_pmu);
345 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_enable);
347 void hisi_uncore_pmu_disable(struct pmu *pmu)
349 struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
351 hisi_pmu->ops->stop_counters(hisi_pmu);
353 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_disable);
357 * The Super CPU Cluster (SCCL) and CPU Cluster (CCL) IDs can be
358 * determined from the MPIDR_EL1, but the encoding varies by CPU:
360 * - For MT variants of TSV110:
361 * SCCL is Aff2[7:3], CCL is Aff2[2:0]
363 * - For other MT parts:
364 * SCCL is Aff3[7:0], CCL is Aff2[7:0]
366 * - For non-MT parts:
367 * SCCL is Aff2[7:0], CCL is Aff1[7:0]
369 static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)
371 u64 mpidr = read_cpuid_mpidr();
372 int aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);
373 int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
374 int aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1);
375 bool mt = mpidr & MPIDR_MT_BITMASK;
378 if (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
396 * Check whether the CPU is associated with this uncore PMU
398 static bool hisi_pmu_cpu_is_associated_pmu(struct hisi_pmu *hisi_pmu)
402 if (hisi_pmu->ccl_id == -1) {
403 /* If CCL_ID is -1, the PMU only shares the same SCCL */
404 hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
406 return sccl_id == hisi_pmu->sccl_id;
409 hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
411 return sccl_id == hisi_pmu->sccl_id && ccl_id == hisi_pmu->ccl_id;
414 int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
416 struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
419 if (!hisi_pmu_cpu_is_associated_pmu(hisi_pmu))
422 cpumask_set_cpu(cpu, &hisi_pmu->associated_cpus);
424 /* If another CPU is already managing this PMU, simply return. */
425 if (hisi_pmu->on_cpu != -1)
428 /* Use this CPU in cpumask for event counting */
429 hisi_pmu->on_cpu = cpu;
431 /* Overflow interrupt also should use the same CPU */
432 WARN_ON(irq_set_affinity_hint(hisi_pmu->irq, cpumask_of(cpu)));
436 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_online_cpu);
438 int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
440 struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
442 cpumask_t pmu_online_cpus;
445 if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->associated_cpus))
448 /* Nothing to do if this CPU doesn't own the PMU */
449 if (hisi_pmu->on_cpu != cpu)
452 /* Give up ownership of the PMU */
453 hisi_pmu->on_cpu = -1;
455 /* Choose a new CPU to migrate ownership of the PMU to */
456 cpumask_and(&pmu_online_cpus, &hisi_pmu->associated_cpus,
458 target = cpumask_any_but(&pmu_online_cpus, cpu);
459 if (target >= nr_cpu_ids)
462 perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
463 /* Use this CPU for event counting */
464 hisi_pmu->on_cpu = target;
465 WARN_ON(irq_set_affinity_hint(hisi_pmu->irq, cpumask_of(target)));
469 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_offline_cpu);
471 MODULE_LICENSE("GPL v2");