drivers/perf/arm_smmuv3_pmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * This driver adds support for perf events to use the Performance
   5  * Monitor Counter Groups (PMCG) associated with an SMMUv3 node
   6  * to monitor that node.
   7  *
   8  * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
   9  * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
  10  * to 4K boundary. For example, the PMCG at 0xff88840000 is named
  11  * smmuv3_pmcg_ff88840
  12  *
  13  * Filtering by stream id is done by specifying filtering parameters
  14  * with the event. options are:
  15  *   filter_enable    - 0 = no filtering, 1 = filtering enabled
  16  *   filter_span      - 0 = exact match, 1 = pattern match
  17  *   filter_stream_id - pattern to filter against
  18  *
  19  * To match a partial StreamID where the X most-significant bits must match
  20  * but the Y least-significant bits might differ, STREAMID is programmed
  21  * with a value that contains:
  22  *  STREAMID[Y - 1] == 0.
  23  *  STREAMID[Y - 2:0] == 1 (where Y > 1).
  24  * The remainder of implemented bits of STREAMID (X bits, from bit Y upwards)
  25  * contain a value to match from the corresponding bits of event StreamID.
  26  *
  27  * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
  28  *                    filter_span=1,filter_stream_id=0x42/ -a netperf
  29  * Applies filter pattern 0x42 to transaction events, which means events
  30  * matching stream ids 0x42 and 0x43 are counted. Further filtering
  31  * information is available in the SMMU documentation.
  32  *
  33  * SMMU events are not attributable to a CPU, so task mode and sampling
  34  * are not supported.
  35  */
  36
  37 #include <linux/acpi.h>
  38 #include <linux/acpi_iort.h>
  39 #include <linux/bitfield.h>
  40 #include <linux/bitops.h>
  41 #include <linux/cpuhotplug.h>
  42 #include <linux/cpumask.h>
  43 #include <linux/device.h>
  44 #include <linux/errno.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/irq.h>
  47 #include <linux/kernel.h>
  48 #include <linux/list.h>
  49 #include <linux/msi.h>
  50 #include <linux/perf_event.h>
  51 #include <linux/platform_device.h>
  52 #include <linux/smp.h>
  53 #include <linux/sysfs.h>
  54 #include <linux/types.h>
  55
  56 #define SMMU_PMCG_EVCNTR0               0x0
  57 #define SMMU_PMCG_EVCNTR(n, stride)     (SMMU_PMCG_EVCNTR0 + (n) * (stride))
  58 #define SMMU_PMCG_EVTYPER0              0x400
  59 #define SMMU_PMCG_EVTYPER(n)            (SMMU_PMCG_EVTYPER0 + (n) * 4)
  60 #define SMMU_PMCG_SID_SPAN_SHIFT        29
  61 #define SMMU_PMCG_SMR0                  0xA00
  62 #define SMMU_PMCG_SMR(n)                (SMMU_PMCG_SMR0 + (n) * 4)
  63 #define SMMU_PMCG_CNTENSET0             0xC00
  64 #define SMMU_PMCG_CNTENCLR0             0xC20
  65 #define SMMU_PMCG_INTENSET0             0xC40
  66 #define SMMU_PMCG_INTENCLR0             0xC60
  67 #define SMMU_PMCG_OVSCLR0               0xC80
  68 #define SMMU_PMCG_OVSSET0               0xCC0
  69 #define SMMU_PMCG_CFGR                  0xE00
  70 #define SMMU_PMCG_CFGR_SID_FILTER_TYPE  BIT(23)
  71 #define SMMU_PMCG_CFGR_MSI              BIT(21)
  72 #define SMMU_PMCG_CFGR_RELOC_CTRS       BIT(20)
  73 #define SMMU_PMCG_CFGR_SIZE             GENMASK(13, 8)
  74 #define SMMU_PMCG_CFGR_NCTR             GENMASK(5, 0)
  75 #define SMMU_PMCG_CR                    0xE04
  76 #define SMMU_PMCG_CR_ENABLE             BIT(0)
  77 #define SMMU_PMCG_CEID0                 0xE20
  78 #define SMMU_PMCG_CEID1                 0xE28
  79 #define SMMU_PMCG_IRQ_CTRL              0xE50
  80 #define SMMU_PMCG_IRQ_CTRL_IRQEN        BIT(0)
  81 #define SMMU_PMCG_IRQ_CFG0              0xE58
  82 #define SMMU_PMCG_IRQ_CFG1              0xE60
  83 #define SMMU_PMCG_IRQ_CFG2              0xE64
  84
  85 /* MSI config fields */
  86 #define MSI_CFG0_ADDR_MASK              GENMASK_ULL(51, 2)
  87 #define MSI_CFG2_MEMATTR_DEVICE_nGnRE   0x1
  88
  89 #define SMMU_PMCG_DEFAULT_FILTER_SPAN   1
  90 #define SMMU_PMCG_DEFAULT_FILTER_SID    GENMASK(31, 0)
  91
  92 #define SMMU_PMCG_MAX_COUNTERS          64
  93 #define SMMU_PMCG_ARCH_MAX_EVENTS       128
  94
  95 #define SMMU_PMCG_PA_SHIFT              12
  96
  97 #define SMMU_PMCG_EVCNTR_RDONLY         BIT(0)
  98
  99 static int cpuhp_state_num;
 100
 101 struct smmu_pmu {
 102         struct hlist_node node;
 103         struct perf_event *events[SMMU_PMCG_MAX_COUNTERS];
 104         DECLARE_BITMAP(used_counters, SMMU_PMCG_MAX_COUNTERS);
 105         DECLARE_BITMAP(supported_events, SMMU_PMCG_ARCH_MAX_EVENTS);
 106         unsigned int irq;
 107         unsigned int on_cpu;
 108         struct pmu pmu;
 109         unsigned int num_counters;
 110         struct device *dev;
 111         void __iomem *reg_base;
 112         void __iomem *reloc_base;
 113         u64 counter_mask;
 114         u32 options;
 115         bool global_filter;
 116 };
 117
 118 #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu))
 119
 120 #define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end)        \
 121         static inline u32 get_##_name(struct perf_event *event)            \
 122         {                                                                  \
 123                 return FIELD_GET(GENMASK_ULL(_end, _start),                \
 124                                  event->attr._config);                     \
 125         }                                                                  \
 126
 127 SMMU_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 15);
 128 SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_stream_id, config1, 0, 31);
 129 SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_span, config1, 32, 32);
 130 SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_enable, config1, 33, 33);
 131
 132 static inline void smmu_pmu_enable(struct pmu *pmu)
 133 {
 134         struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
 135
 136         writel(SMMU_PMCG_IRQ_CTRL_IRQEN,
 137                smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
 138         writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
 139 }
 140
 141 static inline void smmu_pmu_disable(struct pmu *pmu)
 142 {
 143         struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
 144
 145         writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
 146         writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
 147 }
 148
 149 static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
 150                                               u32 idx, u64 value)
 151 {
 152         if (smmu_pmu->counter_mask & BIT(32))
 153                 writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
 154         else
 155                 writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
 156 }
 157
 158 static inline u64 smmu_pmu_counter_get_value(struct smmu_pmu *smmu_pmu, u32 idx)
 159 {
 160         u64 value;
 161
 162         if (smmu_pmu->counter_mask & BIT(32))
 163                 value = readq(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
 164         else
 165                 value = readl(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
 166
 167         return value;
 168 }
 169
 170 static inline void smmu_pmu_counter_enable(struct smmu_pmu *smmu_pmu, u32 idx)
 171 {
 172         writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
 173 }
 174
 175 static inline void smmu_pmu_counter_disable(struct smmu_pmu *smmu_pmu, u32 idx)
 176 {
 177         writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
 178 }
 179
 180 static inline void smmu_pmu_interrupt_enable(struct smmu_pmu *smmu_pmu, u32 idx)
 181 {
 182         writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
 183 }
 184
 185 static inline void smmu_pmu_interrupt_disable(struct smmu_pmu *smmu_pmu,
 186                                               u32 idx)
 187 {
 188         writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
 189 }
 190
 191 static inline void smmu_pmu_set_evtyper(struct smmu_pmu *smmu_pmu, u32 idx,
 192                                         u32 val)
 193 {
 194         writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
 195 }
 196
 197 static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val)
 198 {
 199         writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
 200 }
 201
 202 static void smmu_pmu_event_update(struct perf_event *event)
 203 {
 204         struct hw_perf_event *hwc = &event->hw;
 205         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 206         u64 delta, prev, now;
 207         u32 idx = hwc->idx;
 208
 209         do {
 210                 prev = local64_read(&hwc->prev_count);
 211                 now = smmu_pmu_counter_get_value(smmu_pmu, idx);
 212         } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);
 213
 214         /* handle overflow. */
 215         delta = now - prev;
 216         delta &= smmu_pmu->counter_mask;
 217
 218         local64_add(delta, &event->count);
 219 }
 220
 221 static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
 222                                 struct hw_perf_event *hwc)
 223 {
 224         u32 idx = hwc->idx;
 225         u64 new;
 226
 227         if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
 228                 /*
 229                  * On platforms that require this quirk, if the counter starts
 230                  * at < half_counter value and wraps, the current logic of
 231                  * handling the overflow may not work. It is expected that,
 232                  * those platforms will have full 64 counter bits implemented
 233                  * so that such a possibility is remote(eg: HiSilicon HIP08).
 234                  */
 235                 new = smmu_pmu_counter_get_value(smmu_pmu, idx);
 236         } else {
 237                 /*
 238                  * We limit the max period to half the max counter value
 239                  * of the counter size, so that even in the case of extreme
 240                  * interrupt latency the counter will (hopefully) not wrap
 241                  * past its initial value.
 242                  */
 243                 new = smmu_pmu->counter_mask >> 1;
 244                 smmu_pmu_counter_set_value(smmu_pmu, idx, new);
 245         }
 246
 247         local64_set(&hwc->prev_count, new);
 248 }
 249
 250 static void smmu_pmu_set_event_filter(struct perf_event *event,
 251                                       int idx, u32 span, u32 sid)
 252 {
 253         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 254         u32 evtyper;
 255
 256         evtyper = get_event(event) | span << SMMU_PMCG_SID_SPAN_SHIFT;
 257         smmu_pmu_set_evtyper(smmu_pmu, idx, evtyper);
 258         smmu_pmu_set_smr(smmu_pmu, idx, sid);
 259 }
 260
 261 static bool smmu_pmu_check_global_filter(struct perf_event *curr,
 262                                          struct perf_event *new)
 263 {
 264         if (get_filter_enable(new) != get_filter_enable(curr))
 265                 return false;
 266
 267         if (!get_filter_enable(new))
 268                 return true;
 269
 270         return get_filter_span(new) == get_filter_span(curr) &&
 271                get_filter_stream_id(new) == get_filter_stream_id(curr);
 272 }
 273
 274 static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
 275                                        struct perf_event *event, int idx)
 276 {
 277         u32 span, sid;
 278         unsigned int cur_idx, num_ctrs = smmu_pmu->num_counters;
 279         bool filter_en = !!get_filter_enable(event);
 280
 281         span = filter_en ? get_filter_span(event) :
 282                            SMMU_PMCG_DEFAULT_FILTER_SPAN;
 283         sid = filter_en ? get_filter_stream_id(event) :
 284                            SMMU_PMCG_DEFAULT_FILTER_SID;
 285
 286         cur_idx = find_first_bit(smmu_pmu->used_counters, num_ctrs);
 287         /*
 288          * Per-counter filtering, or scheduling the first globally-filtered
 289          * event into an empty PMU so idx == 0 and it works out equivalent.
 290          */
 291         if (!smmu_pmu->global_filter || cur_idx == num_ctrs) {
 292                 smmu_pmu_set_event_filter(event, idx, span, sid);
 293                 return 0;
 294         }
 295
 296         /* Otherwise, must match whatever's currently scheduled */
 297         if (smmu_pmu_check_global_filter(smmu_pmu->events[cur_idx], event)) {
 298                 smmu_pmu_set_evtyper(smmu_pmu, idx, get_event(event));
 299                 return 0;
 300         }
 301
 302         return -EAGAIN;
 303 }
 304
 305 static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu_pmu,
 306                                   struct perf_event *event)
 307 {
 308         int idx, err;
 309         unsigned int num_ctrs = smmu_pmu->num_counters;
 310
 311         idx = find_first_zero_bit(smmu_pmu->used_counters, num_ctrs);
 312         if (idx == num_ctrs)
 313                 /* The counters are all in use. */
 314                 return -EAGAIN;
 315
 316         err = smmu_pmu_apply_event_filter(smmu_pmu, event, idx);
 317         if (err)
 318                 return err;
 319
 320         set_bit(idx, smmu_pmu->used_counters);
 321
 322         return idx;
 323 }
 324
 325 static bool smmu_pmu_events_compatible(struct perf_event *curr,
 326                                        struct perf_event *new)
 327 {
 328         if (new->pmu != curr->pmu)
 329                 return false;
 330
 331         if (to_smmu_pmu(new->pmu)->global_filter &&
 332             !smmu_pmu_check_global_filter(curr, new))
 333                 return false;
 334
 335         return true;
 336 }
 337
 338 /*
 339  * Implementation of abstract pmu functionality required by
 340  * the core perf events code.
 341  */
 342
 343 static int smmu_pmu_event_init(struct perf_event *event)
 344 {
 345         struct hw_perf_event *hwc = &event->hw;
 346         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 347         struct device *dev = smmu_pmu->dev;
 348         struct perf_event *sibling;
 349         int group_num_events = 1;
 350         u16 event_id;
 351
 352         if (event->attr.type != event->pmu->type)
 353                 return -ENOENT;
 354
 355         if (hwc->sample_period) {
 356                 dev_dbg(dev, "Sampling not supported\n");
 357                 return -EOPNOTSUPP;
 358         }
 359
 360         if (event->cpu < 0) {
 361                 dev_dbg(dev, "Per-task mode not supported\n");
 362                 return -EOPNOTSUPP;
 363         }
 364
 365         /* Verify specified event is supported on this PMU */
 366         event_id = get_event(event);
 367         if (event_id < SMMU_PMCG_ARCH_MAX_EVENTS &&
 368             (!test_bit(event_id, smmu_pmu->supported_events))) {
 369                 dev_dbg(dev, "Invalid event %d for this PMU\n", event_id);
 370                 return -EINVAL;
 371         }
 372
 373         /* Don't allow groups with mixed PMUs, except for s/w events */
 374         if (!is_software_event(event->group_leader)) {
 375                 if (!smmu_pmu_events_compatible(event->group_leader, event))
 376                         return -EINVAL;
 377
 378                 if (++group_num_events > smmu_pmu->num_counters)
 379                         return -EINVAL;
 380         }
 381
 382         for_each_sibling_event(sibling, event->group_leader) {
 383                 if (is_software_event(sibling))
 384                         continue;
 385
 386                 if (!smmu_pmu_events_compatible(sibling, event))
 387                         return -EINVAL;
 388
 389                 if (++group_num_events > smmu_pmu->num_counters)
 390                         return -EINVAL;
 391         }
 392
 393         hwc->idx = -1;
 394
 395         /*
 396          * Ensure all events are on the same cpu so all events are in the
 397          * same cpu context, to avoid races on pmu_enable etc.
 398          */
 399         event->cpu = smmu_pmu->on_cpu;
 400
 401         return 0;
 402 }
 403
 404 static void smmu_pmu_event_start(struct perf_event *event, int flags)
 405 {
 406         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 407         struct hw_perf_event *hwc = &event->hw;
 408         int idx = hwc->idx;
 409
 410         hwc->state = 0;
 411
 412         smmu_pmu_set_period(smmu_pmu, hwc);
 413
 414         smmu_pmu_counter_enable(smmu_pmu, idx);
 415 }
 416
 417 static void smmu_pmu_event_stop(struct perf_event *event, int flags)
 418 {
 419         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 420         struct hw_perf_event *hwc = &event->hw;
 421         int idx = hwc->idx;
 422
 423         if (hwc->state & PERF_HES_STOPPED)
 424                 return;
 425
 426         smmu_pmu_counter_disable(smmu_pmu, idx);
 427         /* As the counter gets updated on _start, ignore PERF_EF_UPDATE */
 428         smmu_pmu_event_update(event);
 429         hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 430 }
 431
 432 static int smmu_pmu_event_add(struct perf_event *event, int flags)
 433 {
 434         struct hw_perf_event *hwc = &event->hw;
 435         int idx;
 436         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 437
 438         idx = smmu_pmu_get_event_idx(smmu_pmu, event);
 439         if (idx < 0)
 440                 return idx;
 441
 442         hwc->idx = idx;
 443         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 444         smmu_pmu->events[idx] = event;
 445         local64_set(&hwc->prev_count, 0);
 446
 447         smmu_pmu_interrupt_enable(smmu_pmu, idx);
 448
 449         if (flags & PERF_EF_START)
 450                 smmu_pmu_event_start(event, flags);
 451
 452         /* Propagate changes to the userspace mapping. */
 453         perf_event_update_userpage(event);
 454
 455         return 0;
 456 }
 457
 458 static void smmu_pmu_event_del(struct perf_event *event, int flags)
 459 {
 460         struct hw_perf_event *hwc = &event->hw;
 461         struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
 462         int idx = hwc->idx;
 463
 464         smmu_pmu_event_stop(event, flags | PERF_EF_UPDATE);
 465         smmu_pmu_interrupt_disable(smmu_pmu, idx);
 466         smmu_pmu->events[idx] = NULL;
 467         clear_bit(idx, smmu_pmu->used_counters);
 468
 469         perf_event_update_userpage(event);
 470 }
 471
 472 static void smmu_pmu_event_read(struct perf_event *event)
 473 {
 474         smmu_pmu_event_update(event);
 475 }
 476
 477 /* cpumask */
 478
 479 static ssize_t smmu_pmu_cpumask_show(struct device *dev,
 480                                      struct device_attribute *attr,
 481                                      char *buf)
 482 {
 483         struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
 484
 485         return cpumap_print_to_pagebuf(true, buf, cpumask_of(smmu_pmu->on_cpu));
 486 }
 487
 488 static struct device_attribute smmu_pmu_cpumask_attr =
 489                 __ATTR(cpumask, 0444, smmu_pmu_cpumask_show, NULL);
 490
 491 static struct attribute *smmu_pmu_cpumask_attrs[] = {
 492         &smmu_pmu_cpumask_attr.attr,
 493         NULL
 494 };
 495
 496 static struct attribute_group smmu_pmu_cpumask_group = {
 497         .attrs = smmu_pmu_cpumask_attrs,
 498 };
 499
 500 /* Events */
 501
 502 static ssize_t smmu_pmu_event_show(struct device *dev,
 503                                    struct device_attribute *attr, char *page)
 504 {
 505         struct perf_pmu_events_attr *pmu_attr;
 506
 507         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 508
 509         return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
 510 }
 511
 512 #define SMMU_EVENT_ATTR(name, config) \
 513         PMU_EVENT_ATTR(name, smmu_event_attr_##name, \
 514                        config, smmu_pmu_event_show)
 515 SMMU_EVENT_ATTR(cycles, 0);
 516 SMMU_EVENT_ATTR(transaction, 1);
 517 SMMU_EVENT_ATTR(tlb_miss, 2);
 518 SMMU_EVENT_ATTR(config_cache_miss, 3);
 519 SMMU_EVENT_ATTR(trans_table_walk_access, 4);
 520 SMMU_EVENT_ATTR(config_struct_access, 5);
 521 SMMU_EVENT_ATTR(pcie_ats_trans_rq, 6);
 522 SMMU_EVENT_ATTR(pcie_ats_trans_passed, 7);
 523
 524 static struct attribute *smmu_pmu_events[] = {
 525         &smmu_event_attr_cycles.attr.attr,
 526         &smmu_event_attr_transaction.attr.attr,
 527         &smmu_event_attr_tlb_miss.attr.attr,
 528         &smmu_event_attr_config_cache_miss.attr.attr,
 529         &smmu_event_attr_trans_table_walk_access.attr.attr,
 530         &smmu_event_attr_config_struct_access.attr.attr,
 531         &smmu_event_attr_pcie_ats_trans_rq.attr.attr,
 532         &smmu_event_attr_pcie_ats_trans_passed.attr.attr,
 533         NULL
 534 };
 535
 536 static umode_t smmu_pmu_event_is_visible(struct kobject *kobj,
 537                                          struct attribute *attr, int unused)
 538 {
 539         struct device *dev = kobj_to_dev(kobj);
 540         struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
 541         struct perf_pmu_events_attr *pmu_attr;
 542
 543         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 544
 545         if (test_bit(pmu_attr->id, smmu_pmu->supported_events))
 546                 return attr->mode;
 547
 548         return 0;
 549 }
 550
 551 static struct attribute_group smmu_pmu_events_group = {
 552         .name = "events",
 553         .attrs = smmu_pmu_events,
 554         .is_visible = smmu_pmu_event_is_visible,
 555 };
 556
 557 /* Formats */
 558 PMU_FORMAT_ATTR(event,             "config:0-15");
 559 PMU_FORMAT_ATTR(filter_stream_id,  "config1:0-31");
 560 PMU_FORMAT_ATTR(filter_span,       "config1:32");
 561 PMU_FORMAT_ATTR(filter_enable,     "config1:33");
 562
 563 static struct attribute *smmu_pmu_formats[] = {
 564         &format_attr_event.attr,
 565         &format_attr_filter_stream_id.attr,
 566         &format_attr_filter_span.attr,
 567         &format_attr_filter_enable.attr,
 568         NULL
 569 };
 570
 571 static struct attribute_group smmu_pmu_format_group = {
 572         .name = "format",
 573         .attrs = smmu_pmu_formats,
 574 };
 575
 576 static const struct attribute_group *smmu_pmu_attr_grps[] = {
 577         &smmu_pmu_cpumask_group,
 578         &smmu_pmu_events_group,
 579         &smmu_pmu_format_group,
 580         NULL
 581 };
 582
 583 /*
 584  * Generic device handlers
 585  */
 586
 587 static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
 588 {
 589         struct smmu_pmu *smmu_pmu;
 590         unsigned int target;
 591
 592         smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node);
 593         if (cpu != smmu_pmu->on_cpu)
 594                 return 0;
 595
 596         target = cpumask_any_but(cpu_online_mask, cpu);
 597         if (target >= nr_cpu_ids)
 598                 return 0;
 599
 600         perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target);
 601         smmu_pmu->on_cpu = target;
 602         WARN_ON(irq_set_affinity_hint(smmu_pmu->irq, cpumask_of(target)));
 603
 604         return 0;
 605 }
 606
 607 static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data)
 608 {
 609         struct smmu_pmu *smmu_pmu = data;
 610         u64 ovsr;
 611         unsigned int idx;
 612
 613         ovsr = readq(smmu_pmu->reloc_base + SMMU_PMCG_OVSSET0);
 614         if (!ovsr)
 615                 return IRQ_NONE;
 616
 617         writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
 618
 619         for_each_set_bit(idx, (unsigned long *)&ovsr, smmu_pmu->num_counters) {
 620                 struct perf_event *event = smmu_pmu->events[idx];
 621                 struct hw_perf_event *hwc;
 622
 623                 if (WARN_ON_ONCE(!event))
 624                         continue;
 625
 626                 smmu_pmu_event_update(event);
 627                 hwc = &event->hw;
 628
 629                 smmu_pmu_set_period(smmu_pmu, hwc);
 630         }
 631
 632         return IRQ_HANDLED;
 633 }
 634
 635 static void smmu_pmu_free_msis(void *data)
 636 {
 637         struct device *dev = data;
 638
 639         platform_msi_domain_free_irqs(dev);
 640 }
 641
 642 static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
 643 {
 644         phys_addr_t doorbell;
 645         struct device *dev = msi_desc_to_dev(desc);
 646         struct smmu_pmu *pmu = dev_get_drvdata(dev);
 647
 648         doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
 649         doorbell &= MSI_CFG0_ADDR_MASK;
 650
 651         writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
 652         writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
 653         writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE,
 654                        pmu->reg_base + SMMU_PMCG_IRQ_CFG2);
 655 }
 656
 657 static void smmu_pmu_setup_msi(struct smmu_pmu *pmu)
 658 {
 659         struct msi_desc *desc;
 660         struct device *dev = pmu->dev;
 661         int ret;
 662
 663         /* Clear MSI address reg */
 664         writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
 665
 666         /* MSI supported or not */
 667         if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI))
 668                 return;
 669
 670         ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg);
 671         if (ret) {
 672                 dev_warn(dev, "failed to allocate MSIs\n");
 673                 return;
 674         }
 675
 676         desc = first_msi_entry(dev);
 677         if (desc)
 678                 pmu->irq = desc->irq;
 679
 680         /* Add callback to free MSIs on teardown */
 681         devm_add_action(dev, smmu_pmu_free_msis, dev);
 682 }
 683
 684 static int smmu_pmu_setup_irq(struct smmu_pmu *pmu)
 685 {
 686         unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD;
 687         int irq, ret = -ENXIO;
 688
 689         smmu_pmu_setup_msi(pmu);
 690
 691         irq = pmu->irq;
 692         if (irq)
 693                 ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq,
 694                                        flags, "smmuv3-pmu", pmu);
 695         return ret;
 696 }
 697
 698 static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
 699 {
 700         u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0);
 701
 702         smmu_pmu_disable(&smmu_pmu->pmu);
 703
 704         /* Disable counter and interrupt */
 705         writeq_relaxed(counter_present_mask,
 706                        smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
 707         writeq_relaxed(counter_present_mask,
 708                        smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
 709         writeq_relaxed(counter_present_mask,
 710                        smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
 711 }
 712
 713 static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
 714 {
 715         u32 model;
 716
 717         model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
 718
 719         switch (model) {
 720         case IORT_SMMU_V3_PMCG_HISI_HIP08:
 721                 /* HiSilicon Erratum 162001800 */
 722                 smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
 723                 break;
 724         }
 725
 726         dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
 727 }
 728
 729 static int smmu_pmu_probe(struct platform_device *pdev)
 730 {
 731         struct smmu_pmu *smmu_pmu;
 732         struct resource *res_0;
 733         u32 cfgr, reg_size;
 734         u64 ceid_64[2];
 735         int irq, err;
 736         char *name;
 737         struct device *dev = &pdev->dev;
 738
 739         smmu_pmu = devm_kzalloc(dev, sizeof(*smmu_pmu), GFP_KERNEL);
 740         if (!smmu_pmu)
 741                 return -ENOMEM;
 742
 743         smmu_pmu->dev = dev;
 744         platform_set_drvdata(pdev, smmu_pmu);
 745
 746         smmu_pmu->pmu = (struct pmu) {
 747                 .module         = THIS_MODULE,
 748                 .task_ctx_nr    = perf_invalid_context,
 749                 .pmu_enable     = smmu_pmu_enable,
 750                 .pmu_disable    = smmu_pmu_disable,
 751                 .event_init     = smmu_pmu_event_init,
 752                 .add            = smmu_pmu_event_add,
 753                 .del            = smmu_pmu_event_del,
 754                 .start          = smmu_pmu_event_start,
 755                 .stop           = smmu_pmu_event_stop,
 756                 .read           = smmu_pmu_event_read,
 757                 .attr_groups    = smmu_pmu_attr_grps,
 758                 .capabilities   = PERF_PMU_CAP_NO_EXCLUDE,
 759         };
 760
 761         smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
 762         if (IS_ERR(smmu_pmu->reg_base))
 763                 return PTR_ERR(smmu_pmu->reg_base);
 764
 765         cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
 766
 767         /* Determine if page 1 is present */
 768         if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
 769                 smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
 770                 if (IS_ERR(smmu_pmu->reloc_base))
 771                         return PTR_ERR(smmu_pmu->reloc_base);
 772         } else {
 773                 smmu_pmu->reloc_base = smmu_pmu->reg_base;
 774         }
 775
 776         irq = platform_get_irq_optional(pdev, 0);
 777         if (irq > 0)
 778                 smmu_pmu->irq = irq;
 779
 780         ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
 781         ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
 782         bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64,
 783                           SMMU_PMCG_ARCH_MAX_EVENTS);
 784
 785         smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1;
 786
 787         smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE);
 788
 789         reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr);
 790         smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);
 791
 792         smmu_pmu_reset(smmu_pmu);
 793
 794         err = smmu_pmu_setup_irq(smmu_pmu);
 795         if (err) {
 796                 dev_err(dev, "Setup irq failed, PMU @%pa\n", &res_0->start);
 797                 return err;
 798         }
 799
 800         name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx",
 801                               (res_0->start) >> SMMU_PMCG_PA_SHIFT);
 802         if (!name) {
 803                 dev_err(dev, "Create name failed, PMU @%pa\n", &res_0->start);
 804                 return -EINVAL;
 805         }
 806
 807         smmu_pmu_get_acpi_options(smmu_pmu);
 808
 809         /* Pick one CPU to be the preferred one to use */
 810         smmu_pmu->on_cpu = raw_smp_processor_id();
 811         WARN_ON(irq_set_affinity_hint(smmu_pmu->irq,
 812                                       cpumask_of(smmu_pmu->on_cpu)));
 813
 814         err = cpuhp_state_add_instance_nocalls(cpuhp_state_num,
 815                                                &smmu_pmu->node);
 816         if (err) {
 817                 dev_err(dev, "Error %d registering hotplug, PMU @%pa\n",
 818                         err, &res_0->start);
 819                 goto out_clear_affinity;
 820         }
 821
 822         err = perf_pmu_register(&smmu_pmu->pmu, name, -1);
 823         if (err) {
 824                 dev_err(dev, "Error %d registering PMU @%pa\n",
 825                         err, &res_0->start);
 826                 goto out_unregister;
 827         }
 828
 829         dev_info(dev, "Registered PMU @ %pa using %d counters with %s filter settings\n",
 830                  &res_0->start, smmu_pmu->num_counters,
 831                  smmu_pmu->global_filter ? "Global(Counter0)" :
 832                  "Individual");
 833
 834         return 0;
 835
 836 out_unregister:
 837         cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
 838 out_clear_affinity:
 839         irq_set_affinity_hint(smmu_pmu->irq, NULL);
 840         return err;
 841 }
 842
 843 static int smmu_pmu_remove(struct platform_device *pdev)
 844 {
 845         struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
 846
 847         perf_pmu_unregister(&smmu_pmu->pmu);
 848         cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
 849         irq_set_affinity_hint(smmu_pmu->irq, NULL);
 850
 851         return 0;
 852 }
 853
 854 static void smmu_pmu_shutdown(struct platform_device *pdev)
 855 {
 856         struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
 857
 858         smmu_pmu_disable(&smmu_pmu->pmu);
 859 }
 860
 861 static struct platform_driver smmu_pmu_driver = {
 862         .driver = {
 863                 .name = "arm-smmu-v3-pmcg",
 864                 .suppress_bind_attrs = true,
 865         },
 866         .probe = smmu_pmu_probe,
 867         .remove = smmu_pmu_remove,
 868         .shutdown = smmu_pmu_shutdown,
 869 };
 870
 871 static int __init arm_smmu_pmu_init(void)
 872 {
 873         cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
 874                                                   "perf/arm/pmcg:online",
 875                                                   NULL,
 876                                                   smmu_pmu_offline_cpu);
 877         if (cpuhp_state_num < 0)
 878                 return cpuhp_state_num;
 879
 880         return platform_driver_register(&smmu_pmu_driver);
 881 }
 882 module_init(arm_smmu_pmu_init);
 883
 884 static void __exit arm_smmu_pmu_exit(void)
 885 {
 886         platform_driver_unregister(&smmu_pmu_driver);
 887         cpuhp_remove_multi_state(cpuhp_state_num);
 888 }
 889
 890 module_exit(arm_smmu_pmu_exit);
 891
 892 MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
 893 MODULE_AUTHOR("Neil Leeder <nleeder@codeaurora.org>");
 894 MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>");
 895 MODULE_LICENSE("GPL v2");