drivers/perf/arm_pmu_platform.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * platform_device probing code for ARM performance counters.
   4  *
   5  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   6  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   7  */
   8 #define pr_fmt(fmt) "hw perfevents: " fmt
   9
  10 #include <linux/bug.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/device.h>
  13 #include <linux/errno.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqdesc.h>
  16 #include <linux/kconfig.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/percpu.h>
  20 #include <linux/perf/arm_pmu.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/printk.h>
  23 #include <linux/smp.h>
  24
  25 static int probe_current_pmu(struct arm_pmu *pmu,
  26                              const struct pmu_probe_info *info)
  27 {
  28         int cpu = get_cpu();
  29         unsigned int cpuid = read_cpuid_id();
  30         int ret = -ENODEV;
  31
  32         pr_info("probing PMU on CPU %d\n", cpu);
  33
  34         for (; info->init != NULL; info++) {
  35                 if ((cpuid & info->mask) != info->cpuid)
  36                         continue;
  37                 ret = info->init(pmu);
  38                 break;
  39         }
  40
  41         put_cpu();
  42         return ret;
  43 }
  44
  45 static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq)
  46 {
  47         int cpu, ret;
  48         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
  49
  50         ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
  51         if (ret)
  52                 return ret;
  53
  54         for_each_cpu(cpu, &pmu->supported_cpus)
  55                 per_cpu(hw_events->irq, cpu) = irq;
  56
  57         return 0;
  58 }
  59
  60 static bool pmu_has_irq_affinity(struct device_node *node)
  61 {
  62         return !!of_find_property(node, "interrupt-affinity", NULL);
  63 }
  64
  65 static int pmu_parse_irq_affinity(struct device_node *node, int i)
  66 {
  67         struct device_node *dn;
  68         int cpu;
  69
  70         /*
  71          * If we don't have an interrupt-affinity property, we guess irq
  72          * affinity matches our logical CPU order, as we used to assume.
  73          * This is fragile, so we'll warn in pmu_parse_irqs().
  74          */
  75         if (!pmu_has_irq_affinity(node))
  76                 return i;
  77
  78         dn = of_parse_phandle(node, "interrupt-affinity", i);
  79         if (!dn) {
  80                 pr_warn("failed to parse interrupt-affinity[%d] for %s\n",
  81                         i, node->name);
  82                 return -EINVAL;
  83         }
  84
  85         /* Now look up the logical CPU number */
  86         for_each_possible_cpu(cpu) {
  87                 struct device_node *cpu_dn;
  88
  89                 cpu_dn = of_cpu_device_node_get(cpu);
  90                 of_node_put(cpu_dn);
  91
  92                 if (dn == cpu_dn)
  93                         break;
  94         }
  95
  96         if (cpu >= nr_cpu_ids) {
  97                 pr_warn("failed to find logical CPU for %s\n", dn->name);
  98         }
  99
 100         of_node_put(dn);
 101
 102         return cpu;
 103 }
 104
 105 static int pmu_parse_irqs(struct arm_pmu *pmu)
 106 {
 107         int i = 0, num_irqs;
 108         struct platform_device *pdev = pmu->plat_device;
 109         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 110
 111         num_irqs = platform_irq_count(pdev);
 112         if (num_irqs < 0) {
 113                 pr_err("unable to count PMU IRQs\n");
 114                 return num_irqs;
 115         }
 116
 117         /*
 118          * In this case we have no idea which CPUs are covered by the PMU.
 119          * To match our prior behaviour, we assume all CPUs in this case.
 120          */
 121         if (num_irqs == 0) {
 122                 pr_warn("no irqs for PMU, sampling events not supported\n");
 123                 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
 124                 cpumask_setall(&pmu->supported_cpus);
 125                 return 0;
 126         }
 127
 128         if (num_irqs == 1) {
 129                 int irq = platform_get_irq(pdev, 0);
 130                 if (irq && irq_is_percpu(irq))
 131                         return pmu_parse_percpu_irq(pmu, irq);
 132         }
 133
 134         if (!pmu_has_irq_affinity(pdev->dev.of_node)) {
 135                 pr_warn("no interrupt-affinity property for %pOF, guessing.\n",
 136                         pdev->dev.of_node);
 137         }
 138
 139         /*
 140          * Some platforms have all PMU IRQs OR'd into a single IRQ, with a
 141          * special platdata function that attempts to demux them.
 142          */
 143         if (dev_get_platdata(&pdev->dev))
 144                 cpumask_setall(&pmu->supported_cpus);
 145
 146         for (i = 0; i < num_irqs; i++) {
 147                 int cpu, irq;
 148
 149                 irq = platform_get_irq(pdev, i);
 150                 if (WARN_ON(irq <= 0))
 151                         continue;
 152
 153                 if (irq_is_percpu(irq)) {
 154                         pr_warn("multiple PPIs or mismatched SPI/PPI detected\n");
 155                         return -EINVAL;
 156                 }
 157
 158                 cpu = pmu_parse_irq_affinity(pdev->dev.of_node, i);
 159                 if (cpu < 0)
 160                         return cpu;
 161                 if (cpu >= nr_cpu_ids)
 162                         continue;
 163
 164                 if (per_cpu(hw_events->irq, cpu)) {
 165                         pr_warn("multiple PMU IRQs for the same CPU detected\n");
 166                         return -EINVAL;
 167                 }
 168
 169                 per_cpu(hw_events->irq, cpu) = irq;
 170                 cpumask_set_cpu(cpu, &pmu->supported_cpus);
 171         }
 172
 173         return 0;
 174 }
 175
 176 int arm_pmu_device_probe(struct platform_device *pdev,
 177                          const struct of_device_id *of_table,
 178                          const struct pmu_probe_info *probe_table)
 179 {
 180         const struct of_device_id *of_id;
 181         armpmu_init_fn init_fn;
 182         struct device_node *node = pdev->dev.of_node;
 183         struct arm_pmu *pmu;
 184         int ret = -ENODEV;
 185
 186         pmu = armpmu_alloc();
 187         if (!pmu)
 188                 return -ENOMEM;
 189
 190         pmu->plat_device = pdev;
 191
 192         ret = pmu_parse_irqs(pmu);
 193         if (ret)
 194                 goto out_free;
 195
 196         if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
 197                 init_fn = of_id->data;
 198
 199                 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
 200                                                            "secure-reg-access");
 201
 202                 /* arm64 systems boot only as non-secure */
 203                 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
 204                         pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
 205                         pmu->secure_access = false;
 206                 }
 207
 208                 ret = init_fn(pmu);
 209         } else if (probe_table) {
 210                 cpumask_setall(&pmu->supported_cpus);
 211                 ret = probe_current_pmu(pmu, probe_table);
 212         }
 213
 214         if (ret) {
 215                 pr_info("%pOF: failed to probe PMU!\n", node);
 216                 goto out_free;
 217         }
 218
 219         ret = armpmu_request_irqs(pmu);
 220         if (ret)
 221                 goto out_free_irqs;
 222
 223         ret = armpmu_register(pmu);
 224         if (ret)
 225                 goto out_free_irqs;
 226
 227         return 0;
 228
 229 out_free_irqs:
 230         armpmu_free_irqs(pmu);
 231 out_free:
 232         pr_info("%pOF: failed to register PMU devices!\n", node);
 233         armpmu_free(pmu);
 234         return ret;
 235 }