GNU Linux-libre 4.4.289-gnu1
[releases.git] / drivers / perf / arm_pmu.c
1 #undef DEBUG
2
3 /*
4  * ARM performance counter support.
5  *
6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
8  *
9  * This code is based on the sparc64 perf event code, which is in turn based
10  * on the x86 code.
11  */
12 #define pr_fmt(fmt) "hw perfevents: " fmt
13
14 #include <linux/bitmap.h>
15 #include <linux/cpumask.h>
16 #include <linux/export.h>
17 #include <linux/kernel.h>
18 #include <linux/of_device.h>
19 #include <linux/perf/arm_pmu.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/irq.h>
24 #include <linux/irqdesc.h>
25
26 #include <asm/cputype.h>
27 #include <asm/irq_regs.h>
28
29 static int
30 armpmu_map_cache_event(const unsigned (*cache_map)
31                                       [PERF_COUNT_HW_CACHE_MAX]
32                                       [PERF_COUNT_HW_CACHE_OP_MAX]
33                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
34                        u64 config)
35 {
36         unsigned int cache_type, cache_op, cache_result, ret;
37
38         cache_type = (config >>  0) & 0xff;
39         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
40                 return -EINVAL;
41
42         cache_op = (config >>  8) & 0xff;
43         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
44                 return -EINVAL;
45
46         cache_result = (config >> 16) & 0xff;
47         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
48                 return -EINVAL;
49
50         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
51
52         if (ret == CACHE_OP_UNSUPPORTED)
53                 return -ENOENT;
54
55         return ret;
56 }
57
58 static int
59 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
60 {
61         int mapping;
62
63         if (config >= PERF_COUNT_HW_MAX)
64                 return -EINVAL;
65
66         mapping = (*event_map)[config];
67         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
68 }
69
70 static int
71 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
72 {
73         return (int)(config & raw_event_mask);
74 }
75
76 int
77 armpmu_map_event(struct perf_event *event,
78                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
79                  const unsigned (*cache_map)
80                                 [PERF_COUNT_HW_CACHE_MAX]
81                                 [PERF_COUNT_HW_CACHE_OP_MAX]
82                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
83                  u32 raw_event_mask)
84 {
85         u64 config = event->attr.config;
86         int type = event->attr.type;
87
88         if (type == event->pmu->type)
89                 return armpmu_map_raw_event(raw_event_mask, config);
90
91         switch (type) {
92         case PERF_TYPE_HARDWARE:
93                 return armpmu_map_hw_event(event_map, config);
94         case PERF_TYPE_HW_CACHE:
95                 return armpmu_map_cache_event(cache_map, config);
96         case PERF_TYPE_RAW:
97                 return armpmu_map_raw_event(raw_event_mask, config);
98         }
99
100         return -ENOENT;
101 }
102
103 int armpmu_event_set_period(struct perf_event *event)
104 {
105         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
106         struct hw_perf_event *hwc = &event->hw;
107         s64 left = local64_read(&hwc->period_left);
108         s64 period = hwc->sample_period;
109         int ret = 0;
110
111         if (unlikely(left <= -period)) {
112                 left = period;
113                 local64_set(&hwc->period_left, left);
114                 hwc->last_period = period;
115                 ret = 1;
116         }
117
118         if (unlikely(left <= 0)) {
119                 left += period;
120                 local64_set(&hwc->period_left, left);
121                 hwc->last_period = period;
122                 ret = 1;
123         }
124
125         /*
126          * Limit the maximum period to prevent the counter value
127          * from overtaking the one we are about to program. In
128          * effect we are reducing max_period to account for
129          * interrupt latency (and we are being very conservative).
130          */
131         if (left > (armpmu->max_period >> 1))
132                 left = armpmu->max_period >> 1;
133
134         local64_set(&hwc->prev_count, (u64)-left);
135
136         armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
137
138         perf_event_update_userpage(event);
139
140         return ret;
141 }
142
143 u64 armpmu_event_update(struct perf_event *event)
144 {
145         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
146         struct hw_perf_event *hwc = &event->hw;
147         u64 delta, prev_raw_count, new_raw_count;
148
149 again:
150         prev_raw_count = local64_read(&hwc->prev_count);
151         new_raw_count = armpmu->read_counter(event);
152
153         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
154                              new_raw_count) != prev_raw_count)
155                 goto again;
156
157         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
158
159         local64_add(delta, &event->count);
160         local64_sub(delta, &hwc->period_left);
161
162         return new_raw_count;
163 }
164
165 static void
166 armpmu_read(struct perf_event *event)
167 {
168         armpmu_event_update(event);
169 }
170
171 static void
172 armpmu_stop(struct perf_event *event, int flags)
173 {
174         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
175         struct hw_perf_event *hwc = &event->hw;
176
177         /*
178          * ARM pmu always has to update the counter, so ignore
179          * PERF_EF_UPDATE, see comments in armpmu_start().
180          */
181         if (!(hwc->state & PERF_HES_STOPPED)) {
182                 armpmu->disable(event);
183                 armpmu_event_update(event);
184                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
185         }
186 }
187
188 static void armpmu_start(struct perf_event *event, int flags)
189 {
190         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
191         struct hw_perf_event *hwc = &event->hw;
192
193         /*
194          * ARM pmu always has to reprogram the period, so ignore
195          * PERF_EF_RELOAD, see the comment below.
196          */
197         if (flags & PERF_EF_RELOAD)
198                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
199
200         hwc->state = 0;
201         /*
202          * Set the period again. Some counters can't be stopped, so when we
203          * were stopped we simply disabled the IRQ source and the counter
204          * may have been left counting. If we don't do this step then we may
205          * get an interrupt too soon or *way* too late if the overflow has
206          * happened since disabling.
207          */
208         armpmu_event_set_period(event);
209         armpmu->enable(event);
210 }
211
212 static void
213 armpmu_del(struct perf_event *event, int flags)
214 {
215         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
216         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
217         struct hw_perf_event *hwc = &event->hw;
218         int idx = hwc->idx;
219
220         armpmu_stop(event, PERF_EF_UPDATE);
221         hw_events->events[idx] = NULL;
222         clear_bit(idx, hw_events->used_mask);
223         if (armpmu->clear_event_idx)
224                 armpmu->clear_event_idx(hw_events, event);
225
226         perf_event_update_userpage(event);
227 }
228
229 static int
230 armpmu_add(struct perf_event *event, int flags)
231 {
232         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
233         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
234         struct hw_perf_event *hwc = &event->hw;
235         int idx;
236         int err = 0;
237
238         /* An event following a process won't be stopped earlier */
239         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
240                 return -ENOENT;
241
242         perf_pmu_disable(event->pmu);
243
244         /* If we don't have a space for the counter then finish early. */
245         idx = armpmu->get_event_idx(hw_events, event);
246         if (idx < 0) {
247                 err = idx;
248                 goto out;
249         }
250
251         /*
252          * If there is an event in the counter we are going to use then make
253          * sure it is disabled.
254          */
255         event->hw.idx = idx;
256         armpmu->disable(event);
257         hw_events->events[idx] = event;
258
259         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
260         if (flags & PERF_EF_START)
261                 armpmu_start(event, PERF_EF_RELOAD);
262
263         /* Propagate our changes to the userspace mapping. */
264         perf_event_update_userpage(event);
265
266 out:
267         perf_pmu_enable(event->pmu);
268         return err;
269 }
270
271 static int
272 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
273                                struct perf_event *event)
274 {
275         struct arm_pmu *armpmu;
276
277         if (is_software_event(event))
278                 return 1;
279
280         /*
281          * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
282          * core perf code won't check that the pmu->ctx == leader->ctx
283          * until after pmu->event_init(event).
284          */
285         if (event->pmu != pmu)
286                 return 0;
287
288         if (event->state < PERF_EVENT_STATE_OFF)
289                 return 1;
290
291         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
292                 return 1;
293
294         armpmu = to_arm_pmu(event->pmu);
295         return armpmu->get_event_idx(hw_events, event) >= 0;
296 }
297
298 static int
299 validate_group(struct perf_event *event)
300 {
301         struct perf_event *sibling, *leader = event->group_leader;
302         struct pmu_hw_events fake_pmu;
303
304         /*
305          * Initialise the fake PMU. We only need to populate the
306          * used_mask for the purposes of validation.
307          */
308         memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
309
310         if (!validate_event(event->pmu, &fake_pmu, leader))
311                 return -EINVAL;
312
313         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
314                 if (!validate_event(event->pmu, &fake_pmu, sibling))
315                         return -EINVAL;
316         }
317
318         if (!validate_event(event->pmu, &fake_pmu, event))
319                 return -EINVAL;
320
321         return 0;
322 }
323
324 static struct arm_pmu_platdata *armpmu_get_platdata(struct arm_pmu *armpmu)
325 {
326         struct platform_device *pdev = armpmu->plat_device;
327
328         return pdev ? dev_get_platdata(&pdev->dev) : NULL;
329 }
330
331 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
332 {
333         struct arm_pmu *armpmu;
334         struct arm_pmu_platdata *plat;
335         int ret;
336         u64 start_clock, finish_clock;
337
338         /*
339          * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
340          * the handlers expect a struct arm_pmu*. The percpu_irq framework will
341          * do any necessary shifting, we just need to perform the first
342          * dereference.
343          */
344         armpmu = *(void **)dev;
345
346         plat = armpmu_get_platdata(armpmu);
347
348         start_clock = sched_clock();
349         if (plat && plat->handle_irq)
350                 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
351         else
352                 ret = armpmu->handle_irq(irq, armpmu);
353         finish_clock = sched_clock();
354
355         perf_sample_event_took(finish_clock - start_clock);
356         return ret;
357 }
358
359 static void
360 armpmu_release_hardware(struct arm_pmu *armpmu)
361 {
362         armpmu->free_irq(armpmu);
363 }
364
365 static int
366 armpmu_reserve_hardware(struct arm_pmu *armpmu)
367 {
368         int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
369         if (err) {
370                 armpmu_release_hardware(armpmu);
371                 return err;
372         }
373
374         return 0;
375 }
376
377 static void
378 hw_perf_event_destroy(struct perf_event *event)
379 {
380         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
381         atomic_t *active_events  = &armpmu->active_events;
382         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
383
384         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
385                 armpmu_release_hardware(armpmu);
386                 mutex_unlock(pmu_reserve_mutex);
387         }
388 }
389
390 static int
391 event_requires_mode_exclusion(struct perf_event_attr *attr)
392 {
393         return attr->exclude_idle || attr->exclude_user ||
394                attr->exclude_kernel || attr->exclude_hv;
395 }
396
397 static int
398 __hw_perf_event_init(struct perf_event *event)
399 {
400         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
401         struct hw_perf_event *hwc = &event->hw;
402         int mapping;
403
404         mapping = armpmu->map_event(event);
405
406         if (mapping < 0) {
407                 pr_debug("event %x:%llx not supported\n", event->attr.type,
408                          event->attr.config);
409                 return mapping;
410         }
411
412         /*
413          * We don't assign an index until we actually place the event onto
414          * hardware. Use -1 to signify that we haven't decided where to put it
415          * yet. For SMP systems, each core has it's own PMU so we can't do any
416          * clever allocation or constraints checking at this point.
417          */
418         hwc->idx                = -1;
419         hwc->config_base        = 0;
420         hwc->config             = 0;
421         hwc->event_base         = 0;
422
423         /*
424          * Check whether we need to exclude the counter from certain modes.
425          */
426         if ((!armpmu->set_event_filter ||
427              armpmu->set_event_filter(hwc, &event->attr)) &&
428              event_requires_mode_exclusion(&event->attr)) {
429                 pr_debug("ARM performance counters do not support "
430                          "mode exclusion\n");
431                 return -EOPNOTSUPP;
432         }
433
434         /*
435          * Store the event encoding into the config_base field.
436          */
437         hwc->config_base            |= (unsigned long)mapping;
438
439         if (!is_sampling_event(event)) {
440                 /*
441                  * For non-sampling runs, limit the sample_period to half
442                  * of the counter width. That way, the new counter value
443                  * is far less likely to overtake the previous one unless
444                  * you have some serious IRQ latency issues.
445                  */
446                 hwc->sample_period  = armpmu->max_period >> 1;
447                 hwc->last_period    = hwc->sample_period;
448                 local64_set(&hwc->period_left, hwc->sample_period);
449         }
450
451         if (event->group_leader != event) {
452                 if (validate_group(event) != 0)
453                         return -EINVAL;
454         }
455
456         return 0;
457 }
458
459 static int armpmu_event_init(struct perf_event *event)
460 {
461         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
462         int err = 0;
463         atomic_t *active_events = &armpmu->active_events;
464
465         /*
466          * Reject CPU-affine events for CPUs that are of a different class to
467          * that which this PMU handles. Process-following events (where
468          * event->cpu == -1) can be migrated between CPUs, and thus we have to
469          * reject them later (in armpmu_add) if they're scheduled on a
470          * different class of CPU.
471          */
472         if (event->cpu != -1 &&
473                 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
474                 return -ENOENT;
475
476         /* does not support taken branch sampling */
477         if (has_branch_stack(event))
478                 return -EOPNOTSUPP;
479
480         if (armpmu->map_event(event) == -ENOENT)
481                 return -ENOENT;
482
483         event->destroy = hw_perf_event_destroy;
484
485         if (!atomic_inc_not_zero(active_events)) {
486                 mutex_lock(&armpmu->reserve_mutex);
487                 if (atomic_read(active_events) == 0)
488                         err = armpmu_reserve_hardware(armpmu);
489
490                 if (!err)
491                         atomic_inc(active_events);
492                 mutex_unlock(&armpmu->reserve_mutex);
493         }
494
495         if (err)
496                 return err;
497
498         err = __hw_perf_event_init(event);
499         if (err)
500                 hw_perf_event_destroy(event);
501
502         return err;
503 }
504
505 static void armpmu_enable(struct pmu *pmu)
506 {
507         struct arm_pmu *armpmu = to_arm_pmu(pmu);
508         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
509         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
510
511         /* For task-bound events we may be called on other CPUs */
512         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
513                 return;
514
515         if (enabled)
516                 armpmu->start(armpmu);
517 }
518
519 static void armpmu_disable(struct pmu *pmu)
520 {
521         struct arm_pmu *armpmu = to_arm_pmu(pmu);
522
523         /* For task-bound events we may be called on other CPUs */
524         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
525                 return;
526
527         armpmu->stop(armpmu);
528 }
529
530 /*
531  * In heterogeneous systems, events are specific to a particular
532  * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
533  * the same microarchitecture.
534  */
535 static int armpmu_filter_match(struct perf_event *event)
536 {
537         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
538         unsigned int cpu = smp_processor_id();
539         return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
540 }
541
542 static void armpmu_init(struct arm_pmu *armpmu)
543 {
544         atomic_set(&armpmu->active_events, 0);
545         mutex_init(&armpmu->reserve_mutex);
546
547         armpmu->pmu = (struct pmu) {
548                 .pmu_enable     = armpmu_enable,
549                 .pmu_disable    = armpmu_disable,
550                 .event_init     = armpmu_event_init,
551                 .add            = armpmu_add,
552                 .del            = armpmu_del,
553                 .start          = armpmu_start,
554                 .stop           = armpmu_stop,
555                 .read           = armpmu_read,
556                 .filter_match   = armpmu_filter_match,
557         };
558 }
559
560 int armpmu_register(struct arm_pmu *armpmu, int type)
561 {
562         armpmu_init(armpmu);
563         pr_info("enabled with %s PMU driver, %d counters available\n",
564                         armpmu->name, armpmu->num_events);
565         return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
566 }
567
568 /* Set at runtime when we know what CPU type we are. */
569 static struct arm_pmu *__oprofile_cpu_pmu;
570
571 /*
572  * Despite the names, these two functions are CPU-specific and are used
573  * by the OProfile/perf code.
574  */
575 const char *perf_pmu_name(void)
576 {
577         if (!__oprofile_cpu_pmu)
578                 return NULL;
579
580         return __oprofile_cpu_pmu->name;
581 }
582 EXPORT_SYMBOL_GPL(perf_pmu_name);
583
584 int perf_num_counters(void)
585 {
586         int max_events = 0;
587
588         if (__oprofile_cpu_pmu != NULL)
589                 max_events = __oprofile_cpu_pmu->num_events;
590
591         return max_events;
592 }
593 EXPORT_SYMBOL_GPL(perf_num_counters);
594
595 static void cpu_pmu_enable_percpu_irq(void *data)
596 {
597         int irq = *(int *)data;
598
599         enable_percpu_irq(irq, IRQ_TYPE_NONE);
600 }
601
602 static void cpu_pmu_disable_percpu_irq(void *data)
603 {
604         int irq = *(int *)data;
605
606         disable_percpu_irq(irq);
607 }
608
609 static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
610 {
611         int i, irq, irqs;
612         struct platform_device *pmu_device = cpu_pmu->plat_device;
613         struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
614
615         irqs = min(pmu_device->num_resources, num_possible_cpus());
616
617         irq = platform_get_irq(pmu_device, 0);
618         if (irq >= 0 && irq_is_percpu(irq)) {
619                 on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1);
620                 free_percpu_irq(irq, &hw_events->percpu_pmu);
621         } else {
622                 for (i = 0; i < irqs; ++i) {
623                         int cpu = i;
624
625                         if (cpu_pmu->irq_affinity)
626                                 cpu = cpu_pmu->irq_affinity[i];
627
628                         if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
629                                 continue;
630                         irq = platform_get_irq(pmu_device, i);
631                         if (irq >= 0)
632                                 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
633                 }
634         }
635 }
636
637 static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
638 {
639         int i, err, irq, irqs;
640         struct platform_device *pmu_device = cpu_pmu->plat_device;
641         struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
642
643         if (!pmu_device)
644                 return -ENODEV;
645
646         irqs = min(pmu_device->num_resources, num_possible_cpus());
647         if (irqs < 1) {
648                 pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
649                 return 0;
650         }
651
652         irq = platform_get_irq(pmu_device, 0);
653         if (irq >= 0 && irq_is_percpu(irq)) {
654                 err = request_percpu_irq(irq, handler, "arm-pmu",
655                                          &hw_events->percpu_pmu);
656                 if (err) {
657                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
658                                 irq);
659                         return err;
660                 }
661                 on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1);
662         } else {
663                 for (i = 0; i < irqs; ++i) {
664                         int cpu = i;
665
666                         err = 0;
667                         irq = platform_get_irq(pmu_device, i);
668                         if (irq < 0)
669                                 continue;
670
671                         if (cpu_pmu->irq_affinity)
672                                 cpu = cpu_pmu->irq_affinity[i];
673
674                         /*
675                          * If we have a single PMU interrupt that we can't shift,
676                          * assume that we're running on a uniprocessor machine and
677                          * continue. Otherwise, continue without this interrupt.
678                          */
679                         if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
680                                 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
681                                         irq, cpu);
682                                 continue;
683                         }
684
685                         err = request_irq(irq, handler,
686                                           IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
687                                           per_cpu_ptr(&hw_events->percpu_pmu, cpu));
688                         if (err) {
689                                 pr_err("unable to request IRQ%d for ARM PMU counters\n",
690                                         irq);
691                                 return err;
692                         }
693
694                         cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
695                 }
696         }
697
698         return 0;
699 }
700
701 /*
702  * PMU hardware loses all context when a CPU goes offline.
703  * When a CPU is hotplugged back in, since some hardware registers are
704  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
705  * junk values out of them.
706  */
707 static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
708                           void *hcpu)
709 {
710         int cpu = (unsigned long)hcpu;
711         struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb);
712
713         if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
714                 return NOTIFY_DONE;
715
716         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
717                 return NOTIFY_DONE;
718
719         if (pmu->reset)
720                 pmu->reset(pmu);
721         else
722                 return NOTIFY_DONE;
723
724         return NOTIFY_OK;
725 }
726
727 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
728 {
729         int err;
730         int cpu;
731         struct pmu_hw_events __percpu *cpu_hw_events;
732
733         cpu_hw_events = alloc_percpu(struct pmu_hw_events);
734         if (!cpu_hw_events)
735                 return -ENOMEM;
736
737         cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify;
738         err = register_cpu_notifier(&cpu_pmu->hotplug_nb);
739         if (err)
740                 goto out_hw_events;
741
742         for_each_possible_cpu(cpu) {
743                 struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
744                 raw_spin_lock_init(&events->pmu_lock);
745                 events->percpu_pmu = cpu_pmu;
746         }
747
748         cpu_pmu->hw_events      = cpu_hw_events;
749         cpu_pmu->request_irq    = cpu_pmu_request_irq;
750         cpu_pmu->free_irq       = cpu_pmu_free_irq;
751
752         /* Ensure the PMU has sane values out of reset. */
753         if (cpu_pmu->reset)
754                 on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset,
755                          cpu_pmu, 1);
756
757         /* If no interrupts available, set the corresponding capability flag */
758         if (!platform_get_irq(cpu_pmu->plat_device, 0))
759                 cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
760
761         return 0;
762
763 out_hw_events:
764         free_percpu(cpu_hw_events);
765         return err;
766 }
767
768 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
769 {
770         unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
771         free_percpu(cpu_pmu->hw_events);
772 }
773
774 /*
775  * CPU PMU identification and probing.
776  */
777 static int probe_current_pmu(struct arm_pmu *pmu,
778                              const struct pmu_probe_info *info)
779 {
780         int cpu = get_cpu();
781         unsigned int cpuid = read_cpuid_id();
782         int ret = -ENODEV;
783
784         pr_info("probing PMU on CPU %d\n", cpu);
785
786         for (; info->init != NULL; info++) {
787                 if ((cpuid & info->mask) != info->cpuid)
788                         continue;
789                 ret = info->init(pmu);
790                 break;
791         }
792
793         put_cpu();
794         return ret;
795 }
796
797 static int of_pmu_irq_cfg(struct arm_pmu *pmu)
798 {
799         int *irqs, i = 0;
800         bool using_spi = false;
801         struct platform_device *pdev = pmu->plat_device;
802
803         irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
804         if (!irqs)
805                 return -ENOMEM;
806
807         do {
808                 struct device_node *dn;
809                 int cpu, irq;
810
811                 /* See if we have an affinity entry */
812                 dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", i);
813                 if (!dn)
814                         break;
815
816                 /* Check the IRQ type and prohibit a mix of PPIs and SPIs */
817                 irq = platform_get_irq(pdev, i);
818                 if (irq >= 0) {
819                         bool spi = !irq_is_percpu(irq);
820
821                         if (i > 0 && spi != using_spi) {
822                                 pr_err("PPI/SPI IRQ type mismatch for %s!\n",
823                                         dn->name);
824                                 of_node_put(dn);
825                                 kfree(irqs);
826                                 return -EINVAL;
827                         }
828
829                         using_spi = spi;
830                 }
831
832                 /* Now look up the logical CPU number */
833                 for_each_possible_cpu(cpu) {
834                         struct device_node *cpu_dn;
835
836                         cpu_dn = of_cpu_device_node_get(cpu);
837                         of_node_put(cpu_dn);
838
839                         if (dn == cpu_dn)
840                                 break;
841                 }
842
843                 if (cpu >= nr_cpu_ids) {
844                         pr_warn("Failed to find logical CPU for %s\n",
845                                 dn->name);
846                         of_node_put(dn);
847                         cpumask_setall(&pmu->supported_cpus);
848                         break;
849                 }
850                 of_node_put(dn);
851
852                 /* For SPIs, we need to track the affinity per IRQ */
853                 if (using_spi) {
854                         if (i >= pdev->num_resources) {
855                                 of_node_put(dn);
856                                 break;
857                         }
858
859                         irqs[i] = cpu;
860                 }
861
862                 /* Keep track of the CPUs containing this PMU type */
863                 cpumask_set_cpu(cpu, &pmu->supported_cpus);
864                 of_node_put(dn);
865                 i++;
866         } while (1);
867
868         /* If we didn't manage to parse anything, claim to support all CPUs */
869         if (cpumask_weight(&pmu->supported_cpus) == 0)
870                 cpumask_setall(&pmu->supported_cpus);
871
872         /* If we matched up the IRQ affinities, use them to route the SPIs */
873         if (using_spi && i == pdev->num_resources)
874                 pmu->irq_affinity = irqs;
875         else
876                 kfree(irqs);
877
878         return 0;
879 }
880
881 int arm_pmu_device_probe(struct platform_device *pdev,
882                          const struct of_device_id *of_table,
883                          const struct pmu_probe_info *probe_table)
884 {
885         const struct of_device_id *of_id;
886         const int (*init_fn)(struct arm_pmu *);
887         struct device_node *node = pdev->dev.of_node;
888         struct arm_pmu *pmu;
889         int ret = -ENODEV;
890
891         pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
892         if (!pmu) {
893                 pr_info("failed to allocate PMU device!\n");
894                 return -ENOMEM;
895         }
896
897         if (!__oprofile_cpu_pmu)
898                 __oprofile_cpu_pmu = pmu;
899
900         pmu->plat_device = pdev;
901
902         if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
903                 init_fn = of_id->data;
904
905                 ret = of_pmu_irq_cfg(pmu);
906                 if (!ret)
907                         ret = init_fn(pmu);
908         } else {
909                 ret = probe_current_pmu(pmu, probe_table);
910                 cpumask_setall(&pmu->supported_cpus);
911         }
912
913         if (ret) {
914                 pr_info("failed to probe PMU!\n");
915                 goto out_free;
916         }
917
918         ret = cpu_pmu_init(pmu);
919         if (ret)
920                 goto out_free;
921
922         ret = armpmu_register(pmu, -1);
923         if (ret)
924                 goto out_destroy;
925
926         return 0;
927
928 out_destroy:
929         cpu_pmu_destroy(pmu);
930 out_free:
931         pr_info("failed to register PMU devices!\n");
932         kfree(pmu);
933         return ret;
934 }