4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
12 #define pr_fmt(fmt) "hw perfevents: " fmt
14 #include <linux/bitmap.h>
15 #include <linux/cpumask.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/export.h>
18 #include <linux/kernel.h>
19 #include <linux/perf/arm_pmu.h>
20 #include <linux/slab.h>
21 #include <linux/sched/clock.h>
22 #include <linux/spinlock.h>
23 #include <linux/irq.h>
24 #include <linux/irqdesc.h>
26 #include <asm/irq_regs.h>
28 static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
29 static DEFINE_PER_CPU(int, cpu_irq);
31 static inline u64 arm_pmu_event_max_period(struct perf_event *event)
33 if (event->hw.flags & ARMPMU_EVT_64BIT)
34 return GENMASK_ULL(63, 0);
36 return GENMASK_ULL(31, 0);
40 armpmu_map_cache_event(const unsigned (*cache_map)
41 [PERF_COUNT_HW_CACHE_MAX]
42 [PERF_COUNT_HW_CACHE_OP_MAX]
43 [PERF_COUNT_HW_CACHE_RESULT_MAX],
46 unsigned int cache_type, cache_op, cache_result, ret;
48 cache_type = (config >> 0) & 0xff;
49 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
52 cache_op = (config >> 8) & 0xff;
53 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
56 cache_result = (config >> 16) & 0xff;
57 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
63 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
65 if (ret == CACHE_OP_UNSUPPORTED)
72 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
76 if (config >= PERF_COUNT_HW_MAX)
82 mapping = (*event_map)[config];
83 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
87 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
89 return (int)(config & raw_event_mask);
93 armpmu_map_event(struct perf_event *event,
94 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
95 const unsigned (*cache_map)
96 [PERF_COUNT_HW_CACHE_MAX]
97 [PERF_COUNT_HW_CACHE_OP_MAX]
98 [PERF_COUNT_HW_CACHE_RESULT_MAX],
101 u64 config = event->attr.config;
102 int type = event->attr.type;
104 if (type == event->pmu->type)
105 return armpmu_map_raw_event(raw_event_mask, config);
108 case PERF_TYPE_HARDWARE:
109 return armpmu_map_hw_event(event_map, config);
110 case PERF_TYPE_HW_CACHE:
111 return armpmu_map_cache_event(cache_map, config);
113 return armpmu_map_raw_event(raw_event_mask, config);
119 int armpmu_event_set_period(struct perf_event *event)
121 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
122 struct hw_perf_event *hwc = &event->hw;
123 s64 left = local64_read(&hwc->period_left);
124 s64 period = hwc->sample_period;
128 max_period = arm_pmu_event_max_period(event);
129 if (unlikely(left <= -period)) {
131 local64_set(&hwc->period_left, left);
132 hwc->last_period = period;
136 if (unlikely(left <= 0)) {
138 local64_set(&hwc->period_left, left);
139 hwc->last_period = period;
144 * Limit the maximum period to prevent the counter value
145 * from overtaking the one we are about to program. In
146 * effect we are reducing max_period to account for
147 * interrupt latency (and we are being very conservative).
149 if (left > (max_period >> 1))
150 left = (max_period >> 1);
152 local64_set(&hwc->prev_count, (u64)-left);
154 armpmu->write_counter(event, (u64)(-left) & max_period);
156 perf_event_update_userpage(event);
161 u64 armpmu_event_update(struct perf_event *event)
163 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
164 struct hw_perf_event *hwc = &event->hw;
165 u64 delta, prev_raw_count, new_raw_count;
166 u64 max_period = arm_pmu_event_max_period(event);
169 prev_raw_count = local64_read(&hwc->prev_count);
170 new_raw_count = armpmu->read_counter(event);
172 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
173 new_raw_count) != prev_raw_count)
176 delta = (new_raw_count - prev_raw_count) & max_period;
178 local64_add(delta, &event->count);
179 local64_sub(delta, &hwc->period_left);
181 return new_raw_count;
185 armpmu_read(struct perf_event *event)
187 armpmu_event_update(event);
191 armpmu_stop(struct perf_event *event, int flags)
193 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
194 struct hw_perf_event *hwc = &event->hw;
197 * ARM pmu always has to update the counter, so ignore
198 * PERF_EF_UPDATE, see comments in armpmu_start().
200 if (!(hwc->state & PERF_HES_STOPPED)) {
201 armpmu->disable(event);
202 armpmu_event_update(event);
203 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
207 static void armpmu_start(struct perf_event *event, int flags)
209 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
210 struct hw_perf_event *hwc = &event->hw;
213 * ARM pmu always has to reprogram the period, so ignore
214 * PERF_EF_RELOAD, see the comment below.
216 if (flags & PERF_EF_RELOAD)
217 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
221 * Set the period again. Some counters can't be stopped, so when we
222 * were stopped we simply disabled the IRQ source and the counter
223 * may have been left counting. If we don't do this step then we may
224 * get an interrupt too soon or *way* too late if the overflow has
225 * happened since disabling.
227 armpmu_event_set_period(event);
228 armpmu->enable(event);
232 armpmu_del(struct perf_event *event, int flags)
234 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
235 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
236 struct hw_perf_event *hwc = &event->hw;
239 armpmu_stop(event, PERF_EF_UPDATE);
240 hw_events->events[idx] = NULL;
241 armpmu->clear_event_idx(hw_events, event);
242 perf_event_update_userpage(event);
243 /* Clear the allocated counter */
248 armpmu_add(struct perf_event *event, int flags)
250 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
251 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
252 struct hw_perf_event *hwc = &event->hw;
255 /* An event following a process won't be stopped earlier */
256 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
259 /* If we don't have a space for the counter then finish early. */
260 idx = armpmu->get_event_idx(hw_events, event);
265 * If there is an event in the counter we are going to use then make
266 * sure it is disabled.
269 armpmu->disable(event);
270 hw_events->events[idx] = event;
272 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
273 if (flags & PERF_EF_START)
274 armpmu_start(event, PERF_EF_RELOAD);
276 /* Propagate our changes to the userspace mapping. */
277 perf_event_update_userpage(event);
283 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
284 struct perf_event *event)
286 struct arm_pmu *armpmu;
288 if (is_software_event(event))
292 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
293 * core perf code won't check that the pmu->ctx == leader->ctx
294 * until after pmu->event_init(event).
296 if (event->pmu != pmu)
299 if (event->state < PERF_EVENT_STATE_OFF)
302 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
305 armpmu = to_arm_pmu(event->pmu);
306 return armpmu->get_event_idx(hw_events, event) >= 0;
310 validate_group(struct perf_event *event)
312 struct perf_event *sibling, *leader = event->group_leader;
313 struct pmu_hw_events fake_pmu;
316 * Initialise the fake PMU. We only need to populate the
317 * used_mask for the purposes of validation.
319 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
321 if (!validate_event(event->pmu, &fake_pmu, leader))
327 for_each_sibling_event(sibling, leader) {
328 if (!validate_event(event->pmu, &fake_pmu, sibling))
332 if (!validate_event(event->pmu, &fake_pmu, event))
338 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
340 struct arm_pmu *armpmu;
342 u64 start_clock, finish_clock;
345 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
346 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
347 * do any necessary shifting, we just need to perform the first
350 armpmu = *(void **)dev;
351 if (WARN_ON_ONCE(!armpmu))
354 start_clock = sched_clock();
355 ret = armpmu->handle_irq(armpmu);
356 finish_clock = sched_clock();
358 perf_sample_event_took(finish_clock - start_clock);
363 event_requires_mode_exclusion(struct perf_event_attr *attr)
365 return attr->exclude_idle || attr->exclude_user ||
366 attr->exclude_kernel || attr->exclude_hv;
370 __hw_perf_event_init(struct perf_event *event)
372 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
373 struct hw_perf_event *hwc = &event->hw;
377 mapping = armpmu->map_event(event);
380 pr_debug("event %x:%llx not supported\n", event->attr.type,
386 * We don't assign an index until we actually place the event onto
387 * hardware. Use -1 to signify that we haven't decided where to put it
388 * yet. For SMP systems, each core has it's own PMU so we can't do any
389 * clever allocation or constraints checking at this point.
392 hwc->config_base = 0;
397 * Check whether we need to exclude the counter from certain modes.
399 if ((!armpmu->set_event_filter ||
400 armpmu->set_event_filter(hwc, &event->attr)) &&
401 event_requires_mode_exclusion(&event->attr)) {
402 pr_debug("ARM performance counters do not support "
408 * Store the event encoding into the config_base field.
410 hwc->config_base |= (unsigned long)mapping;
412 if (!is_sampling_event(event)) {
414 * For non-sampling runs, limit the sample_period to half
415 * of the counter width. That way, the new counter value
416 * is far less likely to overtake the previous one unless
417 * you have some serious IRQ latency issues.
419 hwc->sample_period = arm_pmu_event_max_period(event) >> 1;
420 hwc->last_period = hwc->sample_period;
421 local64_set(&hwc->period_left, hwc->sample_period);
424 return validate_group(event);
427 static int armpmu_event_init(struct perf_event *event)
429 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
432 * Reject CPU-affine events for CPUs that are of a different class to
433 * that which this PMU handles. Process-following events (where
434 * event->cpu == -1) can be migrated between CPUs, and thus we have to
435 * reject them later (in armpmu_add) if they're scheduled on a
436 * different class of CPU.
438 if (event->cpu != -1 &&
439 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
442 /* does not support taken branch sampling */
443 if (has_branch_stack(event))
446 if (armpmu->map_event(event) == -ENOENT)
449 return __hw_perf_event_init(event);
452 static void armpmu_enable(struct pmu *pmu)
454 struct arm_pmu *armpmu = to_arm_pmu(pmu);
455 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
456 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
458 /* For task-bound events we may be called on other CPUs */
459 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
463 armpmu->start(armpmu);
466 static void armpmu_disable(struct pmu *pmu)
468 struct arm_pmu *armpmu = to_arm_pmu(pmu);
470 /* For task-bound events we may be called on other CPUs */
471 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
474 armpmu->stop(armpmu);
478 * In heterogeneous systems, events are specific to a particular
479 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
480 * the same microarchitecture.
482 static int armpmu_filter_match(struct perf_event *event)
484 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
485 unsigned int cpu = smp_processor_id();
488 ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus);
489 if (ret && armpmu->filter_match)
490 return armpmu->filter_match(event);
495 static ssize_t armpmu_cpumask_show(struct device *dev,
496 struct device_attribute *attr, char *buf)
498 struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
499 return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
502 static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
504 static struct attribute *armpmu_common_attrs[] = {
509 static struct attribute_group armpmu_common_attr_group = {
510 .attrs = armpmu_common_attrs,
513 /* Set at runtime when we know what CPU type we are. */
514 static struct arm_pmu *__oprofile_cpu_pmu;
517 * Despite the names, these two functions are CPU-specific and are used
518 * by the OProfile/perf code.
520 const char *perf_pmu_name(void)
522 if (!__oprofile_cpu_pmu)
525 return __oprofile_cpu_pmu->name;
527 EXPORT_SYMBOL_GPL(perf_pmu_name);
529 int perf_num_counters(void)
533 if (__oprofile_cpu_pmu != NULL)
534 max_events = __oprofile_cpu_pmu->num_events;
538 EXPORT_SYMBOL_GPL(perf_num_counters);
540 static int armpmu_count_irq_users(const int irq)
544 for_each_possible_cpu(cpu) {
545 if (per_cpu(cpu_irq, cpu) == irq)
552 void armpmu_free_irq(int irq, int cpu)
554 if (per_cpu(cpu_irq, cpu) == 0)
556 if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
559 if (!irq_is_percpu_devid(irq))
560 free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
561 else if (armpmu_count_irq_users(irq) == 1)
562 free_percpu_irq(irq, &cpu_armpmu);
564 per_cpu(cpu_irq, cpu) = 0;
567 int armpmu_request_irq(int irq, int cpu)
570 const irq_handler_t handler = armpmu_dispatch_irq;
574 if (!irq_is_percpu_devid(irq)) {
575 unsigned long irq_flags;
577 err = irq_force_affinity(irq, cpumask_of(cpu));
579 if (err && num_possible_cpus() > 1) {
580 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
585 irq_flags = IRQF_PERCPU |
589 irq_set_status_flags(irq, IRQ_NOAUTOEN);
590 err = request_irq(irq, handler, irq_flags, "arm-pmu",
591 per_cpu_ptr(&cpu_armpmu, cpu));
592 } else if (armpmu_count_irq_users(irq) == 0) {
593 err = request_percpu_irq(irq, handler, "arm-pmu",
600 per_cpu(cpu_irq, cpu) = irq;
604 pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
608 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
610 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
611 return per_cpu(hw_events->irq, cpu);
615 * PMU hardware loses all context when a CPU goes offline.
616 * When a CPU is hotplugged back in, since some hardware registers are
617 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
618 * junk values out of them.
620 static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
622 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
625 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
630 per_cpu(cpu_armpmu, cpu) = pmu;
632 irq = armpmu_get_cpu_irq(pmu, cpu);
634 if (irq_is_percpu_devid(irq))
635 enable_percpu_irq(irq, IRQ_TYPE_NONE);
643 static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
645 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
648 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
651 irq = armpmu_get_cpu_irq(pmu, cpu);
653 if (irq_is_percpu_devid(irq))
654 disable_percpu_irq(irq);
656 disable_irq_nosync(irq);
659 per_cpu(cpu_armpmu, cpu) = NULL;
665 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
667 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
668 struct perf_event *event;
671 for (idx = 0; idx < armpmu->num_events; idx++) {
672 event = hw_events->events[idx];
679 * Stop and update the counter
681 armpmu_stop(event, PERF_EF_UPDATE);
684 case CPU_PM_ENTER_FAILED:
686 * Restore and enable the counter.
687 * armpmu_start() indirectly calls
689 * perf_event_update_userpage()
691 * that requires RCU read locking to be functional,
692 * wrap the call within RCU_NONIDLE to make the
693 * RCU subsystem aware this cpu is not idle from
694 * an RCU perspective for the armpmu_start() call
697 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
705 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
708 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
709 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
710 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
712 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
716 * Always reset the PMU registers on power-up even if
717 * there are no events running.
719 if (cmd == CPU_PM_EXIT && armpmu->reset)
720 armpmu->reset(armpmu);
727 armpmu->stop(armpmu);
728 cpu_pm_pmu_setup(armpmu, cmd);
731 case CPU_PM_ENTER_FAILED:
732 cpu_pm_pmu_setup(armpmu, cmd);
733 armpmu->start(armpmu);
742 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
744 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
745 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
748 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
750 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
753 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
754 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
757 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
761 err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
766 err = cpu_pm_pmu_register(cpu_pmu);
773 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
779 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
781 cpu_pm_pmu_unregister(cpu_pmu);
782 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
786 static struct arm_pmu *__armpmu_alloc(gfp_t flags)
791 pmu = kzalloc(sizeof(*pmu), flags);
793 pr_info("failed to allocate PMU device!\n");
797 pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
798 if (!pmu->hw_events) {
799 pr_info("failed to allocate per-cpu PMU data.\n");
803 pmu->pmu = (struct pmu) {
804 .pmu_enable = armpmu_enable,
805 .pmu_disable = armpmu_disable,
806 .event_init = armpmu_event_init,
809 .start = armpmu_start,
812 .filter_match = armpmu_filter_match,
813 .attr_groups = pmu->attr_groups,
815 * This is a CPU PMU potentially in a heterogeneous
816 * configuration (e.g. big.LITTLE). This is not an uncore PMU,
817 * and we have taken ctx sharing into account (e.g. with our
818 * pmu::filter_match callback and pmu::event_init group
821 .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
824 pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
825 &armpmu_common_attr_group;
827 for_each_possible_cpu(cpu) {
828 struct pmu_hw_events *events;
830 events = per_cpu_ptr(pmu->hw_events, cpu);
831 raw_spin_lock_init(&events->pmu_lock);
832 events->percpu_pmu = pmu;
843 struct arm_pmu *armpmu_alloc(void)
845 return __armpmu_alloc(GFP_KERNEL);
848 struct arm_pmu *armpmu_alloc_atomic(void)
850 return __armpmu_alloc(GFP_ATOMIC);
854 void armpmu_free(struct arm_pmu *pmu)
856 free_percpu(pmu->hw_events);
860 int armpmu_register(struct arm_pmu *pmu)
864 ret = cpu_pmu_init(pmu);
868 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
872 if (!__oprofile_cpu_pmu)
873 __oprofile_cpu_pmu = pmu;
875 pr_info("enabled with %s PMU driver, %d counters available\n",
876 pmu->name, pmu->num_events);
881 cpu_pmu_destroy(pmu);
885 static int arm_pmu_hp_init(void)
889 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
890 "perf/arm/pmu:starting",
891 arm_perf_starting_cpu,
892 arm_perf_teardown_cpu);
894 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
898 subsys_initcall(arm_pmu_hp_init);