1 // SPDX-License-Identifier: GPL-2.0
3 * Support routines for initializing a PCI subsystem
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/cache.h>
22 #include <linux/slab.h>
25 static void pci_std_update_resource(struct pci_dev *dev, int resno)
27 struct pci_bus_region region;
32 struct resource *res = dev->resource + resno;
34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
39 * Ignore resources for unimplemented BARs and unused resource slots
45 if (res->flags & IORESOURCE_UNSET)
49 * Ignore non-moveable resources. This might be legacy resources for
50 * which no functional BAR register exists or another important
51 * system resource we shouldn't move around.
53 if (res->flags & IORESOURCE_PCI_FIXED)
56 pcibios_resource_to_bus(dev->bus, ®ion, res);
59 if (res->flags & IORESOURCE_IO) {
60 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
61 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
62 } else if (resno == PCI_ROM_RESOURCE) {
63 mask = PCI_ROM_ADDRESS_MASK;
65 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
66 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
69 if (resno < PCI_ROM_RESOURCE) {
70 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
71 } else if (resno == PCI_ROM_RESOURCE) {
74 * Apparently some Matrox devices have ROM BARs that read
75 * as zero when disabled, so don't update ROM BARs unless
76 * they're enabled. See https://lkml.org/lkml/2005/8/30/138.
78 if (!(res->flags & IORESOURCE_ROM_ENABLE))
81 reg = dev->rom_base_reg;
82 new |= PCI_ROM_ADDRESS_ENABLE;
87 * We can't update a 64-bit BAR atomically, so when possible,
88 * disable decoding so that a half-updated BAR won't conflict
89 * with another device.
91 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
93 pci_read_config_word(dev, PCI_COMMAND, &cmd);
94 pci_write_config_word(dev, PCI_COMMAND,
95 cmd & ~PCI_COMMAND_MEMORY);
98 pci_write_config_dword(dev, reg, new);
99 pci_read_config_dword(dev, reg, &check);
101 if ((new ^ check) & mask) {
102 pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
106 if (res->flags & IORESOURCE_MEM_64) {
107 new = region.start >> 16 >> 16;
108 pci_write_config_dword(dev, reg + 4, new);
109 pci_read_config_dword(dev, reg + 4, &check);
111 pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
117 pci_write_config_word(dev, PCI_COMMAND, cmd);
120 void pci_update_resource(struct pci_dev *dev, int resno)
122 if (resno <= PCI_ROM_RESOURCE)
123 pci_std_update_resource(dev, resno);
124 #ifdef CONFIG_PCI_IOV
125 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
126 pci_iov_update_resource(dev, resno);
130 int pci_claim_resource(struct pci_dev *dev, int resource)
132 struct resource *res = &dev->resource[resource];
133 struct resource *root, *conflict;
135 if (res->flags & IORESOURCE_UNSET) {
136 pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
142 * If we have a shadow copy in RAM, the PCI device doesn't respond
143 * to the shadow range, so we don't need to claim it, and upstream
144 * bridges don't need to route the range to the device.
146 if (res->flags & IORESOURCE_ROM_SHADOW)
149 root = pci_find_parent_resource(dev, res);
151 pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
153 res->flags |= IORESOURCE_UNSET;
157 conflict = request_resource_conflict(root, res);
159 pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
160 resource, res, conflict->name, conflict);
161 res->flags |= IORESOURCE_UNSET;
167 EXPORT_SYMBOL(pci_claim_resource);
169 void pci_disable_bridge_window(struct pci_dev *dev)
171 /* MMIO Base/Limit */
172 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
174 /* Prefetchable MMIO Base/Limit */
175 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
176 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
177 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
181 * Generic function that returns a value indicating that the device's
182 * original BIOS BAR address was not saved and so is not available for
185 * Can be over-ridden by architecture specific code that implements
186 * reinstatement functionality rather than leaving it disabled when
187 * normal allocation attempts fail.
189 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
194 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
195 int resno, resource_size_t size)
197 struct resource *root, *conflict;
198 resource_size_t fw_addr, start, end;
200 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
206 res->start = fw_addr;
207 res->end = res->start + size - 1;
208 res->flags &= ~IORESOURCE_UNSET;
210 root = pci_find_parent_resource(dev, res);
213 * If dev is behind a bridge, accesses will only reach it
214 * if res is inside the relevant bridge window.
216 if (pci_upstream_bridge(dev))
220 * On the root bus, assume the host bridge will forward
223 if (res->flags & IORESOURCE_IO)
224 root = &ioport_resource;
226 root = &iomem_resource;
229 pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
231 conflict = request_resource_conflict(root, res);
233 pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
234 resno, res, conflict->name, conflict);
237 res->flags |= IORESOURCE_UNSET;
244 * We don't have to worry about legacy ISA devices, so nothing to do here.
245 * This is marked as __weak because multiple architectures define it; it should
246 * eventually go away.
248 resource_size_t __weak pcibios_align_resource(void *data,
249 const struct resource *res,
250 resource_size_t size,
251 resource_size_t align)
256 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
257 int resno, resource_size_t size, resource_size_t align)
259 struct resource *res = dev->resource + resno;
263 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
266 * First, try exact prefetching match. Even if a 64-bit
267 * prefetchable bridge window is below 4GB, we can't put a 32-bit
268 * prefetchable resource in it because pbus_size_mem() assumes a
269 * 64-bit window will contain no 32-bit resources. If we assign
270 * things differently than they were sized, not everything will fit.
272 ret = pci_bus_alloc_resource(bus, res, size, align, min,
273 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
274 pcibios_align_resource, dev);
279 * If the prefetchable window is only 32 bits wide, we can put
280 * 64-bit prefetchable resources in it.
282 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
283 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
284 ret = pci_bus_alloc_resource(bus, res, size, align, min,
286 pcibios_align_resource, dev);
292 * If we didn't find a better match, we can put any memory resource
293 * in a non-prefetchable window. If this resource is 32 bits and
294 * non-prefetchable, the first call already tried the only possibility
295 * so we don't need to try again.
297 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
298 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
299 pcibios_align_resource, dev);
304 static int _pci_assign_resource(struct pci_dev *dev, int resno,
305 resource_size_t size, resource_size_t min_align)
311 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
312 if (!bus->parent || !bus->self->transparent)
320 int pci_assign_resource(struct pci_dev *dev, int resno)
322 struct resource *res = dev->resource + resno;
323 resource_size_t align, size;
326 if (res->flags & IORESOURCE_PCI_FIXED)
329 res->flags |= IORESOURCE_UNSET;
330 align = pci_resource_alignment(dev, res);
332 pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
337 size = resource_size(res);
338 ret = _pci_assign_resource(dev, resno, size, align);
341 * If we failed to assign anything, let's try the address
342 * where firmware left it. That at least has a chance of
343 * working, which is better than just leaving it disabled.
346 pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
347 ret = pci_revert_fw_address(res, dev, resno, size);
351 pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
355 res->flags &= ~IORESOURCE_UNSET;
356 res->flags &= ~IORESOURCE_STARTALIGN;
357 pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
358 if (resno < PCI_BRIDGE_RESOURCES)
359 pci_update_resource(dev, resno);
363 EXPORT_SYMBOL(pci_assign_resource);
365 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
366 resource_size_t min_align)
368 struct resource *res = dev->resource + resno;
370 resource_size_t new_size;
373 if (res->flags & IORESOURCE_PCI_FIXED)
377 res->flags |= IORESOURCE_UNSET;
379 pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
384 /* already aligned with min_align */
385 new_size = resource_size(res) + addsize;
386 ret = _pci_assign_resource(dev, resno, new_size, min_align);
389 pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
390 resno, res, (unsigned long long) addsize);
394 res->flags &= ~IORESOURCE_UNSET;
395 res->flags &= ~IORESOURCE_STARTALIGN;
396 pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
397 resno, res, (unsigned long long) addsize);
398 if (resno < PCI_BRIDGE_RESOURCES)
399 pci_update_resource(dev, resno);
404 void pci_release_resource(struct pci_dev *dev, int resno)
406 struct resource *res = dev->resource + resno;
408 pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
413 release_resource(res);
414 res->end = resource_size(res) - 1;
416 res->flags |= IORESOURCE_UNSET;
418 EXPORT_SYMBOL(pci_release_resource);
420 int pci_resize_resource(struct pci_dev *dev, int resno, int size)
422 struct resource *res = dev->resource + resno;
423 struct pci_host_bridge *host;
428 /* Check if we must preserve the firmware's resource assignment */
429 host = pci_find_host_bridge(dev->bus);
430 if (host->preserve_config)
433 /* Make sure the resource isn't assigned before resizing it. */
434 if (!(res->flags & IORESOURCE_UNSET))
437 pci_read_config_word(dev, PCI_COMMAND, &cmd);
438 if (cmd & PCI_COMMAND_MEMORY)
441 sizes = pci_rebar_get_possible_sizes(dev, resno);
445 if (!(sizes & BIT(size)))
448 old = pci_rebar_get_current_size(dev, resno);
452 ret = pci_rebar_set_size(dev, resno, size);
456 res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
458 /* Check if the new config works by trying to assign everything. */
459 if (dev->bus->self) {
460 ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
467 pci_rebar_set_size(dev, resno, old);
468 res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
471 EXPORT_SYMBOL(pci_resize_resource);
473 int pci_enable_resources(struct pci_dev *dev, int mask)
479 pci_read_config_word(dev, PCI_COMMAND, &cmd);
482 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
483 if (!(mask & (1 << i)))
486 r = &dev->resource[i];
488 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
490 if ((i == PCI_ROM_RESOURCE) &&
491 (!(r->flags & IORESOURCE_ROM_ENABLE)))
494 if (r->flags & IORESOURCE_UNSET) {
495 pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
501 pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
506 if (r->flags & IORESOURCE_IO)
507 cmd |= PCI_COMMAND_IO;
508 if (r->flags & IORESOURCE_MEM)
509 cmd |= PCI_COMMAND_MEMORY;
512 if (cmd != old_cmd) {
513 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
514 pci_write_config_word(dev, PCI_COMMAND, cmd);