1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/pci/setup-res.c
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
10 * Support routines for initializing a PCI subsystem.
13 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
16 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
20 #include <linux/kernel.h>
21 #include <linux/export.h>
22 #include <linux/pci.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/cache.h>
26 #include <linux/slab.h>
29 static void pci_std_update_resource(struct pci_dev *dev, int resno)
31 struct pci_bus_region region;
36 struct resource *res = dev->resource + resno;
38 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
43 * Ignore resources for unimplemented BARs and unused resource slots
49 if (res->flags & IORESOURCE_UNSET)
53 * Ignore non-moveable resources. This might be legacy resources for
54 * which no functional BAR register exists or another important
55 * system resource we shouldn't move around.
57 if (res->flags & IORESOURCE_PCI_FIXED)
60 pcibios_resource_to_bus(dev->bus, ®ion, res);
63 if (res->flags & IORESOURCE_IO) {
64 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
65 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
66 } else if (resno == PCI_ROM_RESOURCE) {
67 mask = PCI_ROM_ADDRESS_MASK;
69 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
70 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
73 if (resno < PCI_ROM_RESOURCE) {
74 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
75 } else if (resno == PCI_ROM_RESOURCE) {
78 * Apparently some Matrox devices have ROM BARs that read
79 * as zero when disabled, so don't update ROM BARs unless
80 * they're enabled. See https://lkml.org/lkml/2005/8/30/138.
82 if (!(res->flags & IORESOURCE_ROM_ENABLE))
85 reg = dev->rom_base_reg;
86 new |= PCI_ROM_ADDRESS_ENABLE;
91 * We can't update a 64-bit BAR atomically, so when possible,
92 * disable decoding so that a half-updated BAR won't conflict
93 * with another device.
95 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
97 pci_read_config_word(dev, PCI_COMMAND, &cmd);
98 pci_write_config_word(dev, PCI_COMMAND,
99 cmd & ~PCI_COMMAND_MEMORY);
102 pci_write_config_dword(dev, reg, new);
103 pci_read_config_dword(dev, reg, &check);
105 if ((new ^ check) & mask) {
106 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
110 if (res->flags & IORESOURCE_MEM_64) {
111 new = region.start >> 16 >> 16;
112 pci_write_config_dword(dev, reg + 4, new);
113 pci_read_config_dword(dev, reg + 4, &check);
115 dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
121 pci_write_config_word(dev, PCI_COMMAND, cmd);
124 void pci_update_resource(struct pci_dev *dev, int resno)
126 if (resno <= PCI_ROM_RESOURCE)
127 pci_std_update_resource(dev, resno);
128 #ifdef CONFIG_PCI_IOV
129 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
130 pci_iov_update_resource(dev, resno);
134 int pci_claim_resource(struct pci_dev *dev, int resource)
136 struct resource *res = &dev->resource[resource];
137 struct resource *root, *conflict;
139 if (res->flags & IORESOURCE_UNSET) {
140 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
146 * If we have a shadow copy in RAM, the PCI device doesn't respond
147 * to the shadow range, so we don't need to claim it, and upstream
148 * bridges don't need to route the range to the device.
150 if (res->flags & IORESOURCE_ROM_SHADOW)
153 root = pci_find_parent_resource(dev, res);
155 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
157 res->flags |= IORESOURCE_UNSET;
161 conflict = request_resource_conflict(root, res);
163 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
164 resource, res, conflict->name, conflict);
165 res->flags |= IORESOURCE_UNSET;
171 EXPORT_SYMBOL(pci_claim_resource);
173 void pci_disable_bridge_window(struct pci_dev *dev)
175 dev_info(&dev->dev, "disabling bridge mem windows\n");
177 /* MMIO Base/Limit */
178 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
180 /* Prefetchable MMIO Base/Limit */
181 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
182 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
183 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
187 * Generic function that returns a value indicating that the device's
188 * original BIOS BAR address was not saved and so is not available for
191 * Can be over-ridden by architecture specific code that implements
192 * reinstatement functionality rather than leaving it disabled when
193 * normal allocation attempts fail.
195 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
200 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
201 int resno, resource_size_t size)
203 struct resource *root, *conflict;
204 resource_size_t fw_addr, start, end;
206 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
212 res->start = fw_addr;
213 res->end = res->start + size - 1;
214 res->flags &= ~IORESOURCE_UNSET;
216 root = pci_find_parent_resource(dev, res);
219 * If dev is behind a bridge, accesses will only reach it
220 * if res is inside the relevant bridge window.
222 if (pci_upstream_bridge(dev))
226 * On the root bus, assume the host bridge will forward
229 if (res->flags & IORESOURCE_IO)
230 root = &ioport_resource;
232 root = &iomem_resource;
235 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
237 conflict = request_resource_conflict(root, res);
239 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
240 resno, res, conflict->name, conflict);
243 res->flags |= IORESOURCE_UNSET;
250 * We don't have to worry about legacy ISA devices, so nothing to do here.
251 * This is marked as __weak because multiple architectures define it; it should
252 * eventually go away.
254 resource_size_t __weak pcibios_align_resource(void *data,
255 const struct resource *res,
256 resource_size_t size,
257 resource_size_t align)
262 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
263 int resno, resource_size_t size, resource_size_t align)
265 struct resource *res = dev->resource + resno;
269 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
272 * First, try exact prefetching match. Even if a 64-bit
273 * prefetchable bridge window is below 4GB, we can't put a 32-bit
274 * prefetchable resource in it because pbus_size_mem() assumes a
275 * 64-bit window will contain no 32-bit resources. If we assign
276 * things differently than they were sized, not everything will fit.
278 ret = pci_bus_alloc_resource(bus, res, size, align, min,
279 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
280 pcibios_align_resource, dev);
285 * If the prefetchable window is only 32 bits wide, we can put
286 * 64-bit prefetchable resources in it.
288 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
289 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
290 ret = pci_bus_alloc_resource(bus, res, size, align, min,
292 pcibios_align_resource, dev);
298 * If we didn't find a better match, we can put any memory resource
299 * in a non-prefetchable window. If this resource is 32 bits and
300 * non-prefetchable, the first call already tried the only possibility
301 * so we don't need to try again.
303 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
304 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
305 pcibios_align_resource, dev);
310 static int _pci_assign_resource(struct pci_dev *dev, int resno,
311 resource_size_t size, resource_size_t min_align)
317 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
318 if (!bus->parent || !bus->self->transparent)
326 int pci_assign_resource(struct pci_dev *dev, int resno)
328 struct resource *res = dev->resource + resno;
329 resource_size_t align, size;
332 if (res->flags & IORESOURCE_PCI_FIXED)
335 res->flags |= IORESOURCE_UNSET;
336 align = pci_resource_alignment(dev, res);
338 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
343 size = resource_size(res);
344 ret = _pci_assign_resource(dev, resno, size, align);
347 * If we failed to assign anything, let's try the address
348 * where firmware left it. That at least has a chance of
349 * working, which is better than just leaving it disabled.
352 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
353 ret = pci_revert_fw_address(res, dev, resno, size);
357 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
362 res->flags &= ~IORESOURCE_UNSET;
363 res->flags &= ~IORESOURCE_STARTALIGN;
364 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
365 if (resno < PCI_BRIDGE_RESOURCES)
366 pci_update_resource(dev, resno);
370 EXPORT_SYMBOL(pci_assign_resource);
372 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
373 resource_size_t min_align)
375 struct resource *res = dev->resource + resno;
377 resource_size_t new_size;
380 if (res->flags & IORESOURCE_PCI_FIXED)
384 res->flags |= IORESOURCE_UNSET;
386 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
391 /* already aligned with min_align */
392 new_size = resource_size(res) + addsize;
393 ret = _pci_assign_resource(dev, resno, new_size, min_align);
396 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
397 resno, res, (unsigned long long) addsize);
401 res->flags &= ~IORESOURCE_UNSET;
402 res->flags &= ~IORESOURCE_STARTALIGN;
403 dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
404 resno, res, (unsigned long long) addsize);
405 if (resno < PCI_BRIDGE_RESOURCES)
406 pci_update_resource(dev, resno);
411 int pci_enable_resources(struct pci_dev *dev, int mask)
417 pci_read_config_word(dev, PCI_COMMAND, &cmd);
420 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
421 if (!(mask & (1 << i)))
424 r = &dev->resource[i];
426 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
428 if ((i == PCI_ROM_RESOURCE) &&
429 (!(r->flags & IORESOURCE_ROM_ENABLE)))
432 if (r->flags & IORESOURCE_UNSET) {
433 dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
439 dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
444 if (r->flags & IORESOURCE_IO)
445 cmd |= PCI_COMMAND_IO;
446 if (r->flags & IORESOURCE_MEM)
447 cmd |= PCI_COMMAND_MEMORY;
450 if (cmd != old_cmd) {
451 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
453 pci_write_config_word(dev, PCI_COMMAND, cmd);