2 * drivers/pci/setup-res.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
19 #include <linux/kernel.h>
20 #include <linux/export.h>
21 #include <linux/pci.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/cache.h>
25 #include <linux/slab.h>
28 static void pci_std_update_resource(struct pci_dev *dev, int resno)
30 struct pci_bus_region region;
35 struct resource *res = dev->resource + resno;
37 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
42 * Ignore resources for unimplemented BARs and unused resource slots
48 if (res->flags & IORESOURCE_UNSET)
52 * Ignore non-moveable resources. This might be legacy resources for
53 * which no functional BAR register exists or another important
54 * system resource we shouldn't move around.
56 if (res->flags & IORESOURCE_PCI_FIXED)
59 pcibios_resource_to_bus(dev->bus, ®ion, res);
62 if (res->flags & IORESOURCE_IO) {
63 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
64 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
65 } else if (resno == PCI_ROM_RESOURCE) {
66 mask = PCI_ROM_ADDRESS_MASK;
68 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
69 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
72 if (resno < PCI_ROM_RESOURCE) {
73 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
74 } else if (resno == PCI_ROM_RESOURCE) {
77 * Apparently some Matrox devices have ROM BARs that read
78 * as zero when disabled, so don't update ROM BARs unless
79 * they're enabled. See https://lkml.org/lkml/2005/8/30/138.
81 if (!(res->flags & IORESOURCE_ROM_ENABLE))
84 reg = dev->rom_base_reg;
85 new |= PCI_ROM_ADDRESS_ENABLE;
90 * We can't update a 64-bit BAR atomically, so when possible,
91 * disable decoding so that a half-updated BAR won't conflict
92 * with another device.
94 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
96 pci_read_config_word(dev, PCI_COMMAND, &cmd);
97 pci_write_config_word(dev, PCI_COMMAND,
98 cmd & ~PCI_COMMAND_MEMORY);
101 pci_write_config_dword(dev, reg, new);
102 pci_read_config_dword(dev, reg, &check);
104 if ((new ^ check) & mask) {
105 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
109 if (res->flags & IORESOURCE_MEM_64) {
110 new = region.start >> 16 >> 16;
111 pci_write_config_dword(dev, reg + 4, new);
112 pci_read_config_dword(dev, reg + 4, &check);
114 dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
120 pci_write_config_word(dev, PCI_COMMAND, cmd);
123 void pci_update_resource(struct pci_dev *dev, int resno)
125 if (resno <= PCI_ROM_RESOURCE)
126 pci_std_update_resource(dev, resno);
127 #ifdef CONFIG_PCI_IOV
128 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
129 pci_iov_update_resource(dev, resno);
133 int pci_claim_resource(struct pci_dev *dev, int resource)
135 struct resource *res = &dev->resource[resource];
136 struct resource *root, *conflict;
138 if (res->flags & IORESOURCE_UNSET) {
139 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
145 * If we have a shadow copy in RAM, the PCI device doesn't respond
146 * to the shadow range, so we don't need to claim it, and upstream
147 * bridges don't need to route the range to the device.
149 if (res->flags & IORESOURCE_ROM_SHADOW)
152 root = pci_find_parent_resource(dev, res);
154 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
156 res->flags |= IORESOURCE_UNSET;
160 conflict = request_resource_conflict(root, res);
162 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
163 resource, res, conflict->name, conflict);
164 res->flags |= IORESOURCE_UNSET;
170 EXPORT_SYMBOL(pci_claim_resource);
172 void pci_disable_bridge_window(struct pci_dev *dev)
174 dev_info(&dev->dev, "disabling bridge mem windows\n");
176 /* MMIO Base/Limit */
177 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
179 /* Prefetchable MMIO Base/Limit */
180 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
181 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
182 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
186 * Generic function that returns a value indicating that the device's
187 * original BIOS BAR address was not saved and so is not available for
190 * Can be over-ridden by architecture specific code that implements
191 * reinstatement functionality rather than leaving it disabled when
192 * normal allocation attempts fail.
194 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
199 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
200 int resno, resource_size_t size)
202 struct resource *root, *conflict;
203 resource_size_t fw_addr, start, end;
205 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
211 res->start = fw_addr;
212 res->end = res->start + size - 1;
213 res->flags &= ~IORESOURCE_UNSET;
215 root = pci_find_parent_resource(dev, res);
218 * If dev is behind a bridge, accesses will only reach it
219 * if res is inside the relevant bridge window.
221 if (pci_upstream_bridge(dev))
225 * On the root bus, assume the host bridge will forward
228 if (res->flags & IORESOURCE_IO)
229 root = &ioport_resource;
231 root = &iomem_resource;
234 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
236 conflict = request_resource_conflict(root, res);
238 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
239 resno, res, conflict->name, conflict);
242 res->flags |= IORESOURCE_UNSET;
248 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
249 int resno, resource_size_t size, resource_size_t align)
251 struct resource *res = dev->resource + resno;
255 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
258 * First, try exact prefetching match. Even if a 64-bit
259 * prefetchable bridge window is below 4GB, we can't put a 32-bit
260 * prefetchable resource in it because pbus_size_mem() assumes a
261 * 64-bit window will contain no 32-bit resources. If we assign
262 * things differently than they were sized, not everything will fit.
264 ret = pci_bus_alloc_resource(bus, res, size, align, min,
265 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
266 pcibios_align_resource, dev);
271 * If the prefetchable window is only 32 bits wide, we can put
272 * 64-bit prefetchable resources in it.
274 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
275 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
276 ret = pci_bus_alloc_resource(bus, res, size, align, min,
278 pcibios_align_resource, dev);
284 * If we didn't find a better match, we can put any memory resource
285 * in a non-prefetchable window. If this resource is 32 bits and
286 * non-prefetchable, the first call already tried the only possibility
287 * so we don't need to try again.
289 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
290 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
291 pcibios_align_resource, dev);
296 static int _pci_assign_resource(struct pci_dev *dev, int resno,
297 resource_size_t size, resource_size_t min_align)
303 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
304 if (!bus->parent || !bus->self->transparent)
312 int pci_assign_resource(struct pci_dev *dev, int resno)
314 struct resource *res = dev->resource + resno;
315 resource_size_t align, size;
318 if (res->flags & IORESOURCE_PCI_FIXED)
321 res->flags |= IORESOURCE_UNSET;
322 align = pci_resource_alignment(dev, res);
324 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
329 size = resource_size(res);
330 ret = _pci_assign_resource(dev, resno, size, align);
333 * If we failed to assign anything, let's try the address
334 * where firmware left it. That at least has a chance of
335 * working, which is better than just leaving it disabled.
338 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
339 ret = pci_revert_fw_address(res, dev, resno, size);
343 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
348 res->flags &= ~IORESOURCE_UNSET;
349 res->flags &= ~IORESOURCE_STARTALIGN;
350 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
351 if (resno < PCI_BRIDGE_RESOURCES)
352 pci_update_resource(dev, resno);
356 EXPORT_SYMBOL(pci_assign_resource);
358 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
359 resource_size_t min_align)
361 struct resource *res = dev->resource + resno;
363 resource_size_t new_size;
366 if (res->flags & IORESOURCE_PCI_FIXED)
370 res->flags |= IORESOURCE_UNSET;
372 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
377 /* already aligned with min_align */
378 new_size = resource_size(res) + addsize;
379 ret = _pci_assign_resource(dev, resno, new_size, min_align);
382 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
383 resno, res, (unsigned long long) addsize);
387 res->flags &= ~IORESOURCE_UNSET;
388 res->flags &= ~IORESOURCE_STARTALIGN;
389 dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
390 resno, res, (unsigned long long) addsize);
391 if (resno < PCI_BRIDGE_RESOURCES)
392 pci_update_resource(dev, resno);
397 int pci_enable_resources(struct pci_dev *dev, int mask)
403 pci_read_config_word(dev, PCI_COMMAND, &cmd);
406 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
407 if (!(mask & (1 << i)))
410 r = &dev->resource[i];
412 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
414 if ((i == PCI_ROM_RESOURCE) &&
415 (!(r->flags & IORESOURCE_ROM_ENABLE)))
418 if (r->flags & IORESOURCE_UNSET) {
419 dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
425 dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
430 if (r->flags & IORESOURCE_IO)
431 cmd |= PCI_COMMAND_IO;
432 if (r->flags & IORESOURCE_MEM)
433 cmd |= PCI_COMMAND_MEMORY;
436 if (cmd != old_cmd) {
437 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
439 pci_write_config_word(dev, PCI_COMMAND, cmd);