1 // SPDX-License-Identifier: GPL-2.0
3 * Support routines for initializing a PCI subsystem
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11 * PCI-PCI bridges cleanup, sorted resource allocation.
12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Converted to allocation in 3 passes, which gives
14 * tighter packing. Prefetchable range support.
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <linux/acpi.h>
28 unsigned int pci_flags;
30 struct pci_dev_resource {
31 struct list_head list;
34 resource_size_t start;
36 resource_size_t add_size;
37 resource_size_t min_align;
41 static void free_list(struct list_head *head)
43 struct pci_dev_resource *dev_res, *tmp;
45 list_for_each_entry_safe(dev_res, tmp, head, list) {
46 list_del(&dev_res->list);
52 * add_to_list() - add a new resource tracker to the list
53 * @head: Head of the list
54 * @dev: device corresponding to which the resource
56 * @res: The resource to be tracked
57 * @add_size: additional size to be optionally added
60 static int add_to_list(struct list_head *head,
61 struct pci_dev *dev, struct resource *res,
62 resource_size_t add_size, resource_size_t min_align)
64 struct pci_dev_resource *tmp;
66 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
72 tmp->start = res->start;
74 tmp->flags = res->flags;
75 tmp->add_size = add_size;
76 tmp->min_align = min_align;
78 list_add(&tmp->list, head);
83 static void remove_from_list(struct list_head *head,
86 struct pci_dev_resource *dev_res, *tmp;
88 list_for_each_entry_safe(dev_res, tmp, head, list) {
89 if (dev_res->res == res) {
90 list_del(&dev_res->list);
97 static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
100 struct pci_dev_resource *dev_res;
102 list_for_each_entry(dev_res, head, list) {
103 if (dev_res->res == res)
110 static resource_size_t get_res_add_size(struct list_head *head,
111 struct resource *res)
113 struct pci_dev_resource *dev_res;
115 dev_res = res_to_dev_res(head, res);
116 return dev_res ? dev_res->add_size : 0;
119 static resource_size_t get_res_add_align(struct list_head *head,
120 struct resource *res)
122 struct pci_dev_resource *dev_res;
124 dev_res = res_to_dev_res(head, res);
125 return dev_res ? dev_res->min_align : 0;
129 /* Sort resources by alignment */
130 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
134 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
136 struct pci_dev_resource *dev_res, *tmp;
137 resource_size_t r_align;
140 r = &dev->resource[i];
142 if (r->flags & IORESOURCE_PCI_FIXED)
145 if (!(r->flags) || r->parent)
148 r_align = pci_resource_alignment(dev, r);
150 pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
155 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
157 panic("pdev_sort_resources(): kmalloc() failed!\n");
161 /* fallback is smallest one or list is empty*/
163 list_for_each_entry(dev_res, head, list) {
164 resource_size_t align;
166 align = pci_resource_alignment(dev_res->dev,
169 if (r_align > align) {
174 /* Insert it just before n*/
175 list_add_tail(&tmp->list, n);
179 static void __dev_sort_resources(struct pci_dev *dev,
180 struct list_head *head)
182 u16 class = dev->class >> 8;
184 /* Don't touch classless devices or host bridges or ioapics. */
185 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
188 /* Don't touch ioapic devices already enabled by firmware */
189 if (class == PCI_CLASS_SYSTEM_PIC) {
191 pci_read_config_word(dev, PCI_COMMAND, &command);
192 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
196 pdev_sort_resources(dev, head);
199 static inline void reset_resource(struct resource *res)
207 * reassign_resources_sorted() - satisfy any additional resource requests
209 * @realloc_head : head of the list tracking requests requiring additional
211 * @head : head of the list tracking requests with allocated
214 * Walk through each element of the realloc_head and try to procure
215 * additional resources for the element, provided the element
216 * is in the head list.
218 static void reassign_resources_sorted(struct list_head *realloc_head,
219 struct list_head *head)
221 struct resource *res;
222 struct pci_dev_resource *add_res, *tmp;
223 struct pci_dev_resource *dev_res;
224 resource_size_t add_size, align;
227 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
228 bool found_match = false;
231 /* skip resource that has been reset */
235 /* skip this resource if not found in head list */
236 list_for_each_entry(dev_res, head, list) {
237 if (dev_res->res == res) {
242 if (!found_match)/* just skip */
245 idx = res - &add_res->dev->resource[0];
246 add_size = add_res->add_size;
247 align = add_res->min_align;
248 if (!resource_size(res)) {
250 res->end = res->start + add_size - 1;
251 if (pci_assign_resource(add_res->dev, idx))
254 res->flags |= add_res->flags &
255 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
256 if (pci_reassign_resource(add_res->dev, idx,
258 pci_printk(KERN_DEBUG, add_res->dev,
259 "failed to add %llx res[%d]=%pR\n",
260 (unsigned long long)add_size,
264 list_del(&add_res->list);
270 * assign_requested_resources_sorted() - satisfy resource requests
272 * @head : head of the list tracking requests for resources
273 * @fail_head : head of the list tracking requests that could
276 * Satisfy resource requests of each element in the list. Add
277 * requests that could not satisfied to the failed_list.
279 static void assign_requested_resources_sorted(struct list_head *head,
280 struct list_head *fail_head)
282 struct resource *res;
283 struct pci_dev_resource *dev_res;
286 list_for_each_entry(dev_res, head, list) {
288 idx = res - &dev_res->dev->resource[0];
289 if (resource_size(res) &&
290 pci_assign_resource(dev_res->dev, idx)) {
293 * if the failed res is for ROM BAR, and it will
294 * be enabled later, don't add it to the list
296 if (!((idx == PCI_ROM_RESOURCE) &&
297 (!(res->flags & IORESOURCE_ROM_ENABLE))))
298 add_to_list(fail_head,
308 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
310 struct pci_dev_resource *fail_res;
311 unsigned long mask = 0;
313 /* check failed type */
314 list_for_each_entry(fail_res, fail_head, list)
315 mask |= fail_res->flags;
318 * one pref failed resource will set IORESOURCE_MEM,
319 * as we can allocate pref in non-pref range.
320 * Will release all assigned non-pref sibling resources
321 * according to that bit.
323 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
326 static bool pci_need_to_release(unsigned long mask, struct resource *res)
328 if (res->flags & IORESOURCE_IO)
329 return !!(mask & IORESOURCE_IO);
331 /* check pref at first */
332 if (res->flags & IORESOURCE_PREFETCH) {
333 if (mask & IORESOURCE_PREFETCH)
335 /* count pref if its parent is non-pref */
336 else if ((mask & IORESOURCE_MEM) &&
337 !(res->parent->flags & IORESOURCE_PREFETCH))
343 if (res->flags & IORESOURCE_MEM)
344 return !!(mask & IORESOURCE_MEM);
346 return false; /* should not get here */
349 static void __assign_resources_sorted(struct list_head *head,
350 struct list_head *realloc_head,
351 struct list_head *fail_head)
354 * Should not assign requested resources at first.
355 * they could be adjacent, so later reassign can not reallocate
356 * them one by one in parent resource window.
357 * Try to assign requested + add_size at beginning
358 * if could do that, could get out early.
359 * if could not do that, we still try to assign requested at first,
360 * then try to reassign add_size for some resources.
362 * Separate three resource type checking if we need to release
363 * assigned resource after requested + add_size try.
364 * 1. if there is io port assign fail, will release assigned
366 * 2. if there is pref mmio assign fail, release assigned
368 * if assigned pref mmio's parent is non-pref mmio and there
369 * is non-pref mmio assign fail, will release that assigned
371 * 3. if there is non-pref mmio assign fail or pref mmio
372 * assigned fail, will release assigned non-pref mmio.
374 LIST_HEAD(save_head);
375 LIST_HEAD(local_fail_head);
376 struct pci_dev_resource *save_res;
377 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
378 unsigned long fail_type;
379 resource_size_t add_align, align;
381 /* Check if optional add_size is there */
382 if (!realloc_head || list_empty(realloc_head))
383 goto requested_and_reassign;
385 /* Save original start, end, flags etc at first */
386 list_for_each_entry(dev_res, head, list) {
387 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
388 free_list(&save_head);
389 goto requested_and_reassign;
393 /* Update res in head list with add_size in realloc_head list */
394 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
395 dev_res->res->end += get_res_add_size(realloc_head,
399 * There are two kinds of additional resources in the list:
400 * 1. bridge resource -- IORESOURCE_STARTALIGN
401 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
402 * Here just fix the additional alignment for bridge
404 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
407 add_align = get_res_add_align(realloc_head, dev_res->res);
410 * The "head" list is sorted by the alignment to make sure
411 * resources with bigger alignment will be assigned first.
412 * After we change the alignment of a dev_res in "head" list,
413 * we need to reorder the list by alignment to make it
416 if (add_align > dev_res->res->start) {
417 resource_size_t r_size = resource_size(dev_res->res);
419 dev_res->res->start = add_align;
420 dev_res->res->end = add_align + r_size - 1;
422 list_for_each_entry(dev_res2, head, list) {
423 align = pci_resource_alignment(dev_res2->dev,
425 if (add_align > align) {
426 list_move_tail(&dev_res->list,
435 /* Try updated head list with add_size added */
436 assign_requested_resources_sorted(head, &local_fail_head);
438 /* all assigned with add_size ? */
439 if (list_empty(&local_fail_head)) {
440 /* Remove head list from realloc_head list */
441 list_for_each_entry(dev_res, head, list)
442 remove_from_list(realloc_head, dev_res->res);
443 free_list(&save_head);
448 /* check failed type */
449 fail_type = pci_fail_res_type_mask(&local_fail_head);
450 /* remove not need to be released assigned res from head list etc */
451 list_for_each_entry_safe(dev_res, tmp_res, head, list)
452 if (dev_res->res->parent &&
453 !pci_need_to_release(fail_type, dev_res->res)) {
454 /* remove it from realloc_head list */
455 remove_from_list(realloc_head, dev_res->res);
456 remove_from_list(&save_head, dev_res->res);
457 list_del(&dev_res->list);
461 free_list(&local_fail_head);
462 /* Release assigned resource */
463 list_for_each_entry(dev_res, head, list)
464 if (dev_res->res->parent)
465 release_resource(dev_res->res);
466 /* Restore start/end/flags from saved list */
467 list_for_each_entry(save_res, &save_head, list) {
468 struct resource *res = save_res->res;
470 res->start = save_res->start;
471 res->end = save_res->end;
472 res->flags = save_res->flags;
474 free_list(&save_head);
476 requested_and_reassign:
477 /* Satisfy the must-have resource requests */
478 assign_requested_resources_sorted(head, fail_head);
480 /* Try to satisfy any additional optional resource
483 reassign_resources_sorted(realloc_head, head);
487 static void pdev_assign_resources_sorted(struct pci_dev *dev,
488 struct list_head *add_head,
489 struct list_head *fail_head)
493 __dev_sort_resources(dev, &head);
494 __assign_resources_sorted(&head, add_head, fail_head);
498 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
499 struct list_head *realloc_head,
500 struct list_head *fail_head)
505 list_for_each_entry(dev, &bus->devices, bus_list)
506 __dev_sort_resources(dev, &head);
508 __assign_resources_sorted(&head, realloc_head, fail_head);
511 void pci_setup_cardbus(struct pci_bus *bus)
513 struct pci_dev *bridge = bus->self;
514 struct resource *res;
515 struct pci_bus_region region;
517 pci_info(bridge, "CardBus bridge to %pR\n",
520 res = bus->resource[0];
521 pcibios_resource_to_bus(bridge->bus, ®ion, res);
522 if (res->flags & IORESOURCE_IO) {
524 * The IO resource is allocated a range twice as large as it
525 * would normally need. This allows us to set both IO regs.
527 pci_info(bridge, " bridge window %pR\n", res);
528 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
530 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
534 res = bus->resource[1];
535 pcibios_resource_to_bus(bridge->bus, ®ion, res);
536 if (res->flags & IORESOURCE_IO) {
537 pci_info(bridge, " bridge window %pR\n", res);
538 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
540 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
544 res = bus->resource[2];
545 pcibios_resource_to_bus(bridge->bus, ®ion, res);
546 if (res->flags & IORESOURCE_MEM) {
547 pci_info(bridge, " bridge window %pR\n", res);
548 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
550 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
554 res = bus->resource[3];
555 pcibios_resource_to_bus(bridge->bus, ®ion, res);
556 if (res->flags & IORESOURCE_MEM) {
557 pci_info(bridge, " bridge window %pR\n", res);
558 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
560 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
564 EXPORT_SYMBOL(pci_setup_cardbus);
566 /* Initialize bridges with base/limit values we have collected.
567 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
568 requires that if there is no I/O ports or memory behind the
569 bridge, corresponding range must be turned off by writing base
570 value greater than limit to the bridge's base/limit registers.
572 Note: care must be taken when updating I/O base/limit registers
573 of bridges which support 32-bit I/O. This update requires two
574 config space writes, so it's quite possible that an I/O window of
575 the bridge will have some undesirable address (e.g. 0) after the
576 first write. Ditto 64-bit prefetchable MMIO. */
577 static void pci_setup_bridge_io(struct pci_dev *bridge)
579 struct resource *res;
580 struct pci_bus_region region;
581 unsigned long io_mask;
582 u8 io_base_lo, io_limit_lo;
586 io_mask = PCI_IO_RANGE_MASK;
587 if (bridge->io_window_1k)
588 io_mask = PCI_IO_1K_RANGE_MASK;
590 /* Set up the top and bottom of the PCI I/O segment for this bus. */
591 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
592 pcibios_resource_to_bus(bridge->bus, ®ion, res);
593 if (res->flags & IORESOURCE_IO) {
594 pci_read_config_word(bridge, PCI_IO_BASE, &l);
595 io_base_lo = (region.start >> 8) & io_mask;
596 io_limit_lo = (region.end >> 8) & io_mask;
597 l = ((u16) io_limit_lo << 8) | io_base_lo;
598 /* Set up upper 16 bits of I/O base/limit. */
599 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
600 pci_info(bridge, " bridge window %pR\n", res);
602 /* Clear upper 16 bits of I/O base/limit. */
606 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
607 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
608 /* Update lower 16 bits of I/O base/limit. */
609 pci_write_config_word(bridge, PCI_IO_BASE, l);
610 /* Update upper 16 bits of I/O base/limit. */
611 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
614 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
616 struct resource *res;
617 struct pci_bus_region region;
620 /* Set up the top and bottom of the PCI Memory segment for this bus. */
621 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
622 pcibios_resource_to_bus(bridge->bus, ®ion, res);
623 if (res->flags & IORESOURCE_MEM) {
624 l = (region.start >> 16) & 0xfff0;
625 l |= region.end & 0xfff00000;
626 pci_info(bridge, " bridge window %pR\n", res);
630 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
633 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
635 struct resource *res;
636 struct pci_bus_region region;
639 /* Clear out the upper 32 bits of PREF limit.
640 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
641 disables PREF range, which is ok. */
642 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
644 /* Set up PREF base/limit. */
646 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
647 pcibios_resource_to_bus(bridge->bus, ®ion, res);
648 if (res->flags & IORESOURCE_PREFETCH) {
649 l = (region.start >> 16) & 0xfff0;
650 l |= region.end & 0xfff00000;
651 if (res->flags & IORESOURCE_MEM_64) {
652 bu = upper_32_bits(region.start);
653 lu = upper_32_bits(region.end);
655 pci_info(bridge, " bridge window %pR\n", res);
659 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
661 /* Set the upper 32 bits of PREF base & limit. */
662 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
663 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
666 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
668 struct pci_dev *bridge = bus->self;
670 pci_info(bridge, "PCI bridge to %pR\n",
673 if (type & IORESOURCE_IO)
674 pci_setup_bridge_io(bridge);
676 if (type & IORESOURCE_MEM)
677 pci_setup_bridge_mmio(bridge);
679 if (type & IORESOURCE_PREFETCH)
680 pci_setup_bridge_mmio_pref(bridge);
682 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
685 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
689 void pci_setup_bridge(struct pci_bus *bus)
691 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
694 pcibios_setup_bridge(bus, type);
695 __pci_setup_bridge(bus, type);
699 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
701 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
704 if (pci_claim_resource(bridge, i) == 0)
705 return 0; /* claimed the window */
707 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
710 if (!pci_bus_clip_resource(bridge, i))
711 return -EINVAL; /* clipping didn't change anything */
713 switch (i - PCI_BRIDGE_RESOURCES) {
715 pci_setup_bridge_io(bridge);
718 pci_setup_bridge_mmio(bridge);
721 pci_setup_bridge_mmio_pref(bridge);
727 if (pci_claim_resource(bridge, i) == 0)
728 return 0; /* claimed a smaller window */
733 /* Check whether the bridge supports optional I/O and
734 prefetchable memory ranges. If not, the respective
735 base/limit registers must be read-only and read as 0. */
736 static void pci_bridge_check_ranges(struct pci_bus *bus)
738 struct pci_dev *bridge = bus->self;
739 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
741 b_res[1].flags |= IORESOURCE_MEM;
743 if (bridge->io_window)
744 b_res[0].flags |= IORESOURCE_IO;
746 if (bridge->pref_window) {
747 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
748 if (bridge->pref_64_window) {
749 b_res[2].flags |= IORESOURCE_MEM_64;
750 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
755 /* Helper function for sizing routines: find first available
756 bus resource of a given type. Note: we intentionally skip
757 the bus resources which have already been assigned (that is,
758 have non-NULL parent resource). */
759 static struct resource *find_free_bus_resource(struct pci_bus *bus,
760 unsigned long type_mask, unsigned long type)
765 pci_bus_for_each_resource(bus, r, i) {
766 if (r == &ioport_resource || r == &iomem_resource)
768 if (r && (r->flags & type_mask) == type && !r->parent)
774 static resource_size_t calculate_iosize(resource_size_t size,
775 resource_size_t min_size,
776 resource_size_t size1,
777 resource_size_t old_size,
778 resource_size_t align)
784 /* To be fixed in 2.5: we should have sort of HAVE_ISA
785 flag in the struct pci_bus. */
786 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
787 size = (size & 0xff) + ((size & ~0xffUL) << 2);
789 size = ALIGN(size + size1, align);
795 static resource_size_t calculate_memsize(resource_size_t size,
796 resource_size_t min_size,
797 resource_size_t size1,
798 resource_size_t old_size,
799 resource_size_t align)
807 size = ALIGN(size + size1, align);
811 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
817 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
818 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
819 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
821 static resource_size_t window_alignment(struct pci_bus *bus,
824 resource_size_t align = 1, arch_align;
826 if (type & IORESOURCE_MEM)
827 align = PCI_P2P_DEFAULT_MEM_ALIGN;
828 else if (type & IORESOURCE_IO) {
830 * Per spec, I/O windows are 4K-aligned, but some
831 * bridges have an extension to support 1K alignment.
833 if (bus->self->io_window_1k)
834 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
836 align = PCI_P2P_DEFAULT_IO_ALIGN;
839 arch_align = pcibios_window_alignment(bus, type);
840 return max(align, arch_align);
844 * pbus_size_io() - size the io window of a given bus
847 * @min_size : the minimum io window that must to be allocated
848 * @add_size : additional optional io window
849 * @realloc_head : track the additional io window on this list
851 * Sizing the IO windows of the PCI-PCI bridge is trivial,
852 * since these windows have 1K or 4K granularity and the IO ranges
853 * of non-bridge PCI devices are limited to 256 bytes.
854 * We must be careful with the ISA aliasing though.
856 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
857 resource_size_t add_size, struct list_head *realloc_head)
860 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
862 resource_size_t size = 0, size0 = 0, size1 = 0;
863 resource_size_t children_add_size = 0;
864 resource_size_t min_align, align;
869 min_align = window_alignment(bus, IORESOURCE_IO);
870 list_for_each_entry(dev, &bus->devices, bus_list) {
873 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
874 struct resource *r = &dev->resource[i];
875 unsigned long r_size;
877 if (r->parent || !(r->flags & IORESOURCE_IO))
879 r_size = resource_size(r);
882 /* Might be re-aligned for ISA */
887 align = pci_resource_alignment(dev, r);
888 if (align > min_align)
892 children_add_size += get_res_add_size(realloc_head, r);
896 size0 = calculate_iosize(size, min_size, size1,
897 resource_size(b_res), min_align);
898 if (children_add_size > add_size)
899 add_size = children_add_size;
900 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
901 calculate_iosize(size, min_size, add_size + size1,
902 resource_size(b_res), min_align);
903 if (!size0 && !size1) {
904 if (b_res->start || b_res->end)
905 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
906 b_res, &bus->busn_res);
911 b_res->start = min_align;
912 b_res->end = b_res->start + size0 - 1;
913 b_res->flags |= IORESOURCE_STARTALIGN;
914 if (size1 > size0 && realloc_head) {
915 add_to_list(realloc_head, bus->self, b_res, size1-size0,
917 pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx\n",
918 b_res, &bus->busn_res,
919 (unsigned long long)size1-size0);
923 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
926 resource_size_t align = 0;
927 resource_size_t min_align = 0;
930 for (order = 0; order <= max_order; order++) {
931 resource_size_t align1 = 1;
933 align1 <<= (order + 20);
937 else if (ALIGN(align + min_align, min_align) < align1)
938 min_align = align1 >> 1;
939 align += aligns[order];
946 * pbus_size_mem() - size the memory window of a given bus
949 * @mask: mask the resource flag, then compare it with type
950 * @type: the type of free resource from bridge
951 * @type2: second match type
952 * @type3: third match type
953 * @min_size : the minimum memory window that must to be allocated
954 * @add_size : additional optional memory window
955 * @realloc_head : track the additional memory window on this list
957 * Calculate the size of the bus and minimal alignment which
958 * guarantees that all child resources fit in this size.
960 * Returns -ENOSPC if there's no available bus resource of the desired type.
961 * Otherwise, sets the bus resource start/end to indicate the required
962 * size, adds things to realloc_head (if supplied), and returns 0.
964 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
965 unsigned long type, unsigned long type2,
967 resource_size_t min_size, resource_size_t add_size,
968 struct list_head *realloc_head)
971 resource_size_t min_align, align, size, size0, size1;
972 resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */
973 int order, max_order;
974 struct resource *b_res = find_free_bus_resource(bus,
975 mask | IORESOURCE_PREFETCH, type);
976 resource_size_t children_add_size = 0;
977 resource_size_t children_add_align = 0;
978 resource_size_t add_align = 0;
983 memset(aligns, 0, sizeof(aligns));
987 list_for_each_entry(dev, &bus->devices, bus_list) {
990 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
991 struct resource *r = &dev->resource[i];
992 resource_size_t r_size;
994 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
995 ((r->flags & mask) != type &&
996 (r->flags & mask) != type2 &&
997 (r->flags & mask) != type3))
999 r_size = resource_size(r);
1000 #ifdef CONFIG_PCI_IOV
1001 /* put SRIOV requested res to the optional list */
1002 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1003 i <= PCI_IOV_RESOURCE_END) {
1004 add_align = max(pci_resource_alignment(dev, r), add_align);
1005 r->end = r->start - 1;
1006 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
1007 children_add_size += r_size;
1012 * aligns[0] is for 1MB (since bridge memory
1013 * windows are always at least 1MB aligned), so
1014 * keep "order" from being negative for smaller
1017 align = pci_resource_alignment(dev, r);
1018 order = __ffs(align) - 20;
1021 if (order >= ARRAY_SIZE(aligns)) {
1022 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1023 i, r, (unsigned long long) align);
1027 size += max(r_size, align);
1028 /* Exclude ranges with size > align from
1029 calculation of the alignment. */
1030 if (r_size <= align)
1031 aligns[order] += align;
1032 if (order > max_order)
1036 children_add_size += get_res_add_size(realloc_head, r);
1037 children_add_align = get_res_add_align(realloc_head, r);
1038 add_align = max(add_align, children_add_align);
1043 min_align = calculate_mem_align(aligns, max_order);
1044 min_align = max(min_align, window_alignment(bus, b_res->flags));
1045 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
1046 add_align = max(min_align, add_align);
1047 if (children_add_size > add_size)
1048 add_size = children_add_size;
1049 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1050 calculate_memsize(size, min_size, add_size,
1051 resource_size(b_res), add_align);
1052 if (!size0 && !size1) {
1053 if (b_res->start || b_res->end)
1054 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1055 b_res, &bus->busn_res);
1059 b_res->start = min_align;
1060 b_res->end = size0 + min_align - 1;
1061 b_res->flags |= IORESOURCE_STARTALIGN;
1062 if (size1 > size0 && realloc_head) {
1063 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1064 pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1065 b_res, &bus->busn_res,
1066 (unsigned long long) (size1 - size0),
1067 (unsigned long long) add_align);
1072 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1074 if (res->flags & IORESOURCE_IO)
1075 return pci_cardbus_io_size;
1076 if (res->flags & IORESOURCE_MEM)
1077 return pci_cardbus_mem_size;
1081 static void pci_bus_size_cardbus(struct pci_bus *bus,
1082 struct list_head *realloc_head)
1084 struct pci_dev *bridge = bus->self;
1085 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1086 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1089 if (b_res[0].parent)
1090 goto handle_b_res_1;
1092 * Reserve some resources for CardBus. We reserve
1093 * a fixed amount of bus space for CardBus bridges.
1095 b_res[0].start = pci_cardbus_io_size;
1096 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1097 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1099 b_res[0].end -= pci_cardbus_io_size;
1100 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1101 pci_cardbus_io_size);
1105 if (b_res[1].parent)
1106 goto handle_b_res_2;
1107 b_res[1].start = pci_cardbus_io_size;
1108 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1109 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1111 b_res[1].end -= pci_cardbus_io_size;
1112 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1113 pci_cardbus_io_size);
1117 /* MEM1 must not be pref mmio */
1118 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1119 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1120 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1121 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1122 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1126 * Check whether prefetchable memory is supported
1129 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1130 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1131 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1132 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1133 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1136 if (b_res[2].parent)
1137 goto handle_b_res_3;
1139 * If we have prefetchable memory support, allocate
1140 * two regions. Otherwise, allocate one region of
1143 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1144 b_res[2].start = pci_cardbus_mem_size;
1145 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1146 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1147 IORESOURCE_STARTALIGN;
1149 b_res[2].end -= pci_cardbus_mem_size;
1150 add_to_list(realloc_head, bridge, b_res+2,
1151 pci_cardbus_mem_size, pci_cardbus_mem_size);
1154 /* reduce that to half */
1155 b_res_3_size = pci_cardbus_mem_size;
1159 if (b_res[3].parent)
1161 b_res[3].start = pci_cardbus_mem_size;
1162 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1163 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1165 b_res[3].end -= b_res_3_size;
1166 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1167 pci_cardbus_mem_size);
1174 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1176 struct pci_dev *dev;
1177 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1178 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1179 struct resource *b_res;
1182 list_for_each_entry(dev, &bus->devices, bus_list) {
1183 struct pci_bus *b = dev->subordinate;
1187 switch (dev->class >> 8) {
1188 case PCI_CLASS_BRIDGE_CARDBUS:
1189 pci_bus_size_cardbus(b, realloc_head);
1192 case PCI_CLASS_BRIDGE_PCI:
1194 __pci_bus_size_bridges(b, realloc_head);
1200 if (pci_is_root_bus(bus))
1203 switch (bus->self->class >> 8) {
1204 case PCI_CLASS_BRIDGE_CARDBUS:
1205 /* don't size cardbuses yet. */
1208 case PCI_CLASS_BRIDGE_PCI:
1209 pci_bridge_check_ranges(bus);
1210 if (bus->self->is_hotplug_bridge) {
1211 additional_io_size = pci_hotplug_io_size;
1212 additional_mem_size = pci_hotplug_mem_size;
1216 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1217 additional_io_size, realloc_head);
1220 * If there's a 64-bit prefetchable MMIO window, compute
1221 * the size required to put all 64-bit prefetchable
1224 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1225 mask = IORESOURCE_MEM;
1226 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1227 if (b_res[2].flags & IORESOURCE_MEM_64) {
1228 prefmask |= IORESOURCE_MEM_64;
1229 ret = pbus_size_mem(bus, prefmask, prefmask,
1231 realloc_head ? 0 : additional_mem_size,
1232 additional_mem_size, realloc_head);
1235 * If successful, all non-prefetchable resources
1236 * and any 32-bit prefetchable resources will go in
1237 * the non-prefetchable window.
1241 type2 = prefmask & ~IORESOURCE_MEM_64;
1242 type3 = prefmask & ~IORESOURCE_PREFETCH;
1247 * If there is no 64-bit prefetchable window, compute the
1248 * size required to put all prefetchable resources in the
1249 * 32-bit prefetchable window (if there is one).
1252 prefmask &= ~IORESOURCE_MEM_64;
1253 ret = pbus_size_mem(bus, prefmask, prefmask,
1255 realloc_head ? 0 : additional_mem_size,
1256 additional_mem_size, realloc_head);
1259 * If successful, only non-prefetchable resources
1260 * will go in the non-prefetchable window.
1265 additional_mem_size += additional_mem_size;
1267 type2 = type3 = IORESOURCE_MEM;
1271 * Compute the size required to put everything else in the
1272 * non-prefetchable window. This includes:
1274 * - all non-prefetchable resources
1275 * - 32-bit prefetchable resources if there's a 64-bit
1276 * prefetchable window or no prefetchable window at all
1277 * - 64-bit prefetchable resources if there's no
1278 * prefetchable window at all
1280 * Note that the strategy in __pci_assign_resource() must
1281 * match that used here. Specifically, we cannot put a
1282 * 32-bit prefetchable resource in a 64-bit prefetchable
1285 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1286 realloc_head ? 0 : additional_mem_size,
1287 additional_mem_size, realloc_head);
1292 void pci_bus_size_bridges(struct pci_bus *bus)
1294 __pci_bus_size_bridges(bus, NULL);
1296 EXPORT_SYMBOL(pci_bus_size_bridges);
1298 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1301 struct resource *parent_r;
1302 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1303 IORESOURCE_PREFETCH;
1305 pci_bus_for_each_resource(b, parent_r, i) {
1309 if ((r->flags & mask) == (parent_r->flags & mask) &&
1310 resource_contains(parent_r, r))
1311 request_resource(parent_r, r);
1316 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they
1317 * are skipped by pbus_assign_resources_sorted().
1319 static void pdev_assign_fixed_resources(struct pci_dev *dev)
1323 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1325 struct resource *r = &dev->resource[i];
1327 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1328 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1332 while (b && !r->parent) {
1333 assign_fixed_resource_on_bus(b, r);
1339 void __pci_bus_assign_resources(const struct pci_bus *bus,
1340 struct list_head *realloc_head,
1341 struct list_head *fail_head)
1344 struct pci_dev *dev;
1346 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1348 list_for_each_entry(dev, &bus->devices, bus_list) {
1349 pdev_assign_fixed_resources(dev);
1351 b = dev->subordinate;
1355 __pci_bus_assign_resources(b, realloc_head, fail_head);
1357 switch (dev->class >> 8) {
1358 case PCI_CLASS_BRIDGE_PCI:
1359 if (!pci_is_enabled(dev))
1360 pci_setup_bridge(b);
1363 case PCI_CLASS_BRIDGE_CARDBUS:
1364 pci_setup_cardbus(b);
1368 pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1369 pci_domain_nr(b), b->number);
1375 void pci_bus_assign_resources(const struct pci_bus *bus)
1377 __pci_bus_assign_resources(bus, NULL, NULL);
1379 EXPORT_SYMBOL(pci_bus_assign_resources);
1381 static void pci_claim_device_resources(struct pci_dev *dev)
1385 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1386 struct resource *r = &dev->resource[i];
1388 if (!r->flags || r->parent)
1391 pci_claim_resource(dev, i);
1395 static void pci_claim_bridge_resources(struct pci_dev *dev)
1399 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1400 struct resource *r = &dev->resource[i];
1402 if (!r->flags || r->parent)
1405 pci_claim_bridge_resource(dev, i);
1409 static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1411 struct pci_dev *dev;
1412 struct pci_bus *child;
1414 list_for_each_entry(dev, &b->devices, bus_list) {
1415 pci_claim_device_resources(dev);
1417 child = dev->subordinate;
1419 pci_bus_allocate_dev_resources(child);
1423 static void pci_bus_allocate_resources(struct pci_bus *b)
1425 struct pci_bus *child;
1428 * Carry out a depth-first search on the PCI bus
1429 * tree to allocate bridge apertures. Read the
1430 * programmed bridge bases and recursively claim
1431 * the respective bridge resources.
1434 pci_read_bridge_bases(b);
1435 pci_claim_bridge_resources(b->self);
1438 list_for_each_entry(child, &b->children, node)
1439 pci_bus_allocate_resources(child);
1442 void pci_bus_claim_resources(struct pci_bus *b)
1444 pci_bus_allocate_resources(b);
1445 pci_bus_allocate_dev_resources(b);
1447 EXPORT_SYMBOL(pci_bus_claim_resources);
1449 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1450 struct list_head *add_head,
1451 struct list_head *fail_head)
1455 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1456 add_head, fail_head);
1458 b = bridge->subordinate;
1462 __pci_bus_assign_resources(b, add_head, fail_head);
1464 switch (bridge->class >> 8) {
1465 case PCI_CLASS_BRIDGE_PCI:
1466 pci_setup_bridge(b);
1469 case PCI_CLASS_BRIDGE_CARDBUS:
1470 pci_setup_cardbus(b);
1474 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1475 pci_domain_nr(b), b->number);
1480 #define PCI_RES_TYPE_MASK \
1481 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1484 static void pci_bridge_release_resources(struct pci_bus *bus,
1487 struct pci_dev *dev = bus->self;
1489 unsigned old_flags = 0;
1490 struct resource *b_res;
1493 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1496 * 1. if there is io port assign fail, will release bridge
1498 * 2. if there is non pref mmio assign fail, release bridge
1500 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1501 * is 64bit, release bridge pref mmio.
1502 * 4. if there is pref mmio assign fail, and bridge pref is
1503 * 32bit mmio, release bridge pref mmio
1504 * 5. if there is pref mmio assign fail, and bridge pref is not
1505 * assigned, release bridge nonpref mmio.
1507 if (type & IORESOURCE_IO)
1509 else if (!(type & IORESOURCE_PREFETCH))
1511 else if ((type & IORESOURCE_MEM_64) &&
1512 (b_res[2].flags & IORESOURCE_MEM_64))
1514 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1515 (b_res[2].flags & IORESOURCE_PREFETCH))
1526 * if there are children under that, we should release them
1529 release_child_resources(r);
1530 if (!release_resource(r)) {
1531 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1532 pci_printk(KERN_DEBUG, dev, "resource %d %pR released\n",
1533 PCI_BRIDGE_RESOURCES + idx, r);
1534 /* keep the old size */
1535 r->end = resource_size(r) - 1;
1539 /* avoiding touch the one without PREF */
1540 if (type & IORESOURCE_PREFETCH)
1541 type = IORESOURCE_PREFETCH;
1542 __pci_setup_bridge(bus, type);
1543 /* for next child res under same bridge */
1544 r->flags = old_flags;
1553 * try to release pci bridge resources that is from leaf bridge,
1554 * so we can allocate big new one later
1556 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1558 enum release_type rel_type)
1560 struct pci_dev *dev;
1561 bool is_leaf_bridge = true;
1563 list_for_each_entry(dev, &bus->devices, bus_list) {
1564 struct pci_bus *b = dev->subordinate;
1568 is_leaf_bridge = false;
1570 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1573 if (rel_type == whole_subtree)
1574 pci_bus_release_bridge_resources(b, type,
1578 if (pci_is_root_bus(bus))
1581 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1584 if ((rel_type == whole_subtree) || is_leaf_bridge)
1585 pci_bridge_release_resources(bus, type);
1588 static void pci_bus_dump_res(struct pci_bus *bus)
1590 struct resource *res;
1593 pci_bus_for_each_resource(bus, res, i) {
1594 if (!res || !res->end || !res->flags)
1597 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1601 static void pci_bus_dump_resources(struct pci_bus *bus)
1604 struct pci_dev *dev;
1607 pci_bus_dump_res(bus);
1609 list_for_each_entry(dev, &bus->devices, bus_list) {
1610 b = dev->subordinate;
1614 pci_bus_dump_resources(b);
1618 static int pci_bus_get_depth(struct pci_bus *bus)
1621 struct pci_bus *child_bus;
1623 list_for_each_entry(child_bus, &bus->children, node) {
1626 ret = pci_bus_get_depth(child_bus);
1627 if (ret + 1 > depth)
1635 * -1: undefined, will auto detect later
1636 * 0: disabled by user
1637 * 1: disabled by auto detect
1638 * 2: enabled by user
1639 * 3: enabled by auto detect
1649 static enum enable_type pci_realloc_enable = undefined;
1650 void __init pci_realloc_get_opt(char *str)
1652 if (!strncmp(str, "off", 3))
1653 pci_realloc_enable = user_disabled;
1654 else if (!strncmp(str, "on", 2))
1655 pci_realloc_enable = user_enabled;
1657 static bool pci_realloc_enabled(enum enable_type enable)
1659 return enable >= user_enabled;
1662 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1663 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1666 bool *unassigned = data;
1668 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1669 struct resource *r = &dev->resource[i];
1670 struct pci_bus_region region;
1672 /* Not assigned or rejected by kernel? */
1676 pcibios_resource_to_bus(dev->bus, ®ion, r);
1677 if (!region.start) {
1679 return 1; /* return early from pci_walk_bus() */
1686 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1687 enum enable_type enable_local)
1689 bool unassigned = false;
1691 if (enable_local != undefined)
1692 return enable_local;
1694 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1696 return auto_enabled;
1698 return enable_local;
1701 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1702 enum enable_type enable_local)
1704 return enable_local;
1709 * first try will not touch pci bridge res
1710 * second and later try will clear small leaf bridge res
1711 * will stop till to the max depth if can not find good one
1713 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1715 LIST_HEAD(realloc_head); /* list of resources that
1716 want additional resources */
1717 struct list_head *add_list = NULL;
1718 int tried_times = 0;
1719 enum release_type rel_type = leaf_only;
1720 LIST_HEAD(fail_head);
1721 struct pci_dev_resource *fail_res;
1722 int pci_try_num = 1;
1723 enum enable_type enable_local;
1725 /* don't realloc if asked to do so */
1726 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1727 if (pci_realloc_enabled(enable_local)) {
1728 int max_depth = pci_bus_get_depth(bus);
1730 pci_try_num = max_depth + 1;
1731 dev_printk(KERN_DEBUG, &bus->dev,
1732 "max bus depth: %d pci_try_num: %d\n",
1733 max_depth, pci_try_num);
1738 * last try will use add_list, otherwise will try good to have as
1739 * must have, so can realloc parent bridge resource
1741 if (tried_times + 1 == pci_try_num)
1742 add_list = &realloc_head;
1743 /* Depth first, calculate sizes and alignments of all
1744 subordinate buses. */
1745 __pci_bus_size_bridges(bus, add_list);
1747 /* Depth last, allocate resources and update the hardware. */
1748 __pci_bus_assign_resources(bus, add_list, &fail_head);
1750 BUG_ON(!list_empty(add_list));
1753 /* any device complain? */
1754 if (list_empty(&fail_head))
1757 if (tried_times >= pci_try_num) {
1758 if (enable_local == undefined)
1759 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1760 else if (enable_local == auto_enabled)
1761 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1763 free_list(&fail_head);
1767 dev_printk(KERN_DEBUG, &bus->dev,
1768 "No. %d try to assign unassigned res\n", tried_times + 1);
1770 /* third times and later will not check if it is leaf */
1771 if ((tried_times + 1) > 2)
1772 rel_type = whole_subtree;
1775 * Try to release leaf bridge's resources that doesn't fit resource of
1776 * child device under that bridge
1778 list_for_each_entry(fail_res, &fail_head, list)
1779 pci_bus_release_bridge_resources(fail_res->dev->bus,
1780 fail_res->flags & PCI_RES_TYPE_MASK,
1783 /* restore size and flags */
1784 list_for_each_entry(fail_res, &fail_head, list) {
1785 struct resource *res = fail_res->res;
1788 res->start = fail_res->start;
1789 res->end = fail_res->end;
1790 res->flags = fail_res->flags;
1792 if (pci_is_bridge(fail_res->dev)) {
1793 idx = res - &fail_res->dev->resource[0];
1794 if (idx >= PCI_BRIDGE_RESOURCES &&
1795 idx <= PCI_BRIDGE_RESOURCE_END)
1799 free_list(&fail_head);
1804 /* dump the resource on buses */
1805 pci_bus_dump_resources(bus);
1808 void __init pci_assign_unassigned_resources(void)
1810 struct pci_bus *root_bus;
1812 list_for_each_entry(root_bus, &pci_root_buses, node) {
1813 pci_assign_unassigned_root_bus_resources(root_bus);
1815 /* Make sure the root bridge has a companion ACPI device: */
1816 if (ACPI_HANDLE(root_bus->bridge))
1817 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1821 static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
1822 struct list_head *add_list, resource_size_t available)
1824 struct pci_dev_resource *dev_res;
1829 if (resource_size(res) >= available)
1832 dev_res = res_to_dev_res(add_list, res);
1836 /* Is there room to extend the window? */
1837 if (available - resource_size(res) <= dev_res->add_size)
1840 dev_res->add_size = available - resource_size(res);
1841 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1842 &dev_res->add_size);
1845 static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1846 struct list_head *add_list, resource_size_t available_io,
1847 resource_size_t available_mmio, resource_size_t available_mmio_pref)
1849 resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;
1850 unsigned int normal_bridges = 0, hotplug_bridges = 0;
1851 struct resource *io_res, *mmio_res, *mmio_pref_res;
1852 struct pci_dev *dev, *bridge = bus->self;
1854 io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1855 mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1856 mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1859 * Update additional resource list (add_list) to fill all the
1860 * extra resource space available for this port except the space
1861 * calculated in __pci_bus_size_bridges() which covers all the
1862 * devices currently connected to the port and below.
1864 extend_bridge_window(bridge, io_res, add_list, available_io);
1865 extend_bridge_window(bridge, mmio_res, add_list, available_mmio);
1866 extend_bridge_window(bridge, mmio_pref_res, add_list,
1867 available_mmio_pref);
1870 * Calculate the total amount of extra resource space we can
1871 * pass to bridges below this one. This is basically the
1872 * extra space reduced by the minimal required space for the
1873 * non-hotplug bridges.
1875 remaining_io = available_io;
1876 remaining_mmio = available_mmio;
1877 remaining_mmio_pref = available_mmio_pref;
1880 * Calculate how many hotplug bridges and normal bridges there
1881 * are on this bus. We will distribute the additional available
1882 * resources between hotplug bridges.
1884 for_each_pci_bridge(dev, bus) {
1885 if (dev->is_hotplug_bridge)
1891 for_each_pci_bridge(dev, bus) {
1892 const struct resource *res;
1894 if (dev->is_hotplug_bridge)
1898 * Reduce the available resource space by what the
1899 * bridge and devices below it occupy.
1901 res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
1902 if (!res->parent && available_io > resource_size(res))
1903 remaining_io -= resource_size(res);
1905 res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
1906 if (!res->parent && available_mmio > resource_size(res))
1907 remaining_mmio -= resource_size(res);
1909 res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
1910 if (!res->parent && available_mmio_pref > resource_size(res))
1911 remaining_mmio_pref -= resource_size(res);
1915 * There is only one bridge on the bus so it gets all available
1916 * resources which it can then distribute to the possible
1917 * hotplug bridges below.
1919 if (hotplug_bridges + normal_bridges == 1) {
1920 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
1921 if (dev->subordinate) {
1922 pci_bus_distribute_available_resources(dev->subordinate,
1923 add_list, available_io, available_mmio,
1924 available_mmio_pref);
1930 * Go over devices on this bus and distribute the remaining
1931 * resource space between hotplug bridges.
1933 for_each_pci_bridge(dev, bus) {
1934 resource_size_t align, io, mmio, mmio_pref;
1937 b = dev->subordinate;
1938 if (!b || !dev->is_hotplug_bridge)
1942 * Distribute available extra resources equally between
1943 * hotplug-capable downstream ports taking alignment into
1946 * Here hotplug_bridges is always != 0.
1948 align = pci_resource_alignment(bridge, io_res);
1949 io = div64_ul(available_io, hotplug_bridges);
1950 io = min(ALIGN(io, align), remaining_io);
1953 align = pci_resource_alignment(bridge, mmio_res);
1954 mmio = div64_ul(available_mmio, hotplug_bridges);
1955 mmio = min(ALIGN(mmio, align), remaining_mmio);
1956 remaining_mmio -= mmio;
1958 align = pci_resource_alignment(bridge, mmio_pref_res);
1959 mmio_pref = div64_ul(available_mmio_pref, hotplug_bridges);
1960 mmio_pref = min(ALIGN(mmio_pref, align), remaining_mmio_pref);
1961 remaining_mmio_pref -= mmio_pref;
1963 pci_bus_distribute_available_resources(b, add_list, io, mmio,
1969 pci_bridge_distribute_available_resources(struct pci_dev *bridge,
1970 struct list_head *add_list)
1972 resource_size_t available_io, available_mmio, available_mmio_pref;
1973 const struct resource *res;
1975 if (!bridge->is_hotplug_bridge)
1978 /* Take the initial extra resources from the hotplug port */
1979 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1980 available_io = resource_size(res);
1981 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1982 available_mmio = resource_size(res);
1983 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1984 available_mmio_pref = resource_size(res);
1986 pci_bus_distribute_available_resources(bridge->subordinate,
1987 add_list, available_io, available_mmio, available_mmio_pref);
1990 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1992 struct pci_bus *parent = bridge->subordinate;
1993 LIST_HEAD(add_list); /* list of resources that
1994 want additional resources */
1995 int tried_times = 0;
1996 LIST_HEAD(fail_head);
1997 struct pci_dev_resource *fail_res;
2001 __pci_bus_size_bridges(parent, &add_list);
2004 * Distribute remaining resources (if any) equally between
2005 * hotplug bridges below. This makes it possible to extend the
2006 * hierarchy later without running out of resources.
2008 pci_bridge_distribute_available_resources(bridge, &add_list);
2010 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2011 BUG_ON(!list_empty(&add_list));
2014 if (list_empty(&fail_head))
2017 if (tried_times >= 2) {
2018 /* still fail, don't need to try more */
2019 free_list(&fail_head);
2023 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2027 * Try to release leaf bridge's resources that doesn't fit resource of
2028 * child device under that bridge
2030 list_for_each_entry(fail_res, &fail_head, list)
2031 pci_bus_release_bridge_resources(fail_res->dev->bus,
2032 fail_res->flags & PCI_RES_TYPE_MASK,
2035 /* restore size and flags */
2036 list_for_each_entry(fail_res, &fail_head, list) {
2037 struct resource *res = fail_res->res;
2040 res->start = fail_res->start;
2041 res->end = fail_res->end;
2042 res->flags = fail_res->flags;
2044 if (pci_is_bridge(fail_res->dev)) {
2045 idx = res - &fail_res->dev->resource[0];
2046 if (idx >= PCI_BRIDGE_RESOURCES &&
2047 idx <= PCI_BRIDGE_RESOURCE_END)
2051 free_list(&fail_head);
2056 retval = pci_reenable_device(bridge);
2058 pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2059 pci_set_master(bridge);
2061 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2063 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2065 struct pci_dev_resource *dev_res;
2066 struct pci_dev *next;
2073 /* Walk to the root hub, releasing bridge BARs when possible */
2077 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2079 struct resource *res = &bridge->resource[i];
2081 if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2084 /* Ignore BARs which are still in use */
2088 ret = add_to_list(&saved, bridge, res, 0, 0);
2092 pci_info(bridge, "BAR %d: releasing %pR\n",
2096 release_resource(res);
2101 if (i == PCI_BRIDGE_RESOURCE_END)
2104 next = bridge->bus ? bridge->bus->self : NULL;
2107 if (list_empty(&saved))
2110 __pci_bus_size_bridges(bridge->subordinate, &added);
2111 __pci_bridge_assign_resources(bridge, &added, &failed);
2112 BUG_ON(!list_empty(&added));
2114 if (!list_empty(&failed)) {
2119 list_for_each_entry(dev_res, &saved, list) {
2120 /* Skip the bridge we just assigned resources for. */
2121 if (bridge == dev_res->dev)
2124 bridge = dev_res->dev;
2125 pci_setup_bridge(bridge->subordinate);
2132 /* restore size and flags */
2133 list_for_each_entry(dev_res, &failed, list) {
2134 struct resource *res = dev_res->res;
2136 res->start = dev_res->start;
2137 res->end = dev_res->end;
2138 res->flags = dev_res->flags;
2142 /* Revert to the old configuration */
2143 list_for_each_entry(dev_res, &saved, list) {
2144 struct resource *res = dev_res->res;
2146 bridge = dev_res->dev;
2147 i = res - bridge->resource;
2149 res->start = dev_res->start;
2150 res->end = dev_res->end;
2151 res->flags = dev_res->flags;
2153 pci_claim_resource(bridge, i);
2154 pci_setup_bridge(bridge->subordinate);
2161 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2163 struct pci_dev *dev;
2164 LIST_HEAD(add_list); /* list of resources that
2165 want additional resources */
2167 down_read(&pci_bus_sem);
2168 for_each_pci_bridge(dev, bus)
2169 if (pci_has_subordinate(dev))
2170 __pci_bus_size_bridges(dev->subordinate, &add_list);
2171 up_read(&pci_bus_sem);
2172 __pci_bus_assign_resources(bus, &add_list, NULL);
2173 BUG_ON(!list_empty(&add_list));
2175 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);