1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware
4 * bugs. Devices present only on certain architectures (host
5 * bridges et cetera) should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the
12 * USB quirks file, where their drivers can access reuse it.
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/kallsyms.h>
23 #include <linux/dmi.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/ktime.h>
29 #include <linux/platform_data/x86/apple.h>
30 #include <linux/pm_runtime.h>
31 #include <asm/dma.h> /* isa_dma_bridge_buggy */
35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
36 * conflict. But doing so may cause problems on host bridge and perhaps other
37 * key system devices. For devices that need to have mmio decoding always-on,
38 * we need to set the dev->mmio_always_on bit.
40 static void quirk_mmio_always_on(struct pci_dev *dev)
42 dev->mmio_always_on = 1;
44 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
47 /* The Mellanox Tavor device gives false positive parity errors
48 * Mark this device with a broken_parity_status, to allow
49 * PCI scanning code to "skip" this now blacklisted device.
51 static void quirk_mellanox_tavor(struct pci_dev *dev)
53 dev->broken_parity_status = 1; /* This device gives false positives */
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
58 /* Deal with broken BIOSes that neglect to enable passive release,
59 which can cause problems in combination with the 82441FX/PPro MTRRs */
60 static void quirk_passive_release(struct pci_dev *dev)
62 struct pci_dev *d = NULL;
65 /* We have to make sure a particular bit is set in the PIIX3
66 ISA bridge, so we have to go out and find it. */
67 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
68 pci_read_config_byte(d, 0x82, &dlc);
70 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
72 pci_write_config_byte(d, 0x82, dlc);
76 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
79 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
80 but VIA don't answer queries. If you happen to have good contacts at VIA
81 ask them for me please -- Alan
83 This appears to be BIOS not version dependent. So presumably there is a
86 static void quirk_isa_dma_hangs(struct pci_dev *dev)
88 if (!isa_dma_bridge_buggy) {
89 isa_dma_bridge_buggy = 1;
90 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
94 * Its not totally clear which chipsets are the problematic ones
95 * We know 82C586 and 82C596 variants are affected.
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
107 * for some HT machines to use C4 w/o hanging.
109 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
114 pci_read_config_dword(dev, 0x40, &pmbase);
115 pmbase = pmbase & 0xff80;
119 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
126 * Chipsets where PCI->PCI transfers vanish or hang
128 static void quirk_nopcipci(struct pci_dev *dev)
130 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
132 pci_pci_problems |= PCIPCI_FAIL;
135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
138 static void quirk_nopciamd(struct pci_dev *dev)
141 pci_read_config_byte(dev, 0x08, &rev);
144 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
145 pci_pci_problems |= PCIAGP_FAIL;
148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
151 * Triton requires workarounds to be used by the drivers
153 static void quirk_triton(struct pci_dev *dev)
155 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
157 pci_pci_problems |= PCIPCI_TRITON;
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
166 * VIA Apollo KT133 needs PCI latency patch
167 * Made according to a windows driver based patch by George E. Breese
168 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
169 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
170 * the info on which Mr Breese based his work.
172 * Updated based on further information from the site and also on
173 * information provided by VIA
175 static void quirk_vialatency(struct pci_dev *dev)
179 /* Ok we have a potential problem chipset here. Now see if we have
180 a buggy southbridge */
182 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
184 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
185 /* Check for buggy part revisions */
186 if (p->revision < 0x40 || p->revision > 0x42)
189 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
190 if (p == NULL) /* No problem parts */
192 /* Check for buggy part revisions */
193 if (p->revision < 0x10 || p->revision > 0x12)
198 * Ok we have the problem. Now set the PCI master grant to
199 * occur every master grant. The apparent bug is that under high
200 * PCI load (quite common in Linux of course) you can get data
201 * loss when the CPU is held off the bus for 3 bus master requests
202 * This happens to include the IDE controllers....
204 * VIA only apply this fix when an SB Live! is present but under
205 * both Linux and Windows this isn't enough, and we have seen
206 * corruption without SB Live! but with things like 3 UDMA IDE
207 * controllers. So we ignore that bit of the VIA recommendation..
210 pci_read_config_byte(dev, 0x76, &busarb);
211 /* Set bit 4 and bi 5 of byte 76 to 0x01
212 "Master priority rotation on every PCI master grant */
215 pci_write_config_byte(dev, 0x76, busarb);
216 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
223 /* Must restore this on a resume from RAM */
224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
225 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
226 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
229 * VIA Apollo VP3 needs ETBF on BT848/878
231 static void quirk_viaetbf(struct pci_dev *dev)
233 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
234 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
235 pci_pci_problems |= PCIPCI_VIAETBF;
238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
240 static void quirk_vsfx(struct pci_dev *dev)
242 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
243 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
244 pci_pci_problems |= PCIPCI_VSFX;
247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
250 * Ali Magik requires workarounds to be used by the drivers
251 * that DMA to AGP space. Latency must be set to 0xA and triton
252 * workaround applied too
253 * [Info kindly provided by ALi]
255 static void quirk_alimagik(struct pci_dev *dev)
257 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
258 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
259 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
266 * Natoma has some interesting boundary conditions with Zoran stuff
269 static void quirk_natoma(struct pci_dev *dev)
271 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
272 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
273 pci_pci_problems |= PCIPCI_NATOMA;
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
284 * This chip can cause PCI parity errors if config register 0xA0 is read
285 * while DMAs are occurring.
287 static void quirk_citrine(struct pci_dev *dev)
289 dev->cfg_size = 0xA0;
291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
294 * This chip can cause bus lockups if config addresses above 0x600
295 * are read or written.
297 static void quirk_nfp6000(struct pci_dev *dev)
299 dev->cfg_size = 0x600;
301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
305 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
306 static void quirk_extend_bar_to_page(struct pci_dev *dev)
310 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
311 struct resource *r = &dev->resource[i];
313 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
314 r->end = PAGE_SIZE - 1;
316 r->flags |= IORESOURCE_UNSET;
317 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
325 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
326 * If it's needed, re-allocate the region.
328 static void quirk_s3_64M(struct pci_dev *dev)
330 struct resource *r = &dev->resource[0];
332 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
333 r->flags |= IORESOURCE_UNSET;
338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
341 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
345 struct pci_bus_region bus_region;
346 struct resource *res = dev->resource + pos;
348 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
353 res->name = pci_name(dev);
354 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
356 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
357 region &= ~(size - 1);
359 /* Convert from PCI bus to resource space */
360 bus_region.start = region;
361 bus_region.end = region + size - 1;
362 pcibios_bus_to_resource(dev->bus, res, &bus_region);
364 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
365 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
369 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
370 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
371 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
372 * (which conflicts w/ BAR1's memory range).
374 * CS553x's ISA PCI BARs may also be read-only (ref:
375 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
377 static void quirk_cs5536_vsa(struct pci_dev *dev)
379 static char *name = "CS5536 ISA bridge";
381 if (pci_resource_len(dev, 0) != 8) {
382 quirk_io(dev, 0, 8, name); /* SMB */
383 quirk_io(dev, 1, 256, name); /* GPIO */
384 quirk_io(dev, 2, 64, name); /* MFGPT */
385 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
389 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
391 static void quirk_io_region(struct pci_dev *dev, int port,
392 unsigned size, int nr, const char *name)
395 struct pci_bus_region bus_region;
396 struct resource *res = dev->resource + nr;
398 pci_read_config_word(dev, port, ®ion);
399 region &= ~(size - 1);
404 res->name = pci_name(dev);
405 res->flags = IORESOURCE_IO;
407 /* Convert from PCI bus to resource space */
408 bus_region.start = region;
409 bus_region.end = region + size - 1;
410 pcibios_bus_to_resource(dev->bus, res, &bus_region);
412 if (!pci_claim_resource(dev, nr))
413 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
417 * ATI Northbridge setups MCE the processor if you even
418 * read somewhere between 0x3b0->0x3bb or read 0x3d3
420 static void quirk_ati_exploding_mce(struct pci_dev *dev)
422 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
423 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
424 request_region(0x3b0, 0x0C, "RadeonIGP");
425 request_region(0x3d3, 0x01, "RadeonIGP");
427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
430 * In the AMD NL platform, this device ([1022:7912]) has a class code of
431 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
433 * But the dwc3 driver is a more specific driver for this device, and we'd
434 * prefer to use it instead of xhci. To prevent xhci from claiming the
435 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
436 * defines as "USB device (not host controller)". The dwc3 driver can then
437 * claim it based on its Vendor and Device ID.
439 static void quirk_amd_nl_class(struct pci_dev *pdev)
441 u32 class = pdev->class;
443 /* Use "USB Device (not host controller)" class */
444 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
445 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
452 * Let's make the southbridge information explicit instead
453 * of having to worry about people probing the ACPI areas,
454 * for example.. (Yes, it happens, and if you read the wrong
455 * ACPI register it will put the machine to sleep with no
456 * way of waking it up again. Bummer).
458 * ALI M7101: Two IO regions pointed to by words at
459 * 0xE0 (64 bytes of ACPI registers)
460 * 0xE2 (32 bytes of SMB registers)
462 static void quirk_ali7101_acpi(struct pci_dev *dev)
464 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
465 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
469 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
472 u32 mask, size, base;
474 pci_read_config_dword(dev, port, &devres);
475 if ((devres & enable) != enable)
477 mask = (devres >> 16) & 15;
478 base = devres & 0xffff;
481 unsigned bit = size >> 1;
482 if ((bit & mask) == bit)
487 * For now we only print it out. Eventually we'll want to
488 * reserve it (at least if it's in the 0x1000+ range), but
489 * let's get enough confirmation reports first.
492 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
496 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
499 u32 mask, size, base;
501 pci_read_config_dword(dev, port, &devres);
502 if ((devres & enable) != enable)
504 base = devres & 0xffff0000;
505 mask = (devres & 0x3f) << 16;
508 unsigned bit = size >> 1;
509 if ((bit & mask) == bit)
514 * For now we only print it out. Eventually we'll want to
515 * reserve it, but let's get enough confirmation reports first.
518 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
523 * PIIX4 ACPI: Two IO regions pointed to by longwords at
524 * 0x40 (64 bytes of ACPI registers)
525 * 0x90 (16 bytes of SMB registers)
526 * and a few strange programmable PIIX4 device resources.
528 static void quirk_piix4_acpi(struct pci_dev *dev)
532 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
533 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
535 /* Device resource A has enables for some of the other ones */
536 pci_read_config_dword(dev, 0x5c, &res_a);
538 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
539 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
541 /* Device resource D is just bitfields for static resources */
543 /* Device 12 enabled? */
544 if (res_a & (1 << 29)) {
545 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
546 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
548 /* Device 13 enabled? */
549 if (res_a & (1 << 30)) {
550 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
551 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
553 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
554 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
557 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
559 #define ICH_PMBASE 0x40
560 #define ICH_ACPI_CNTL 0x44
561 #define ICH4_ACPI_EN 0x10
562 #define ICH6_ACPI_EN 0x80
563 #define ICH4_GPIOBASE 0x58
564 #define ICH4_GPIO_CNTL 0x5c
565 #define ICH4_GPIO_EN 0x10
566 #define ICH6_GPIOBASE 0x48
567 #define ICH6_GPIO_CNTL 0x4c
568 #define ICH6_GPIO_EN 0x10
571 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
572 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
573 * 0x58 (64 bytes of GPIO I/O space)
575 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
580 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
581 * with low legacy (and fixed) ports. We don't know the decoding
582 * priority and can't tell whether the legacy device or the one created
583 * here is really at that address. This happens on boards with broken
587 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
588 if (enable & ICH4_ACPI_EN)
589 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
590 "ICH4 ACPI/GPIO/TCO");
592 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
593 if (enable & ICH4_GPIO_EN)
594 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
606 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
608 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
612 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
613 if (enable & ICH6_ACPI_EN)
614 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
615 "ICH6 ACPI/GPIO/TCO");
617 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
618 if (enable & ICH6_GPIO_EN)
619 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
623 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
628 pci_read_config_dword(dev, reg, &val);
636 * This is not correct. It is 16, 32 or 64 bytes depending on
637 * register D31:F0:ADh bits 5:4.
639 * But this gets us at least _part_ of it.
647 /* Just print it out for now. We should reserve it after more debugging */
648 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
651 static void quirk_ich6_lpc(struct pci_dev *dev)
653 /* Shared ACPI/GPIO decode with all ICH6+ */
654 ich6_lpc_acpi_gpio(dev);
656 /* ICH6-specific generic IO decode */
657 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
658 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
663 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
668 pci_read_config_dword(dev, reg, &val);
675 * IO base in bits 15:2, mask in bits 23:18, both
679 mask = (val >> 16) & 0xfc;
682 /* Just print it out for now. We should reserve it after more debugging */
683 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
686 /* ICH7-10 has the same common LPC generic IO decode registers */
687 static void quirk_ich7_lpc(struct pci_dev *dev)
689 /* We share the common ACPI/GPIO decode with ICH6 */
690 ich6_lpc_acpi_gpio(dev);
692 /* And have 4 ICH7+ generic decodes */
693 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
694 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
695 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
696 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
708 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
709 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
710 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
713 * VIA ACPI: One IO region pointed to by longword at
714 * 0x48 or 0x20 (256 bytes of ACPI registers)
716 static void quirk_vt82c586_acpi(struct pci_dev *dev)
718 if (dev->revision & 0x10)
719 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
722 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
725 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
726 * 0x48 (256 bytes of ACPI registers)
727 * 0x70 (128 bytes of hardware monitoring register)
728 * 0x90 (16 bytes of SMB registers)
730 static void quirk_vt82c686_acpi(struct pci_dev *dev)
732 quirk_vt82c586_acpi(dev);
734 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
737 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
739 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
742 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
743 * 0x88 (128 bytes of power management registers)
744 * 0xd0 (16 bytes of SMB registers)
746 static void quirk_vt8235_acpi(struct pci_dev *dev)
748 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
749 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
751 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
754 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
755 * Disable fast back-to-back on the secondary bus segment
757 static void quirk_xio2000a(struct pci_dev *dev)
759 struct pci_dev *pdev;
762 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
763 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
764 pci_read_config_word(pdev, PCI_COMMAND, &command);
765 if (command & PCI_COMMAND_FAST_BACK)
766 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
769 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
772 #ifdef CONFIG_X86_IO_APIC
774 #include <asm/io_apic.h>
777 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
778 * devices to the external APIC.
780 * TODO: When we have device-specific interrupt routers,
781 * this code will go away from quirks.
783 static void quirk_via_ioapic(struct pci_dev *dev)
788 tmp = 0; /* nothing routed to external APIC */
790 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
792 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
793 tmp == 0 ? "Disa" : "Ena");
795 /* Offset 0x58: External APIC IRQ output control */
796 pci_write_config_byte(dev, 0x58, tmp);
798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
799 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
802 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
803 * This leads to doubled level interrupt rates.
804 * Set this bit to get rid of cycle wastage.
805 * Otherwise uncritical.
807 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
810 #define BYPASS_APIC_DEASSERT 8
812 pci_read_config_byte(dev, 0x5B, &misc_control2);
813 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
814 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
815 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
819 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
822 * The AMD io apic can hang the box when an apic irq is masked.
823 * We check all revs >= B0 (yet not in the pre production!) as the bug
824 * is currently marked NoFix
826 * We have multiple reports of hangs with this chipset that went away with
827 * noapic specified. For the moment we assume it's the erratum. We may be wrong
828 * of course. However the advice is demonstrably good even if so..
830 static void quirk_amd_ioapic(struct pci_dev *dev)
832 if (dev->revision >= 0x02) {
833 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
834 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
838 #endif /* CONFIG_X86_IO_APIC */
840 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
842 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
844 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
845 if (dev->subsystem_device == 0xa118)
846 dev->sriov->link = dev->devfn;
848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
852 * Some settings of MMRBC can lead to data corruption so block changes.
853 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
855 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
857 if (dev->subordinate && dev->revision <= 0x12) {
858 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
860 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
866 * FIXME: it is questionable that quirk_via_acpi
867 * is needed. It shows up as an ISA bridge, and does not
868 * support the PCI_INTERRUPT_LINE register at all. Therefore
869 * it seems like setting the pci_dev's 'irq' to the
870 * value of the ACPI SCI interrupt is only done for convenience.
873 static void quirk_via_acpi(struct pci_dev *d)
876 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
879 pci_read_config_byte(d, 0x42, &irq);
881 if (irq && (irq != 2))
884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
889 * VIA bridges which have VLink
892 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
894 static void quirk_via_bridge(struct pci_dev *dev)
896 /* See what bridge we have and find the device ranges */
897 switch (dev->device) {
898 case PCI_DEVICE_ID_VIA_82C686:
899 /* The VT82C686 is special, it attaches to PCI and can have
900 any device number. All its subdevices are functions of
901 that single device. */
902 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
903 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
905 case PCI_DEVICE_ID_VIA_8237:
906 case PCI_DEVICE_ID_VIA_8237A:
907 via_vlink_dev_lo = 15;
909 case PCI_DEVICE_ID_VIA_8235:
910 via_vlink_dev_lo = 16;
912 case PCI_DEVICE_ID_VIA_8231:
913 case PCI_DEVICE_ID_VIA_8233_0:
914 case PCI_DEVICE_ID_VIA_8233A:
915 case PCI_DEVICE_ID_VIA_8233C_0:
916 via_vlink_dev_lo = 17;
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
927 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
930 * quirk_via_vlink - VIA VLink IRQ number update
933 * If the device we are dealing with is on a PIC IRQ we need to
934 * ensure that the IRQ line register which usually is not relevant
935 * for PCI cards, is actually written so that interrupts get sent
936 * to the right place.
937 * We only do this on systems where a VIA south bridge was detected,
938 * and only for VIA devices on the motherboard (see quirk_via_bridge
942 static void quirk_via_vlink(struct pci_dev *dev)
946 /* Check if we have VLink at all */
947 if (via_vlink_dev_lo == -1)
952 /* Don't quirk interrupts outside the legacy IRQ range */
953 if (!new_irq || new_irq > 15)
956 /* Internal device ? */
957 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
958 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
961 /* This is an internal VLink device on a PIC interrupt. The BIOS
962 ought to have set this but may not have, so we redo it */
964 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
965 if (new_irq != irq) {
966 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
968 udelay(15); /* unknown if delay really needed */
969 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
972 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
975 * VIA VT82C598 has its device ID settable and many BIOSes
976 * set it to the ID of VT82C597 for backward compatibility.
977 * We need to switch it off to be able to recognize the real
980 static void quirk_vt82c598_id(struct pci_dev *dev)
982 pci_write_config_byte(dev, 0xfc, 0);
983 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
988 * CardBus controllers have a legacy base address that enables them
989 * to respond as i82365 pcmcia controllers. We don't want them to
990 * do this even if the Linux CardBus driver is not loaded, because
991 * the Linux i82365 driver does not (and should not) handle CardBus.
993 static void quirk_cardbus_legacy(struct pci_dev *dev)
995 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
997 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
998 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
999 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1000 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1003 * Following the PCI ordering rules is optional on the AMD762. I'm not
1004 * sure what the designers were smoking but let's not inhale...
1006 * To be fair to AMD, it follows the spec by default, its BIOS people
1009 static void quirk_amd_ordering(struct pci_dev *dev)
1012 pci_read_config_dword(dev, 0x4C, &pcic);
1013 if ((pcic & 6) != 6) {
1015 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1016 pci_write_config_dword(dev, 0x4C, pcic);
1017 pci_read_config_dword(dev, 0x84, &pcic);
1018 pcic |= (1 << 23); /* Required in this mode */
1019 pci_write_config_dword(dev, 0x84, pcic);
1022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1023 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1026 * DreamWorks provided workaround for Dunord I-3000 problem
1028 * This card decodes and responds to addresses not apparently
1029 * assigned to it. We force a larger allocation to ensure that
1030 * nothing gets put too close to it.
1032 static void quirk_dunord(struct pci_dev *dev)
1034 struct resource *r = &dev->resource[1];
1036 r->flags |= IORESOURCE_UNSET;
1040 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1043 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1044 * is subtractive decoding (transparent), and does indicate this
1045 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1048 static void quirk_transparent_bridge(struct pci_dev *dev)
1050 dev->transparent = 1;
1052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1056 * Common misconfiguration of the MediaGX/Geode PCI master that will
1057 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1058 * datasheets found at http://www.national.com/analog for info on what
1059 * these bits do. <christer@weinigel.se>
1061 static void quirk_mediagx_master(struct pci_dev *dev)
1065 pci_read_config_byte(dev, 0x41, ®);
1068 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1070 pci_write_config_byte(dev, 0x41, reg);
1073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1074 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1077 * Ensure C0 rev restreaming is off. This is normally done by
1078 * the BIOS but in the odd case it is not the results are corruption
1079 * hence the presence of a Linux check
1081 static void quirk_disable_pxb(struct pci_dev *pdev)
1085 if (pdev->revision != 0x04) /* Only C0 requires this */
1087 pci_read_config_word(pdev, 0x40, &config);
1088 if (config & (1<<6)) {
1090 pci_write_config_word(pdev, 0x40, config);
1091 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1095 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1097 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1099 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1102 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1104 pci_read_config_byte(pdev, 0x40, &tmp);
1105 pci_write_config_byte(pdev, 0x40, tmp|1);
1106 pci_write_config_byte(pdev, 0x9, 1);
1107 pci_write_config_byte(pdev, 0xa, 6);
1108 pci_write_config_byte(pdev, 0x40, tmp);
1110 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1111 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1115 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1117 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1119 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1121 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1124 * Serverworks CSB5 IDE does not fully support native mode
1126 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1129 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1133 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1134 /* PCI layer will sort out resources */
1137 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1140 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1142 static void quirk_ide_samemode(struct pci_dev *pdev)
1146 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1148 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1149 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1152 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1155 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1158 * Some ATA devices break if put into D3
1161 static void quirk_no_ata_d3(struct pci_dev *pdev)
1163 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1165 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1166 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1167 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1168 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1169 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1170 /* ALi loses some register settings that we cannot then restore */
1171 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1172 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1173 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1174 occur when mode detecting */
1175 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1176 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1178 /* This was originally an Alpha specific thing, but it really fits here.
1179 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1181 static void quirk_eisa_bridge(struct pci_dev *dev)
1183 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1189 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1190 * is not activated. The myth is that Asus said that they do not want the
1191 * users to be irritated by just another PCI Device in the Win98 device
1192 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1193 * package 2.7.0 for details)
1195 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1196 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1197 * becomes necessary to do this tweak in two steps -- the chosen trigger
1198 * is either the Host bridge (preferred) or on-board VGA controller.
1200 * Note that we used to unhide the SMBus that way on Toshiba laptops
1201 * (Satellite A40 and Tecra M2) but then found that the thermal management
1202 * was done by SMM code, which could cause unsynchronized concurrent
1203 * accesses to the SMBus registers, with potentially bad effects. Thus you
1204 * should be very careful when adding new entries: if SMM is accessing the
1205 * Intel SMBus, this is a very good reason to leave it hidden.
1207 * Likewise, many recent laptops use ACPI for thermal management. If the
1208 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1209 * natively, and keeping the SMBus hidden is the right thing to do. If you
1210 * are about to add an entry in the table below, please first disassemble
1211 * the DSDT and double-check that there is no code accessing the SMBus.
1213 static int asus_hides_smbus;
1215 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1217 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1218 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1219 switch (dev->subsystem_device) {
1220 case 0x8025: /* P4B-LX */
1221 case 0x8070: /* P4B */
1222 case 0x8088: /* P4B533 */
1223 case 0x1626: /* L3C notebook */
1224 asus_hides_smbus = 1;
1226 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1227 switch (dev->subsystem_device) {
1228 case 0x80b1: /* P4GE-V */
1229 case 0x80b2: /* P4PE */
1230 case 0x8093: /* P4B533-V */
1231 asus_hides_smbus = 1;
1233 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1234 switch (dev->subsystem_device) {
1235 case 0x8030: /* P4T533 */
1236 asus_hides_smbus = 1;
1238 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1239 switch (dev->subsystem_device) {
1240 case 0x8070: /* P4G8X Deluxe */
1241 asus_hides_smbus = 1;
1243 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1244 switch (dev->subsystem_device) {
1245 case 0x80c9: /* PU-DLS */
1246 asus_hides_smbus = 1;
1248 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1249 switch (dev->subsystem_device) {
1250 case 0x1751: /* M2N notebook */
1251 case 0x1821: /* M5N notebook */
1252 case 0x1897: /* A6L notebook */
1253 asus_hides_smbus = 1;
1255 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1256 switch (dev->subsystem_device) {
1257 case 0x184b: /* W1N notebook */
1258 case 0x186a: /* M6Ne notebook */
1259 asus_hides_smbus = 1;
1261 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1262 switch (dev->subsystem_device) {
1263 case 0x80f2: /* P4P800-X */
1264 asus_hides_smbus = 1;
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1267 switch (dev->subsystem_device) {
1268 case 0x1882: /* M6V notebook */
1269 case 0x1977: /* A6VA notebook */
1270 asus_hides_smbus = 1;
1272 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1273 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1274 switch (dev->subsystem_device) {
1275 case 0x088C: /* HP Compaq nc8000 */
1276 case 0x0890: /* HP Compaq nc6000 */
1277 asus_hides_smbus = 1;
1279 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1280 switch (dev->subsystem_device) {
1281 case 0x12bc: /* HP D330L */
1282 case 0x12bd: /* HP D530 */
1283 case 0x006a: /* HP Compaq nx9500 */
1284 asus_hides_smbus = 1;
1286 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1287 switch (dev->subsystem_device) {
1288 case 0x12bf: /* HP xw4100 */
1289 asus_hides_smbus = 1;
1291 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1292 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1293 switch (dev->subsystem_device) {
1294 case 0xC00C: /* Samsung P35 notebook */
1295 asus_hides_smbus = 1;
1297 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1298 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1299 switch (dev->subsystem_device) {
1300 case 0x0058: /* Compaq Evo N620c */
1301 asus_hides_smbus = 1;
1303 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1304 switch (dev->subsystem_device) {
1305 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1306 /* Motherboard doesn't have Host bridge
1307 * subvendor/subdevice IDs, therefore checking
1308 * its on-board VGA controller */
1309 asus_hides_smbus = 1;
1311 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1312 switch (dev->subsystem_device) {
1313 case 0x00b8: /* Compaq Evo D510 CMT */
1314 case 0x00b9: /* Compaq Evo D510 SFF */
1315 case 0x00ba: /* Compaq Evo D510 USDT */
1316 /* Motherboard doesn't have Host bridge
1317 * subvendor/subdevice IDs and on-board VGA
1318 * controller is disabled if an AGP card is
1319 * inserted, therefore checking USB UHCI
1321 asus_hides_smbus = 1;
1323 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1324 switch (dev->subsystem_device) {
1325 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1326 /* Motherboard doesn't have host bridge
1327 * subvendor/subdevice IDs, therefore checking
1328 * its on-board VGA controller */
1329 asus_hides_smbus = 1;
1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1348 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1352 if (likely(!asus_hides_smbus))
1355 pci_read_config_word(dev, 0xF2, &val);
1357 pci_write_config_word(dev, 0xF2, val & (~0x8));
1358 pci_read_config_word(dev, 0xF2, &val);
1360 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1363 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1377 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1378 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1379 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1381 /* It appears we just have one such device. If not, we have a warning */
1382 static void __iomem *asus_rcba_base;
1383 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1387 if (likely(!asus_hides_smbus))
1389 WARN_ON(asus_rcba_base);
1391 pci_read_config_dword(dev, 0xF0, &rcba);
1392 /* use bits 31:14, 16 kB aligned */
1393 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1394 if (asus_rcba_base == NULL)
1398 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1402 if (likely(!asus_hides_smbus || !asus_rcba_base))
1404 /* read the Function Disable register, dword mode only */
1405 val = readl(asus_rcba_base + 0x3418);
1406 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1409 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1411 if (likely(!asus_hides_smbus || !asus_rcba_base))
1413 iounmap(asus_rcba_base);
1414 asus_rcba_base = NULL;
1415 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1418 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1420 asus_hides_smbus_lpc_ich6_suspend(dev);
1421 asus_hides_smbus_lpc_ich6_resume_early(dev);
1422 asus_hides_smbus_lpc_ich6_resume(dev);
1424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1425 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1426 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1427 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1430 * SiS 96x south bridge: BIOS typically hides SMBus device...
1432 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1435 pci_read_config_byte(dev, 0x77, &val);
1437 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1438 pci_write_config_byte(dev, 0x77, val & ~0x10);
1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1446 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1447 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1448 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1451 * ... This is further complicated by the fact that some SiS96x south
1452 * bridges pretend to be 85C503/5513 instead. In that case see if we
1453 * spotted a compatible north bridge to make sure.
1454 * (pci_find_device doesn't work yet)
1456 * We can also enable the sis96x bit in the discovery register..
1458 #define SIS_DETECT_REGISTER 0x40
1460 static void quirk_sis_503(struct pci_dev *dev)
1465 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1467 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1468 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1469 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1474 * Ok, it now shows up as a 96x.. run the 96x quirk by
1475 * hand in case it has already been processed.
1476 * (depends on link order, which is apparently not guaranteed)
1478 dev->device = devid;
1479 quirk_sis_96x_smbus(dev);
1481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1482 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1486 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1487 * and MC97 modem controller are disabled when a second PCI soundcard is
1488 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1491 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1494 int asus_hides_ac97 = 0;
1496 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1497 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1498 asus_hides_ac97 = 1;
1501 if (!asus_hides_ac97)
1504 pci_read_config_byte(dev, 0x50, &val);
1506 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1507 pci_read_config_byte(dev, 0x50, &val);
1509 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1512 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1516 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1518 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1521 * If we are using libata we can drive this chip properly but must
1522 * do this early on to make the additional device appear during
1525 static void quirk_jmicron_ata(struct pci_dev *pdev)
1527 u32 conf1, conf5, class;
1530 /* Only poke fn 0 */
1531 if (PCI_FUNC(pdev->devfn))
1534 pci_read_config_dword(pdev, 0x40, &conf1);
1535 pci_read_config_dword(pdev, 0x80, &conf5);
1537 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1538 conf5 &= ~(1 << 24); /* Clear bit 24 */
1540 switch (pdev->device) {
1541 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1542 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1543 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1544 /* The controller should be in single function ahci mode */
1545 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1548 case PCI_DEVICE_ID_JMICRON_JMB365:
1549 case PCI_DEVICE_ID_JMICRON_JMB366:
1550 /* Redirect IDE second PATA port to the right spot */
1553 case PCI_DEVICE_ID_JMICRON_JMB361:
1554 case PCI_DEVICE_ID_JMICRON_JMB363:
1555 case PCI_DEVICE_ID_JMICRON_JMB369:
1556 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1557 /* Set the class codes correctly and then direct IDE 0 */
1558 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1561 case PCI_DEVICE_ID_JMICRON_JMB368:
1562 /* The controller should be in single function IDE mode */
1563 conf1 |= 0x00C00000; /* Set 22, 23 */
1567 pci_write_config_dword(pdev, 0x40, conf1);
1568 pci_write_config_dword(pdev, 0x80, conf5);
1570 /* Update pdev accordingly */
1571 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1572 pdev->hdr_type = hdr & 0x7f;
1573 pdev->multifunction = !!(hdr & 0x80);
1575 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1576 pdev->class = class >> 8;
1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1593 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1594 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1595 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1599 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1601 if (dev->multifunction) {
1602 device_disable_async_suspend(&dev->dev);
1603 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1606 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1607 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1611 #ifdef CONFIG_X86_IO_APIC
1612 static void quirk_alder_ioapic(struct pci_dev *pdev)
1616 if ((pdev->class >> 8) != 0xff00)
1619 /* the first BAR is the location of the IO APIC...we must
1620 * not touch this (and it's already covered by the fixmap), so
1621 * forcibly insert it into the resource tree */
1622 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1623 insert_resource(&iomem_resource, &pdev->resource[0]);
1625 /* The next five BARs all seem to be rubbish, so just clean
1627 for (i = 1; i < 6; i++)
1628 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1633 static void quirk_pcie_mch(struct pci_dev *pdev)
1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1641 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1644 * It's possible for the MSI to get corrupted if shpc and acpi
1645 * are used together on certain PXH-based systems.
1647 static void quirk_pcie_pxh(struct pci_dev *dev)
1650 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1654 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1655 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1656 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1659 * Some Intel PCI Express chipsets have trouble with downstream
1660 * device power management.
1662 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1664 pci_pm_d3_delay = 120;
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1690 static void quirk_radeon_pm(struct pci_dev *dev)
1692 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1693 dev->subsystem_device == 0x00e2) {
1694 if (dev->d3_delay < 20) {
1696 dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n",
1701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1703 #ifdef CONFIG_X86_IO_APIC
1704 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1706 noioapicreroute = 1;
1707 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1712 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1714 * Systems to exclude from boot interrupt reroute quirks
1717 .callback = dmi_disable_ioapicreroute,
1718 .ident = "ASUSTek Computer INC. M2N-LR",
1720 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1721 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1728 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1729 * remap the original interrupt in the linux kernel to the boot interrupt, so
1730 * that a PCI device's interrupt handler is installed on the boot interrupt
1733 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1735 dmi_check_system(boot_interrupt_dmi_table);
1736 if (noioapicquirk || noioapicreroute)
1739 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1740 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1741 dev->vendor, dev->device);
1743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1748 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1749 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1750 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1751 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1752 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1753 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1754 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1755 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1756 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1757 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1758 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1761 * On some chipsets we can disable the generation of legacy INTx boot
1766 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1767 * 300641-004US, section 5.7.3.
1769 #define INTEL_6300_IOAPIC_ABAR 0x40
1770 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1772 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1774 u16 pci_config_word;
1779 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1780 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1781 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1783 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1784 dev->vendor, dev->device);
1786 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1787 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1790 * disable boot interrupts on HT-1000
1792 #define BC_HT1000_FEATURE_REG 0x64
1793 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1794 #define BC_HT1000_MAP_IDX 0xC00
1795 #define BC_HT1000_MAP_DATA 0xC01
1797 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1799 u32 pci_config_dword;
1805 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1806 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1807 BC_HT1000_PIC_REGS_ENABLE);
1809 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1810 outb(irq, BC_HT1000_MAP_IDX);
1811 outb(0x00, BC_HT1000_MAP_DATA);
1814 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1816 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1817 dev->vendor, dev->device);
1819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1820 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1823 * disable boot interrupts on AMD and ATI chipsets
1826 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1827 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1828 * (due to an erratum).
1830 #define AMD_813X_MISC 0x40
1831 #define AMD_813X_NOIOAMODE (1<<0)
1832 #define AMD_813X_REV_B1 0x12
1833 #define AMD_813X_REV_B2 0x13
1835 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1837 u32 pci_config_dword;
1841 if ((dev->revision == AMD_813X_REV_B1) ||
1842 (dev->revision == AMD_813X_REV_B2))
1845 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1846 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1847 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1849 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1850 dev->vendor, dev->device);
1852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1853 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1855 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1857 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1859 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1861 u16 pci_config_word;
1866 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1867 if (!pci_config_word) {
1868 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1869 dev->vendor, dev->device);
1872 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1873 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1874 dev->vendor, dev->device);
1876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1877 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1878 #endif /* CONFIG_X86_IO_APIC */
1881 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1882 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1883 * Re-allocate the region if needed...
1885 static void quirk_tc86c001_ide(struct pci_dev *dev)
1887 struct resource *r = &dev->resource[0];
1889 if (r->start & 0x8) {
1890 r->flags |= IORESOURCE_UNSET;
1895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1896 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1897 quirk_tc86c001_ide);
1900 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1901 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1902 * being read correctly if bit 7 of the base address is set.
1903 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1904 * Re-allocate the regions to a 256-byte boundary if necessary.
1906 static void quirk_plx_pci9050(struct pci_dev *dev)
1910 /* Fixed in revision 2 (PCI 9052). */
1911 if (dev->revision >= 2)
1913 for (bar = 0; bar <= 1; bar++)
1914 if (pci_resource_len(dev, bar) == 0x80 &&
1915 (pci_resource_start(dev, bar) & 0x80)) {
1916 struct resource *r = &dev->resource[bar];
1917 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1919 r->flags |= IORESOURCE_UNSET;
1924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1927 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1928 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1929 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1930 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1932 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1935 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1936 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1938 static void quirk_netmos(struct pci_dev *dev)
1940 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1941 unsigned int num_serial = dev->subsystem_device & 0xf;
1944 * These Netmos parts are multiport serial devices with optional
1945 * parallel ports. Even when parallel ports are present, they
1946 * are identified as class SERIAL, which means the serial driver
1947 * will claim them. To prevent this, mark them as class OTHER.
1948 * These combo devices should be claimed by parport_serial.
1950 * The subdevice ID is of the form 0x00PS, where <P> is the number
1951 * of parallel ports and <S> is the number of serial ports.
1953 switch (dev->device) {
1954 case PCI_DEVICE_ID_NETMOS_9835:
1955 /* Well, this rule doesn't hold for the following 9835 device */
1956 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1957 dev->subsystem_device == 0x0299)
1959 case PCI_DEVICE_ID_NETMOS_9735:
1960 case PCI_DEVICE_ID_NETMOS_9745:
1961 case PCI_DEVICE_ID_NETMOS_9845:
1962 case PCI_DEVICE_ID_NETMOS_9855:
1964 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1965 dev->device, num_parallel, num_serial);
1966 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1967 (dev->class & 0xff);
1971 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1972 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1975 * Quirk non-zero PCI functions to route VPD access through function 0 for
1976 * devices that share VPD resources between functions. The functions are
1977 * expected to be identical devices.
1979 static void quirk_f0_vpd_link(struct pci_dev *dev)
1983 if (!PCI_FUNC(dev->devfn))
1986 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1990 if (f0->vpd && dev->class == f0->class &&
1991 dev->vendor == f0->vendor && dev->device == f0->device)
1992 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1996 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1997 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1999 static void quirk_e100_interrupt(struct pci_dev *dev)
2005 switch (dev->device) {
2006 /* PCI IDs taken from drivers/net/e100.c */
2008 case 0x1030 ... 0x1034:
2009 case 0x1038 ... 0x103E:
2010 case 0x1050 ... 0x1057:
2012 case 0x1064 ... 0x106B:
2013 case 0x1091 ... 0x1095:
2026 * Some firmware hands off the e100 with interrupts enabled,
2027 * which can cause a flood of interrupts if packets are
2028 * received before the driver attaches to the device. So
2029 * disable all e100 interrupts here. The driver will
2030 * re-enable them when it's ready.
2032 pci_read_config_word(dev, PCI_COMMAND, &command);
2034 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2038 * Check that the device is in the D0 power state. If it's not,
2039 * there is no point to look any further.
2042 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2043 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2047 /* Convert from PCI bus to resource space. */
2048 csr = ioremap(pci_resource_start(dev, 0), 8);
2050 dev_warn(&dev->dev, "Can't map e100 registers\n");
2054 cmd_hi = readb(csr + 3);
2056 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2062 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2063 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2066 * The 82575 and 82598 may experience data corruption issues when transitioning
2067 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2069 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2071 dev_info(&dev->dev, "Disabling L0s\n");
2072 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2087 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2089 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2091 pci_info(dev, "Disabling ASPM L0s/L1\n");
2092 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2096 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2097 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2098 * disable both L0s and L1 for now to be safe.
2100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2103 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2104 * Link bit cleared after starting the link retrain process to allow this
2105 * process to finish.
2107 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2108 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2110 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2112 dev->clear_retrain_link = 1;
2113 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2115 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2116 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2117 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2119 static void fixup_rev1_53c810(struct pci_dev *dev)
2121 u32 class = dev->class;
2124 * rev 1 ncr53c810 chips don't set the class at all which means
2125 * they don't get their resources remapped. Fix that here.
2130 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2131 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2136 /* Enable 1k I/O space granularity on the Intel P64H2 */
2137 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2141 pci_read_config_word(dev, 0x40, &en1k);
2144 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2145 dev->io_window_1k = 1;
2148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2150 /* Under some circumstances, AER is not linked with extended capabilities.
2151 * Force it to be linked by setting the corresponding control bit in the
2154 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2157 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2159 pci_write_config_byte(dev, 0xf41, b | 0x20);
2160 dev_info(&dev->dev, "Linking AER extended capability\n");
2164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2165 quirk_nvidia_ck804_pcie_aer_ext_cap);
2166 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2167 quirk_nvidia_ck804_pcie_aer_ext_cap);
2169 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2172 * Disable PCI Bus Parking and PCI Master read caching on CX700
2173 * which causes unspecified timing errors with a VT6212L on the PCI
2174 * bus leading to USB2.0 packet loss.
2176 * This quirk is only enabled if a second (on the external PCI bus)
2177 * VT6212L is found -- the CX700 core itself also contains a USB
2178 * host controller with the same PCI ID as the VT6212L.
2181 /* Count VT6212L instances */
2182 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2183 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2186 /* p should contain the first (internal) VT6212L -- see if we have
2187 an external one by searching again */
2188 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2193 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2195 /* Turn off PCI Bus Parking */
2196 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2198 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2202 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2204 /* Turn off PCI Master read caching */
2205 pci_write_config_byte(dev, 0x72, 0x0);
2207 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2208 pci_write_config_byte(dev, 0x75, 0x1);
2210 /* Disable "Read FIFO Timer" */
2211 pci_write_config_byte(dev, 0x77, 0x0);
2213 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2220 * If a device follows the VPD format spec, the PCI core will not read or
2221 * write past the VPD End Tag. But some vendors do not follow the VPD
2222 * format spec, so we can't tell how much data is safe to access. Devices
2223 * may behave unpredictably if we access too much. Blacklist these devices
2224 * so we don't touch VPD at all.
2226 static void quirk_blacklist_vpd(struct pci_dev *dev)
2230 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2246 quirk_blacklist_vpd);
2247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2250 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2251 * VPD end tag will hang the device. This problem was initially
2252 * observed when a vpd entry was created in sysfs
2253 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2254 * will dump 32k of data. Reading a full 32k will cause an access
2255 * beyond the VPD end tag causing the device to hang. Once the device
2256 * is hung, the bnx2 driver will not be able to reset the device.
2257 * We believe that it is legal to read beyond the end tag and
2258 * therefore the solution is to limit the read/write length.
2260 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2263 * Only disable the VPD capability for 5706, 5706S, 5708,
2264 * 5708S and 5709 rev. A
2266 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2267 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2268 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2269 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2270 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2271 (dev->revision & 0xf0) == 0x0)) {
2273 dev->vpd->len = 0x80;
2277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2278 PCI_DEVICE_ID_NX2_5706,
2279 quirk_brcm_570x_limit_vpd);
2280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2281 PCI_DEVICE_ID_NX2_5706S,
2282 quirk_brcm_570x_limit_vpd);
2283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2284 PCI_DEVICE_ID_NX2_5708,
2285 quirk_brcm_570x_limit_vpd);
2286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2287 PCI_DEVICE_ID_NX2_5708S,
2288 quirk_brcm_570x_limit_vpd);
2289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2290 PCI_DEVICE_ID_NX2_5709,
2291 quirk_brcm_570x_limit_vpd);
2292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2293 PCI_DEVICE_ID_NX2_5709S,
2294 quirk_brcm_570x_limit_vpd);
2296 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2300 pci_read_config_dword(dev, 0xf4, &rev);
2302 /* Only CAP the MRRS if the device is a 5719 A0 */
2303 if (rev == 0x05719000) {
2304 int readrq = pcie_get_readrq(dev);
2306 pcie_set_readrq(dev, 2048);
2310 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2311 PCI_DEVICE_ID_TIGON3_5719,
2312 quirk_brcm_5719_limit_mrrs);
2314 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2315 static void quirk_paxc_bridge(struct pci_dev *pdev)
2317 /* The PCI config space is shared with the PAXC root port and the first
2318 * Ethernet device. So, we need to workaround this by telling the PCI
2319 * code that the bridge is not an Ethernet device.
2321 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2322 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2324 /* MPSS is not being set properly (as it is currently 0). This is
2325 * because that area of the PCI config space is hard coded to zero, and
2326 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2327 * so that the MPS can be set to the real max value.
2329 pdev->pcie_mpss = 2;
2331 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2332 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2335 /* Originally in EDAC sources for i82875P:
2336 * Intel tells BIOS developers to hide device 6 which
2337 * configures the overflow device access containing
2338 * the DRBs - this is where we expose device 6.
2339 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2341 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2345 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2346 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2347 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2351 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2352 quirk_unhide_mch_dev6);
2353 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2354 quirk_unhide_mch_dev6);
2356 #ifdef CONFIG_TILEPRO
2358 * The Tilera TILEmpower tilepro platform needs to set the link speed
2359 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2360 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2361 * capability register of the PEX8624 PCIe switch. The switch
2362 * supports link speed auto negotiation, but falsely sets
2363 * the link speed to 5GT/s.
2365 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2367 if (tile_plx_gen1) {
2368 pci_write_config_dword(dev, 0x98, 0x1);
2372 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2373 #endif /* CONFIG_TILEPRO */
2375 #ifdef CONFIG_PCI_MSI
2376 /* Some chipsets do not support MSI. We cannot easily rely on setting
2377 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2378 * some other buses controlled by the chipset even if Linux is not
2379 * aware of it. Instead of setting the flag on all buses in the
2380 * machine, simply disable MSI globally.
2382 static void quirk_disable_all_msi(struct pci_dev *dev)
2385 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2396 /* Disable MSI on chipsets that are known to not support it */
2397 static void quirk_disable_msi(struct pci_dev *dev)
2399 if (dev->subordinate) {
2400 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2401 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2409 * The APC bridge device in AMD 780 family northbridges has some random
2410 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2411 * we use the possible vendor/device IDs of the host bridge for the
2412 * declared quirk, and search for the APC bridge by slot number.
2414 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2416 struct pci_dev *apc_bridge;
2418 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2420 if (apc_bridge->device == 0x9602)
2421 quirk_disable_msi(apc_bridge);
2422 pci_dev_put(apc_bridge);
2425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2428 /* Go through the list of Hypertransport capabilities and
2429 * return 1 if a HT MSI capability is found and enabled */
2430 static int msi_ht_cap_enabled(struct pci_dev *dev)
2432 int pos, ttl = PCI_FIND_CAP_TTL;
2434 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2435 while (pos && ttl--) {
2438 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2440 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2441 flags & HT_MSI_FLAGS_ENABLE ?
2442 "enabled" : "disabled");
2443 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2446 pos = pci_find_next_ht_capability(dev, pos,
2447 HT_CAPTYPE_MSI_MAPPING);
2452 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2453 static void quirk_msi_ht_cap(struct pci_dev *dev)
2455 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2456 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2457 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2463 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2464 * MSI are supported if the MSI capability set in any of these mappings.
2466 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2468 struct pci_dev *pdev;
2470 if (!dev->subordinate)
2473 /* check HT MSI cap on this chipset and the root one.
2474 * a single one having MSI is enough to be sure that MSI are supported.
2476 pdev = pci_get_slot(dev->bus, 0);
2479 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2480 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2481 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2486 quirk_nvidia_ck804_msi_ht_cap);
2488 /* Force enable MSI mapping capability on HT bridges */
2489 static void ht_enable_msi_mapping(struct pci_dev *dev)
2491 int pos, ttl = PCI_FIND_CAP_TTL;
2493 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2494 while (pos && ttl--) {
2497 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2499 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2501 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2502 flags | HT_MSI_FLAGS_ENABLE);
2504 pos = pci_find_next_ht_capability(dev, pos,
2505 HT_CAPTYPE_MSI_MAPPING);
2508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2509 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2510 ht_enable_msi_mapping);
2512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2513 ht_enable_msi_mapping);
2515 /* The P5N32-SLI motherboards from Asus have a problem with msi
2516 * for the MCP55 NIC. It is not yet determined whether the msi problem
2517 * also affects other devices. As for now, turn off msi for this device.
2519 static void nvenet_msi_disable(struct pci_dev *dev)
2521 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2524 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2525 strstr(board_name, "P5N32-E SLI"))) {
2526 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2530 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2531 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2532 nvenet_msi_disable);
2535 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2536 * config register. This register controls the routing of legacy
2537 * interrupts from devices that route through the MCP55. If this register
2538 * is misprogrammed, interrupts are only sent to the BSP, unlike
2539 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2540 * having this register set properly prevents kdump from booting up
2541 * properly, so let's make sure that we have it set correctly.
2542 * Note that this is an undocumented register.
2544 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2548 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2551 pci_read_config_dword(dev, 0x74, &cfg);
2553 if (cfg & ((1 << 2) | (1 << 15))) {
2554 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2555 cfg &= ~((1 << 2) | (1 << 15));
2556 pci_write_config_dword(dev, 0x74, cfg);
2560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2561 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2562 nvbridge_check_legacy_irq_routing);
2564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2565 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2566 nvbridge_check_legacy_irq_routing);
2568 static int ht_check_msi_mapping(struct pci_dev *dev)
2570 int pos, ttl = PCI_FIND_CAP_TTL;
2573 /* check if there is HT MSI cap or enabled on this device */
2574 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2575 while (pos && ttl--) {
2580 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2582 if (flags & HT_MSI_FLAGS_ENABLE) {
2589 pos = pci_find_next_ht_capability(dev, pos,
2590 HT_CAPTYPE_MSI_MAPPING);
2596 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2598 struct pci_dev *dev;
2603 dev_no = host_bridge->devfn >> 3;
2604 for (i = dev_no + 1; i < 0x20; i++) {
2605 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2609 /* found next host bridge ?*/
2610 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2616 if (ht_check_msi_mapping(dev)) {
2627 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2628 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2630 static int is_end_of_ht_chain(struct pci_dev *dev)
2636 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2641 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2643 ctrl_off = ((flags >> 10) & 1) ?
2644 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2645 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2647 if (ctrl & (1 << 6))
2654 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2656 struct pci_dev *host_bridge;
2661 dev_no = dev->devfn >> 3;
2662 for (i = dev_no; i >= 0; i--) {
2663 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2667 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2672 pci_dev_put(host_bridge);
2678 /* don't enable end_device/host_bridge with leaf directly here */
2679 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2680 host_bridge_with_leaf(host_bridge))
2683 /* root did that ! */
2684 if (msi_ht_cap_enabled(host_bridge))
2687 ht_enable_msi_mapping(dev);
2690 pci_dev_put(host_bridge);
2693 static void ht_disable_msi_mapping(struct pci_dev *dev)
2695 int pos, ttl = PCI_FIND_CAP_TTL;
2697 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2698 while (pos && ttl--) {
2701 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2703 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2705 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2706 flags & ~HT_MSI_FLAGS_ENABLE);
2708 pos = pci_find_next_ht_capability(dev, pos,
2709 HT_CAPTYPE_MSI_MAPPING);
2713 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2715 struct pci_dev *host_bridge;
2719 if (!pci_msi_enabled())
2722 /* check if there is HT MSI cap or enabled on this device */
2723 found = ht_check_msi_mapping(dev);
2730 * HT MSI mapping should be disabled on devices that are below
2731 * a non-Hypertransport host bridge. Locate the host bridge...
2733 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2734 if (host_bridge == NULL) {
2735 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2739 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2741 /* Host bridge is to HT */
2743 /* it is not enabled, try to enable it */
2745 ht_enable_msi_mapping(dev);
2747 nv_ht_enable_msi_mapping(dev);
2752 /* HT MSI is not enabled */
2756 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2757 ht_disable_msi_mapping(dev);
2760 pci_dev_put(host_bridge);
2763 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2765 return __nv_msi_ht_cap_quirk(dev, 1);
2768 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2770 return __nv_msi_ht_cap_quirk(dev, 0);
2773 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2774 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2776 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2777 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2779 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2781 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2783 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2787 /* SB700 MSI issue will be fixed at HW level from revision A21,
2788 * we need check PCI REVISION ID of SMBus controller to get SB700
2791 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2796 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2797 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2800 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2802 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2803 if (dev->revision < 0x18) {
2804 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2805 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2808 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2809 PCI_DEVICE_ID_TIGON3_5780,
2810 quirk_msi_intx_disable_bug);
2811 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2812 PCI_DEVICE_ID_TIGON3_5780S,
2813 quirk_msi_intx_disable_bug);
2814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2815 PCI_DEVICE_ID_TIGON3_5714,
2816 quirk_msi_intx_disable_bug);
2817 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2818 PCI_DEVICE_ID_TIGON3_5714S,
2819 quirk_msi_intx_disable_bug);
2820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2821 PCI_DEVICE_ID_TIGON3_5715,
2822 quirk_msi_intx_disable_bug);
2823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2824 PCI_DEVICE_ID_TIGON3_5715S,
2825 quirk_msi_intx_disable_bug);
2827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2828 quirk_msi_intx_disable_ati_bug);
2829 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2830 quirk_msi_intx_disable_ati_bug);
2831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2832 quirk_msi_intx_disable_ati_bug);
2833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2834 quirk_msi_intx_disable_ati_bug);
2835 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2836 quirk_msi_intx_disable_ati_bug);
2838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2839 quirk_msi_intx_disable_bug);
2840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2841 quirk_msi_intx_disable_bug);
2842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2843 quirk_msi_intx_disable_bug);
2845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2846 quirk_msi_intx_disable_bug);
2847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2848 quirk_msi_intx_disable_bug);
2849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2850 quirk_msi_intx_disable_bug);
2851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2852 quirk_msi_intx_disable_bug);
2853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2854 quirk_msi_intx_disable_bug);
2855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2856 quirk_msi_intx_disable_bug);
2857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2858 quirk_msi_intx_disable_qca_bug);
2859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2860 quirk_msi_intx_disable_qca_bug);
2861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2862 quirk_msi_intx_disable_qca_bug);
2863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2864 quirk_msi_intx_disable_qca_bug);
2865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2866 quirk_msi_intx_disable_qca_bug);
2867 #endif /* CONFIG_PCI_MSI */
2869 /* Allow manual resource allocation for PCI hotplug bridges
2870 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2871 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2872 * kernel fails to allocate resources when hotplug device is
2873 * inserted and PCI bus is rescanned.
2875 static void quirk_hotplug_bridge(struct pci_dev *dev)
2877 dev->is_hotplug_bridge = 1;
2880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2883 * This is a quirk for the Ricoh MMC controller found as a part of
2884 * some mulifunction chips.
2886 * This is very similar and based on the ricoh_mmc driver written by
2887 * Philip Langdale. Thank you for these magic sequences.
2889 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2890 * and one or both of cardbus or firewire.
2892 * It happens that they implement SD and MMC
2893 * support as separate controllers (and PCI functions). The linux SDHCI
2894 * driver supports MMC cards but the chip detects MMC cards in hardware
2895 * and directs them to the MMC controller - so the SDHCI driver never sees
2898 * To get around this, we must disable the useless MMC controller.
2899 * At that point, the SDHCI controller will start seeing them
2900 * It seems to be the case that the relevant PCI registers to deactivate the
2901 * MMC controller live on PCI function 0, which might be the cardbus controller
2902 * or the firewire controller, depending on the particular chip in question
2904 * This has to be done early, because as soon as we disable the MMC controller
2905 * other pci functions shift up one level, e.g. function #2 becomes function
2906 * #1, and this will confuse the pci core.
2909 #ifdef CONFIG_MMC_RICOH_MMC
2910 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2912 /* disable via cardbus interface */
2917 /* disable must be done via function #0 */
2918 if (PCI_FUNC(dev->devfn))
2921 pci_read_config_byte(dev, 0xB7, &disable);
2925 pci_read_config_byte(dev, 0x8E, &write_enable);
2926 pci_write_config_byte(dev, 0x8E, 0xAA);
2927 pci_read_config_byte(dev, 0x8D, &write_target);
2928 pci_write_config_byte(dev, 0x8D, 0xB7);
2929 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2930 pci_write_config_byte(dev, 0x8E, write_enable);
2931 pci_write_config_byte(dev, 0x8D, write_target);
2933 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2934 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2936 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2937 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2939 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2941 /* disable via firewire interface */
2945 /* disable must be done via function #0 */
2946 if (PCI_FUNC(dev->devfn))
2949 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2950 * certain types of SD/MMC cards. Lowering the SD base
2951 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2953 * 0x150 - SD2.0 mode enable for changing base clock
2954 * frequency to 50Mhz
2955 * 0xe1 - Base clock frequency
2956 * 0x32 - 50Mhz new clock frequency
2957 * 0xf9 - Key register for 0x150
2958 * 0xfc - key register for 0xe1
2960 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2961 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2962 pci_write_config_byte(dev, 0xf9, 0xfc);
2963 pci_write_config_byte(dev, 0x150, 0x10);
2964 pci_write_config_byte(dev, 0xf9, 0x00);
2965 pci_write_config_byte(dev, 0xfc, 0x01);
2966 pci_write_config_byte(dev, 0xe1, 0x32);
2967 pci_write_config_byte(dev, 0xfc, 0x00);
2969 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2972 pci_read_config_byte(dev, 0xCB, &disable);
2977 pci_read_config_byte(dev, 0xCA, &write_enable);
2978 pci_write_config_byte(dev, 0xCA, 0x57);
2979 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2980 pci_write_config_byte(dev, 0xCA, write_enable);
2982 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2983 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2986 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2987 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2988 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2989 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2990 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2991 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2992 #endif /*CONFIG_MMC_RICOH_MMC*/
2994 #ifdef CONFIG_DMAR_TABLE
2995 #define VTUNCERRMSK_REG 0x1ac
2996 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2998 * This is a quirk for masking vt-d spec defined errors to platform error
2999 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
3000 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3001 * on the RAS config settings of the platform) when a vt-d fault happens.
3002 * The resulting SMI caused the system to hang.
3004 * VT-d spec related errors are already handled by the VT-d OS code, so no
3005 * need to report the same error through other channels.
3007 static void vtd_mask_spec_errors(struct pci_dev *dev)
3011 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3012 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3014 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3015 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3018 static void fixup_ti816x_class(struct pci_dev *dev)
3020 u32 class = dev->class;
3022 /* TI 816x devices do not have class code set when in PCIe boot mode */
3023 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3024 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
3027 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3028 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3030 /* Some PCIe devices do not work reliably with the claimed maximum
3031 * payload size supported.
3033 static void fixup_mpss_256(struct pci_dev *dev)
3035 dev->pcie_mpss = 1; /* 256 bytes */
3037 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3038 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3039 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3040 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3041 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3042 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3043 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3045 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
3046 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3047 * Since there is no way of knowing what the PCIE MPS on each fabric will be
3048 * until all of the devices are discovered and buses walked, read completion
3049 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3050 * it is possible to hotplug a device with MPS of 256B.
3052 static void quirk_intel_mc_errata(struct pci_dev *dev)
3057 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3058 pcie_bus_config == PCIE_BUS_DEFAULT)
3061 /* Intel errata specifies bits to change but does not say what they are.
3062 * Keeping them magical until such time as the registers and values can
3065 err = pci_read_config_word(dev, 0x48, &rcc);
3067 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
3071 if (!(rcc & (1 << 10)))
3076 err = pci_write_config_word(dev, 0x48, rcc);
3078 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
3082 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3084 /* Intel 5000 series memory controllers and ports 2-7 */
3085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3097 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3099 /* Intel 5100 series memory controllers and ports 2-7 */
3100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3114 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3115 * work around this, query the size it should be configured to by the device and
3116 * modify the resource end to correspond to this new size.
3118 static void quirk_intel_ntb(struct pci_dev *dev)
3123 rc = pci_read_config_byte(dev, 0x00D0, &val);
3127 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3129 rc = pci_read_config_byte(dev, 0x00D1, &val);
3133 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3138 static ktime_t fixup_debug_start(struct pci_dev *dev,
3139 void (*fn)(struct pci_dev *dev))
3141 ktime_t calltime = 0;
3143 dev_dbg(&dev->dev, "calling %pF\n", fn);
3144 if (initcall_debug) {
3145 pr_debug("calling %pF @ %i for %s\n",
3146 fn, task_pid_nr(current), dev_name(&dev->dev));
3147 calltime = ktime_get();
3153 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3154 void (*fn)(struct pci_dev *dev))
3156 ktime_t delta, rettime;
3157 unsigned long long duration;
3159 if (initcall_debug) {
3160 rettime = ktime_get();
3161 delta = ktime_sub(rettime, calltime);
3162 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3163 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3164 fn, duration, dev_name(&dev->dev));
3169 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3170 * even though no one is handling them (f.e. i915 driver is never loaded).
3171 * Additionally the interrupt destination is not set up properly
3172 * and the interrupt ends up -somewhere-.
3174 * These spurious interrupts are "sticky" and the kernel disables
3175 * the (shared) interrupt line after 100.000+ generated interrupts.
3177 * Fix it by disabling the still enabled interrupts.
3178 * This resolves crashes often seen on monitor unplug.
3180 #define I915_DEIER_REG 0x4400c
3181 static void disable_igfx_irq(struct pci_dev *dev)
3183 void __iomem *regs = pci_iomap(dev, 0, 0);
3185 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3189 /* Check if any interrupt line is still enabled */
3190 if (readl(regs + I915_DEIER_REG) != 0) {
3191 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3193 writel(0, regs + I915_DEIER_REG);
3196 pci_iounmap(dev, regs);
3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3207 * PCI devices which are on Intel chips can skip the 10ms delay
3208 * before entering D3 mode.
3210 static void quirk_remove_d3_delay(struct pci_dev *dev)
3214 /* C600 Series devices do not need 10ms d3_delay */
3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3218 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3230 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3242 * Some devices may pass our check in pci_intx_mask_supported() if
3243 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3244 * support this feature.
3246 static void quirk_broken_intx_masking(struct pci_dev *dev)
3248 dev->broken_intx_masking = 1;
3250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3251 quirk_broken_intx_masking);
3252 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3253 quirk_broken_intx_masking);
3256 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3257 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3259 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3262 quirk_broken_intx_masking);
3265 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3266 * DisINTx can be set but the interrupt status bit is non-functional.
3268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3269 quirk_broken_intx_masking);
3270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3271 quirk_broken_intx_masking);
3272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3273 quirk_broken_intx_masking);
3274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3275 quirk_broken_intx_masking);
3276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3277 quirk_broken_intx_masking);
3278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3279 quirk_broken_intx_masking);
3280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3281 quirk_broken_intx_masking);
3282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3283 quirk_broken_intx_masking);
3284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3285 quirk_broken_intx_masking);
3286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3287 quirk_broken_intx_masking);
3288 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3289 quirk_broken_intx_masking);
3290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3291 quirk_broken_intx_masking);
3292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3293 quirk_broken_intx_masking);
3294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3295 quirk_broken_intx_masking);
3296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3297 quirk_broken_intx_masking);
3298 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3299 quirk_broken_intx_masking);
3301 static u16 mellanox_broken_intx_devs[] = {
3302 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3303 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3304 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3305 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3306 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3307 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3308 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3309 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3310 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3311 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3312 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3313 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3314 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3315 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3318 #define CONNECTX_4_CURR_MAX_MINOR 99
3319 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3322 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3323 * If so, don't mark it as broken.
3324 * FW minor > 99 means older FW version format and no INTx masking support.
3325 * FW minor < 14 means new FW version format and no INTx masking support.
3327 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3329 __be32 __iomem *fw_ver;
3337 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3338 if (pdev->device == mellanox_broken_intx_devs[i]) {
3339 pdev->broken_intx_masking = 1;
3344 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3345 * support so shouldn't be checked further
3347 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3350 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3351 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3354 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3355 if (pci_enable_device_mem(pdev)) {
3356 dev_warn(&pdev->dev, "Can't enable device memory\n");
3360 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3362 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3366 /* Reading from resource space should be 32b aligned */
3367 fw_maj_min = ioread32be(fw_ver);
3368 fw_sub_min = ioread32be(fw_ver + 1);
3369 fw_major = fw_maj_min & 0xffff;
3370 fw_minor = fw_maj_min >> 16;
3371 fw_subminor = fw_sub_min & 0xffff;
3372 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3373 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3374 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3375 fw_major, fw_minor, fw_subminor, pdev->device ==
3376 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3377 pdev->broken_intx_masking = 1;
3383 pci_disable_device(pdev);
3385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3386 mellanox_check_broken_intx_masking);
3388 static void quirk_no_bus_reset(struct pci_dev *dev)
3390 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3394 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3395 * prevented for those affected devices.
3397 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3399 if ((dev->device & 0xffc0) == 0x2340)
3400 quirk_no_bus_reset(dev);
3402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3403 quirk_nvidia_no_bus_reset);
3406 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3407 * The device will throw a Link Down error on AER-capable systems and
3408 * regardless of AER, config space of the device is never accessible again
3409 * and typically causes the system to hang or reset when access is attempted.
3410 * http://www.spinics.net/lists/linux-pci/msg34797.html
3412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3416 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3419 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3420 * automatically disables LTSSM when Secondary Bus Reset is received and
3421 * the device stops working. Prevent bus reset for these devices. With
3422 * this change, the device can be assigned to VMs with VFIO, but it will
3423 * leak state between VMs. Reference
3424 * https://e2e.ti.com/support/processors/f/791/t/954382
3426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3428 static void quirk_no_pm_reset(struct pci_dev *dev)
3431 * We can't do a bus reset on root bus devices, but an ineffective
3432 * PM reset may be better than nothing.
3434 if (!pci_is_root_bus(dev->bus))
3435 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3439 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3440 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3441 * to have no effect on the device: it retains the framebuffer contents and
3442 * monitor sync. Advertising this support makes other layers, like VFIO,
3443 * assume pci_reset_function() is viable for this device. Mark it as
3444 * unavailable to skip it when testing reset methods.
3446 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3447 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3450 * Thunderbolt controllers with broken MSI hotplug signaling:
3451 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3452 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3454 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3456 if (pdev->is_hotplug_bridge &&
3457 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3458 pdev->revision <= 1))
3461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3462 quirk_thunderbolt_hotplug_msi);
3463 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3464 quirk_thunderbolt_hotplug_msi);
3465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3466 quirk_thunderbolt_hotplug_msi);
3467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3468 quirk_thunderbolt_hotplug_msi);
3469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3470 quirk_thunderbolt_hotplug_msi);
3472 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3474 int chip = (dev->device & 0xf000) >> 12;
3475 int func = (dev->device & 0x0f00) >> 8;
3476 int prod = (dev->device & 0x00ff) >> 0;
3479 * If this is a T3-based adapter, there's a 1KB VPD area at offset
3480 * 0xc00 which contains the preferred VPD values. If this is a T4 or
3481 * later based adapter, the special VPD is at offset 0x400 for the
3482 * Physical Functions (the SR-IOV Virtual Functions have no VPD
3483 * Capabilities). The PCI VPD Access core routines will normally
3484 * compute the size of the VPD by parsing the VPD Data Structure at
3485 * offset 0x000. This will result in silent failures when attempting
3486 * to accesses these other VPD areas which are beyond those computed
3489 if (chip == 0x0 && prod >= 0x20)
3490 pci_set_vpd_size(dev, 8192);
3491 else if (chip >= 0x4 && func < 0x8)
3492 pci_set_vpd_size(dev, 2048);
3495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3496 quirk_chelsio_extend_vpd);
3500 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3502 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3503 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3504 * be present after resume if a device was plugged in before suspend.
3506 * The thunderbolt controller consists of a pcie switch with downstream
3507 * bridges leading to the NHI and to the tunnel pci bridges.
3509 * This quirk cuts power to the whole chip. Therefore we have to apply it
3510 * during suspend_noirq of the upstream bridge.
3512 * Power is automagically restored before resume. No action is needed.
3514 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3516 acpi_handle bridge, SXIO, SXFP, SXLV;
3518 if (!x86_apple_machine)
3520 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3522 bridge = ACPI_HANDLE(&dev->dev);
3526 * SXIO and SXLV are present only on machines requiring this quirk.
3527 * TB bridges in external devices might have the same device id as those
3528 * on the host, but they will not have the associated ACPI methods. This
3529 * implicitly checks that we are at the right bridge.
3531 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3532 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3533 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3535 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3537 /* magic sequence */
3538 acpi_execute_simple_method(SXIO, NULL, 1);
3539 acpi_execute_simple_method(SXFP, NULL, 0);
3541 acpi_execute_simple_method(SXLV, NULL, 0);
3542 acpi_execute_simple_method(SXIO, NULL, 0);
3543 acpi_execute_simple_method(SXLV, NULL, 0);
3545 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3546 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3547 quirk_apple_poweroff_thunderbolt);
3550 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3552 * During suspend the thunderbolt controller is reset and all pci
3553 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3554 * during resume. We have to manually wait for the NHI since there is
3555 * no parent child relationship between the NHI and the tunneled
3558 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3560 struct pci_dev *sibling = NULL;
3561 struct pci_dev *nhi = NULL;
3563 if (!x86_apple_machine)
3565 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3568 * Find the NHI and confirm that we are a bridge on the tb host
3569 * controller and not on a tb endpoint.
3571 sibling = pci_get_slot(dev->bus, 0x0);
3573 goto out; /* we are the downstream bridge to the NHI */
3574 if (!sibling || !sibling->subordinate)
3576 nhi = pci_get_slot(sibling->subordinate, 0x0);
3579 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3580 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3581 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3582 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3583 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3584 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3586 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3587 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3590 pci_dev_put(sibling);
3592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3593 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3594 quirk_apple_wait_for_thunderbolt);
3595 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3596 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3597 quirk_apple_wait_for_thunderbolt);
3598 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3599 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3600 quirk_apple_wait_for_thunderbolt);
3601 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3602 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3603 quirk_apple_wait_for_thunderbolt);
3606 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3607 struct pci_fixup *end)
3611 for (; f < end; f++)
3612 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3613 f->class == (u32) PCI_ANY_ID) &&
3614 (f->vendor == dev->vendor ||
3615 f->vendor == (u16) PCI_ANY_ID) &&
3616 (f->device == dev->device ||
3617 f->device == (u16) PCI_ANY_ID)) {
3618 calltime = fixup_debug_start(dev, f->hook);
3620 fixup_debug_report(dev, calltime, f->hook);
3624 extern struct pci_fixup __start_pci_fixups_early[];
3625 extern struct pci_fixup __end_pci_fixups_early[];
3626 extern struct pci_fixup __start_pci_fixups_header[];
3627 extern struct pci_fixup __end_pci_fixups_header[];
3628 extern struct pci_fixup __start_pci_fixups_final[];
3629 extern struct pci_fixup __end_pci_fixups_final[];
3630 extern struct pci_fixup __start_pci_fixups_enable[];
3631 extern struct pci_fixup __end_pci_fixups_enable[];
3632 extern struct pci_fixup __start_pci_fixups_resume[];
3633 extern struct pci_fixup __end_pci_fixups_resume[];
3634 extern struct pci_fixup __start_pci_fixups_resume_early[];
3635 extern struct pci_fixup __end_pci_fixups_resume_early[];
3636 extern struct pci_fixup __start_pci_fixups_suspend[];
3637 extern struct pci_fixup __end_pci_fixups_suspend[];
3638 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3639 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3641 static bool pci_apply_fixup_final_quirks;
3643 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3645 struct pci_fixup *start, *end;
3648 case pci_fixup_early:
3649 start = __start_pci_fixups_early;
3650 end = __end_pci_fixups_early;
3653 case pci_fixup_header:
3654 start = __start_pci_fixups_header;
3655 end = __end_pci_fixups_header;
3658 case pci_fixup_final:
3659 if (!pci_apply_fixup_final_quirks)
3661 start = __start_pci_fixups_final;
3662 end = __end_pci_fixups_final;
3665 case pci_fixup_enable:
3666 start = __start_pci_fixups_enable;
3667 end = __end_pci_fixups_enable;
3670 case pci_fixup_resume:
3671 start = __start_pci_fixups_resume;
3672 end = __end_pci_fixups_resume;
3675 case pci_fixup_resume_early:
3676 start = __start_pci_fixups_resume_early;
3677 end = __end_pci_fixups_resume_early;
3680 case pci_fixup_suspend:
3681 start = __start_pci_fixups_suspend;
3682 end = __end_pci_fixups_suspend;
3685 case pci_fixup_suspend_late:
3686 start = __start_pci_fixups_suspend_late;
3687 end = __end_pci_fixups_suspend_late;
3691 /* stupid compiler warning, you would think with an enum... */
3694 pci_do_fixups(dev, start, end);
3696 EXPORT_SYMBOL(pci_fixup_device);
3699 static int __init pci_apply_final_quirks(void)
3701 struct pci_dev *dev = NULL;
3705 if (pci_cache_line_size)
3706 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3707 pci_cache_line_size << 2);
3709 pci_apply_fixup_final_quirks = true;
3710 for_each_pci_dev(dev) {
3711 pci_fixup_device(pci_fixup_final, dev);
3713 * If arch hasn't set it explicitly yet, use the CLS
3714 * value shared by all PCI devices. If there's a
3715 * mismatch, fall back to the default value.
3717 if (!pci_cache_line_size) {
3718 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3721 if (!tmp || cls == tmp)
3724 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3726 pci_dfl_cache_line_size << 2);
3727 pci_cache_line_size = pci_dfl_cache_line_size;
3731 if (!pci_cache_line_size) {
3732 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3733 cls << 2, pci_dfl_cache_line_size << 2);
3734 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3740 fs_initcall_sync(pci_apply_final_quirks);
3743 * Following are device-specific reset methods which can be used to
3744 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3747 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3750 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3752 * The 82599 supports FLR on VFs, but FLR support is reported only
3753 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3754 * Thus we must call pcie_flr() directly without first checking if it is
3762 #define SOUTH_CHICKEN2 0xc2004
3763 #define PCH_PP_STATUS 0xc7200
3764 #define PCH_PP_CONTROL 0xc7204
3765 #define MSG_CTL 0x45010
3766 #define NSDE_PWR_STATE 0xd0100
3767 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3769 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3771 void __iomem *mmio_base;
3772 unsigned long timeout;
3778 mmio_base = pci_iomap(dev, 0, 0);
3782 iowrite32(0x00000002, mmio_base + MSG_CTL);
3785 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3786 * driver loaded sets the right bits. However, this's a reset and
3787 * the bits have been set by i915 previously, so we clobber
3788 * SOUTH_CHICKEN2 register directly here.
3790 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3792 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3793 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3795 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3797 val = ioread32(mmio_base + PCH_PP_STATUS);
3798 if ((val & 0xb0000000) == 0)
3799 goto reset_complete;
3801 } while (time_before(jiffies, timeout));
3802 dev_warn(&dev->dev, "timeout during reset\n");
3805 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3807 pci_iounmap(dev, mmio_base);
3812 * Device-specific reset method for Chelsio T4-based adapters.
3814 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3820 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3821 * that we have no device-specific reset method.
3823 if ((dev->device & 0xf000) != 0x4000)
3827 * If this is the "probe" phase, return 0 indicating that we can
3828 * reset this device.
3834 * T4 can wedge if there are DMAs in flight within the chip and Bus
3835 * Master has been disabled. We need to have it on till the Function
3836 * Level Reset completes. (BUS_MASTER is disabled in
3837 * pci_reset_function()).
3839 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3840 pci_write_config_word(dev, PCI_COMMAND,
3841 old_command | PCI_COMMAND_MASTER);
3844 * Perform the actual device function reset, saving and restoring
3845 * configuration information around the reset.
3847 pci_save_state(dev);
3850 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3851 * are disabled when an MSI-X interrupt message needs to be delivered.
3852 * So we briefly re-enable MSI-X interrupts for the duration of the
3853 * FLR. The pci_restore_state() below will restore the original
3856 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3857 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3858 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3860 PCI_MSIX_FLAGS_ENABLE |
3861 PCI_MSIX_FLAGS_MASKALL);
3866 * Restore the configuration information (BAR values, etc.) including
3867 * the original PCI Configuration Space Command word, and return
3870 pci_restore_state(dev);
3871 pci_write_config_word(dev, PCI_COMMAND, old_command);
3875 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3876 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3877 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3879 #define PCI_DEVICE_ID_HINIC_VF 0x375E
3880 #define HINIC_VF_FLR_TYPE 0x1000
3881 #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
3882 #define HINIC_VF_OP 0xE80
3883 #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
3884 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
3886 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3887 static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe)
3889 unsigned long timeout;
3896 bar = pci_iomap(pdev, 0, 0);
3900 /* Get and check firmware capabilities */
3901 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
3902 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
3903 pci_iounmap(pdev, bar);
3907 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
3908 val = ioread32be(bar + HINIC_VF_OP);
3909 val = val | HINIC_VF_FLR_PROC_BIT;
3910 iowrite32be(val, bar + HINIC_VF_OP);
3915 * The device must recapture its Bus and Device Numbers after FLR
3916 * in order generate Completions. Issue a config write to let the
3917 * device capture this information.
3919 pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
3921 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
3922 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
3924 val = ioread32be(bar + HINIC_VF_OP);
3925 if (!(val & HINIC_VF_FLR_PROC_BIT))
3926 goto reset_complete;
3928 } while (time_before(jiffies, timeout));
3930 val = ioread32be(bar + HINIC_VF_OP);
3931 if (!(val & HINIC_VF_FLR_PROC_BIT))
3932 goto reset_complete;
3934 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
3937 pci_iounmap(pdev, bar);
3942 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3943 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3944 reset_intel_82599_sfp_virtfn },
3945 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3947 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3949 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3950 reset_chelsio_generic_dev },
3951 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
3952 reset_hinic_vf_dev },
3957 * These device-specific reset methods are here rather than in a driver
3958 * because when a host assigns a device to a guest VM, the host may need
3959 * to reset the device but probably doesn't have a driver for it.
3961 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3963 const struct pci_dev_reset_methods *i;
3965 for (i = pci_dev_reset_methods; i->reset; i++) {
3966 if ((i->vendor == dev->vendor ||
3967 i->vendor == (u16)PCI_ANY_ID) &&
3968 (i->device == dev->device ||
3969 i->device == (u16)PCI_ANY_ID))
3970 return i->reset(dev, probe);
3976 static void quirk_dma_func0_alias(struct pci_dev *dev)
3978 if (PCI_FUNC(dev->devfn) != 0)
3979 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3983 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3985 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3990 static void quirk_dma_func1_alias(struct pci_dev *dev)
3992 if (PCI_FUNC(dev->devfn) != 1)
3993 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3997 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3998 * SKUs function 1 is present and is a legacy IDE controller, in other
3999 * SKUs this function is not present, making this a ghost requester.
4000 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4002 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4003 quirk_dma_func1_alias);
4004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4005 quirk_dma_func1_alias);
4006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4007 quirk_dma_func1_alias);
4008 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4010 quirk_dma_func1_alias);
4011 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4012 quirk_dma_func1_alias);
4013 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4015 quirk_dma_func1_alias);
4016 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4018 quirk_dma_func1_alias);
4019 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4021 quirk_dma_func1_alias);
4022 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4024 quirk_dma_func1_alias);
4025 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4027 quirk_dma_func1_alias);
4028 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4029 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4030 quirk_dma_func1_alias);
4031 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4032 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4033 quirk_dma_func1_alias);
4034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4035 quirk_dma_func1_alias);
4036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4037 quirk_dma_func1_alias);
4038 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4040 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4041 quirk_dma_func1_alias);
4042 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4043 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4044 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4045 quirk_dma_func1_alias);
4048 * Some devices DMA with the wrong devfn, not just the wrong function.
4049 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4050 * the alias is "fixed" and independent of the device devfn.
4052 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4053 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4054 * single device on the secondary bus. In reality, the single exposed
4055 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4056 * that provides a bridge to the internal bus of the I/O processor. The
4057 * controller supports private devices, which can be hidden from PCI config
4058 * space. In the case of the Adaptec 3405, a private device at 01.0
4059 * appears to be the DMA engine, which therefore needs to become a DMA
4060 * alias for the device.
4062 static const struct pci_device_id fixed_dma_alias_tbl[] = {
4063 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4064 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4065 .driver_data = PCI_DEVFN(1, 0) },
4066 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4067 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4068 .driver_data = PCI_DEVFN(1, 0) },
4072 static void quirk_fixed_dma_alias(struct pci_dev *dev)
4074 const struct pci_device_id *id;
4076 id = pci_match_id(fixed_dma_alias_tbl, dev);
4078 pci_add_dma_alias(dev, id->driver_data);
4081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4084 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4085 * using the wrong DMA alias for the device. Some of these devices can be
4086 * used as either forward or reverse bridges, so we need to test whether the
4087 * device is operating in the correct mode. We could probably apply this
4088 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4089 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4090 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4092 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4094 if (!pci_is_root_bus(pdev->bus) &&
4095 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4096 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4097 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4098 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4100 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4102 quirk_use_pcie_bridge_dma_alias);
4103 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4104 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4105 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4106 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4107 /* ITE 8893 has the same problem as the 8892 */
4108 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4109 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4110 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4113 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4114 * be added as aliases to the DMA device in order to allow buffer access
4115 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4116 * programmed in the EEPROM.
4118 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4120 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
4121 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
4122 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
4124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4128 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4129 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4131 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4132 * when IOMMU is enabled. These aliases allow computational unit access to
4133 * host memory. These aliases mark the whole VCA device as one IOMMU
4136 * All possible slot numbers (0x20) are used, since we are unable to tell
4137 * what slot is used on other side. This quirk is intended for both host
4138 * and computational unit sides. The VCA devices have up to five functions
4139 * (four for DMA channels and one additional).
4141 static void quirk_pex_vca_alias(struct pci_dev *pdev)
4143 const unsigned int num_pci_slots = 0x20;
4146 for (slot = 0; slot < num_pci_slots; slot++) {
4147 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0));
4148 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x1));
4149 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x2));
4150 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x3));
4151 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x4));
4154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4162 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4163 * associated not at the root bus, but at a bridge below. This quirk avoids
4164 * generating invalid DMA aliases.
4166 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4168 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4171 quirk_bridge_cavm_thrx2_pcie_root);
4172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4173 quirk_bridge_cavm_thrx2_pcie_root);
4176 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4177 * class code. Fix it.
4179 static void quirk_tw686x_class(struct pci_dev *pdev)
4181 u32 class = pdev->class;
4183 /* Use "Multimedia controller" class */
4184 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4185 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4186 class, pdev->class);
4188 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4189 quirk_tw686x_class);
4190 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4191 quirk_tw686x_class);
4192 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4193 quirk_tw686x_class);
4194 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4195 quirk_tw686x_class);
4198 * Some devices have problems with Transaction Layer Packets with the Relaxed
4199 * Ordering Attribute set. Such devices should mark themselves and other
4200 * Device Drivers should check before sending TLPs with RO set.
4202 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4204 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4205 dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4209 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4210 * Complex has a Flow Control Credit issue which can cause performance
4211 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4213 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4214 quirk_relaxedordering_disable);
4215 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4216 quirk_relaxedordering_disable);
4217 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4218 quirk_relaxedordering_disable);
4219 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4220 quirk_relaxedordering_disable);
4221 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4222 quirk_relaxedordering_disable);
4223 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4224 quirk_relaxedordering_disable);
4225 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4226 quirk_relaxedordering_disable);
4227 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4228 quirk_relaxedordering_disable);
4229 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4230 quirk_relaxedordering_disable);
4231 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4232 quirk_relaxedordering_disable);
4233 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4234 quirk_relaxedordering_disable);
4235 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4236 quirk_relaxedordering_disable);
4237 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4238 quirk_relaxedordering_disable);
4239 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4240 quirk_relaxedordering_disable);
4241 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4242 quirk_relaxedordering_disable);
4243 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4244 quirk_relaxedordering_disable);
4245 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4246 quirk_relaxedordering_disable);
4247 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4248 quirk_relaxedordering_disable);
4249 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4250 quirk_relaxedordering_disable);
4251 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4252 quirk_relaxedordering_disable);
4253 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4254 quirk_relaxedordering_disable);
4255 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4256 quirk_relaxedordering_disable);
4257 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4258 quirk_relaxedordering_disable);
4259 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4260 quirk_relaxedordering_disable);
4261 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4262 quirk_relaxedordering_disable);
4263 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4264 quirk_relaxedordering_disable);
4265 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4266 quirk_relaxedordering_disable);
4267 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4268 quirk_relaxedordering_disable);
4271 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
4272 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4273 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4274 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4275 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4276 * November 10, 2010). As a result, on this platform we can't use Relaxed
4277 * Ordering for Upstream TLPs.
4279 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4280 quirk_relaxedordering_disable);
4281 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4282 quirk_relaxedordering_disable);
4283 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4284 quirk_relaxedordering_disable);
4287 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4288 * values for the Attribute as were supplied in the header of the
4289 * corresponding Request, except as explicitly allowed when IDO is used."
4291 * If a non-compliant device generates a completion with a different
4292 * attribute than the request, the receiver may accept it (which itself
4293 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4294 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4295 * device access timeout.
4297 * If the non-compliant device generates completions with zero attributes
4298 * (instead of copying the attributes from the request), we can work around
4299 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4300 * upstream devices so they always generate requests with zero attributes.
4302 * This affects other devices under the same Root Port, but since these
4303 * attributes are performance hints, there should be no functional problem.
4305 * Note that Configuration Space accesses are never supposed to have TLP
4306 * Attributes, so we're safe waiting till after any Configuration Space
4307 * accesses to do the Root Port fixup.
4309 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4311 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4314 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4318 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4319 dev_name(&pdev->dev));
4320 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4321 PCI_EXP_DEVCTL_RELAX_EN |
4322 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4326 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4327 * Completion it generates.
4329 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4332 * This mask/compare operation selects for Physical Function 4 on a
4333 * T5. We only need to fix up the Root Port once for any of the
4334 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4335 * 0x54xx so we use that one,
4337 if ((pdev->device & 0xff00) == 0x5400)
4338 quirk_disable_root_port_attributes(pdev);
4340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4341 quirk_chelsio_T5_disable_root_port_attributes);
4344 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4346 * @acs_ctrl_req: Bitmask of desired ACS controls
4347 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4348 * the hardware design
4350 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4351 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4352 * caller desires. Return 0 otherwise.
4354 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4356 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4362 * AMD has indicated that the devices below do not support peer-to-peer
4363 * in any system where they are found in the southbridge with an AMD
4364 * IOMMU in the system. Multifunction devices that do not support
4365 * peer-to-peer between functions can claim to support a subset of ACS.
4366 * Such devices effectively enable request redirect (RR) and completion
4367 * redirect (CR) since all transactions are redirected to the upstream
4370 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4371 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4372 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4374 * 1002:4385 SBx00 SMBus Controller
4375 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4376 * 1002:4383 SBx00 Azalia (Intel HDA)
4377 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4378 * 1002:4384 SBx00 PCI to PCI Bridge
4379 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4381 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4383 * 1022:780f [AMD] FCH PCI Bridge
4384 * 1022:7809 [AMD] FCH USB OHCI Controller
4386 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4389 struct acpi_table_header *header = NULL;
4392 /* Targeting multifunction devices on the SB (appears on root bus) */
4393 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4396 /* The IVRS table describes the AMD IOMMU */
4397 status = acpi_get_table("IVRS", 0, &header);
4398 if (ACPI_FAILURE(status))
4401 acpi_put_table(header);
4403 /* Filter out flags not applicable to multifunction */
4404 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4406 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4412 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4414 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4417 switch (dev->device) {
4419 * Effectively selects all downstream ports for whole ThunderX1
4420 * (which represents 8 SoCs).
4422 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4423 case 0xaf84: /* ThunderX2 */
4424 case 0xb884: /* ThunderX3 */
4431 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4433 if (!pci_quirk_cavium_acs_match(dev))
4437 * Cavium Root Ports don't advertise an ACS capability. However,
4438 * the RTL internally implements similar protection as if ACS had
4439 * Source Validation, Request Redirection, Completion Redirection,
4440 * and Upstream Forwarding features enabled. Assert that the
4441 * hardware implements and enables equivalent ACS functionality for
4444 return pci_acs_ctrl_enabled(acs_flags,
4445 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4448 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4451 * X-Gene root matching this quirk do not allow peer-to-peer
4452 * transactions with others, allowing masking out these bits as if they
4453 * were unimplemented in the ACS capability.
4455 return pci_acs_ctrl_enabled(acs_flags,
4456 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4460 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4461 * transactions and validate bus numbers in requests, but do not provide an
4462 * actual PCIe ACS capability. This is the list of device IDs known to fall
4463 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4465 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4467 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4468 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4469 /* Cougarpoint PCH */
4470 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4471 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4472 /* Pantherpoint PCH */
4473 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4474 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4475 /* Lynxpoint-H PCH */
4476 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4477 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4478 /* Lynxpoint-LP PCH */
4479 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4480 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4482 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4483 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4484 /* Patsburg (X79) PCH */
4485 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4486 /* Wellsburg (X99) PCH */
4487 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4488 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4489 /* Lynx Point (9 series) PCH */
4490 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4493 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4497 /* Filter out a few obvious non-matches first */
4498 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4501 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4502 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4508 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4510 if (!pci_quirk_intel_pch_acs_match(dev))
4513 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4514 return pci_acs_ctrl_enabled(acs_flags,
4515 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4517 return pci_acs_ctrl_enabled(acs_flags, 0);
4521 * These QCOM Root Ports do provide ACS-like features to disable peer
4522 * transactions and validate bus numbers in requests, but do not provide an
4523 * actual PCIe ACS capability. Hardware supports source validation but it
4524 * will report the issue as Completer Abort instead of ACS Violation.
4525 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4526 * Complex with unique segment numbers. It is not possible for one Root
4527 * Port to pass traffic to another Root Port. All PCIe transactions are
4528 * terminated inside the Root Port.
4530 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4532 return pci_acs_ctrl_enabled(acs_flags,
4533 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4537 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4538 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4539 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4540 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4541 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4542 * control register is at offset 8 instead of 6 and we should probably use
4543 * dword accesses to them. This applies to the following PCI Device IDs, as
4544 * found in volume 1 of the datasheet[2]:
4546 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4547 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4549 * N.B. This doesn't fix what lspci shows.
4551 * The 100 series chipset specification update includes this as errata #23[3].
4553 * The 200 series chipset (Union Point) has the same bug according to the
4554 * specification update (Intel 200 Series Chipset Family Platform Controller
4555 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4556 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4559 * 0xa290-0xa29f PCI Express Root port #{0-16}
4560 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4562 * Mobile chipsets are also affected, 7th & 8th Generation
4563 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4564 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4565 * Processor Family I/O for U Quad Core Platforms Specification Update,
4566 * August 2017, Revision 002, Document#: 334660-002)[6]
4567 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4568 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4569 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4571 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4573 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4574 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4575 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4576 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4577 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4578 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4579 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4581 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4583 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4586 switch (dev->device) {
4587 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4588 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4589 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4596 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4598 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4603 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4606 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4610 /* see pci_acs_flags_enabled() */
4611 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4612 acs_flags &= (cap | PCI_ACS_EC);
4614 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4616 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4619 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4622 * SV, TB, and UF are not relevant to multifunction endpoints.
4624 * Multifunction devices are only required to implement RR, CR, and DT
4625 * in their ACS capability if they support peer-to-peer transactions.
4626 * Devices matching this quirk have been verified by the vendor to not
4627 * perform peer-to-peer with other functions, allowing us to mask out
4628 * these bits as if they were unimplemented in the ACS capability.
4630 return pci_acs_ctrl_enabled(acs_flags,
4631 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4632 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4635 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4638 * Intel RCiEP's are required to allow p2p only on translated
4639 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4640 * "Root-Complex Peer to Peer Considerations".
4642 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4645 return pci_acs_ctrl_enabled(acs_flags,
4646 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4649 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4652 * iProc PAXB Root Ports don't advertise an ACS capability, but
4653 * they do not allow peer-to-peer transactions between Root Ports.
4654 * Allow each Root Port to be in a separate IOMMU group by masking
4657 return pci_acs_ctrl_enabled(acs_flags,
4658 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4661 static const struct pci_dev_acs_enabled {
4664 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4665 } pci_dev_acs_enabled[] = {
4666 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4667 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4668 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4669 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4670 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4671 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4672 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4673 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4674 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4675 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4676 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4677 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4678 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4679 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4680 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4681 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4682 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4683 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4684 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4685 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4686 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4687 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4688 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4689 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4690 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4691 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4692 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4693 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4694 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4695 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4696 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4698 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4699 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4700 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4701 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4702 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4703 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4704 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4706 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4707 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4708 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4709 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4710 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4711 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4712 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4713 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4715 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4716 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4717 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4719 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4720 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4721 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4722 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4723 /* 82571 (Quads omitted due to non-ACS switch) */
4724 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4725 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4726 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4727 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4729 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4730 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4731 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4732 /* QCOM QDF2xxx root ports */
4733 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4734 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4735 /* Intel PCH root ports */
4736 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4737 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4738 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4739 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4740 /* Cavium ThunderX */
4741 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4742 /* Cavium multi-function devices */
4743 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4744 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4745 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4747 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4748 /* Ampere Computing */
4749 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4750 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4751 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4752 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4753 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4754 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4755 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4756 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4757 /* Broadcom multi-function device */
4758 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4759 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4764 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4766 * @acs_flags: Bitmask of desired ACS controls
4769 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4770 * device provides the desired controls
4771 * 0: Device does not provide all the desired controls
4772 * >0: Device provides all the controls in @acs_flags
4774 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4776 const struct pci_dev_acs_enabled *i;
4780 * Allow devices that do not expose standard PCIe ACS capabilities
4781 * or control to indicate their support here. Multi-function express
4782 * devices which do not allow internal peer-to-peer between functions,
4783 * but do not implement PCIe ACS may wish to return true here.
4785 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4786 if ((i->vendor == dev->vendor ||
4787 i->vendor == (u16)PCI_ANY_ID) &&
4788 (i->device == dev->device ||
4789 i->device == (u16)PCI_ANY_ID)) {
4790 ret = i->acs_enabled(dev, acs_flags);
4799 /* Config space offset of Root Complex Base Address register */
4800 #define INTEL_LPC_RCBA_REG 0xf0
4801 /* 31:14 RCBA address */
4802 #define INTEL_LPC_RCBA_MASK 0xffffc000
4804 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4806 /* Backbone Scratch Pad Register */
4807 #define INTEL_BSPR_REG 0x1104
4808 /* Backbone Peer Non-Posted Disable */
4809 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4810 /* Backbone Peer Posted Disable */
4811 #define INTEL_BSPR_REG_BPPD (1 << 9)
4813 /* Upstream Peer Decode Configuration Register */
4814 #define INTEL_UPDCR_REG 0x1014
4815 /* 5:0 Peer Decode Enable bits */
4816 #define INTEL_UPDCR_REG_MASK 0x3f
4818 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4820 u32 rcba, bspr, updcr;
4821 void __iomem *rcba_mem;
4824 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4825 * are D28:F* and therefore get probed before LPC, thus we can't
4826 * use pci_get_slot/pci_read_config_dword here.
4828 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4829 INTEL_LPC_RCBA_REG, &rcba);
4830 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4833 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4834 PAGE_ALIGN(INTEL_UPDCR_REG));
4839 * The BSPR can disallow peer cycles, but it's set by soft strap and
4840 * therefore read-only. If both posted and non-posted peer cycles are
4841 * disallowed, we're ok. If either are allowed, then we need to use
4842 * the UPDCR to disable peer decodes for each port. This provides the
4843 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4845 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4846 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4847 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4848 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4849 if (updcr & INTEL_UPDCR_REG_MASK) {
4850 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4851 updcr &= ~INTEL_UPDCR_REG_MASK;
4852 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4860 /* Miscellaneous Port Configuration register */
4861 #define INTEL_MPC_REG 0xd8
4862 /* MPC: Invalid Receive Bus Number Check Enable */
4863 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4865 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4870 * When enabled, the IRBNCE bit of the MPC register enables the
4871 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4872 * ensures that requester IDs fall within the bus number range
4873 * of the bridge. Enable if not already.
4875 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4876 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4877 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4878 mpc |= INTEL_MPC_REG_IRBNCE;
4879 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4883 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4885 if (!pci_quirk_intel_pch_acs_match(dev))
4888 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4889 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4893 pci_quirk_enable_intel_rp_mpc_acs(dev);
4895 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4897 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4902 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4907 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4910 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4914 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4915 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4917 ctrl |= (cap & PCI_ACS_SV);
4918 ctrl |= (cap & PCI_ACS_RR);
4919 ctrl |= (cap & PCI_ACS_CR);
4920 ctrl |= (cap & PCI_ACS_UF);
4922 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4924 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4929 static const struct pci_dev_enable_acs {
4932 int (*enable_acs)(struct pci_dev *dev);
4933 } pci_dev_enable_acs[] = {
4934 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4935 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4939 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4941 const struct pci_dev_enable_acs *i;
4944 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4945 if ((i->vendor == dev->vendor ||
4946 i->vendor == (u16)PCI_ANY_ID) &&
4947 (i->device == dev->device ||
4948 i->device == (u16)PCI_ANY_ID)) {
4949 ret = i->enable_acs(dev);
4959 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4960 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4961 * Next Capability pointer in the MSI Capability Structure should point to
4962 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4965 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4970 struct pci_cap_saved_state *state;
4972 /* Bail if the hardware bug is fixed */
4973 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4976 /* Bail if MSI Capability Structure is not found for some reason */
4977 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4982 * Bail if Next Capability pointer in the MSI Capability Structure
4983 * is not the expected incorrect 0x00.
4985 pci_read_config_byte(pdev, pos + 1, &next_cap);
4990 * PCIe Capability Structure is expected to be at 0x50 and should
4991 * terminate the list (Next Capability pointer is 0x00). Verify
4992 * Capability Id and Next Capability pointer is as expected.
4993 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4994 * to correctly set kernel data structures which have already been
4995 * set incorrectly due to the hardware bug.
4998 pci_read_config_word(pdev, pos, ®16);
4999 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5001 #ifndef PCI_EXP_SAVE_REGS
5002 #define PCI_EXP_SAVE_REGS 7
5004 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5006 pdev->pcie_cap = pos;
5007 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5008 pdev->pcie_flags_reg = reg16;
5009 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5010 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5012 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5013 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5014 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5015 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5017 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5023 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5027 state->cap.cap_nr = PCI_CAP_ID_EXP;
5028 state->cap.cap_extended = 0;
5029 state->cap.size = size;
5030 cap = (u16 *)&state->cap.data[0];
5031 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5032 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5033 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5034 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5035 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5036 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5037 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5038 hlist_add_head(&state->next, &pdev->saved_cap_space);
5041 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5044 * FLR may cause the following to devices to hang:
5046 * AMD Starship/Matisse HD Audio Controller 0x1487
5047 * AMD Starship USB 3.0 Host Controller 0x148c
5048 * AMD Matisse USB 3.0 Host Controller 0x149c
5049 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5050 * Intel 82579V Gigabit Ethernet Controller 0x1503
5053 static void quirk_no_flr(struct pci_dev *dev)
5055 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5057 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5058 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5059 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5060 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5061 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5063 static void quirk_no_ext_tags(struct pci_dev *pdev)
5065 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5070 bridge->no_ext_tags = 1;
5071 dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n");
5073 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5075 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5076 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5077 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5078 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5079 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5080 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5081 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5083 #ifdef CONFIG_PCI_ATS
5085 * Some devices have a broken ATS implementation causing IOMMU stalls.
5086 * Don't use ATS for those devices.
5088 static void quirk_no_ats(struct pci_dev *pdev)
5090 dev_info(&pdev->dev, "disabling ATS (broken on this device)\n");
5094 /* AMD Stoney platform GPU */
5095 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
5096 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
5097 #endif /* CONFIG_PCI_ATS */
5099 /* Freescale PCIe doesn't support MSI in RC mode */
5100 static void quirk_fsl_no_msi(struct pci_dev *pdev)
5102 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5108 * Although not allowed by the spec, some multi-function devices have
5109 * dependencies of one function (consumer) on another (supplier). For the
5110 * consumer to work in D0, the supplier must also be in D0. Create a
5111 * device link from the consumer to the supplier to enforce this
5112 * dependency. Runtime PM is allowed by default on the consumer to prevent
5113 * it from permanently keeping the supplier awake.
5115 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5116 unsigned int supplier, unsigned int class,
5117 unsigned int class_shift)
5119 struct pci_dev *supplier_pdev;
5121 if (PCI_FUNC(pdev->devfn) != consumer)
5124 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5126 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5127 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5128 pci_dev_put(supplier_pdev);
5132 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5133 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5134 pci_info(pdev, "D0 power state depends on %s\n",
5135 pci_name(supplier_pdev));
5137 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5138 pci_name(supplier_pdev));
5140 pm_runtime_allow(&pdev->dev);
5141 pci_dev_put(supplier_pdev);
5145 * Create device link for GPUs with integrated HDA controller for streaming
5146 * audio to attached displays.
5148 static void quirk_gpu_hda(struct pci_dev *hda)
5150 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5152 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5153 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5154 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5155 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5156 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5157 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);