2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
37 static void quirk_mmio_always_on(struct pci_dev *dev)
39 dev->mmio_always_on = 1;
41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
44 /* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
48 static void quirk_mellanox_tavor(struct pci_dev *dev)
50 dev->broken_parity_status = 1; /* This device gives false positives */
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
55 /* Deal with broken BIOSes that neglect to enable passive release,
56 which can cause problems in combination with the 82441FX/PPro MTRRs */
57 static void quirk_passive_release(struct pci_dev *dev)
59 struct pci_dev *d = NULL;
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
69 pci_write_config_byte(d, 0x82, dlc);
73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
78 ask them for me please -- Alan
80 This appears to be BIOS not version dependent. So presumably there is a
83 static void quirk_isa_dma_hangs(struct pci_dev *dev)
85 if (!isa_dma_bridge_buggy) {
86 isa_dma_bridge_buggy = 1;
87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
123 * Chipsets where PCI->PCI transfers vanish or hang
125 static void quirk_nopcipci(struct pci_dev *dev)
127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
129 pci_pci_problems |= PCIPCI_FAIL;
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
135 static void quirk_nopciamd(struct pci_dev *dev)
138 pci_read_config_byte(dev, 0x08, &rev);
141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
142 pci_pci_problems |= PCIAGP_FAIL;
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
148 * Triton requires workarounds to be used by the drivers
150 static void quirk_triton(struct pci_dev *dev)
152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
154 pci_pci_problems |= PCIPCI_TRITON;
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
169 * Updated based on further information from the site and also on
170 * information provided by VIA
172 static void quirk_vialatency(struct pci_dev *dev)
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
183 if (p->revision < 0x40 || p->revision > 0x42)
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
187 if (p == NULL) /* No problem parts */
189 /* Check for buggy part revisions */
190 if (p->revision < 0x10 || p->revision > 0x12)
195 * Ok we have the problem. Now set the PCI master grant to
196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
201 * VIA only apply this fix when an SB Live! is present but under
202 * both Linux and Windows this isn't enough, and we have seen
203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
207 pci_read_config_byte(dev, 0x76, &busarb);
208 /* Set bit 4 and bi 5 of byte 76 to 0x01
209 "Master priority rotation on every PCI master grant */
212 pci_write_config_byte(dev, 0x76, busarb);
213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
220 /* Must restore this on a resume from RAM */
221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
226 * VIA Apollo VP3 needs ETBF on BT848/878
228 static void quirk_viaetbf(struct pci_dev *dev)
230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
232 pci_pci_problems |= PCIPCI_VIAETBF;
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
237 static void quirk_vsfx(struct pci_dev *dev)
239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
241 pci_pci_problems |= PCIPCI_VSFX;
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
252 static void quirk_alimagik(struct pci_dev *dev)
254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
263 * Natoma has some interesting boundary conditions with Zoran stuff
266 static void quirk_natoma(struct pci_dev *dev)
268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
270 pci_pci_problems |= PCIPCI_NATOMA;
273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
284 static void quirk_citrine(struct pci_dev *dev)
286 dev->cfg_size = 0xA0;
288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
291 * This chip can cause bus lockups if config addresses above 0x600
292 * are read or written.
294 static void quirk_nfp6000(struct pci_dev *dev)
296 dev->cfg_size = 0x600;
298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
302 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
303 static void quirk_extend_bar_to_page(struct pci_dev *dev)
307 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
308 struct resource *r = &dev->resource[i];
310 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
311 r->end = PAGE_SIZE - 1;
313 r->flags |= IORESOURCE_UNSET;
314 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
322 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
323 * If it's needed, re-allocate the region.
325 static void quirk_s3_64M(struct pci_dev *dev)
327 struct resource *r = &dev->resource[0];
329 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
330 r->flags |= IORESOURCE_UNSET;
335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
338 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
342 struct pci_bus_region bus_region;
343 struct resource *res = dev->resource + pos;
345 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
350 res->name = pci_name(dev);
351 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
353 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
354 region &= ~(size - 1);
356 /* Convert from PCI bus to resource space */
357 bus_region.start = region;
358 bus_region.end = region + size - 1;
359 pcibios_bus_to_resource(dev->bus, res, &bus_region);
361 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
362 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
366 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
367 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
368 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
369 * (which conflicts w/ BAR1's memory range).
371 * CS553x's ISA PCI BARs may also be read-only (ref:
372 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
374 static void quirk_cs5536_vsa(struct pci_dev *dev)
376 static char *name = "CS5536 ISA bridge";
378 if (pci_resource_len(dev, 0) != 8) {
379 quirk_io(dev, 0, 8, name); /* SMB */
380 quirk_io(dev, 1, 256, name); /* GPIO */
381 quirk_io(dev, 2, 64, name); /* MFGPT */
382 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
388 static void quirk_io_region(struct pci_dev *dev, int port,
389 unsigned size, int nr, const char *name)
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
395 pci_read_config_word(dev, port, ®ion);
396 region &= ~(size - 1);
401 res->name = pci_name(dev);
402 res->flags = IORESOURCE_IO;
404 /* Convert from PCI bus to resource space */
405 bus_region.start = region;
406 bus_region.end = region + size - 1;
407 pcibios_bus_to_resource(dev->bus, res, &bus_region);
409 if (!pci_claim_resource(dev, nr))
410 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
414 * ATI Northbridge setups MCE the processor if you even
415 * read somewhere between 0x3b0->0x3bb or read 0x3d3
417 static void quirk_ati_exploding_mce(struct pci_dev *dev)
419 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
420 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
421 request_region(0x3b0, 0x0C, "RadeonIGP");
422 request_region(0x3d3, 0x01, "RadeonIGP");
424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
427 * In the AMD NL platform, this device ([1022:7912]) has a class code of
428 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
430 * But the dwc3 driver is a more specific driver for this device, and we'd
431 * prefer to use it instead of xhci. To prevent xhci from claiming the
432 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
433 * defines as "USB device (not host controller)". The dwc3 driver can then
434 * claim it based on its Vendor and Device ID.
436 static void quirk_amd_nl_class(struct pci_dev *pdev)
438 u32 class = pdev->class;
440 /* Use "USB Device (not host controller)" class */
441 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
442 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
449 * Let's make the southbridge information explicit instead
450 * of having to worry about people probing the ACPI areas,
451 * for example.. (Yes, it happens, and if you read the wrong
452 * ACPI register it will put the machine to sleep with no
453 * way of waking it up again. Bummer).
455 * ALI M7101: Two IO regions pointed to by words at
456 * 0xE0 (64 bytes of ACPI registers)
457 * 0xE2 (32 bytes of SMB registers)
459 static void quirk_ali7101_acpi(struct pci_dev *dev)
461 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
462 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
466 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
469 u32 mask, size, base;
471 pci_read_config_dword(dev, port, &devres);
472 if ((devres & enable) != enable)
474 mask = (devres >> 16) & 15;
475 base = devres & 0xffff;
478 unsigned bit = size >> 1;
479 if ((bit & mask) == bit)
484 * For now we only print it out. Eventually we'll want to
485 * reserve it (at least if it's in the 0x1000+ range), but
486 * let's get enough confirmation reports first.
489 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
493 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
496 u32 mask, size, base;
498 pci_read_config_dword(dev, port, &devres);
499 if ((devres & enable) != enable)
501 base = devres & 0xffff0000;
502 mask = (devres & 0x3f) << 16;
505 unsigned bit = size >> 1;
506 if ((bit & mask) == bit)
511 * For now we only print it out. Eventually we'll want to
512 * reserve it, but let's get enough confirmation reports first.
515 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
520 * PIIX4 ACPI: Two IO regions pointed to by longwords at
521 * 0x40 (64 bytes of ACPI registers)
522 * 0x90 (16 bytes of SMB registers)
523 * and a few strange programmable PIIX4 device resources.
525 static void quirk_piix4_acpi(struct pci_dev *dev)
529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
532 /* Device resource A has enables for some of the other ones */
533 pci_read_config_dword(dev, 0x5c, &res_a);
535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
538 /* Device resource D is just bitfields for static resources */
540 /* Device 12 enabled? */
541 if (res_a & (1 << 29)) {
542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
545 /* Device 13 enabled? */
546 if (res_a & (1 << 30)) {
547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
556 #define ICH_PMBASE 0x40
557 #define ICH_ACPI_CNTL 0x44
558 #define ICH4_ACPI_EN 0x10
559 #define ICH6_ACPI_EN 0x80
560 #define ICH4_GPIOBASE 0x58
561 #define ICH4_GPIO_CNTL 0x5c
562 #define ICH4_GPIO_EN 0x10
563 #define ICH6_GPIOBASE 0x48
564 #define ICH6_GPIO_CNTL 0x4c
565 #define ICH6_GPIO_EN 0x10
568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
570 * 0x58 (64 bytes of GPIO I/O space)
572 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
578 * with low legacy (and fixed) ports. We don't know the decoding
579 * priority and can't tell whether the legacy device or the one created
580 * here is really at that address. This happens on boards with broken
584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
585 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
587 "ICH4 ACPI/GPIO/TCO");
589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
590 if (enable & ICH4_GPIO_EN)
591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
605 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
610 if (enable & ICH6_ACPI_EN)
611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
612 "ICH6 ACPI/GPIO/TCO");
614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
615 if (enable & ICH6_GPIO_EN)
616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
620 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
625 pci_read_config_dword(dev, reg, &val);
633 * This is not correct. It is 16, 32 or 64 bytes depending on
634 * register D31:F0:ADh bits 5:4.
636 * But this gets us at least _part_ of it.
644 /* Just print it out for now. We should reserve it after more debugging */
645 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
648 static void quirk_ich6_lpc(struct pci_dev *dev)
650 /* Shared ACPI/GPIO decode with all ICH6+ */
651 ich6_lpc_acpi_gpio(dev);
653 /* ICH6-specific generic IO decode */
654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
660 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
665 pci_read_config_dword(dev, reg, &val);
672 * IO base in bits 15:2, mask in bits 23:18, both
676 mask = (val >> 16) & 0xfc;
679 /* Just print it out for now. We should reserve it after more debugging */
680 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
683 /* ICH7-10 has the same common LPC generic IO decode registers */
684 static void quirk_ich7_lpc(struct pci_dev *dev)
686 /* We share the common ACPI/GPIO decode with ICH6 */
687 ich6_lpc_acpi_gpio(dev);
689 /* And have 4 ICH7+ generic decodes */
690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
710 * VIA ACPI: One IO region pointed to by longword at
711 * 0x48 or 0x20 (256 bytes of ACPI registers)
713 static void quirk_vt82c586_acpi(struct pci_dev *dev)
715 if (dev->revision & 0x10)
716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
723 * 0x48 (256 bytes of ACPI registers)
724 * 0x70 (128 bytes of hardware monitoring register)
725 * 0x90 (16 bytes of SMB registers)
727 static void quirk_vt82c686_acpi(struct pci_dev *dev)
729 quirk_vt82c586_acpi(dev);
731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
740 * 0x88 (128 bytes of power management registers)
741 * 0xd0 (16 bytes of SMB registers)
743 static void quirk_vt8235_acpi(struct pci_dev *dev)
745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
752 * Disable fast back-to-back on the secondary bus segment
754 static void quirk_xio2000a(struct pci_dev *dev)
756 struct pci_dev *pdev;
759 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
761 pci_read_config_word(pdev, PCI_COMMAND, &command);
762 if (command & PCI_COMMAND_FAST_BACK)
763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
769 #ifdef CONFIG_X86_IO_APIC
771 #include <asm/io_apic.h>
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC.
777 * TODO: When we have device-specific interrupt routers,
778 * this code will go away from quirks.
780 static void quirk_via_ioapic(struct pci_dev *dev)
785 tmp = 0; /* nothing routed to external APIC */
787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
789 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
790 tmp == 0 ? "Disa" : "Ena");
792 /* Offset 0x58: External APIC IRQ output control */
793 pci_write_config_byte(dev, 0x58, tmp);
795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
796 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
800 * This leads to doubled level interrupt rates.
801 * Set this bit to get rid of cycle wastage.
802 * Otherwise uncritical.
804 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
807 #define BYPASS_APIC_DEASSERT 8
809 pci_read_config_byte(dev, 0x5B, &misc_control2);
810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
811 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
816 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
819 * The AMD io apic can hang the box when an apic irq is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix
823 * We have multiple reports of hangs with this chipset that went away with
824 * noapic specified. For the moment we assume it's the erratum. We may be wrong
825 * of course. However the advice is demonstrably good even if so..
827 static void quirk_amd_ioapic(struct pci_dev *dev)
829 if (dev->revision >= 0x02) {
830 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
835 #endif /* CONFIG_X86_IO_APIC */
837 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
839 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
841 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
842 if (dev->subsystem_device == 0xa118)
843 dev->sriov->link = dev->devfn;
845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
849 * Some settings of MMRBC can lead to data corruption so block changes.
850 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
852 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
854 if (dev->subordinate && dev->revision <= 0x12) {
855 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
857 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
863 * FIXME: it is questionable that quirk_via_acpi
864 * is needed. It shows up as an ISA bridge, and does not
865 * support the PCI_INTERRUPT_LINE register at all. Therefore
866 * it seems like setting the pci_dev's 'irq' to the
867 * value of the ACPI SCI interrupt is only done for convenience.
870 static void quirk_via_acpi(struct pci_dev *d)
873 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
876 pci_read_config_byte(d, 0x42, &irq);
878 if (irq && (irq != 2))
881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
886 * VIA bridges which have VLink
889 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
891 static void quirk_via_bridge(struct pci_dev *dev)
893 /* See what bridge we have and find the device ranges */
894 switch (dev->device) {
895 case PCI_DEVICE_ID_VIA_82C686:
896 /* The VT82C686 is special, it attaches to PCI and can have
897 any device number. All its subdevices are functions of
898 that single device. */
899 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
900 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
902 case PCI_DEVICE_ID_VIA_8237:
903 case PCI_DEVICE_ID_VIA_8237A:
904 via_vlink_dev_lo = 15;
906 case PCI_DEVICE_ID_VIA_8235:
907 via_vlink_dev_lo = 16;
909 case PCI_DEVICE_ID_VIA_8231:
910 case PCI_DEVICE_ID_VIA_8233_0:
911 case PCI_DEVICE_ID_VIA_8233A:
912 case PCI_DEVICE_ID_VIA_8233C_0:
913 via_vlink_dev_lo = 17;
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
927 * quirk_via_vlink - VIA VLink IRQ number update
930 * If the device we are dealing with is on a PIC IRQ we need to
931 * ensure that the IRQ line register which usually is not relevant
932 * for PCI cards, is actually written so that interrupts get sent
933 * to the right place.
934 * We only do this on systems where a VIA south bridge was detected,
935 * and only for VIA devices on the motherboard (see quirk_via_bridge
939 static void quirk_via_vlink(struct pci_dev *dev)
943 /* Check if we have VLink at all */
944 if (via_vlink_dev_lo == -1)
949 /* Don't quirk interrupts outside the legacy IRQ range */
950 if (!new_irq || new_irq > 15)
953 /* Internal device ? */
954 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
955 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
958 /* This is an internal VLink device on a PIC interrupt. The BIOS
959 ought to have set this but may not have, so we redo it */
961 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
962 if (new_irq != irq) {
963 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
965 udelay(15); /* unknown if delay really needed */
966 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
969 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
972 * VIA VT82C598 has its device ID settable and many BIOSes
973 * set it to the ID of VT82C597 for backward compatibility.
974 * We need to switch it off to be able to recognize the real
977 static void quirk_vt82c598_id(struct pci_dev *dev)
979 pci_write_config_byte(dev, 0xfc, 0);
980 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
985 * CardBus controllers have a legacy base address that enables them
986 * to respond as i82365 pcmcia controllers. We don't want them to
987 * do this even if the Linux CardBus driver is not loaded, because
988 * the Linux i82365 driver does not (and should not) handle CardBus.
990 static void quirk_cardbus_legacy(struct pci_dev *dev)
992 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
994 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
995 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
996 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1000 * Following the PCI ordering rules is optional on the AMD762. I'm not
1001 * sure what the designers were smoking but let's not inhale...
1003 * To be fair to AMD, it follows the spec by default, its BIOS people
1006 static void quirk_amd_ordering(struct pci_dev *dev)
1009 pci_read_config_dword(dev, 0x4C, &pcic);
1010 if ((pcic & 6) != 6) {
1012 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1013 pci_write_config_dword(dev, 0x4C, pcic);
1014 pci_read_config_dword(dev, 0x84, &pcic);
1015 pcic |= (1 << 23); /* Required in this mode */
1016 pci_write_config_dword(dev, 0x84, pcic);
1019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1020 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1023 * DreamWorks provided workaround for Dunord I-3000 problem
1025 * This card decodes and responds to addresses not apparently
1026 * assigned to it. We force a larger allocation to ensure that
1027 * nothing gets put too close to it.
1029 static void quirk_dunord(struct pci_dev *dev)
1031 struct resource *r = &dev->resource[1];
1033 r->flags |= IORESOURCE_UNSET;
1037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1040 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1041 * is subtractive decoding (transparent), and does indicate this
1042 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1045 static void quirk_transparent_bridge(struct pci_dev *dev)
1047 dev->transparent = 1;
1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1053 * Common misconfiguration of the MediaGX/Geode PCI master that will
1054 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1055 * datasheets found at http://www.national.com/analog for info on what
1056 * these bits do. <christer@weinigel.se>
1058 static void quirk_mediagx_master(struct pci_dev *dev)
1062 pci_read_config_byte(dev, 0x41, ®);
1065 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1067 pci_write_config_byte(dev, 0x41, reg);
1070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1071 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1074 * Ensure C0 rev restreaming is off. This is normally done by
1075 * the BIOS but in the odd case it is not the results are corruption
1076 * hence the presence of a Linux check
1078 static void quirk_disable_pxb(struct pci_dev *pdev)
1082 if (pdev->revision != 0x04) /* Only C0 requires this */
1084 pci_read_config_word(pdev, 0x40, &config);
1085 if (config & (1<<6)) {
1087 pci_write_config_word(pdev, 0x40, config);
1088 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1092 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1094 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1096 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1099 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1101 pci_read_config_byte(pdev, 0x40, &tmp);
1102 pci_write_config_byte(pdev, 0x40, tmp|1);
1103 pci_write_config_byte(pdev, 0x9, 1);
1104 pci_write_config_byte(pdev, 0xa, 6);
1105 pci_write_config_byte(pdev, 0x40, tmp);
1107 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1108 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1112 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1116 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1118 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1121 * Serverworks CSB5 IDE does not fully support native mode
1123 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1130 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1131 /* PCI layer will sort out resources */
1134 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1137 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1139 static void quirk_ide_samemode(struct pci_dev *pdev)
1143 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1145 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1146 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1149 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1152 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1155 * Some ATA devices break if put into D3
1158 static void quirk_no_ata_d3(struct pci_dev *pdev)
1160 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1162 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1163 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1164 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1165 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1166 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1167 /* ALi loses some register settings that we cannot then restore */
1168 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1169 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1170 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1171 occur when mode detecting */
1172 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1175 /* This was originally an Alpha specific thing, but it really fits here.
1176 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1178 static void quirk_eisa_bridge(struct pci_dev *dev)
1180 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1186 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1187 * is not activated. The myth is that Asus said that they do not want the
1188 * users to be irritated by just another PCI Device in the Win98 device
1189 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1190 * package 2.7.0 for details)
1192 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1193 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1194 * becomes necessary to do this tweak in two steps -- the chosen trigger
1195 * is either the Host bridge (preferred) or on-board VGA controller.
1197 * Note that we used to unhide the SMBus that way on Toshiba laptops
1198 * (Satellite A40 and Tecra M2) but then found that the thermal management
1199 * was done by SMM code, which could cause unsynchronized concurrent
1200 * accesses to the SMBus registers, with potentially bad effects. Thus you
1201 * should be very careful when adding new entries: if SMM is accessing the
1202 * Intel SMBus, this is a very good reason to leave it hidden.
1204 * Likewise, many recent laptops use ACPI for thermal management. If the
1205 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1206 * natively, and keeping the SMBus hidden is the right thing to do. If you
1207 * are about to add an entry in the table below, please first disassemble
1208 * the DSDT and double-check that there is no code accessing the SMBus.
1210 static int asus_hides_smbus;
1212 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1214 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1215 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1216 switch (dev->subsystem_device) {
1217 case 0x8025: /* P4B-LX */
1218 case 0x8070: /* P4B */
1219 case 0x8088: /* P4B533 */
1220 case 0x1626: /* L3C notebook */
1221 asus_hides_smbus = 1;
1223 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1224 switch (dev->subsystem_device) {
1225 case 0x80b1: /* P4GE-V */
1226 case 0x80b2: /* P4PE */
1227 case 0x8093: /* P4B533-V */
1228 asus_hides_smbus = 1;
1230 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1231 switch (dev->subsystem_device) {
1232 case 0x8030: /* P4T533 */
1233 asus_hides_smbus = 1;
1235 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1236 switch (dev->subsystem_device) {
1237 case 0x8070: /* P4G8X Deluxe */
1238 asus_hides_smbus = 1;
1240 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1241 switch (dev->subsystem_device) {
1242 case 0x80c9: /* PU-DLS */
1243 asus_hides_smbus = 1;
1245 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1246 switch (dev->subsystem_device) {
1247 case 0x1751: /* M2N notebook */
1248 case 0x1821: /* M5N notebook */
1249 case 0x1897: /* A6L notebook */
1250 asus_hides_smbus = 1;
1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1253 switch (dev->subsystem_device) {
1254 case 0x184b: /* W1N notebook */
1255 case 0x186a: /* M6Ne notebook */
1256 asus_hides_smbus = 1;
1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1259 switch (dev->subsystem_device) {
1260 case 0x80f2: /* P4P800-X */
1261 asus_hides_smbus = 1;
1263 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1264 switch (dev->subsystem_device) {
1265 case 0x1882: /* M6V notebook */
1266 case 0x1977: /* A6VA notebook */
1267 asus_hides_smbus = 1;
1269 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1270 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1271 switch (dev->subsystem_device) {
1272 case 0x088C: /* HP Compaq nc8000 */
1273 case 0x0890: /* HP Compaq nc6000 */
1274 asus_hides_smbus = 1;
1276 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1277 switch (dev->subsystem_device) {
1278 case 0x12bc: /* HP D330L */
1279 case 0x12bd: /* HP D530 */
1280 case 0x006a: /* HP Compaq nx9500 */
1281 asus_hides_smbus = 1;
1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1284 switch (dev->subsystem_device) {
1285 case 0x12bf: /* HP xw4100 */
1286 asus_hides_smbus = 1;
1288 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1289 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1290 switch (dev->subsystem_device) {
1291 case 0xC00C: /* Samsung P35 notebook */
1292 asus_hides_smbus = 1;
1294 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1295 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1296 switch (dev->subsystem_device) {
1297 case 0x0058: /* Compaq Evo N620c */
1298 asus_hides_smbus = 1;
1300 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1301 switch (dev->subsystem_device) {
1302 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1303 /* Motherboard doesn't have Host bridge
1304 * subvendor/subdevice IDs, therefore checking
1305 * its on-board VGA controller */
1306 asus_hides_smbus = 1;
1308 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1309 switch (dev->subsystem_device) {
1310 case 0x00b8: /* Compaq Evo D510 CMT */
1311 case 0x00b9: /* Compaq Evo D510 SFF */
1312 case 0x00ba: /* Compaq Evo D510 USDT */
1313 /* Motherboard doesn't have Host bridge
1314 * subvendor/subdevice IDs and on-board VGA
1315 * controller is disabled if an AGP card is
1316 * inserted, therefore checking USB UHCI
1318 asus_hides_smbus = 1;
1320 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1321 switch (dev->subsystem_device) {
1322 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1323 /* Motherboard doesn't have host bridge
1324 * subvendor/subdevice IDs, therefore checking
1325 * its on-board VGA controller */
1326 asus_hides_smbus = 1;
1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1345 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1349 if (likely(!asus_hides_smbus))
1352 pci_read_config_word(dev, 0xF2, &val);
1354 pci_write_config_word(dev, 0xF2, val & (~0x8));
1355 pci_read_config_word(dev, 0xF2, &val);
1357 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1360 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1370 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1371 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1378 /* It appears we just have one such device. If not, we have a warning */
1379 static void __iomem *asus_rcba_base;
1380 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1384 if (likely(!asus_hides_smbus))
1386 WARN_ON(asus_rcba_base);
1388 pci_read_config_dword(dev, 0xF0, &rcba);
1389 /* use bits 31:14, 16 kB aligned */
1390 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1391 if (asus_rcba_base == NULL)
1395 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1399 if (likely(!asus_hides_smbus || !asus_rcba_base))
1401 /* read the Function Disable register, dword mode only */
1402 val = readl(asus_rcba_base + 0x3418);
1403 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1406 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1408 if (likely(!asus_hides_smbus || !asus_rcba_base))
1410 iounmap(asus_rcba_base);
1411 asus_rcba_base = NULL;
1412 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1415 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1417 asus_hides_smbus_lpc_ich6_suspend(dev);
1418 asus_hides_smbus_lpc_ich6_resume_early(dev);
1419 asus_hides_smbus_lpc_ich6_resume(dev);
1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1422 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1423 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1427 * SiS 96x south bridge: BIOS typically hides SMBus device...
1429 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1432 pci_read_config_byte(dev, 0x77, &val);
1434 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1435 pci_write_config_byte(dev, 0x77, val & ~0x10);
1438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1442 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1443 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1448 * ... This is further complicated by the fact that some SiS96x south
1449 * bridges pretend to be 85C503/5513 instead. In that case see if we
1450 * spotted a compatible north bridge to make sure.
1451 * (pci_find_device doesn't work yet)
1453 * We can also enable the sis96x bit in the discovery register..
1455 #define SIS_DETECT_REGISTER 0x40
1457 static void quirk_sis_503(struct pci_dev *dev)
1462 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1463 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1464 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1465 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1471 * Ok, it now shows up as a 96x.. run the 96x quirk by
1472 * hand in case it has already been processed.
1473 * (depends on link order, which is apparently not guaranteed)
1475 dev->device = devid;
1476 quirk_sis_96x_smbus(dev);
1478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1479 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1483 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1484 * and MC97 modem controller are disabled when a second PCI soundcard is
1485 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1488 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1491 int asus_hides_ac97 = 0;
1493 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1494 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1495 asus_hides_ac97 = 1;
1498 if (!asus_hides_ac97)
1501 pci_read_config_byte(dev, 0x50, &val);
1503 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1504 pci_read_config_byte(dev, 0x50, &val);
1506 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1509 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1513 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1515 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1518 * If we are using libata we can drive this chip properly but must
1519 * do this early on to make the additional device appear during
1522 static void quirk_jmicron_ata(struct pci_dev *pdev)
1524 u32 conf1, conf5, class;
1527 /* Only poke fn 0 */
1528 if (PCI_FUNC(pdev->devfn))
1531 pci_read_config_dword(pdev, 0x40, &conf1);
1532 pci_read_config_dword(pdev, 0x80, &conf5);
1534 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1535 conf5 &= ~(1 << 24); /* Clear bit 24 */
1537 switch (pdev->device) {
1538 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1539 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1540 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1541 /* The controller should be in single function ahci mode */
1542 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1545 case PCI_DEVICE_ID_JMICRON_JMB365:
1546 case PCI_DEVICE_ID_JMICRON_JMB366:
1547 /* Redirect IDE second PATA port to the right spot */
1550 case PCI_DEVICE_ID_JMICRON_JMB361:
1551 case PCI_DEVICE_ID_JMICRON_JMB363:
1552 case PCI_DEVICE_ID_JMICRON_JMB369:
1553 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1554 /* Set the class codes correctly and then direct IDE 0 */
1555 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1558 case PCI_DEVICE_ID_JMICRON_JMB368:
1559 /* The controller should be in single function IDE mode */
1560 conf1 |= 0x00C00000; /* Set 22, 23 */
1564 pci_write_config_dword(pdev, 0x40, conf1);
1565 pci_write_config_dword(pdev, 0x80, conf5);
1567 /* Update pdev accordingly */
1568 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1569 pdev->hdr_type = hdr & 0x7f;
1570 pdev->multifunction = !!(hdr & 0x80);
1572 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1573 pdev->class = class >> 8;
1575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1584 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1585 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1596 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1598 if (dev->multifunction) {
1599 device_disable_async_suspend(&dev->dev);
1600 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1603 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1604 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1608 #ifdef CONFIG_X86_IO_APIC
1609 static void quirk_alder_ioapic(struct pci_dev *pdev)
1613 if ((pdev->class >> 8) != 0xff00)
1616 /* the first BAR is the location of the IO APIC...we must
1617 * not touch this (and it's already covered by the fixmap), so
1618 * forcibly insert it into the resource tree */
1619 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1620 insert_resource(&iomem_resource, &pdev->resource[0]);
1622 /* The next five BARs all seem to be rubbish, so just clean
1624 for (i = 1; i < 6; i++)
1625 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1630 static void quirk_pcie_mch(struct pci_dev *pdev)
1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1638 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1641 * It's possible for the MSI to get corrupted if shpc and acpi
1642 * are used together on certain PXH-based systems.
1644 static void quirk_pcie_pxh(struct pci_dev *dev)
1647 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1649 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1656 * Some Intel PCI Express chipsets have trouble with downstream
1657 * device power management.
1659 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1661 pci_pm_d3_delay = 120;
1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1687 #ifdef CONFIG_X86_IO_APIC
1689 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1690 * remap the original interrupt in the linux kernel to the boot interrupt, so
1691 * that a PCI device's interrupt handler is installed on the boot interrupt
1694 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1696 if (noioapicquirk || noioapicreroute)
1699 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1700 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1701 dev->vendor, dev->device);
1703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1711 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1712 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1713 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1714 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1715 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1716 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1717 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1718 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1721 * On some chipsets we can disable the generation of legacy INTx boot
1726 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1727 * 300641-004US, section 5.7.3.
1729 #define INTEL_6300_IOAPIC_ABAR 0x40
1730 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1732 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1734 u16 pci_config_word;
1739 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1740 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1741 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1743 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1744 dev->vendor, dev->device);
1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1747 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1750 * disable boot interrupts on HT-1000
1752 #define BC_HT1000_FEATURE_REG 0x64
1753 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1754 #define BC_HT1000_MAP_IDX 0xC00
1755 #define BC_HT1000_MAP_DATA 0xC01
1757 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1759 u32 pci_config_dword;
1765 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1766 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1767 BC_HT1000_PIC_REGS_ENABLE);
1769 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1770 outb(irq, BC_HT1000_MAP_IDX);
1771 outb(0x00, BC_HT1000_MAP_DATA);
1774 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1776 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1777 dev->vendor, dev->device);
1779 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1780 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1783 * disable boot interrupts on AMD and ATI chipsets
1786 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1787 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1788 * (due to an erratum).
1790 #define AMD_813X_MISC 0x40
1791 #define AMD_813X_NOIOAMODE (1<<0)
1792 #define AMD_813X_REV_B1 0x12
1793 #define AMD_813X_REV_B2 0x13
1795 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1797 u32 pci_config_dword;
1801 if ((dev->revision == AMD_813X_REV_B1) ||
1802 (dev->revision == AMD_813X_REV_B2))
1805 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1806 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1807 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1809 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1810 dev->vendor, dev->device);
1812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1813 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1815 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1817 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1819 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1821 u16 pci_config_word;
1826 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1827 if (!pci_config_word) {
1828 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1829 dev->vendor, dev->device);
1832 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1833 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1834 dev->vendor, dev->device);
1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1837 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1838 #endif /* CONFIG_X86_IO_APIC */
1841 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1842 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1843 * Re-allocate the region if needed...
1845 static void quirk_tc86c001_ide(struct pci_dev *dev)
1847 struct resource *r = &dev->resource[0];
1849 if (r->start & 0x8) {
1850 r->flags |= IORESOURCE_UNSET;
1855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1856 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1857 quirk_tc86c001_ide);
1860 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1861 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1862 * being read correctly if bit 7 of the base address is set.
1863 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1864 * Re-allocate the regions to a 256-byte boundary if necessary.
1866 static void quirk_plx_pci9050(struct pci_dev *dev)
1870 /* Fixed in revision 2 (PCI 9052). */
1871 if (dev->revision >= 2)
1873 for (bar = 0; bar <= 1; bar++)
1874 if (pci_resource_len(dev, bar) == 0x80 &&
1875 (pci_resource_start(dev, bar) & 0x80)) {
1876 struct resource *r = &dev->resource[bar];
1877 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1879 r->flags |= IORESOURCE_UNSET;
1884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1887 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1888 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1889 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1890 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1892 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1895 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1896 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1898 static void quirk_netmos(struct pci_dev *dev)
1900 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1901 unsigned int num_serial = dev->subsystem_device & 0xf;
1904 * These Netmos parts are multiport serial devices with optional
1905 * parallel ports. Even when parallel ports are present, they
1906 * are identified as class SERIAL, which means the serial driver
1907 * will claim them. To prevent this, mark them as class OTHER.
1908 * These combo devices should be claimed by parport_serial.
1910 * The subdevice ID is of the form 0x00PS, where <P> is the number
1911 * of parallel ports and <S> is the number of serial ports.
1913 switch (dev->device) {
1914 case PCI_DEVICE_ID_NETMOS_9835:
1915 /* Well, this rule doesn't hold for the following 9835 device */
1916 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1917 dev->subsystem_device == 0x0299)
1919 case PCI_DEVICE_ID_NETMOS_9735:
1920 case PCI_DEVICE_ID_NETMOS_9745:
1921 case PCI_DEVICE_ID_NETMOS_9845:
1922 case PCI_DEVICE_ID_NETMOS_9855:
1924 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1925 dev->device, num_parallel, num_serial);
1926 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1927 (dev->class & 0xff);
1931 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1932 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1935 * Quirk non-zero PCI functions to route VPD access through function 0 for
1936 * devices that share VPD resources between functions. The functions are
1937 * expected to be identical devices.
1939 static void quirk_f0_vpd_link(struct pci_dev *dev)
1943 if (!PCI_FUNC(dev->devfn))
1946 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1950 if (f0->vpd && dev->class == f0->class &&
1951 dev->vendor == f0->vendor && dev->device == f0->device)
1952 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1956 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1957 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1959 static void quirk_e100_interrupt(struct pci_dev *dev)
1965 switch (dev->device) {
1966 /* PCI IDs taken from drivers/net/e100.c */
1968 case 0x1030 ... 0x1034:
1969 case 0x1038 ... 0x103E:
1970 case 0x1050 ... 0x1057:
1972 case 0x1064 ... 0x106B:
1973 case 0x1091 ... 0x1095:
1986 * Some firmware hands off the e100 with interrupts enabled,
1987 * which can cause a flood of interrupts if packets are
1988 * received before the driver attaches to the device. So
1989 * disable all e100 interrupts here. The driver will
1990 * re-enable them when it's ready.
1992 pci_read_config_word(dev, PCI_COMMAND, &command);
1994 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1998 * Check that the device is in the D0 power state. If it's not,
1999 * there is no point to look any further.
2002 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2003 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2007 /* Convert from PCI bus to resource space. */
2008 csr = ioremap(pci_resource_start(dev, 0), 8);
2010 dev_warn(&dev->dev, "Can't map e100 registers\n");
2014 cmd_hi = readb(csr + 3);
2016 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2022 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2023 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2026 * The 82575 and 82598 may experience data corruption issues when transitioning
2027 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2029 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2031 dev_info(&dev->dev, "Disabling L0s\n");
2032 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2049 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2051 pci_info(dev, "Disabling ASPM L0s/L1\n");
2052 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2056 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2057 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2058 * disable both L0s and L1 for now to be safe.
2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2063 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2064 * Link bit cleared after starting the link retrain process to allow this
2065 * process to finish.
2067 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2068 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2070 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2072 dev->clear_retrain_link = 1;
2073 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2075 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2076 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2077 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2079 static void fixup_rev1_53c810(struct pci_dev *dev)
2081 u32 class = dev->class;
2084 * rev 1 ncr53c810 chips don't set the class at all which means
2085 * they don't get their resources remapped. Fix that here.
2090 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2091 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2096 /* Enable 1k I/O space granularity on the Intel P64H2 */
2097 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2101 pci_read_config_word(dev, 0x40, &en1k);
2104 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2105 dev->io_window_1k = 1;
2108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2110 /* Under some circumstances, AER is not linked with extended capabilities.
2111 * Force it to be linked by setting the corresponding control bit in the
2114 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2117 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2119 pci_write_config_byte(dev, 0xf41, b | 0x20);
2120 dev_info(&dev->dev, "Linking AER extended capability\n");
2124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2125 quirk_nvidia_ck804_pcie_aer_ext_cap);
2126 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2127 quirk_nvidia_ck804_pcie_aer_ext_cap);
2129 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2132 * Disable PCI Bus Parking and PCI Master read caching on CX700
2133 * which causes unspecified timing errors with a VT6212L on the PCI
2134 * bus leading to USB2.0 packet loss.
2136 * This quirk is only enabled if a second (on the external PCI bus)
2137 * VT6212L is found -- the CX700 core itself also contains a USB
2138 * host controller with the same PCI ID as the VT6212L.
2141 /* Count VT6212L instances */
2142 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2143 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2146 /* p should contain the first (internal) VT6212L -- see if we have
2147 an external one by searching again */
2148 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2153 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2155 /* Turn off PCI Bus Parking */
2156 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2158 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2162 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2164 /* Turn off PCI Master read caching */
2165 pci_write_config_byte(dev, 0x72, 0x0);
2167 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2168 pci_write_config_byte(dev, 0x75, 0x1);
2170 /* Disable "Read FIFO Timer" */
2171 pci_write_config_byte(dev, 0x77, 0x0);
2173 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2180 * If a device follows the VPD format spec, the PCI core will not read or
2181 * write past the VPD End Tag. But some vendors do not follow the VPD
2182 * format spec, so we can't tell how much data is safe to access. Devices
2183 * may behave unpredictably if we access too much. Blacklist these devices
2184 * so we don't touch VPD at all.
2186 static void quirk_blacklist_vpd(struct pci_dev *dev)
2190 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2206 quirk_blacklist_vpd);
2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2210 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2211 * VPD end tag will hang the device. This problem was initially
2212 * observed when a vpd entry was created in sysfs
2213 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2214 * will dump 32k of data. Reading a full 32k will cause an access
2215 * beyond the VPD end tag causing the device to hang. Once the device
2216 * is hung, the bnx2 driver will not be able to reset the device.
2217 * We believe that it is legal to read beyond the end tag and
2218 * therefore the solution is to limit the read/write length.
2220 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2223 * Only disable the VPD capability for 5706, 5706S, 5708,
2224 * 5708S and 5709 rev. A
2226 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2227 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2228 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2229 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2230 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2231 (dev->revision & 0xf0) == 0x0)) {
2233 dev->vpd->len = 0x80;
2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2238 PCI_DEVICE_ID_NX2_5706,
2239 quirk_brcm_570x_limit_vpd);
2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2241 PCI_DEVICE_ID_NX2_5706S,
2242 quirk_brcm_570x_limit_vpd);
2243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2244 PCI_DEVICE_ID_NX2_5708,
2245 quirk_brcm_570x_limit_vpd);
2246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2247 PCI_DEVICE_ID_NX2_5708S,
2248 quirk_brcm_570x_limit_vpd);
2249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2250 PCI_DEVICE_ID_NX2_5709,
2251 quirk_brcm_570x_limit_vpd);
2252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2253 PCI_DEVICE_ID_NX2_5709S,
2254 quirk_brcm_570x_limit_vpd);
2256 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2260 pci_read_config_dword(dev, 0xf4, &rev);
2262 /* Only CAP the MRRS if the device is a 5719 A0 */
2263 if (rev == 0x05719000) {
2264 int readrq = pcie_get_readrq(dev);
2266 pcie_set_readrq(dev, 2048);
2270 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2271 PCI_DEVICE_ID_TIGON3_5719,
2272 quirk_brcm_5719_limit_mrrs);
2274 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2275 static void quirk_paxc_bridge(struct pci_dev *pdev)
2277 /* The PCI config space is shared with the PAXC root port and the first
2278 * Ethernet device. So, we need to workaround this by telling the PCI
2279 * code that the bridge is not an Ethernet device.
2281 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2282 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2284 /* MPSS is not being set properly (as it is currently 0). This is
2285 * because that area of the PCI config space is hard coded to zero, and
2286 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2287 * so that the MPS can be set to the real max value.
2289 pdev->pcie_mpss = 2;
2291 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2292 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2295 /* Originally in EDAC sources for i82875P:
2296 * Intel tells BIOS developers to hide device 6 which
2297 * configures the overflow device access containing
2298 * the DRBs - this is where we expose device 6.
2299 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2301 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2305 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2306 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2307 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2311 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2312 quirk_unhide_mch_dev6);
2313 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2314 quirk_unhide_mch_dev6);
2316 #ifdef CONFIG_TILEPRO
2318 * The Tilera TILEmpower tilepro platform needs to set the link speed
2319 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2320 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2321 * capability register of the PEX8624 PCIe switch. The switch
2322 * supports link speed auto negotiation, but falsely sets
2323 * the link speed to 5GT/s.
2325 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2327 if (tile_plx_gen1) {
2328 pci_write_config_dword(dev, 0x98, 0x1);
2332 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2333 #endif /* CONFIG_TILEPRO */
2335 #ifdef CONFIG_PCI_MSI
2336 /* Some chipsets do not support MSI. We cannot easily rely on setting
2337 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2338 * some other buses controlled by the chipset even if Linux is not
2339 * aware of it. Instead of setting the flag on all buses in the
2340 * machine, simply disable MSI globally.
2342 static void quirk_disable_all_msi(struct pci_dev *dev)
2345 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2347 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2351 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2352 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2353 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2354 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2356 /* Disable MSI on chipsets that are known to not support it */
2357 static void quirk_disable_msi(struct pci_dev *dev)
2359 if (dev->subordinate) {
2360 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2361 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2364 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2365 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2366 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2369 * The APC bridge device in AMD 780 family northbridges has some random
2370 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2371 * we use the possible vendor/device IDs of the host bridge for the
2372 * declared quirk, and search for the APC bridge by slot number.
2374 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2376 struct pci_dev *apc_bridge;
2378 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2380 if (apc_bridge->device == 0x9602)
2381 quirk_disable_msi(apc_bridge);
2382 pci_dev_put(apc_bridge);
2385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2388 /* Go through the list of Hypertransport capabilities and
2389 * return 1 if a HT MSI capability is found and enabled */
2390 static int msi_ht_cap_enabled(struct pci_dev *dev)
2392 int pos, ttl = PCI_FIND_CAP_TTL;
2394 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2395 while (pos && ttl--) {
2398 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2400 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2401 flags & HT_MSI_FLAGS_ENABLE ?
2402 "enabled" : "disabled");
2403 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2406 pos = pci_find_next_ht_capability(dev, pos,
2407 HT_CAPTYPE_MSI_MAPPING);
2412 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2413 static void quirk_msi_ht_cap(struct pci_dev *dev)
2415 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2416 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2417 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2423 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2424 * MSI are supported if the MSI capability set in any of these mappings.
2426 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2428 struct pci_dev *pdev;
2430 if (!dev->subordinate)
2433 /* check HT MSI cap on this chipset and the root one.
2434 * a single one having MSI is enough to be sure that MSI are supported.
2436 pdev = pci_get_slot(dev->bus, 0);
2439 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2440 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2441 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2446 quirk_nvidia_ck804_msi_ht_cap);
2448 /* Force enable MSI mapping capability on HT bridges */
2449 static void ht_enable_msi_mapping(struct pci_dev *dev)
2451 int pos, ttl = PCI_FIND_CAP_TTL;
2453 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2454 while (pos && ttl--) {
2457 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2459 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2461 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2462 flags | HT_MSI_FLAGS_ENABLE);
2464 pos = pci_find_next_ht_capability(dev, pos,
2465 HT_CAPTYPE_MSI_MAPPING);
2468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2469 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2470 ht_enable_msi_mapping);
2472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2473 ht_enable_msi_mapping);
2475 /* The P5N32-SLI motherboards from Asus have a problem with msi
2476 * for the MCP55 NIC. It is not yet determined whether the msi problem
2477 * also affects other devices. As for now, turn off msi for this device.
2479 static void nvenet_msi_disable(struct pci_dev *dev)
2481 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2484 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2485 strstr(board_name, "P5N32-E SLI"))) {
2486 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2490 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2491 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2492 nvenet_msi_disable);
2495 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2496 * config register. This register controls the routing of legacy
2497 * interrupts from devices that route through the MCP55. If this register
2498 * is misprogrammed, interrupts are only sent to the BSP, unlike
2499 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2500 * having this register set properly prevents kdump from booting up
2501 * properly, so let's make sure that we have it set correctly.
2502 * Note that this is an undocumented register.
2504 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2508 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2511 pci_read_config_dword(dev, 0x74, &cfg);
2513 if (cfg & ((1 << 2) | (1 << 15))) {
2514 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2515 cfg &= ~((1 << 2) | (1 << 15));
2516 pci_write_config_dword(dev, 0x74, cfg);
2520 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2521 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2522 nvbridge_check_legacy_irq_routing);
2524 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2525 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2526 nvbridge_check_legacy_irq_routing);
2528 static int ht_check_msi_mapping(struct pci_dev *dev)
2530 int pos, ttl = PCI_FIND_CAP_TTL;
2533 /* check if there is HT MSI cap or enabled on this device */
2534 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2535 while (pos && ttl--) {
2540 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2542 if (flags & HT_MSI_FLAGS_ENABLE) {
2549 pos = pci_find_next_ht_capability(dev, pos,
2550 HT_CAPTYPE_MSI_MAPPING);
2556 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2558 struct pci_dev *dev;
2563 dev_no = host_bridge->devfn >> 3;
2564 for (i = dev_no + 1; i < 0x20; i++) {
2565 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2569 /* found next host bridge ?*/
2570 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2576 if (ht_check_msi_mapping(dev)) {
2587 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2588 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2590 static int is_end_of_ht_chain(struct pci_dev *dev)
2596 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2601 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2603 ctrl_off = ((flags >> 10) & 1) ?
2604 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2605 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2607 if (ctrl & (1 << 6))
2614 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2616 struct pci_dev *host_bridge;
2621 dev_no = dev->devfn >> 3;
2622 for (i = dev_no; i >= 0; i--) {
2623 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2627 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2632 pci_dev_put(host_bridge);
2638 /* don't enable end_device/host_bridge with leaf directly here */
2639 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2640 host_bridge_with_leaf(host_bridge))
2643 /* root did that ! */
2644 if (msi_ht_cap_enabled(host_bridge))
2647 ht_enable_msi_mapping(dev);
2650 pci_dev_put(host_bridge);
2653 static void ht_disable_msi_mapping(struct pci_dev *dev)
2655 int pos, ttl = PCI_FIND_CAP_TTL;
2657 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2658 while (pos && ttl--) {
2661 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2663 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2665 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2666 flags & ~HT_MSI_FLAGS_ENABLE);
2668 pos = pci_find_next_ht_capability(dev, pos,
2669 HT_CAPTYPE_MSI_MAPPING);
2673 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2675 struct pci_dev *host_bridge;
2679 if (!pci_msi_enabled())
2682 /* check if there is HT MSI cap or enabled on this device */
2683 found = ht_check_msi_mapping(dev);
2690 * HT MSI mapping should be disabled on devices that are below
2691 * a non-Hypertransport host bridge. Locate the host bridge...
2693 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2694 if (host_bridge == NULL) {
2695 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2699 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2701 /* Host bridge is to HT */
2703 /* it is not enabled, try to enable it */
2705 ht_enable_msi_mapping(dev);
2707 nv_ht_enable_msi_mapping(dev);
2712 /* HT MSI is not enabled */
2716 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2717 ht_disable_msi_mapping(dev);
2720 pci_dev_put(host_bridge);
2723 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2725 return __nv_msi_ht_cap_quirk(dev, 1);
2728 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2730 return __nv_msi_ht_cap_quirk(dev, 0);
2733 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2734 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2736 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2737 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2739 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2741 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2743 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2747 /* SB700 MSI issue will be fixed at HW level from revision A21,
2748 * we need check PCI REVISION ID of SMBus controller to get SB700
2751 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2756 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2757 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2760 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2762 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2763 if (dev->revision < 0x18) {
2764 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2765 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2769 PCI_DEVICE_ID_TIGON3_5780,
2770 quirk_msi_intx_disable_bug);
2771 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2772 PCI_DEVICE_ID_TIGON3_5780S,
2773 quirk_msi_intx_disable_bug);
2774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2775 PCI_DEVICE_ID_TIGON3_5714,
2776 quirk_msi_intx_disable_bug);
2777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2778 PCI_DEVICE_ID_TIGON3_5714S,
2779 quirk_msi_intx_disable_bug);
2780 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2781 PCI_DEVICE_ID_TIGON3_5715,
2782 quirk_msi_intx_disable_bug);
2783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2784 PCI_DEVICE_ID_TIGON3_5715S,
2785 quirk_msi_intx_disable_bug);
2787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2788 quirk_msi_intx_disable_ati_bug);
2789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2790 quirk_msi_intx_disable_ati_bug);
2791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2792 quirk_msi_intx_disable_ati_bug);
2793 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2794 quirk_msi_intx_disable_ati_bug);
2795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2796 quirk_msi_intx_disable_ati_bug);
2798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2799 quirk_msi_intx_disable_bug);
2800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2801 quirk_msi_intx_disable_bug);
2802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2803 quirk_msi_intx_disable_bug);
2805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2806 quirk_msi_intx_disable_bug);
2807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2808 quirk_msi_intx_disable_bug);
2809 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2810 quirk_msi_intx_disable_bug);
2811 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2812 quirk_msi_intx_disable_bug);
2813 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2814 quirk_msi_intx_disable_bug);
2815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2816 quirk_msi_intx_disable_bug);
2817 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2818 quirk_msi_intx_disable_qca_bug);
2819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2820 quirk_msi_intx_disable_qca_bug);
2821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2822 quirk_msi_intx_disable_qca_bug);
2823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2824 quirk_msi_intx_disable_qca_bug);
2825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2826 quirk_msi_intx_disable_qca_bug);
2827 #endif /* CONFIG_PCI_MSI */
2829 /* Allow manual resource allocation for PCI hotplug bridges
2830 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2831 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2832 * kernel fails to allocate resources when hotplug device is
2833 * inserted and PCI bus is rescanned.
2835 static void quirk_hotplug_bridge(struct pci_dev *dev)
2837 dev->is_hotplug_bridge = 1;
2840 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2843 * This is a quirk for the Ricoh MMC controller found as a part of
2844 * some mulifunction chips.
2846 * This is very similar and based on the ricoh_mmc driver written by
2847 * Philip Langdale. Thank you for these magic sequences.
2849 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2850 * and one or both of cardbus or firewire.
2852 * It happens that they implement SD and MMC
2853 * support as separate controllers (and PCI functions). The linux SDHCI
2854 * driver supports MMC cards but the chip detects MMC cards in hardware
2855 * and directs them to the MMC controller - so the SDHCI driver never sees
2858 * To get around this, we must disable the useless MMC controller.
2859 * At that point, the SDHCI controller will start seeing them
2860 * It seems to be the case that the relevant PCI registers to deactivate the
2861 * MMC controller live on PCI function 0, which might be the cardbus controller
2862 * or the firewire controller, depending on the particular chip in question
2864 * This has to be done early, because as soon as we disable the MMC controller
2865 * other pci functions shift up one level, e.g. function #2 becomes function
2866 * #1, and this will confuse the pci core.
2869 #ifdef CONFIG_MMC_RICOH_MMC
2870 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2872 /* disable via cardbus interface */
2877 /* disable must be done via function #0 */
2878 if (PCI_FUNC(dev->devfn))
2881 pci_read_config_byte(dev, 0xB7, &disable);
2885 pci_read_config_byte(dev, 0x8E, &write_enable);
2886 pci_write_config_byte(dev, 0x8E, 0xAA);
2887 pci_read_config_byte(dev, 0x8D, &write_target);
2888 pci_write_config_byte(dev, 0x8D, 0xB7);
2889 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2890 pci_write_config_byte(dev, 0x8E, write_enable);
2891 pci_write_config_byte(dev, 0x8D, write_target);
2893 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2894 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2896 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2897 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2899 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2901 /* disable via firewire interface */
2905 /* disable must be done via function #0 */
2906 if (PCI_FUNC(dev->devfn))
2909 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2910 * certain types of SD/MMC cards. Lowering the SD base
2911 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2913 * 0x150 - SD2.0 mode enable for changing base clock
2914 * frequency to 50Mhz
2915 * 0xe1 - Base clock frequency
2916 * 0x32 - 50Mhz new clock frequency
2917 * 0xf9 - Key register for 0x150
2918 * 0xfc - key register for 0xe1
2920 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2921 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2922 pci_write_config_byte(dev, 0xf9, 0xfc);
2923 pci_write_config_byte(dev, 0x150, 0x10);
2924 pci_write_config_byte(dev, 0xf9, 0x00);
2925 pci_write_config_byte(dev, 0xfc, 0x01);
2926 pci_write_config_byte(dev, 0xe1, 0x32);
2927 pci_write_config_byte(dev, 0xfc, 0x00);
2929 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2932 pci_read_config_byte(dev, 0xCB, &disable);
2937 pci_read_config_byte(dev, 0xCA, &write_enable);
2938 pci_write_config_byte(dev, 0xCA, 0x57);
2939 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2940 pci_write_config_byte(dev, 0xCA, write_enable);
2942 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2943 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2946 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2947 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2948 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2949 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2950 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2951 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2952 #endif /*CONFIG_MMC_RICOH_MMC*/
2954 #ifdef CONFIG_DMAR_TABLE
2955 #define VTUNCERRMSK_REG 0x1ac
2956 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2958 * This is a quirk for masking vt-d spec defined errors to platform error
2959 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2960 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2961 * on the RAS config settings of the platform) when a vt-d fault happens.
2962 * The resulting SMI caused the system to hang.
2964 * VT-d spec related errors are already handled by the VT-d OS code, so no
2965 * need to report the same error through other channels.
2967 static void vtd_mask_spec_errors(struct pci_dev *dev)
2971 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2972 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2974 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2975 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2978 static void fixup_ti816x_class(struct pci_dev *dev)
2980 u32 class = dev->class;
2982 /* TI 816x devices do not have class code set when in PCIe boot mode */
2983 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2984 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2987 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2988 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2990 /* Some PCIe devices do not work reliably with the claimed maximum
2991 * payload size supported.
2993 static void fixup_mpss_256(struct pci_dev *dev)
2995 dev->pcie_mpss = 1; /* 256 bytes */
2997 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
2998 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2999 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3000 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3001 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3002 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3003 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3005 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
3006 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3007 * Since there is no way of knowing what the PCIE MPS on each fabric will be
3008 * until all of the devices are discovered and buses walked, read completion
3009 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3010 * it is possible to hotplug a device with MPS of 256B.
3012 static void quirk_intel_mc_errata(struct pci_dev *dev)
3017 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3018 pcie_bus_config == PCIE_BUS_DEFAULT)
3021 /* Intel errata specifies bits to change but does not say what they are.
3022 * Keeping them magical until such time as the registers and values can
3025 err = pci_read_config_word(dev, 0x48, &rcc);
3027 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
3031 if (!(rcc & (1 << 10)))
3036 err = pci_write_config_word(dev, 0x48, rcc);
3038 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
3042 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3044 /* Intel 5000 series memory controllers and ports 2-7 */
3045 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3047 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3059 /* Intel 5100 series memory controllers and ports 2-7 */
3060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3074 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3075 * work around this, query the size it should be configured to by the device and
3076 * modify the resource end to correspond to this new size.
3078 static void quirk_intel_ntb(struct pci_dev *dev)
3083 rc = pci_read_config_byte(dev, 0x00D0, &val);
3087 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3089 rc = pci_read_config_byte(dev, 0x00D1, &val);
3093 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3098 static ktime_t fixup_debug_start(struct pci_dev *dev,
3099 void (*fn)(struct pci_dev *dev))
3101 ktime_t calltime = ktime_set(0, 0);
3103 dev_dbg(&dev->dev, "calling %pF\n", fn);
3104 if (initcall_debug) {
3105 pr_debug("calling %pF @ %i for %s\n",
3106 fn, task_pid_nr(current), dev_name(&dev->dev));
3107 calltime = ktime_get();
3113 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3114 void (*fn)(struct pci_dev *dev))
3116 ktime_t delta, rettime;
3117 unsigned long long duration;
3119 if (initcall_debug) {
3120 rettime = ktime_get();
3121 delta = ktime_sub(rettime, calltime);
3122 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3123 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3124 fn, duration, dev_name(&dev->dev));
3129 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3130 * even though no one is handling them (f.e. i915 driver is never loaded).
3131 * Additionally the interrupt destination is not set up properly
3132 * and the interrupt ends up -somewhere-.
3134 * These spurious interrupts are "sticky" and the kernel disables
3135 * the (shared) interrupt line after 100.000+ generated interrupts.
3137 * Fix it by disabling the still enabled interrupts.
3138 * This resolves crashes often seen on monitor unplug.
3140 #define I915_DEIER_REG 0x4400c
3141 static void disable_igfx_irq(struct pci_dev *dev)
3143 void __iomem *regs = pci_iomap(dev, 0, 0);
3145 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3149 /* Check if any interrupt line is still enabled */
3150 if (readl(regs + I915_DEIER_REG) != 0) {
3151 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3153 writel(0, regs + I915_DEIER_REG);
3156 pci_iounmap(dev, regs);
3158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3167 * PCI devices which are on Intel chips can skip the 10ms delay
3168 * before entering D3 mode.
3170 static void quirk_remove_d3_delay(struct pci_dev *dev)
3174 /* C600 Series devices do not need 10ms d3_delay */
3175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3178 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3190 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3202 * Some devices may pass our check in pci_intx_mask_supported() if
3203 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3204 * support this feature.
3206 static void quirk_broken_intx_masking(struct pci_dev *dev)
3208 dev->broken_intx_masking = 1;
3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3211 quirk_broken_intx_masking);
3212 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3213 quirk_broken_intx_masking);
3216 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3217 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3219 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3222 quirk_broken_intx_masking);
3225 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3226 * DisINTx can be set but the interrupt status bit is non-functional.
3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3229 quirk_broken_intx_masking);
3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3231 quirk_broken_intx_masking);
3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3233 quirk_broken_intx_masking);
3234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3235 quirk_broken_intx_masking);
3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3237 quirk_broken_intx_masking);
3238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3239 quirk_broken_intx_masking);
3240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3241 quirk_broken_intx_masking);
3242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3243 quirk_broken_intx_masking);
3244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3245 quirk_broken_intx_masking);
3246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3247 quirk_broken_intx_masking);
3248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3249 quirk_broken_intx_masking);
3250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3251 quirk_broken_intx_masking);
3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3253 quirk_broken_intx_masking);
3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3255 quirk_broken_intx_masking);
3257 static u16 mellanox_broken_intx_devs[] = {
3258 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3259 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3260 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3261 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3262 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3263 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3264 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3265 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3266 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3267 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3268 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3269 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3270 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3271 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3274 #define CONNECTX_4_CURR_MAX_MINOR 99
3275 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3278 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3279 * If so, don't mark it as broken.
3280 * FW minor > 99 means older FW version format and no INTx masking support.
3281 * FW minor < 14 means new FW version format and no INTx masking support.
3283 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3285 __be32 __iomem *fw_ver;
3293 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3294 if (pdev->device == mellanox_broken_intx_devs[i]) {
3295 pdev->broken_intx_masking = 1;
3300 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3301 * support so shouldn't be checked further
3303 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3306 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3307 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3310 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3311 if (pci_enable_device_mem(pdev)) {
3312 dev_warn(&pdev->dev, "Can't enable device memory\n");
3316 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3318 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3322 /* Reading from resource space should be 32b aligned */
3323 fw_maj_min = ioread32be(fw_ver);
3324 fw_sub_min = ioread32be(fw_ver + 1);
3325 fw_major = fw_maj_min & 0xffff;
3326 fw_minor = fw_maj_min >> 16;
3327 fw_subminor = fw_sub_min & 0xffff;
3328 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3329 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3330 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3331 fw_major, fw_minor, fw_subminor, pdev->device ==
3332 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3333 pdev->broken_intx_masking = 1;
3339 pci_disable_device(pdev);
3341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3342 mellanox_check_broken_intx_masking);
3344 static void quirk_no_bus_reset(struct pci_dev *dev)
3346 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3350 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3351 * prevented for those affected devices.
3353 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3355 if ((dev->device & 0xffc0) == 0x2340)
3356 quirk_no_bus_reset(dev);
3358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3359 quirk_nvidia_no_bus_reset);
3362 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3363 * The device will throw a Link Down error on AER-capable systems and
3364 * regardless of AER, config space of the device is never accessible again
3365 * and typically causes the system to hang or reset when access is attempted.
3366 * http://www.spinics.net/lists/linux-pci/msg34797.html
3368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3376 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3377 * automatically disables LTSSM when Secondary Bus Reset is received and
3378 * the device stops working. Prevent bus reset for these devices. With
3379 * this change, the device can be assigned to VMs with VFIO, but it will
3380 * leak state between VMs. Reference
3381 * https://e2e.ti.com/support/processors/f/791/t/954382
3383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3385 static void quirk_no_pm_reset(struct pci_dev *dev)
3388 * We can't do a bus reset on root bus devices, but an ineffective
3389 * PM reset may be better than nothing.
3391 if (!pci_is_root_bus(dev->bus))
3392 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3396 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3397 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3398 * to have no effect on the device: it retains the framebuffer contents and
3399 * monitor sync. Advertising this support makes other layers, like VFIO,
3400 * assume pci_reset_function() is viable for this device. Mark it as
3401 * unavailable to skip it when testing reset methods.
3403 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3404 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3407 * Thunderbolt controllers with broken MSI hotplug signaling:
3408 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3409 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3411 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3413 if (pdev->is_hotplug_bridge &&
3414 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3415 pdev->revision <= 1))
3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3419 quirk_thunderbolt_hotplug_msi);
3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3421 quirk_thunderbolt_hotplug_msi);
3422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3423 quirk_thunderbolt_hotplug_msi);
3424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3425 quirk_thunderbolt_hotplug_msi);
3426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3427 quirk_thunderbolt_hotplug_msi);
3429 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3431 int chip = (dev->device & 0xf000) >> 12;
3432 int func = (dev->device & 0x0f00) >> 8;
3433 int prod = (dev->device & 0x00ff) >> 0;
3436 * If this is a T3-based adapter, there's a 1KB VPD area at offset
3437 * 0xc00 which contains the preferred VPD values. If this is a T4 or
3438 * later based adapter, the special VPD is at offset 0x400 for the
3439 * Physical Functions (the SR-IOV Virtual Functions have no VPD
3440 * Capabilities). The PCI VPD Access core routines will normally
3441 * compute the size of the VPD by parsing the VPD Data Structure at
3442 * offset 0x000. This will result in silent failures when attempting
3443 * to accesses these other VPD areas which are beyond those computed
3446 if (chip == 0x0 && prod >= 0x20)
3447 pci_set_vpd_size(dev, 8192);
3448 else if (chip >= 0x4 && func < 0x8)
3449 pci_set_vpd_size(dev, 2048);
3452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3453 quirk_chelsio_extend_vpd);
3457 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3459 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3460 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3461 * be present after resume if a device was plugged in before suspend.
3463 * The thunderbolt controller consists of a pcie switch with downstream
3464 * bridges leading to the NHI and to the tunnel pci bridges.
3466 * This quirk cuts power to the whole chip. Therefore we have to apply it
3467 * during suspend_noirq of the upstream bridge.
3469 * Power is automagically restored before resume. No action is needed.
3471 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3473 acpi_handle bridge, SXIO, SXFP, SXLV;
3475 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3477 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3479 bridge = ACPI_HANDLE(&dev->dev);
3483 * SXIO and SXLV are present only on machines requiring this quirk.
3484 * TB bridges in external devices might have the same device id as those
3485 * on the host, but they will not have the associated ACPI methods. This
3486 * implicitly checks that we are at the right bridge.
3488 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3489 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3490 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3492 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3494 /* magic sequence */
3495 acpi_execute_simple_method(SXIO, NULL, 1);
3496 acpi_execute_simple_method(SXFP, NULL, 0);
3498 acpi_execute_simple_method(SXLV, NULL, 0);
3499 acpi_execute_simple_method(SXIO, NULL, 0);
3500 acpi_execute_simple_method(SXLV, NULL, 0);
3502 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3503 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3504 quirk_apple_poweroff_thunderbolt);
3507 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3509 * During suspend the thunderbolt controller is reset and all pci
3510 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3511 * during resume. We have to manually wait for the NHI since there is
3512 * no parent child relationship between the NHI and the tunneled
3515 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3517 struct pci_dev *sibling = NULL;
3518 struct pci_dev *nhi = NULL;
3520 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3522 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3525 * Find the NHI and confirm that we are a bridge on the tb host
3526 * controller and not on a tb endpoint.
3528 sibling = pci_get_slot(dev->bus, 0x0);
3530 goto out; /* we are the downstream bridge to the NHI */
3531 if (!sibling || !sibling->subordinate)
3533 nhi = pci_get_slot(sibling->subordinate, 0x0);
3536 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3537 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3538 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3539 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3540 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3541 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3543 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3544 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3547 pci_dev_put(sibling);
3549 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3550 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3551 quirk_apple_wait_for_thunderbolt);
3552 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3553 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3554 quirk_apple_wait_for_thunderbolt);
3555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3556 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3557 quirk_apple_wait_for_thunderbolt);
3558 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3559 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3560 quirk_apple_wait_for_thunderbolt);
3563 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3564 struct pci_fixup *end)
3568 for (; f < end; f++)
3569 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3570 f->class == (u32) PCI_ANY_ID) &&
3571 (f->vendor == dev->vendor ||
3572 f->vendor == (u16) PCI_ANY_ID) &&
3573 (f->device == dev->device ||
3574 f->device == (u16) PCI_ANY_ID)) {
3575 calltime = fixup_debug_start(dev, f->hook);
3577 fixup_debug_report(dev, calltime, f->hook);
3581 extern struct pci_fixup __start_pci_fixups_early[];
3582 extern struct pci_fixup __end_pci_fixups_early[];
3583 extern struct pci_fixup __start_pci_fixups_header[];
3584 extern struct pci_fixup __end_pci_fixups_header[];
3585 extern struct pci_fixup __start_pci_fixups_final[];
3586 extern struct pci_fixup __end_pci_fixups_final[];
3587 extern struct pci_fixup __start_pci_fixups_enable[];
3588 extern struct pci_fixup __end_pci_fixups_enable[];
3589 extern struct pci_fixup __start_pci_fixups_resume[];
3590 extern struct pci_fixup __end_pci_fixups_resume[];
3591 extern struct pci_fixup __start_pci_fixups_resume_early[];
3592 extern struct pci_fixup __end_pci_fixups_resume_early[];
3593 extern struct pci_fixup __start_pci_fixups_suspend[];
3594 extern struct pci_fixup __end_pci_fixups_suspend[];
3595 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3596 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3598 static bool pci_apply_fixup_final_quirks;
3600 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3602 struct pci_fixup *start, *end;
3605 case pci_fixup_early:
3606 start = __start_pci_fixups_early;
3607 end = __end_pci_fixups_early;
3610 case pci_fixup_header:
3611 start = __start_pci_fixups_header;
3612 end = __end_pci_fixups_header;
3615 case pci_fixup_final:
3616 if (!pci_apply_fixup_final_quirks)
3618 start = __start_pci_fixups_final;
3619 end = __end_pci_fixups_final;
3622 case pci_fixup_enable:
3623 start = __start_pci_fixups_enable;
3624 end = __end_pci_fixups_enable;
3627 case pci_fixup_resume:
3628 start = __start_pci_fixups_resume;
3629 end = __end_pci_fixups_resume;
3632 case pci_fixup_resume_early:
3633 start = __start_pci_fixups_resume_early;
3634 end = __end_pci_fixups_resume_early;
3637 case pci_fixup_suspend:
3638 start = __start_pci_fixups_suspend;
3639 end = __end_pci_fixups_suspend;
3642 case pci_fixup_suspend_late:
3643 start = __start_pci_fixups_suspend_late;
3644 end = __end_pci_fixups_suspend_late;
3648 /* stupid compiler warning, you would think with an enum... */
3651 pci_do_fixups(dev, start, end);
3653 EXPORT_SYMBOL(pci_fixup_device);
3656 static int __init pci_apply_final_quirks(void)
3658 struct pci_dev *dev = NULL;
3662 if (pci_cache_line_size)
3663 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3664 pci_cache_line_size << 2);
3666 pci_apply_fixup_final_quirks = true;
3667 for_each_pci_dev(dev) {
3668 pci_fixup_device(pci_fixup_final, dev);
3670 * If arch hasn't set it explicitly yet, use the CLS
3671 * value shared by all PCI devices. If there's a
3672 * mismatch, fall back to the default value.
3674 if (!pci_cache_line_size) {
3675 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3678 if (!tmp || cls == tmp)
3681 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3683 pci_dfl_cache_line_size << 2);
3684 pci_cache_line_size = pci_dfl_cache_line_size;
3688 if (!pci_cache_line_size) {
3689 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3690 cls << 2, pci_dfl_cache_line_size << 2);
3691 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3697 fs_initcall_sync(pci_apply_final_quirks);
3700 * Followings are device-specific reset methods which can be used to
3701 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3704 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3707 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3709 * The 82599 supports FLR on VFs, but FLR support is reported only
3710 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3711 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3717 if (!pci_wait_for_pending_transaction(dev))
3718 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3720 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3727 #define SOUTH_CHICKEN2 0xc2004
3728 #define PCH_PP_STATUS 0xc7200
3729 #define PCH_PP_CONTROL 0xc7204
3730 #define MSG_CTL 0x45010
3731 #define NSDE_PWR_STATE 0xd0100
3732 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3734 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3736 void __iomem *mmio_base;
3737 unsigned long timeout;
3743 mmio_base = pci_iomap(dev, 0, 0);
3747 iowrite32(0x00000002, mmio_base + MSG_CTL);
3750 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3751 * driver loaded sets the right bits. However, this's a reset and
3752 * the bits have been set by i915 previously, so we clobber
3753 * SOUTH_CHICKEN2 register directly here.
3755 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3757 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3758 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3760 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3762 val = ioread32(mmio_base + PCH_PP_STATUS);
3763 if ((val & 0xb0000000) == 0)
3764 goto reset_complete;
3766 } while (time_before(jiffies, timeout));
3767 dev_warn(&dev->dev, "timeout during reset\n");
3770 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3772 pci_iounmap(dev, mmio_base);
3777 * Device-specific reset method for Chelsio T4-based adapters.
3779 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3785 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3786 * that we have no device-specific reset method.
3788 if ((dev->device & 0xf000) != 0x4000)
3792 * If this is the "probe" phase, return 0 indicating that we can
3793 * reset this device.
3799 * T4 can wedge if there are DMAs in flight within the chip and Bus
3800 * Master has been disabled. We need to have it on till the Function
3801 * Level Reset completes. (BUS_MASTER is disabled in
3802 * pci_reset_function()).
3804 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3805 pci_write_config_word(dev, PCI_COMMAND,
3806 old_command | PCI_COMMAND_MASTER);
3809 * Perform the actual device function reset, saving and restoring
3810 * configuration information around the reset.
3812 pci_save_state(dev);
3815 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3816 * are disabled when an MSI-X interrupt message needs to be delivered.
3817 * So we briefly re-enable MSI-X interrupts for the duration of the
3818 * FLR. The pci_restore_state() below will restore the original
3821 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3822 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3823 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3825 PCI_MSIX_FLAGS_ENABLE |
3826 PCI_MSIX_FLAGS_MASKALL);
3829 * Start of pcie_flr() code sequence. This reset code is a copy of
3830 * the guts of pcie_flr() because that's not an exported function.
3833 if (!pci_wait_for_pending_transaction(dev))
3834 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3836 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3840 * End of pcie_flr() code sequence.
3844 * Restore the configuration information (BAR values, etc.) including
3845 * the original PCI Configuration Space Command word, and return
3848 pci_restore_state(dev);
3849 pci_write_config_word(dev, PCI_COMMAND, old_command);
3853 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3854 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3855 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3857 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3858 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3859 reset_intel_82599_sfp_virtfn },
3860 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3862 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3864 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3865 reset_chelsio_generic_dev },
3870 * These device-specific reset methods are here rather than in a driver
3871 * because when a host assigns a device to a guest VM, the host may need
3872 * to reset the device but probably doesn't have a driver for it.
3874 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3876 const struct pci_dev_reset_methods *i;
3878 for (i = pci_dev_reset_methods; i->reset; i++) {
3879 if ((i->vendor == dev->vendor ||
3880 i->vendor == (u16)PCI_ANY_ID) &&
3881 (i->device == dev->device ||
3882 i->device == (u16)PCI_ANY_ID))
3883 return i->reset(dev, probe);
3889 static void quirk_dma_func0_alias(struct pci_dev *dev)
3891 if (PCI_FUNC(dev->devfn) != 0)
3892 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3896 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3898 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3903 static void quirk_dma_func1_alias(struct pci_dev *dev)
3905 if (PCI_FUNC(dev->devfn) != 1)
3906 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3910 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3911 * SKUs function 1 is present and is a legacy IDE controller, in other
3912 * SKUs this function is not present, making this a ghost requester.
3913 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3916 quirk_dma_func1_alias);
3917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3918 quirk_dma_func1_alias);
3919 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
3920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
3921 quirk_dma_func1_alias);
3922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3923 quirk_dma_func1_alias);
3924 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3926 quirk_dma_func1_alias);
3927 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
3928 quirk_dma_func1_alias);
3929 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3931 quirk_dma_func1_alias);
3932 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3934 quirk_dma_func1_alias);
3935 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3937 quirk_dma_func1_alias);
3938 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3940 quirk_dma_func1_alias);
3941 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
3942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
3943 quirk_dma_func1_alias);
3944 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3945 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3946 quirk_dma_func1_alias);
3947 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3949 quirk_dma_func1_alias);
3950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3951 quirk_dma_func1_alias);
3952 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3953 quirk_dma_func1_alias);
3954 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3955 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3956 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3957 quirk_dma_func1_alias);
3958 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3959 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3960 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3961 quirk_dma_func1_alias);
3964 * Some devices DMA with the wrong devfn, not just the wrong function.
3965 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3966 * the alias is "fixed" and independent of the device devfn.
3968 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3969 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3970 * single device on the secondary bus. In reality, the single exposed
3971 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3972 * that provides a bridge to the internal bus of the I/O processor. The
3973 * controller supports private devices, which can be hidden from PCI config
3974 * space. In the case of the Adaptec 3405, a private device at 01.0
3975 * appears to be the DMA engine, which therefore needs to become a DMA
3976 * alias for the device.
3978 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3979 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3980 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3981 .driver_data = PCI_DEVFN(1, 0) },
3982 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3983 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3984 .driver_data = PCI_DEVFN(1, 0) },
3988 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3990 const struct pci_device_id *id;
3992 id = pci_match_id(fixed_dma_alias_tbl, dev);
3994 pci_add_dma_alias(dev, id->driver_data);
3997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4000 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4001 * using the wrong DMA alias for the device. Some of these devices can be
4002 * used as either forward or reverse bridges, so we need to test whether the
4003 * device is operating in the correct mode. We could probably apply this
4004 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4005 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4006 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4008 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4010 if (!pci_is_root_bus(pdev->bus) &&
4011 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4012 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4013 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4014 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4016 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4018 quirk_use_pcie_bridge_dma_alias);
4019 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4020 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4021 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4022 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4023 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4024 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4027 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4028 * be added as aliases to the DMA device in order to allow buffer access
4029 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4030 * programmed in the EEPROM.
4032 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4034 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
4035 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
4036 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
4038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4042 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4043 * class code. Fix it.
4045 static void quirk_tw686x_class(struct pci_dev *pdev)
4047 u32 class = pdev->class;
4049 /* Use "Multimedia controller" class */
4050 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4051 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4052 class, pdev->class);
4054 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4055 quirk_tw686x_class);
4056 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4057 quirk_tw686x_class);
4058 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4059 quirk_tw686x_class);
4060 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4061 quirk_tw686x_class);
4064 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4065 * values for the Attribute as were supplied in the header of the
4066 * corresponding Request, except as explicitly allowed when IDO is used."
4068 * If a non-compliant device generates a completion with a different
4069 * attribute than the request, the receiver may accept it (which itself
4070 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4071 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4072 * device access timeout.
4074 * If the non-compliant device generates completions with zero attributes
4075 * (instead of copying the attributes from the request), we can work around
4076 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4077 * upstream devices so they always generate requests with zero attributes.
4079 * This affects other devices under the same Root Port, but since these
4080 * attributes are performance hints, there should be no functional problem.
4082 * Note that Configuration Space accesses are never supposed to have TLP
4083 * Attributes, so we're safe waiting till after any Configuration Space
4084 * accesses to do the Root Port fixup.
4086 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4088 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4091 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4095 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4096 dev_name(&pdev->dev));
4097 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4098 PCI_EXP_DEVCTL_RELAX_EN |
4099 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4103 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4104 * Completion it generates.
4106 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4109 * This mask/compare operation selects for Physical Function 4 on a
4110 * T5. We only need to fix up the Root Port once for any of the
4111 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4112 * 0x54xx so we use that one,
4114 if ((pdev->device & 0xff00) == 0x5400)
4115 quirk_disable_root_port_attributes(pdev);
4117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4118 quirk_chelsio_T5_disable_root_port_attributes);
4121 * AMD has indicated that the devices below do not support peer-to-peer
4122 * in any system where they are found in the southbridge with an AMD
4123 * IOMMU in the system. Multifunction devices that do not support
4124 * peer-to-peer between functions can claim to support a subset of ACS.
4125 * Such devices effectively enable request redirect (RR) and completion
4126 * redirect (CR) since all transactions are redirected to the upstream
4129 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4130 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4131 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4133 * 1002:4385 SBx00 SMBus Controller
4134 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4135 * 1002:4383 SBx00 Azalia (Intel HDA)
4136 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4137 * 1002:4384 SBx00 PCI to PCI Bridge
4138 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4140 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4142 * 1022:780f [AMD] FCH PCI Bridge
4143 * 1022:7809 [AMD] FCH USB OHCI Controller
4145 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4148 struct acpi_table_header *header = NULL;
4151 /* Targeting multifunction devices on the SB (appears on root bus) */
4152 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4155 /* The IVRS table describes the AMD IOMMU */
4156 status = acpi_get_table("IVRS", 0, &header);
4157 if (ACPI_FAILURE(status))
4160 /* Filter out flags not applicable to multifunction */
4161 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4163 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4169 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4172 * Cavium root ports don't advertise an ACS capability. However,
4173 * the RTL internally implements similar protection as if ACS had
4174 * Request Redirection, Completion Redirection, Source Validation,
4175 * and Upstream Forwarding features enabled. Assert that the
4176 * hardware implements and enables equivalent ACS functionality for
4179 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
4181 if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))
4184 return acs_flags ? 0 : 1;
4188 * Many Intel PCH root ports do provide ACS-like features to disable peer
4189 * transactions and validate bus numbers in requests, but do not provide an
4190 * actual PCIe ACS capability. This is the list of device IDs known to fall
4191 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4193 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4195 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4196 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4197 /* Cougarpoint PCH */
4198 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4199 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4200 /* Pantherpoint PCH */
4201 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4202 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4203 /* Lynxpoint-H PCH */
4204 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4205 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4206 /* Lynxpoint-LP PCH */
4207 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4208 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4210 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4211 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4212 /* Patsburg (X79) PCH */
4213 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4214 /* Wellsburg (X99) PCH */
4215 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4216 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4217 /* Lynx Point (9 series) PCH */
4218 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4221 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4225 /* Filter out a few obvious non-matches first */
4226 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4229 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4230 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4236 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4238 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4240 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4241 INTEL_PCH_ACS_FLAGS : 0;
4243 if (!pci_quirk_intel_pch_acs_match(dev))
4246 return acs_flags & ~flags ? 0 : 1;
4250 * These QCOM root ports do provide ACS-like features to disable peer
4251 * transactions and validate bus numbers in requests, but do not provide an
4252 * actual PCIe ACS capability. Hardware supports source validation but it
4253 * will report the issue as Completer Abort instead of ACS Violation.
4254 * Hardware doesn't support peer-to-peer and each root port is a root
4255 * complex with unique segment numbers. It is not possible for one root
4256 * port to pass traffic to another root port. All PCIe transactions are
4257 * terminated inside the root port.
4259 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4261 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4262 int ret = acs_flags & ~flags ? 0 : 1;
4264 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4270 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4271 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4272 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4273 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4274 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4275 * control register is at offset 8 instead of 6 and we should probably use
4276 * dword accesses to them. This applies to the following PCI Device IDs, as
4277 * found in volume 1 of the datasheet[2]:
4279 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4280 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4282 * N.B. This doesn't fix what lspci shows.
4284 * The 100 series chipset specification update includes this as errata #23[3].
4286 * The 200 series chipset (Union Point) has the same bug according to the
4287 * specification update (Intel 200 Series Chipset Family Platform Controller
4288 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4289 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4292 * 0xa290-0xa29f PCI Express Root port #{0-16}
4293 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4295 * Mobile chipsets are also affected, 7th & 8th Generation
4296 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4297 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4298 * Processor Family I/O for U Quad Core Platforms Specification Update,
4299 * August 2017, Revision 002, Document#: 334660-002)[6]
4300 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4301 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4302 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4304 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4306 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4307 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4308 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4309 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4310 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4311 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4312 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4314 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4316 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4319 switch (dev->device) {
4320 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4321 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4322 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4329 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4331 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4336 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4339 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4343 /* see pci_acs_flags_enabled() */
4344 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4345 acs_flags &= (cap | PCI_ACS_EC);
4347 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4349 return acs_flags & ~ctrl ? 0 : 1;
4352 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4355 * SV, TB, and UF are not relevant to multifunction endpoints.
4357 * Multifunction devices are only required to implement RR, CR, and DT
4358 * in their ACS capability if they support peer-to-peer transactions.
4359 * Devices matching this quirk have been verified by the vendor to not
4360 * perform peer-to-peer with other functions, allowing us to mask out
4361 * these bits as if they were unimplemented in the ACS capability.
4363 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4364 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4366 return acs_flags ? 0 : 1;
4369 static const struct pci_dev_acs_enabled {
4372 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4373 } pci_dev_acs_enabled[] = {
4374 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4375 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4376 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4377 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4378 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4379 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4380 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4381 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4382 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4383 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4384 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4385 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4386 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4387 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4388 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4389 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4390 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4391 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4392 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4393 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4394 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4395 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4396 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4397 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4398 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4399 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4400 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4401 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4402 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4403 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4404 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4406 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4407 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4408 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4409 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4410 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4411 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4412 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4414 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4415 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4416 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4417 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4418 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4419 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4420 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4421 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4423 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4424 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4425 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4427 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4428 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4429 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4430 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4431 /* 82571 (Quads omitted due to non-ACS switch) */
4432 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4433 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4434 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4435 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4437 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4438 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4439 /* QCOM QDF2xxx root ports */
4440 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4441 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4442 /* Intel PCH root ports */
4443 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4444 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4445 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4446 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4447 /* Cavium ThunderX */
4448 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4452 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4454 const struct pci_dev_acs_enabled *i;
4458 * Allow devices that do not expose standard PCIe ACS capabilities
4459 * or control to indicate their support here. Multi-function express
4460 * devices which do not allow internal peer-to-peer between functions,
4461 * but do not implement PCIe ACS may wish to return true here.
4463 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4464 if ((i->vendor == dev->vendor ||
4465 i->vendor == (u16)PCI_ANY_ID) &&
4466 (i->device == dev->device ||
4467 i->device == (u16)PCI_ANY_ID)) {
4468 ret = i->acs_enabled(dev, acs_flags);
4477 /* Config space offset of Root Complex Base Address register */
4478 #define INTEL_LPC_RCBA_REG 0xf0
4479 /* 31:14 RCBA address */
4480 #define INTEL_LPC_RCBA_MASK 0xffffc000
4482 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4484 /* Backbone Scratch Pad Register */
4485 #define INTEL_BSPR_REG 0x1104
4486 /* Backbone Peer Non-Posted Disable */
4487 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4488 /* Backbone Peer Posted Disable */
4489 #define INTEL_BSPR_REG_BPPD (1 << 9)
4491 /* Upstream Peer Decode Configuration Register */
4492 #define INTEL_UPDCR_REG 0x1014
4493 /* 5:0 Peer Decode Enable bits */
4494 #define INTEL_UPDCR_REG_MASK 0x3f
4496 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4498 u32 rcba, bspr, updcr;
4499 void __iomem *rcba_mem;
4502 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4503 * are D28:F* and therefore get probed before LPC, thus we can't
4504 * use pci_get_slot/pci_read_config_dword here.
4506 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4507 INTEL_LPC_RCBA_REG, &rcba);
4508 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4511 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4512 PAGE_ALIGN(INTEL_UPDCR_REG));
4517 * The BSPR can disallow peer cycles, but it's set by soft strap and
4518 * therefore read-only. If both posted and non-posted peer cycles are
4519 * disallowed, we're ok. If either are allowed, then we need to use
4520 * the UPDCR to disable peer decodes for each port. This provides the
4521 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4523 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4524 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4525 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4526 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4527 if (updcr & INTEL_UPDCR_REG_MASK) {
4528 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4529 updcr &= ~INTEL_UPDCR_REG_MASK;
4530 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4538 /* Miscellaneous Port Configuration register */
4539 #define INTEL_MPC_REG 0xd8
4540 /* MPC: Invalid Receive Bus Number Check Enable */
4541 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4543 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4548 * When enabled, the IRBNCE bit of the MPC register enables the
4549 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4550 * ensures that requester IDs fall within the bus number range
4551 * of the bridge. Enable if not already.
4553 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4554 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4555 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4556 mpc |= INTEL_MPC_REG_IRBNCE;
4557 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4561 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4563 if (!pci_quirk_intel_pch_acs_match(dev))
4566 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4567 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4571 pci_quirk_enable_intel_rp_mpc_acs(dev);
4573 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4575 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4580 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4585 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4588 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4592 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4593 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4595 ctrl |= (cap & PCI_ACS_SV);
4596 ctrl |= (cap & PCI_ACS_RR);
4597 ctrl |= (cap & PCI_ACS_CR);
4598 ctrl |= (cap & PCI_ACS_UF);
4600 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4602 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4607 static const struct pci_dev_enable_acs {
4610 int (*enable_acs)(struct pci_dev *dev);
4611 } pci_dev_enable_acs[] = {
4612 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4613 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4617 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4619 const struct pci_dev_enable_acs *i;
4622 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4623 if ((i->vendor == dev->vendor ||
4624 i->vendor == (u16)PCI_ANY_ID) &&
4625 (i->device == dev->device ||
4626 i->device == (u16)PCI_ANY_ID)) {
4627 ret = i->enable_acs(dev);
4637 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4638 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4639 * Next Capability pointer in the MSI Capability Structure should point to
4640 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4643 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4648 struct pci_cap_saved_state *state;
4650 /* Bail if the hardware bug is fixed */
4651 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4654 /* Bail if MSI Capability Structure is not found for some reason */
4655 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4660 * Bail if Next Capability pointer in the MSI Capability Structure
4661 * is not the expected incorrect 0x00.
4663 pci_read_config_byte(pdev, pos + 1, &next_cap);
4668 * PCIe Capability Structure is expected to be at 0x50 and should
4669 * terminate the list (Next Capability pointer is 0x00). Verify
4670 * Capability Id and Next Capability pointer is as expected.
4671 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4672 * to correctly set kernel data structures which have already been
4673 * set incorrectly due to the hardware bug.
4676 pci_read_config_word(pdev, pos, ®16);
4677 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4679 #ifndef PCI_EXP_SAVE_REGS
4680 #define PCI_EXP_SAVE_REGS 7
4682 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4684 pdev->pcie_cap = pos;
4685 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
4686 pdev->pcie_flags_reg = reg16;
4687 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
4688 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4690 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4691 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4692 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4693 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4695 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4701 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4705 state->cap.cap_nr = PCI_CAP_ID_EXP;
4706 state->cap.cap_extended = 0;
4707 state->cap.size = size;
4708 cap = (u16 *)&state->cap.data[0];
4709 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4710 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4711 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4712 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4713 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4714 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4715 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4716 hlist_add_head(&state->next, &pdev->saved_cap_space);
4719 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4722 * VMD-enabled root ports will change the source ID for all messages
4723 * to the VMD device. Rather than doing device matching with the source
4724 * ID, the AER driver should traverse the child device tree, reading
4725 * AER registers to find the faulting device.
4727 static void quirk_no_aersid(struct pci_dev *pdev)
4730 if (pdev->bus->sysdata && pci_domain_nr(pdev->bus) >= 0x10000)
4731 pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
4733 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
4734 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
4735 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
4736 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);