1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
15 #include <linux/bitfield.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/acpi.h>
23 #include <linux/dmi.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
28 #include <linux/nvme.h>
29 #include <linux/platform_data/x86/apple.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/suspend.h>
32 #include <linux/switchtec.h>
33 #include <asm/dma.h> /* isa_dma_bridge_buggy */
36 static ktime_t fixup_debug_start(struct pci_dev *dev,
37 void (*fn)(struct pci_dev *dev))
40 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
45 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
46 void (*fn)(struct pci_dev *dev))
48 ktime_t delta, rettime;
49 unsigned long long duration;
51 rettime = ktime_get();
52 delta = ktime_sub(rettime, calltime);
53 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
54 if (initcall_debug || duration > 10000)
55 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
58 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
59 struct pci_fixup *end)
64 if ((f->class == (u32) (dev->class >> f->class_shift) ||
65 f->class == (u32) PCI_ANY_ID) &&
66 (f->vendor == dev->vendor ||
67 f->vendor == (u16) PCI_ANY_ID) &&
68 (f->device == dev->device ||
69 f->device == (u16) PCI_ANY_ID)) {
70 void (*hook)(struct pci_dev *dev);
71 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
72 hook = offset_to_ptr(&f->hook_offset);
76 calltime = fixup_debug_start(dev, hook);
78 fixup_debug_report(dev, calltime, hook);
82 extern struct pci_fixup __start_pci_fixups_early[];
83 extern struct pci_fixup __end_pci_fixups_early[];
84 extern struct pci_fixup __start_pci_fixups_header[];
85 extern struct pci_fixup __end_pci_fixups_header[];
86 extern struct pci_fixup __start_pci_fixups_final[];
87 extern struct pci_fixup __end_pci_fixups_final[];
88 extern struct pci_fixup __start_pci_fixups_enable[];
89 extern struct pci_fixup __end_pci_fixups_enable[];
90 extern struct pci_fixup __start_pci_fixups_resume[];
91 extern struct pci_fixup __end_pci_fixups_resume[];
92 extern struct pci_fixup __start_pci_fixups_resume_early[];
93 extern struct pci_fixup __end_pci_fixups_resume_early[];
94 extern struct pci_fixup __start_pci_fixups_suspend[];
95 extern struct pci_fixup __end_pci_fixups_suspend[];
96 extern struct pci_fixup __start_pci_fixups_suspend_late[];
97 extern struct pci_fixup __end_pci_fixups_suspend_late[];
99 static bool pci_apply_fixup_final_quirks;
101 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
103 struct pci_fixup *start, *end;
106 case pci_fixup_early:
107 start = __start_pci_fixups_early;
108 end = __end_pci_fixups_early;
111 case pci_fixup_header:
112 start = __start_pci_fixups_header;
113 end = __end_pci_fixups_header;
116 case pci_fixup_final:
117 if (!pci_apply_fixup_final_quirks)
119 start = __start_pci_fixups_final;
120 end = __end_pci_fixups_final;
123 case pci_fixup_enable:
124 start = __start_pci_fixups_enable;
125 end = __end_pci_fixups_enable;
128 case pci_fixup_resume:
129 start = __start_pci_fixups_resume;
130 end = __end_pci_fixups_resume;
133 case pci_fixup_resume_early:
134 start = __start_pci_fixups_resume_early;
135 end = __end_pci_fixups_resume_early;
138 case pci_fixup_suspend:
139 start = __start_pci_fixups_suspend;
140 end = __end_pci_fixups_suspend;
143 case pci_fixup_suspend_late:
144 start = __start_pci_fixups_suspend_late;
145 end = __end_pci_fixups_suspend_late;
149 /* stupid compiler warning, you would think with an enum... */
152 pci_do_fixups(dev, start, end);
154 EXPORT_SYMBOL(pci_fixup_device);
156 static int __init pci_apply_final_quirks(void)
158 struct pci_dev *dev = NULL;
162 if (pci_cache_line_size)
163 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
165 pci_apply_fixup_final_quirks = true;
166 for_each_pci_dev(dev) {
167 pci_fixup_device(pci_fixup_final, dev);
169 * If arch hasn't set it explicitly yet, use the CLS
170 * value shared by all PCI devices. If there's a
171 * mismatch, fall back to the default value.
173 if (!pci_cache_line_size) {
174 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
177 if (!tmp || cls == tmp)
180 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
182 pci_dfl_cache_line_size << 2);
183 pci_cache_line_size = pci_dfl_cache_line_size;
187 if (!pci_cache_line_size) {
188 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
189 pci_dfl_cache_line_size << 2);
190 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
195 fs_initcall_sync(pci_apply_final_quirks);
198 * Decoding should be disabled for a PCI device during BAR sizing to avoid
199 * conflict. But doing so may cause problems on host bridge and perhaps other
200 * key system devices. For devices that need to have mmio decoding always-on,
201 * we need to set the dev->mmio_always_on bit.
203 static void quirk_mmio_always_on(struct pci_dev *dev)
205 dev->mmio_always_on = 1;
207 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
208 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
211 * The Mellanox Tavor device gives false positive parity errors. Mark this
212 * device with a broken_parity_status to allow PCI scanning code to "skip"
213 * this now blacklisted device.
215 static void quirk_mellanox_tavor(struct pci_dev *dev)
217 dev->broken_parity_status = 1; /* This device gives false positives */
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
223 * Deal with broken BIOSes that neglect to enable passive release,
224 * which can cause problems in combination with the 82441FX/PPro MTRRs
226 static void quirk_passive_release(struct pci_dev *dev)
228 struct pci_dev *d = NULL;
232 * We have to make sure a particular bit is set in the PIIX3
233 * ISA bridge, so we have to go out and find it.
235 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
236 pci_read_config_byte(d, 0x82, &dlc);
238 pci_info(d, "PIIX3: Enabling Passive Release\n");
240 pci_write_config_byte(d, 0x82, dlc);
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
245 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
248 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
249 * workaround but VIA don't answer queries. If you happen to have good
250 * contacts at VIA ask them for me please -- Alan
252 * This appears to be BIOS not version dependent. So presumably there is a
255 static void quirk_isa_dma_hangs(struct pci_dev *dev)
257 if (!isa_dma_bridge_buggy) {
258 isa_dma_bridge_buggy = 1;
259 pci_info(dev, "Activating ISA DMA hang workarounds\n");
263 * It's not totally clear which chipsets are the problematic ones. We know
264 * 82C586 and 82C596 variants are affected.
266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
275 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
276 * for some HT machines to use C4 w/o hanging.
278 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
283 pci_read_config_dword(dev, 0x40, &pmbase);
284 pmbase = pmbase & 0xff80;
288 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
294 /* Chipsets where PCI->PCI transfers vanish or hang */
295 static void quirk_nopcipci(struct pci_dev *dev)
297 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
298 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
299 pci_pci_problems |= PCIPCI_FAIL;
302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
305 static void quirk_nopciamd(struct pci_dev *dev)
308 pci_read_config_byte(dev, 0x08, &rev);
311 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
312 pci_pci_problems |= PCIAGP_FAIL;
315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
317 /* Triton requires workarounds to be used by the drivers */
318 static void quirk_triton(struct pci_dev *dev)
320 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
321 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
322 pci_pci_problems |= PCIPCI_TRITON;
325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
331 * VIA Apollo KT133 needs PCI latency patch
332 * Made according to a Windows driver-based patch by George E. Breese;
333 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
334 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
335 * which Mr Breese based his work.
337 * Updated based on further information from the site and also on
338 * information provided by VIA
340 static void quirk_vialatency(struct pci_dev *dev)
346 * Ok, we have a potential problem chipset here. Now see if we have
347 * a buggy southbridge.
349 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
353 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
355 * Check for buggy part revisions
357 if (p->revision < 0x40 || p->revision > 0x42)
360 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
361 if (p == NULL) /* No problem parts */
364 /* Check for buggy part revisions */
365 if (p->revision < 0x10 || p->revision > 0x12)
370 * Ok we have the problem. Now set the PCI master grant to occur
371 * every master grant. The apparent bug is that under high PCI load
372 * (quite common in Linux of course) you can get data loss when the
373 * CPU is held off the bus for 3 bus master requests. This happens
374 * to include the IDE controllers....
376 * VIA only apply this fix when an SB Live! is present but under
377 * both Linux and Windows this isn't enough, and we have seen
378 * corruption without SB Live! but with things like 3 UDMA IDE
379 * controllers. So we ignore that bit of the VIA recommendation..
381 pci_read_config_byte(dev, 0x76, &busarb);
384 * Set bit 4 and bit 5 of byte 76 to 0x01
385 * "Master priority rotation on every PCI master grant"
389 pci_write_config_byte(dev, 0x76, busarb);
390 pci_info(dev, "Applying VIA southbridge workaround\n");
394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
397 /* Must restore this on a resume from RAM */
398 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
399 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
400 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
402 /* VIA Apollo VP3 needs ETBF on BT848/878 */
403 static void quirk_viaetbf(struct pci_dev *dev)
405 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
406 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
407 pci_pci_problems |= PCIPCI_VIAETBF;
410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
412 static void quirk_vsfx(struct pci_dev *dev)
414 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
415 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
416 pci_pci_problems |= PCIPCI_VSFX;
419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
422 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
423 * space. Latency must be set to 0xA and Triton workaround applied too.
424 * [Info kindly provided by ALi]
426 static void quirk_alimagik(struct pci_dev *dev)
428 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
429 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
430 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
436 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
437 static void quirk_natoma(struct pci_dev *dev)
439 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
440 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
441 pci_pci_problems |= PCIPCI_NATOMA;
444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
452 * This chip can cause PCI parity errors if config register 0xA0 is read
453 * while DMAs are occurring.
455 static void quirk_citrine(struct pci_dev *dev)
457 dev->cfg_size = 0xA0;
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
462 * This chip can cause bus lockups if config addresses above 0x600
463 * are read or written.
465 static void quirk_nfp6000(struct pci_dev *dev)
467 dev->cfg_size = 0x600;
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
474 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
475 static void quirk_extend_bar_to_page(struct pci_dev *dev)
479 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
480 struct resource *r = &dev->resource[i];
482 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
483 r->end = PAGE_SIZE - 1;
485 r->flags |= IORESOURCE_UNSET;
486 pci_info(dev, "expanded BAR %d to page size: %pR\n",
491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
494 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
495 * If it's needed, re-allocate the region.
497 static void quirk_s3_64M(struct pci_dev *dev)
499 struct resource *r = &dev->resource[0];
501 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
502 r->flags |= IORESOURCE_UNSET;
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
510 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
514 struct pci_bus_region bus_region;
515 struct resource *res = dev->resource + pos;
517 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
522 res->name = pci_name(dev);
523 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
525 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
526 region &= ~(size - 1);
528 /* Convert from PCI bus to resource space */
529 bus_region.start = region;
530 bus_region.end = region + size - 1;
531 pcibios_bus_to_resource(dev->bus, res, &bus_region);
533 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
534 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
538 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
539 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
540 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
541 * (which conflicts w/ BAR1's memory range).
543 * CS553x's ISA PCI BARs may also be read-only (ref:
544 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
546 static void quirk_cs5536_vsa(struct pci_dev *dev)
548 static char *name = "CS5536 ISA bridge";
550 if (pci_resource_len(dev, 0) != 8) {
551 quirk_io(dev, 0, 8, name); /* SMB */
552 quirk_io(dev, 1, 256, name); /* GPIO */
553 quirk_io(dev, 2, 64, name); /* MFGPT */
554 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
560 static void quirk_io_region(struct pci_dev *dev, int port,
561 unsigned size, int nr, const char *name)
564 struct pci_bus_region bus_region;
565 struct resource *res = dev->resource + nr;
567 pci_read_config_word(dev, port, ®ion);
568 region &= ~(size - 1);
573 res->name = pci_name(dev);
574 res->flags = IORESOURCE_IO;
576 /* Convert from PCI bus to resource space */
577 bus_region.start = region;
578 bus_region.end = region + size - 1;
579 pcibios_bus_to_resource(dev->bus, res, &bus_region);
581 if (!pci_claim_resource(dev, nr))
582 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
586 * ATI Northbridge setups MCE the processor if you even read somewhere
587 * between 0x3b0->0x3bb or read 0x3d3
589 static void quirk_ati_exploding_mce(struct pci_dev *dev)
591 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
592 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
593 request_region(0x3b0, 0x0C, "RadeonIGP");
594 request_region(0x3d3, 0x01, "RadeonIGP");
596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
599 * In the AMD NL platform, this device ([1022:7912]) has a class code of
600 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
601 * claim it. The same applies on the VanGogh platform device ([1022:163a]).
603 * But the dwc3 driver is a more specific driver for this device, and we'd
604 * prefer to use it instead of xhci. To prevent xhci from claiming the
605 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
606 * defines as "USB device (not host controller)". The dwc3 driver can then
607 * claim it based on its Vendor and Device ID.
609 static void quirk_amd_dwc_class(struct pci_dev *pdev)
611 u32 class = pdev->class;
613 if (class != PCI_CLASS_SERIAL_USB_DEVICE) {
614 /* Use "USB Device (not host controller)" class */
615 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
617 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
622 quirk_amd_dwc_class);
623 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB,
624 quirk_amd_dwc_class);
627 * Synopsys USB 3.x host HAPS platform has a class code of
628 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
629 * devices should use dwc3-haps driver. Change these devices' class code to
630 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
633 static void quirk_synopsys_haps(struct pci_dev *pdev)
635 u32 class = pdev->class;
637 switch (pdev->device) {
638 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
639 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
640 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
641 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
642 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
647 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
648 PCI_CLASS_SERIAL_USB_XHCI, 0,
649 quirk_synopsys_haps);
652 * Let's make the southbridge information explicit instead of having to
653 * worry about people probing the ACPI areas, for example.. (Yes, it
654 * happens, and if you read the wrong ACPI register it will put the machine
655 * to sleep with no way of waking it up again. Bummer).
657 * ALI M7101: Two IO regions pointed to by words at
658 * 0xE0 (64 bytes of ACPI registers)
659 * 0xE2 (32 bytes of SMB registers)
661 static void quirk_ali7101_acpi(struct pci_dev *dev)
663 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
664 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
668 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
671 u32 mask, size, base;
673 pci_read_config_dword(dev, port, &devres);
674 if ((devres & enable) != enable)
676 mask = (devres >> 16) & 15;
677 base = devres & 0xffff;
680 unsigned bit = size >> 1;
681 if ((bit & mask) == bit)
686 * For now we only print it out. Eventually we'll want to
687 * reserve it (at least if it's in the 0x1000+ range), but
688 * let's get enough confirmation reports first.
691 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
694 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
697 u32 mask, size, base;
699 pci_read_config_dword(dev, port, &devres);
700 if ((devres & enable) != enable)
702 base = devres & 0xffff0000;
703 mask = (devres & 0x3f) << 16;
706 unsigned bit = size >> 1;
707 if ((bit & mask) == bit)
713 * For now we only print it out. Eventually we'll want to
714 * reserve it, but let's get enough confirmation reports first.
717 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
721 * PIIX4 ACPI: Two IO regions pointed to by longwords at
722 * 0x40 (64 bytes of ACPI registers)
723 * 0x90 (16 bytes of SMB registers)
724 * and a few strange programmable PIIX4 device resources.
726 static void quirk_piix4_acpi(struct pci_dev *dev)
730 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
731 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
733 /* Device resource A has enables for some of the other ones */
734 pci_read_config_dword(dev, 0x5c, &res_a);
736 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
737 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
739 /* Device resource D is just bitfields for static resources */
741 /* Device 12 enabled? */
742 if (res_a & (1 << 29)) {
743 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
744 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
746 /* Device 13 enabled? */
747 if (res_a & (1 << 30)) {
748 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
749 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
751 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
752 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
754 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
755 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
757 #define ICH_PMBASE 0x40
758 #define ICH_ACPI_CNTL 0x44
759 #define ICH4_ACPI_EN 0x10
760 #define ICH6_ACPI_EN 0x80
761 #define ICH4_GPIOBASE 0x58
762 #define ICH4_GPIO_CNTL 0x5c
763 #define ICH4_GPIO_EN 0x10
764 #define ICH6_GPIOBASE 0x48
765 #define ICH6_GPIO_CNTL 0x4c
766 #define ICH6_GPIO_EN 0x10
769 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
770 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
771 * 0x58 (64 bytes of GPIO I/O space)
773 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
778 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
779 * with low legacy (and fixed) ports. We don't know the decoding
780 * priority and can't tell whether the legacy device or the one created
781 * here is really at that address. This happens on boards with broken
784 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
785 if (enable & ICH4_ACPI_EN)
786 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
787 "ICH4 ACPI/GPIO/TCO");
789 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
790 if (enable & ICH4_GPIO_EN)
791 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
795 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
797 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
798 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
799 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
800 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
801 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
805 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
809 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
810 if (enable & ICH6_ACPI_EN)
811 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
812 "ICH6 ACPI/GPIO/TCO");
814 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
815 if (enable & ICH6_GPIO_EN)
816 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
820 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
821 const char *name, int dynsize)
826 pci_read_config_dword(dev, reg, &val);
834 * This is not correct. It is 16, 32 or 64 bytes depending on
835 * register D31:F0:ADh bits 5:4.
837 * But this gets us at least _part_ of it.
846 * Just print it out for now. We should reserve it after more
849 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
852 static void quirk_ich6_lpc(struct pci_dev *dev)
854 /* Shared ACPI/GPIO decode with all ICH6+ */
855 ich6_lpc_acpi_gpio(dev);
857 /* ICH6-specific generic IO decode */
858 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
859 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
864 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
870 pci_read_config_dword(dev, reg, &val);
876 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
878 mask = (val >> 16) & 0xfc;
882 * Just print it out for now. We should reserve it after more
885 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
888 /* ICH7-10 has the same common LPC generic IO decode registers */
889 static void quirk_ich7_lpc(struct pci_dev *dev)
891 /* We share the common ACPI/GPIO decode with ICH6 */
892 ich6_lpc_acpi_gpio(dev);
894 /* And have 4 ICH7+ generic decodes */
895 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
896 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
897 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
898 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
915 * VIA ACPI: One IO region pointed to by longword at
916 * 0x48 or 0x20 (256 bytes of ACPI registers)
918 static void quirk_vt82c586_acpi(struct pci_dev *dev)
920 if (dev->revision & 0x10)
921 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
927 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
928 * 0x48 (256 bytes of ACPI registers)
929 * 0x70 (128 bytes of hardware monitoring register)
930 * 0x90 (16 bytes of SMB registers)
932 static void quirk_vt82c686_acpi(struct pci_dev *dev)
934 quirk_vt82c586_acpi(dev);
936 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
939 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
944 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
945 * 0x88 (128 bytes of power management registers)
946 * 0xd0 (16 bytes of SMB registers)
948 static void quirk_vt8235_acpi(struct pci_dev *dev)
950 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
951 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
953 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
956 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
957 * back-to-back: Disable fast back-to-back on the secondary bus segment
959 static void quirk_xio2000a(struct pci_dev *dev)
961 struct pci_dev *pdev;
964 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
965 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
966 pci_read_config_word(pdev, PCI_COMMAND, &command);
967 if (command & PCI_COMMAND_FAST_BACK)
968 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
974 #ifdef CONFIG_X86_IO_APIC
976 #include <asm/io_apic.h>
979 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
980 * devices to the external APIC.
982 * TODO: When we have device-specific interrupt routers, this code will go
985 static void quirk_via_ioapic(struct pci_dev *dev)
990 tmp = 0; /* nothing routed to external APIC */
992 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
994 pci_info(dev, "%sbling VIA external APIC routing\n",
995 tmp == 0 ? "Disa" : "Ena");
997 /* Offset 0x58: External APIC IRQ output control */
998 pci_write_config_byte(dev, 0x58, tmp);
1000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1001 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1004 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1005 * This leads to doubled level interrupt rates.
1006 * Set this bit to get rid of cycle wastage.
1007 * Otherwise uncritical.
1009 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1012 #define BYPASS_APIC_DEASSERT 8
1014 pci_read_config_byte(dev, 0x5B, &misc_control2);
1015 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1016 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1017 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1021 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1024 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1025 * We check all revs >= B0 (yet not in the pre production!) as the bug
1026 * is currently marked NoFix
1028 * We have multiple reports of hangs with this chipset that went away with
1029 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1030 * of course. However the advice is demonstrably good even if so.
1032 static void quirk_amd_ioapic(struct pci_dev *dev)
1034 if (dev->revision >= 0x02) {
1035 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1036 pci_warn(dev, " : booting with the \"noapic\" option\n");
1039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1040 #endif /* CONFIG_X86_IO_APIC */
1042 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1044 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1046 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1047 if (dev->subsystem_device == 0xa118)
1048 dev->sriov->link = dev->devfn;
1050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1054 * Some settings of MMRBC can lead to data corruption so block changes.
1055 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1057 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1059 if (dev->subordinate && dev->revision <= 0x12) {
1060 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1062 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1068 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1069 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1070 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1071 * of the ACPI SCI interrupt is only done for convenience.
1074 static void quirk_via_acpi(struct pci_dev *d)
1078 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1079 pci_read_config_byte(d, 0x42, &irq);
1081 if (irq && (irq != 2))
1084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1087 /* VIA bridges which have VLink */
1088 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1090 static void quirk_via_bridge(struct pci_dev *dev)
1092 /* See what bridge we have and find the device ranges */
1093 switch (dev->device) {
1094 case PCI_DEVICE_ID_VIA_82C686:
1096 * The VT82C686 is special; it attaches to PCI and can have
1097 * any device number. All its subdevices are functions of
1098 * that single device.
1100 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1101 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1103 case PCI_DEVICE_ID_VIA_8237:
1104 case PCI_DEVICE_ID_VIA_8237A:
1105 via_vlink_dev_lo = 15;
1107 case PCI_DEVICE_ID_VIA_8235:
1108 via_vlink_dev_lo = 16;
1110 case PCI_DEVICE_ID_VIA_8231:
1111 case PCI_DEVICE_ID_VIA_8233_0:
1112 case PCI_DEVICE_ID_VIA_8233A:
1113 case PCI_DEVICE_ID_VIA_8233C_0:
1114 via_vlink_dev_lo = 17;
1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1128 * quirk_via_vlink - VIA VLink IRQ number update
1131 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1132 * the IRQ line register which usually is not relevant for PCI cards, is
1133 * actually written so that interrupts get sent to the right place.
1135 * We only do this on systems where a VIA south bridge was detected, and
1136 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1138 static void quirk_via_vlink(struct pci_dev *dev)
1142 /* Check if we have VLink at all */
1143 if (via_vlink_dev_lo == -1)
1148 /* Don't quirk interrupts outside the legacy IRQ range */
1149 if (!new_irq || new_irq > 15)
1152 /* Internal device ? */
1153 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1154 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1158 * This is an internal VLink device on a PIC interrupt. The BIOS
1159 * ought to have set this but may not have, so we redo it.
1161 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1162 if (new_irq != irq) {
1163 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1165 udelay(15); /* unknown if delay really needed */
1166 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1169 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1172 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1173 * of VT82C597 for backward compatibility. We need to switch it off to be
1174 * able to recognize the real type of the chip.
1176 static void quirk_vt82c598_id(struct pci_dev *dev)
1178 pci_write_config_byte(dev, 0xfc, 0);
1179 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1184 * CardBus controllers have a legacy base address that enables them to
1185 * respond as i82365 pcmcia controllers. We don't want them to do this
1186 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1187 * driver does not (and should not) handle CardBus.
1189 static void quirk_cardbus_legacy(struct pci_dev *dev)
1191 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1193 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1194 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1195 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1196 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1199 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1200 * what the designers were smoking but let's not inhale...
1202 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1205 static void quirk_amd_ordering(struct pci_dev *dev)
1208 pci_read_config_dword(dev, 0x4C, &pcic);
1209 if ((pcic & 6) != 6) {
1211 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1212 pci_write_config_dword(dev, 0x4C, pcic);
1213 pci_read_config_dword(dev, 0x84, &pcic);
1214 pcic |= (1 << 23); /* Required in this mode */
1215 pci_write_config_dword(dev, 0x84, pcic);
1218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1219 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1222 * DreamWorks-provided workaround for Dunord I-3000 problem
1224 * This card decodes and responds to addresses not apparently assigned to
1225 * it. We force a larger allocation to ensure that nothing gets put too
1228 static void quirk_dunord(struct pci_dev *dev)
1230 struct resource *r = &dev->resource[1];
1232 r->flags |= IORESOURCE_UNSET;
1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1239 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1240 * decoding (transparent), and does indicate this in the ProgIf.
1241 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1243 static void quirk_transparent_bridge(struct pci_dev *dev)
1245 dev->transparent = 1;
1247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1251 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1252 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1253 * found at http://www.national.com/analog for info on what these bits do.
1254 * <christer@weinigel.se>
1256 static void quirk_mediagx_master(struct pci_dev *dev)
1260 pci_read_config_byte(dev, 0x41, ®);
1263 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1265 pci_write_config_byte(dev, 0x41, reg);
1268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1269 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1272 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1273 * in the odd case it is not the results are corruption hence the presence
1276 static void quirk_disable_pxb(struct pci_dev *pdev)
1280 if (pdev->revision != 0x04) /* Only C0 requires this */
1282 pci_read_config_word(pdev, 0x40, &config);
1283 if (config & (1<<6)) {
1285 pci_write_config_word(pdev, 0x40, config);
1286 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1290 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1292 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1294 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1297 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1299 pci_read_config_byte(pdev, 0x40, &tmp);
1300 pci_write_config_byte(pdev, 0x40, tmp|1);
1301 pci_write_config_byte(pdev, 0x9, 1);
1302 pci_write_config_byte(pdev, 0xa, 6);
1303 pci_write_config_byte(pdev, 0x40, tmp);
1305 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1306 pci_info(pdev, "set SATA to AHCI mode\n");
1309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1310 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1312 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1314 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1316 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1318 /* Serverworks CSB5 IDE does not fully support native mode */
1319 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1322 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1326 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1327 /* PCI layer will sort out resources */
1330 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1332 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1333 static void quirk_ide_samemode(struct pci_dev *pdev)
1337 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1339 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1340 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1343 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1346 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1348 /* Some ATA devices break if put into D3 */
1349 static void quirk_no_ata_d3(struct pci_dev *pdev)
1351 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1353 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1354 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1355 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1356 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1357 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1358 /* ALi loses some register settings that we cannot then restore */
1359 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1360 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1361 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1362 occur when mode detecting */
1363 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1364 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1367 * This was originally an Alpha-specific thing, but it really fits here.
1368 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1370 static void quirk_eisa_bridge(struct pci_dev *dev)
1372 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1377 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1378 * is not activated. The myth is that Asus said that they do not want the
1379 * users to be irritated by just another PCI Device in the Win98 device
1380 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1381 * package 2.7.0 for details)
1383 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1384 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1385 * becomes necessary to do this tweak in two steps -- the chosen trigger
1386 * is either the Host bridge (preferred) or on-board VGA controller.
1388 * Note that we used to unhide the SMBus that way on Toshiba laptops
1389 * (Satellite A40 and Tecra M2) but then found that the thermal management
1390 * was done by SMM code, which could cause unsynchronized concurrent
1391 * accesses to the SMBus registers, with potentially bad effects. Thus you
1392 * should be very careful when adding new entries: if SMM is accessing the
1393 * Intel SMBus, this is a very good reason to leave it hidden.
1395 * Likewise, many recent laptops use ACPI for thermal management. If the
1396 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1397 * natively, and keeping the SMBus hidden is the right thing to do. If you
1398 * are about to add an entry in the table below, please first disassemble
1399 * the DSDT and double-check that there is no code accessing the SMBus.
1401 static int asus_hides_smbus;
1403 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1405 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1406 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1407 switch (dev->subsystem_device) {
1408 case 0x8025: /* P4B-LX */
1409 case 0x8070: /* P4B */
1410 case 0x8088: /* P4B533 */
1411 case 0x1626: /* L3C notebook */
1412 asus_hides_smbus = 1;
1414 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1415 switch (dev->subsystem_device) {
1416 case 0x80b1: /* P4GE-V */
1417 case 0x80b2: /* P4PE */
1418 case 0x8093: /* P4B533-V */
1419 asus_hides_smbus = 1;
1421 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1422 switch (dev->subsystem_device) {
1423 case 0x8030: /* P4T533 */
1424 asus_hides_smbus = 1;
1426 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1427 switch (dev->subsystem_device) {
1428 case 0x8070: /* P4G8X Deluxe */
1429 asus_hides_smbus = 1;
1431 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1432 switch (dev->subsystem_device) {
1433 case 0x80c9: /* PU-DLS */
1434 asus_hides_smbus = 1;
1436 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1437 switch (dev->subsystem_device) {
1438 case 0x1751: /* M2N notebook */
1439 case 0x1821: /* M5N notebook */
1440 case 0x1897: /* A6L notebook */
1441 asus_hides_smbus = 1;
1443 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1444 switch (dev->subsystem_device) {
1445 case 0x184b: /* W1N notebook */
1446 case 0x186a: /* M6Ne notebook */
1447 asus_hides_smbus = 1;
1449 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1450 switch (dev->subsystem_device) {
1451 case 0x80f2: /* P4P800-X */
1452 asus_hides_smbus = 1;
1454 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1455 switch (dev->subsystem_device) {
1456 case 0x1882: /* M6V notebook */
1457 case 0x1977: /* A6VA notebook */
1458 asus_hides_smbus = 1;
1460 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1461 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1462 switch (dev->subsystem_device) {
1463 case 0x088C: /* HP Compaq nc8000 */
1464 case 0x0890: /* HP Compaq nc6000 */
1465 asus_hides_smbus = 1;
1467 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1468 switch (dev->subsystem_device) {
1469 case 0x12bc: /* HP D330L */
1470 case 0x12bd: /* HP D530 */
1471 case 0x006a: /* HP Compaq nx9500 */
1472 asus_hides_smbus = 1;
1474 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1475 switch (dev->subsystem_device) {
1476 case 0x12bf: /* HP xw4100 */
1477 asus_hides_smbus = 1;
1479 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1480 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1481 switch (dev->subsystem_device) {
1482 case 0xC00C: /* Samsung P35 notebook */
1483 asus_hides_smbus = 1;
1485 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1486 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1487 switch (dev->subsystem_device) {
1488 case 0x0058: /* Compaq Evo N620c */
1489 asus_hides_smbus = 1;
1491 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1492 switch (dev->subsystem_device) {
1493 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1494 /* Motherboard doesn't have Host bridge
1495 * subvendor/subdevice IDs, therefore checking
1496 * its on-board VGA controller */
1497 asus_hides_smbus = 1;
1499 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1500 switch (dev->subsystem_device) {
1501 case 0x00b8: /* Compaq Evo D510 CMT */
1502 case 0x00b9: /* Compaq Evo D510 SFF */
1503 case 0x00ba: /* Compaq Evo D510 USDT */
1504 /* Motherboard doesn't have Host bridge
1505 * subvendor/subdevice IDs and on-board VGA
1506 * controller is disabled if an AGP card is
1507 * inserted, therefore checking USB UHCI
1509 asus_hides_smbus = 1;
1511 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1512 switch (dev->subsystem_device) {
1513 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1514 /* Motherboard doesn't have host bridge
1515 * subvendor/subdevice IDs, therefore checking
1516 * its on-board VGA controller */
1517 asus_hides_smbus = 1;
1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1536 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1540 if (likely(!asus_hides_smbus))
1543 pci_read_config_word(dev, 0xF2, &val);
1545 pci_write_config_word(dev, 0xF2, val & (~0x8));
1546 pci_read_config_word(dev, 0xF2, &val);
1548 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1551 pci_info(dev, "Enabled i801 SMBus device\n");
1554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1557 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1559 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1560 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1561 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1562 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1563 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1564 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1565 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1566 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1567 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1569 /* It appears we just have one such device. If not, we have a warning */
1570 static void __iomem *asus_rcba_base;
1571 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1575 if (likely(!asus_hides_smbus))
1577 WARN_ON(asus_rcba_base);
1579 pci_read_config_dword(dev, 0xF0, &rcba);
1580 /* use bits 31:14, 16 kB aligned */
1581 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1582 if (asus_rcba_base == NULL)
1586 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1590 if (likely(!asus_hides_smbus || !asus_rcba_base))
1593 /* read the Function Disable register, dword mode only */
1594 val = readl(asus_rcba_base + 0x3418);
1596 /* enable the SMBus device */
1597 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1600 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1602 if (likely(!asus_hides_smbus || !asus_rcba_base))
1605 iounmap(asus_rcba_base);
1606 asus_rcba_base = NULL;
1607 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1610 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1612 asus_hides_smbus_lpc_ich6_suspend(dev);
1613 asus_hides_smbus_lpc_ich6_resume_early(dev);
1614 asus_hides_smbus_lpc_ich6_resume(dev);
1616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1617 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1618 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1619 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1621 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1622 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1625 pci_read_config_byte(dev, 0x77, &val);
1627 pci_info(dev, "Enabling SiS 96x SMBus\n");
1628 pci_write_config_byte(dev, 0x77, val & ~0x10);
1631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1635 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1636 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1637 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1638 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1641 * ... This is further complicated by the fact that some SiS96x south
1642 * bridges pretend to be 85C503/5513 instead. In that case see if we
1643 * spotted a compatible north bridge to make sure.
1644 * (pci_find_device() doesn't work yet)
1646 * We can also enable the sis96x bit in the discovery register..
1648 #define SIS_DETECT_REGISTER 0x40
1650 static void quirk_sis_503(struct pci_dev *dev)
1655 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1656 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1657 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1658 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1659 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1664 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1665 * it has already been processed. (Depends on link order, which is
1666 * apparently not guaranteed)
1668 dev->device = devid;
1669 quirk_sis_96x_smbus(dev);
1671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1672 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1675 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1676 * and MC97 modem controller are disabled when a second PCI soundcard is
1677 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1680 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1683 int asus_hides_ac97 = 0;
1685 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1686 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1687 asus_hides_ac97 = 1;
1690 if (!asus_hides_ac97)
1693 pci_read_config_byte(dev, 0x50, &val);
1695 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1696 pci_read_config_byte(dev, 0x50, &val);
1698 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1701 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1705 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1707 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1710 * If we are using libata we can drive this chip properly but must do this
1711 * early on to make the additional device appear during the PCI scanning.
1713 static void quirk_jmicron_ata(struct pci_dev *pdev)
1715 u32 conf1, conf5, class;
1718 /* Only poke fn 0 */
1719 if (PCI_FUNC(pdev->devfn))
1722 pci_read_config_dword(pdev, 0x40, &conf1);
1723 pci_read_config_dword(pdev, 0x80, &conf5);
1725 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1726 conf5 &= ~(1 << 24); /* Clear bit 24 */
1728 switch (pdev->device) {
1729 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1730 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1731 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1732 /* The controller should be in single function ahci mode */
1733 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1736 case PCI_DEVICE_ID_JMICRON_JMB365:
1737 case PCI_DEVICE_ID_JMICRON_JMB366:
1738 /* Redirect IDE second PATA port to the right spot */
1741 case PCI_DEVICE_ID_JMICRON_JMB361:
1742 case PCI_DEVICE_ID_JMICRON_JMB363:
1743 case PCI_DEVICE_ID_JMICRON_JMB369:
1744 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1745 /* Set the class codes correctly and then direct IDE 0 */
1746 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1749 case PCI_DEVICE_ID_JMICRON_JMB368:
1750 /* The controller should be in single function IDE mode */
1751 conf1 |= 0x00C00000; /* Set 22, 23 */
1755 pci_write_config_dword(pdev, 0x40, conf1);
1756 pci_write_config_dword(pdev, 0x80, conf5);
1758 /* Update pdev accordingly */
1759 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1760 pdev->hdr_type = hdr & 0x7f;
1761 pdev->multifunction = !!(hdr & 0x80);
1763 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1764 pdev->class = class >> 8;
1766 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1768 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1769 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1770 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1771 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1772 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1773 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1774 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1775 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1776 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1777 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1778 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1779 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1780 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1781 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1782 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1783 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1787 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1789 if (dev->multifunction) {
1790 device_disable_async_suspend(&dev->dev);
1791 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1794 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1795 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1796 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1799 #ifdef CONFIG_X86_IO_APIC
1800 static void quirk_alder_ioapic(struct pci_dev *pdev)
1804 if ((pdev->class >> 8) != 0xff00)
1808 * The first BAR is the location of the IO-APIC... we must
1809 * not touch this (and it's already covered by the fixmap), so
1810 * forcibly insert it into the resource tree.
1812 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1813 insert_resource(&iomem_resource, &pdev->resource[0]);
1816 * The next five BARs all seem to be rubbish, so just clean
1819 for (i = 1; i < PCI_STD_NUM_BARS; i++)
1820 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1825 static void quirk_no_msi(struct pci_dev *dev)
1827 pci_info(dev, "avoiding MSI to work around a hardware defect\n");
1830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1835 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1837 static void quirk_pcie_mch(struct pci_dev *pdev)
1841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1845 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1848 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1849 * together on certain PXH-based systems.
1851 static void quirk_pcie_pxh(struct pci_dev *dev)
1854 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1857 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1858 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1859 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1860 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1863 * Some Intel PCI Express chipsets have trouble with downstream device
1866 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1868 pci_pm_d3hot_delay = 120;
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1878 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1880 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1882 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1884 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1888 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1890 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1891 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1893 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1895 if (dev->d3hot_delay >= delay)
1898 dev->d3hot_delay = delay;
1899 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1903 static void quirk_radeon_pm(struct pci_dev *dev)
1905 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1906 dev->subsystem_device == 0x00e2)
1907 quirk_d3hot_delay(dev, 20);
1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1912 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1913 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1915 * The kernel attempts to transition these devices to D3cold, but that seems
1916 * to be ineffective on the platforms in question; the PCI device appears to
1917 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1918 * extended delay in order to succeed.
1920 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1922 quirk_d3hot_delay(dev, 20);
1924 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1926 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
1928 #ifdef CONFIG_X86_IO_APIC
1929 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1931 noioapicreroute = 1;
1932 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1937 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1939 * Systems to exclude from boot interrupt reroute quirks
1942 .callback = dmi_disable_ioapicreroute,
1943 .ident = "ASUSTek Computer INC. M2N-LR",
1945 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1946 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1953 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1954 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1955 * that a PCI device's interrupt handler is installed on the boot interrupt
1958 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1960 dmi_check_system(boot_interrupt_dmi_table);
1961 if (noioapicquirk || noioapicreroute)
1964 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1965 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1966 dev->vendor, dev->device);
1968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1976 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1977 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1978 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1979 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1980 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1981 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1982 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1983 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1986 * On some chipsets we can disable the generation of legacy INTx boot
1991 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1992 * 300641-004US, section 5.7.3.
1994 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1995 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1996 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1997 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1998 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1999 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2000 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2001 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2002 * Core IO on Xeon Scalable, see Intel order no 610950.
2004 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2005 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
2007 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2008 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
2010 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
2012 u16 pci_config_word;
2013 u32 pci_config_dword;
2018 switch (dev->device) {
2019 case PCI_DEVICE_ID_INTEL_ESB_10:
2020 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2022 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2023 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2026 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2027 case 0x0e28: /* Xeon E5/E7 V2 */
2028 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2029 case 0x6f28: /* Xeon D-1500 */
2030 case 0x2034: /* Xeon Scalable Family */
2031 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2033 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2034 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2040 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2041 dev->vendor, dev->device);
2044 * Device 29 Func 5 Device IDs of IO-APIC
2045 * containing ABAR—APIC1 Alternate Base Address Register
2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2048 quirk_disable_intel_boot_interrupt);
2049 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2050 quirk_disable_intel_boot_interrupt);
2053 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2054 * containing Coherent Interface Protocol Interrupt Control
2056 * Device IDs obtained from volume 2 datasheets of commented
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2060 quirk_disable_intel_boot_interrupt);
2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2062 quirk_disable_intel_boot_interrupt);
2063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2064 quirk_disable_intel_boot_interrupt);
2065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2066 quirk_disable_intel_boot_interrupt);
2067 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2068 quirk_disable_intel_boot_interrupt);
2069 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2070 quirk_disable_intel_boot_interrupt);
2071 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2072 quirk_disable_intel_boot_interrupt);
2073 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2074 quirk_disable_intel_boot_interrupt);
2075 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2076 quirk_disable_intel_boot_interrupt);
2077 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2078 quirk_disable_intel_boot_interrupt);
2080 /* Disable boot interrupts on HT-1000 */
2081 #define BC_HT1000_FEATURE_REG 0x64
2082 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2083 #define BC_HT1000_MAP_IDX 0xC00
2084 #define BC_HT1000_MAP_DATA 0xC01
2086 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2088 u32 pci_config_dword;
2094 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2095 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2096 BC_HT1000_PIC_REGS_ENABLE);
2098 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2099 outb(irq, BC_HT1000_MAP_IDX);
2100 outb(0x00, BC_HT1000_MAP_DATA);
2103 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2105 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2106 dev->vendor, dev->device);
2108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2109 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2111 /* Disable boot interrupts on AMD and ATI chipsets */
2114 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2115 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2116 * (due to an erratum).
2118 #define AMD_813X_MISC 0x40
2119 #define AMD_813X_NOIOAMODE (1<<0)
2120 #define AMD_813X_REV_B1 0x12
2121 #define AMD_813X_REV_B2 0x13
2123 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2125 u32 pci_config_dword;
2129 if ((dev->revision == AMD_813X_REV_B1) ||
2130 (dev->revision == AMD_813X_REV_B2))
2133 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2134 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2135 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2137 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2138 dev->vendor, dev->device);
2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2141 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2143 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2145 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2147 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2149 u16 pci_config_word;
2154 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2155 if (!pci_config_word) {
2156 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2157 dev->vendor, dev->device);
2160 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2161 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2162 dev->vendor, dev->device);
2164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2165 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2166 #endif /* CONFIG_X86_IO_APIC */
2169 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2170 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2171 * Re-allocate the region if needed...
2173 static void quirk_tc86c001_ide(struct pci_dev *dev)
2175 struct resource *r = &dev->resource[0];
2177 if (r->start & 0x8) {
2178 r->flags |= IORESOURCE_UNSET;
2183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2184 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2185 quirk_tc86c001_ide);
2188 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2189 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2190 * being read correctly if bit 7 of the base address is set.
2191 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2192 * Re-allocate the regions to a 256-byte boundary if necessary.
2194 static void quirk_plx_pci9050(struct pci_dev *dev)
2198 /* Fixed in revision 2 (PCI 9052). */
2199 if (dev->revision >= 2)
2201 for (bar = 0; bar <= 1; bar++)
2202 if (pci_resource_len(dev, bar) == 0x80 &&
2203 (pci_resource_start(dev, bar) & 0x80)) {
2204 struct resource *r = &dev->resource[bar];
2205 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2207 r->flags |= IORESOURCE_UNSET;
2212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2215 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2216 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2217 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2218 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2220 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2223 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2224 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2226 static void quirk_netmos(struct pci_dev *dev)
2228 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2229 unsigned int num_serial = dev->subsystem_device & 0xf;
2232 * These Netmos parts are multiport serial devices with optional
2233 * parallel ports. Even when parallel ports are present, they
2234 * are identified as class SERIAL, which means the serial driver
2235 * will claim them. To prevent this, mark them as class OTHER.
2236 * These combo devices should be claimed by parport_serial.
2238 * The subdevice ID is of the form 0x00PS, where <P> is the number
2239 * of parallel ports and <S> is the number of serial ports.
2241 switch (dev->device) {
2242 case PCI_DEVICE_ID_NETMOS_9835:
2243 /* Well, this rule doesn't hold for the following 9835 device */
2244 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2245 dev->subsystem_device == 0x0299)
2248 case PCI_DEVICE_ID_NETMOS_9735:
2249 case PCI_DEVICE_ID_NETMOS_9745:
2250 case PCI_DEVICE_ID_NETMOS_9845:
2251 case PCI_DEVICE_ID_NETMOS_9855:
2253 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2254 dev->device, num_parallel, num_serial);
2255 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2256 (dev->class & 0xff);
2260 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2261 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2263 static void quirk_e100_interrupt(struct pci_dev *dev)
2269 switch (dev->device) {
2270 /* PCI IDs taken from drivers/net/e100.c */
2272 case 0x1030 ... 0x1034:
2273 case 0x1038 ... 0x103E:
2274 case 0x1050 ... 0x1057:
2276 case 0x1064 ... 0x106B:
2277 case 0x1091 ... 0x1095:
2290 * Some firmware hands off the e100 with interrupts enabled,
2291 * which can cause a flood of interrupts if packets are
2292 * received before the driver attaches to the device. So
2293 * disable all e100 interrupts here. The driver will
2294 * re-enable them when it's ready.
2296 pci_read_config_word(dev, PCI_COMMAND, &command);
2298 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2302 * Check that the device is in the D0 power state. If it's not,
2303 * there is no point to look any further.
2306 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2307 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2311 /* Convert from PCI bus to resource space. */
2312 csr = ioremap(pci_resource_start(dev, 0), 8);
2314 pci_warn(dev, "Can't map e100 registers\n");
2318 cmd_hi = readb(csr + 3);
2320 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2326 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2327 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2330 * The 82575 and 82598 may experience data corruption issues when transitioning
2331 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2333 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2335 pci_info(dev, "Disabling L0s\n");
2336 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2346 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2347 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2351 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2353 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2355 pci_info(dev, "Disabling ASPM L0s/L1\n");
2356 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2360 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2361 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2362 * disable both L0s and L1 for now to be safe.
2364 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2367 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2368 * Link bit cleared after starting the link retrain process to allow this
2369 * process to finish.
2371 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2372 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2374 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2376 dev->clear_retrain_link = 1;
2377 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2379 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2380 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2381 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2383 static void fixup_rev1_53c810(struct pci_dev *dev)
2385 u32 class = dev->class;
2388 * rev 1 ncr53c810 chips don't set the class at all which means
2389 * they don't get their resources remapped. Fix that here.
2394 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2395 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2400 /* Enable 1k I/O space granularity on the Intel P64H2 */
2401 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2405 pci_read_config_word(dev, 0x40, &en1k);
2408 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2409 dev->io_window_1k = 1;
2412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2415 * Under some circumstances, AER is not linked with extended capabilities.
2416 * Force it to be linked by setting the corresponding control bit in the
2419 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2423 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2425 pci_write_config_byte(dev, 0xf41, b | 0x20);
2426 pci_info(dev, "Linking AER extended capability\n");
2430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2431 quirk_nvidia_ck804_pcie_aer_ext_cap);
2432 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2433 quirk_nvidia_ck804_pcie_aer_ext_cap);
2435 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2438 * Disable PCI Bus Parking and PCI Master read caching on CX700
2439 * which causes unspecified timing errors with a VT6212L on the PCI
2440 * bus leading to USB2.0 packet loss.
2442 * This quirk is only enabled if a second (on the external PCI bus)
2443 * VT6212L is found -- the CX700 core itself also contains a USB
2444 * host controller with the same PCI ID as the VT6212L.
2447 /* Count VT6212L instances */
2448 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2449 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2453 * p should contain the first (internal) VT6212L -- see if we have
2454 * an external one by searching again.
2456 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2461 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2463 /* Turn off PCI Bus Parking */
2464 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2466 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2470 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2472 /* Turn off PCI Master read caching */
2473 pci_write_config_byte(dev, 0x72, 0x0);
2475 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2476 pci_write_config_byte(dev, 0x75, 0x1);
2478 /* Disable "Read FIFO Timer" */
2479 pci_write_config_byte(dev, 0x77, 0x0);
2481 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2487 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2491 pci_read_config_dword(dev, 0xf4, &rev);
2493 /* Only CAP the MRRS if the device is a 5719 A0 */
2494 if (rev == 0x05719000) {
2495 int readrq = pcie_get_readrq(dev);
2497 pcie_set_readrq(dev, 2048);
2500 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2501 PCI_DEVICE_ID_TIGON3_5719,
2502 quirk_brcm_5719_limit_mrrs);
2505 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2506 * hide device 6 which configures the overflow device access containing the
2507 * DRBs - this is where we expose device 6.
2508 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2510 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2514 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2515 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2516 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2519 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2520 quirk_unhide_mch_dev6);
2521 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2522 quirk_unhide_mch_dev6);
2524 #ifdef CONFIG_PCI_MSI
2526 * Some chipsets do not support MSI. We cannot easily rely on setting
2527 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2528 * other buses controlled by the chipset even if Linux is not aware of it.
2529 * Instead of setting the flag on all buses in the machine, simply disable
2532 static void quirk_disable_all_msi(struct pci_dev *dev)
2535 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2546 /* Disable MSI on chipsets that are known to not support it */
2547 static void quirk_disable_msi(struct pci_dev *dev)
2549 if (dev->subordinate) {
2550 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2551 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2559 * The APC bridge device in AMD 780 family northbridges has some random
2560 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2561 * we use the possible vendor/device IDs of the host bridge for the
2562 * declared quirk, and search for the APC bridge by slot number.
2564 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2566 struct pci_dev *apc_bridge;
2568 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2570 if (apc_bridge->device == 0x9602)
2571 quirk_disable_msi(apc_bridge);
2572 pci_dev_put(apc_bridge);
2575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2579 * Go through the list of HyperTransport capabilities and return 1 if a HT
2580 * MSI capability is found and enabled.
2582 static int msi_ht_cap_enabled(struct pci_dev *dev)
2584 int pos, ttl = PCI_FIND_CAP_TTL;
2586 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2587 while (pos && ttl--) {
2590 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2592 pci_info(dev, "Found %s HT MSI Mapping\n",
2593 flags & HT_MSI_FLAGS_ENABLE ?
2594 "enabled" : "disabled");
2595 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2598 pos = pci_find_next_ht_capability(dev, pos,
2599 HT_CAPTYPE_MSI_MAPPING);
2604 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2605 static void quirk_msi_ht_cap(struct pci_dev *dev)
2607 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2608 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2609 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2616 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2617 * if the MSI capability is set in any of these mappings.
2619 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2621 struct pci_dev *pdev;
2623 if (!dev->subordinate)
2627 * Check HT MSI cap on this chipset and the root one. A single one
2628 * having MSI is enough to be sure that MSI is supported.
2630 pdev = pci_get_slot(dev->bus, 0);
2633 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2634 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2635 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2640 quirk_nvidia_ck804_msi_ht_cap);
2642 /* Force enable MSI mapping capability on HT bridges */
2643 static void ht_enable_msi_mapping(struct pci_dev *dev)
2645 int pos, ttl = PCI_FIND_CAP_TTL;
2647 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2648 while (pos && ttl--) {
2651 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2653 pci_info(dev, "Enabling HT MSI Mapping\n");
2655 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2656 flags | HT_MSI_FLAGS_ENABLE);
2658 pos = pci_find_next_ht_capability(dev, pos,
2659 HT_CAPTYPE_MSI_MAPPING);
2662 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2663 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2664 ht_enable_msi_mapping);
2665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2666 ht_enable_msi_mapping);
2669 * The P5N32-SLI motherboards from Asus have a problem with MSI
2670 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2671 * also affects other devices. As for now, turn off MSI for this device.
2673 static void nvenet_msi_disable(struct pci_dev *dev)
2675 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2678 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2679 strstr(board_name, "P5N32-E SLI"))) {
2680 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2684 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2685 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2686 nvenet_msi_disable);
2689 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2690 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2691 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2692 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2693 * for other events, since PCIe specificiation doesn't support using a mix of
2694 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2695 * service drivers registering their respective ISRs for MSIs.
2697 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2701 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2702 PCI_CLASS_BRIDGE_PCI, 8,
2703 pci_quirk_nvidia_tegra_disable_rp_msi);
2704 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2705 PCI_CLASS_BRIDGE_PCI, 8,
2706 pci_quirk_nvidia_tegra_disable_rp_msi);
2707 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2708 PCI_CLASS_BRIDGE_PCI, 8,
2709 pci_quirk_nvidia_tegra_disable_rp_msi);
2710 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2711 PCI_CLASS_BRIDGE_PCI, 8,
2712 pci_quirk_nvidia_tegra_disable_rp_msi);
2713 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2714 PCI_CLASS_BRIDGE_PCI, 8,
2715 pci_quirk_nvidia_tegra_disable_rp_msi);
2716 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2717 PCI_CLASS_BRIDGE_PCI, 8,
2718 pci_quirk_nvidia_tegra_disable_rp_msi);
2719 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2720 PCI_CLASS_BRIDGE_PCI, 8,
2721 pci_quirk_nvidia_tegra_disable_rp_msi);
2722 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2723 PCI_CLASS_BRIDGE_PCI, 8,
2724 pci_quirk_nvidia_tegra_disable_rp_msi);
2725 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2726 PCI_CLASS_BRIDGE_PCI, 8,
2727 pci_quirk_nvidia_tegra_disable_rp_msi);
2728 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2729 PCI_CLASS_BRIDGE_PCI, 8,
2730 pci_quirk_nvidia_tegra_disable_rp_msi);
2731 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2732 PCI_CLASS_BRIDGE_PCI, 8,
2733 pci_quirk_nvidia_tegra_disable_rp_msi);
2734 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2735 PCI_CLASS_BRIDGE_PCI, 8,
2736 pci_quirk_nvidia_tegra_disable_rp_msi);
2737 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2738 PCI_CLASS_BRIDGE_PCI, 8,
2739 pci_quirk_nvidia_tegra_disable_rp_msi);
2742 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2743 * config register. This register controls the routing of legacy
2744 * interrupts from devices that route through the MCP55. If this register
2745 * is misprogrammed, interrupts are only sent to the BSP, unlike
2746 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2747 * having this register set properly prevents kdump from booting up
2748 * properly, so let's make sure that we have it set correctly.
2749 * Note that this is an undocumented register.
2751 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2755 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2758 pci_read_config_dword(dev, 0x74, &cfg);
2760 if (cfg & ((1 << 2) | (1 << 15))) {
2761 pr_info("Rewriting IRQ routing register on MCP55\n");
2762 cfg &= ~((1 << 2) | (1 << 15));
2763 pci_write_config_dword(dev, 0x74, cfg);
2766 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2767 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2768 nvbridge_check_legacy_irq_routing);
2769 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2770 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2771 nvbridge_check_legacy_irq_routing);
2773 static int ht_check_msi_mapping(struct pci_dev *dev)
2775 int pos, ttl = PCI_FIND_CAP_TTL;
2778 /* Check if there is HT MSI cap or enabled on this device */
2779 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2780 while (pos && ttl--) {
2785 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2787 if (flags & HT_MSI_FLAGS_ENABLE) {
2794 pos = pci_find_next_ht_capability(dev, pos,
2795 HT_CAPTYPE_MSI_MAPPING);
2801 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2803 struct pci_dev *dev;
2808 dev_no = host_bridge->devfn >> 3;
2809 for (i = dev_no + 1; i < 0x20; i++) {
2810 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2814 /* found next host bridge? */
2815 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2821 if (ht_check_msi_mapping(dev)) {
2832 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2833 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2835 static int is_end_of_ht_chain(struct pci_dev *dev)
2841 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2846 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2848 ctrl_off = ((flags >> 10) & 1) ?
2849 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2850 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2852 if (ctrl & (1 << 6))
2859 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2861 struct pci_dev *host_bridge;
2866 dev_no = dev->devfn >> 3;
2867 for (i = dev_no; i >= 0; i--) {
2868 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2872 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2877 pci_dev_put(host_bridge);
2883 /* don't enable end_device/host_bridge with leaf directly here */
2884 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2885 host_bridge_with_leaf(host_bridge))
2888 /* root did that ! */
2889 if (msi_ht_cap_enabled(host_bridge))
2892 ht_enable_msi_mapping(dev);
2895 pci_dev_put(host_bridge);
2898 static void ht_disable_msi_mapping(struct pci_dev *dev)
2900 int pos, ttl = PCI_FIND_CAP_TTL;
2902 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2903 while (pos && ttl--) {
2906 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2908 pci_info(dev, "Disabling HT MSI Mapping\n");
2910 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2911 flags & ~HT_MSI_FLAGS_ENABLE);
2913 pos = pci_find_next_ht_capability(dev, pos,
2914 HT_CAPTYPE_MSI_MAPPING);
2918 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2920 struct pci_dev *host_bridge;
2924 if (!pci_msi_enabled())
2927 /* check if there is HT MSI cap or enabled on this device */
2928 found = ht_check_msi_mapping(dev);
2935 * HT MSI mapping should be disabled on devices that are below
2936 * a non-Hypertransport host bridge. Locate the host bridge...
2938 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2940 if (host_bridge == NULL) {
2941 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2945 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2947 /* Host bridge is to HT */
2949 /* it is not enabled, try to enable it */
2951 ht_enable_msi_mapping(dev);
2953 nv_ht_enable_msi_mapping(dev);
2958 /* HT MSI is not enabled */
2962 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2963 ht_disable_msi_mapping(dev);
2966 pci_dev_put(host_bridge);
2969 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2971 return __nv_msi_ht_cap_quirk(dev, 1);
2973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2974 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2976 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2978 return __nv_msi_ht_cap_quirk(dev, 0);
2980 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2981 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2983 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2985 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2988 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2993 * SB700 MSI issue will be fixed at HW level from revision A21;
2994 * we need check PCI REVISION ID of SMBus controller to get SB700
2997 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3002 if ((p->revision < 0x3B) && (p->revision >= 0x30))
3003 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3007 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
3009 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
3010 if (dev->revision < 0x18) {
3011 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
3012 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3016 PCI_DEVICE_ID_TIGON3_5780,
3017 quirk_msi_intx_disable_bug);
3018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3019 PCI_DEVICE_ID_TIGON3_5780S,
3020 quirk_msi_intx_disable_bug);
3021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3022 PCI_DEVICE_ID_TIGON3_5714,
3023 quirk_msi_intx_disable_bug);
3024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3025 PCI_DEVICE_ID_TIGON3_5714S,
3026 quirk_msi_intx_disable_bug);
3027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3028 PCI_DEVICE_ID_TIGON3_5715,
3029 quirk_msi_intx_disable_bug);
3030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3031 PCI_DEVICE_ID_TIGON3_5715S,
3032 quirk_msi_intx_disable_bug);
3034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3035 quirk_msi_intx_disable_ati_bug);
3036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3037 quirk_msi_intx_disable_ati_bug);
3038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3039 quirk_msi_intx_disable_ati_bug);
3040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3041 quirk_msi_intx_disable_ati_bug);
3042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3043 quirk_msi_intx_disable_ati_bug);
3045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3046 quirk_msi_intx_disable_bug);
3047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3048 quirk_msi_intx_disable_bug);
3049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3050 quirk_msi_intx_disable_bug);
3052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3053 quirk_msi_intx_disable_bug);
3054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3055 quirk_msi_intx_disable_bug);
3056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3057 quirk_msi_intx_disable_bug);
3058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3059 quirk_msi_intx_disable_bug);
3060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3061 quirk_msi_intx_disable_bug);
3062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3063 quirk_msi_intx_disable_bug);
3064 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3065 quirk_msi_intx_disable_qca_bug);
3066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3067 quirk_msi_intx_disable_qca_bug);
3068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3069 quirk_msi_intx_disable_qca_bug);
3070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3071 quirk_msi_intx_disable_qca_bug);
3072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3073 quirk_msi_intx_disable_qca_bug);
3076 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3077 * should be disabled on platforms where the device (mistakenly) advertises it.
3079 * Notice that this quirk also disables MSI (which may work, but hasn't been
3080 * tested), since currently there is no standard way to disable only MSI-X.
3082 * The 0031 device id is reused for other non Root Port device types,
3083 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3085 static void quirk_al_msi_disable(struct pci_dev *dev)
3088 pci_warn(dev, "Disabling MSI/MSI-X\n");
3090 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3091 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3092 #endif /* CONFIG_PCI_MSI */
3095 * Allow manual resource allocation for PCI hotplug bridges via
3096 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3097 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3098 * allocate resources when hotplug device is inserted and PCI bus is
3101 static void quirk_hotplug_bridge(struct pci_dev *dev)
3103 dev->is_hotplug_bridge = 1;
3105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3108 * This is a quirk for the Ricoh MMC controller found as a part of some
3109 * multifunction chips.
3111 * This is very similar and based on the ricoh_mmc driver written by
3112 * Philip Langdale. Thank you for these magic sequences.
3114 * These chips implement the four main memory card controllers (SD, MMC,
3115 * MS, xD) and one or both of CardBus or FireWire.
3117 * It happens that they implement SD and MMC support as separate
3118 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3119 * cards but the chip detects MMC cards in hardware and directs them to the
3120 * MMC controller - so the SDHCI driver never sees them.
3122 * To get around this, we must disable the useless MMC controller. At that
3123 * point, the SDHCI controller will start seeing them. It seems to be the
3124 * case that the relevant PCI registers to deactivate the MMC controller
3125 * live on PCI function 0, which might be the CardBus controller or the
3126 * FireWire controller, depending on the particular chip in question
3128 * This has to be done early, because as soon as we disable the MMC controller
3129 * other PCI functions shift up one level, e.g. function #2 becomes function
3130 * #1, and this will confuse the PCI core.
3132 #ifdef CONFIG_MMC_RICOH_MMC
3133 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3140 * Disable via CardBus interface
3142 * This must be done via function #0
3144 if (PCI_FUNC(dev->devfn))
3147 pci_read_config_byte(dev, 0xB7, &disable);
3151 pci_read_config_byte(dev, 0x8E, &write_enable);
3152 pci_write_config_byte(dev, 0x8E, 0xAA);
3153 pci_read_config_byte(dev, 0x8D, &write_target);
3154 pci_write_config_byte(dev, 0x8D, 0xB7);
3155 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3156 pci_write_config_byte(dev, 0x8E, write_enable);
3157 pci_write_config_byte(dev, 0x8D, write_target);
3159 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3160 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3162 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3163 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3165 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3171 * Disable via FireWire interface
3173 * This must be done via function #0
3175 if (PCI_FUNC(dev->devfn))
3178 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3179 * certain types of SD/MMC cards. Lowering the SD base clock
3180 * frequency from 200Mhz to 50Mhz fixes this issue.
3182 * 0x150 - SD2.0 mode enable for changing base clock
3183 * frequency to 50Mhz
3184 * 0xe1 - Base clock frequency
3185 * 0x32 - 50Mhz new clock frequency
3186 * 0xf9 - Key register for 0x150
3187 * 0xfc - key register for 0xe1
3189 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3190 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3191 pci_write_config_byte(dev, 0xf9, 0xfc);
3192 pci_write_config_byte(dev, 0x150, 0x10);
3193 pci_write_config_byte(dev, 0xf9, 0x00);
3194 pci_write_config_byte(dev, 0xfc, 0x01);
3195 pci_write_config_byte(dev, 0xe1, 0x32);
3196 pci_write_config_byte(dev, 0xfc, 0x00);
3198 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3201 pci_read_config_byte(dev, 0xCB, &disable);
3206 pci_read_config_byte(dev, 0xCA, &write_enable);
3207 pci_write_config_byte(dev, 0xCA, 0x57);
3208 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3209 pci_write_config_byte(dev, 0xCA, write_enable);
3211 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3212 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3215 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3216 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3217 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3218 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3219 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3220 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3221 #endif /*CONFIG_MMC_RICOH_MMC*/
3223 #ifdef CONFIG_DMAR_TABLE
3224 #define VTUNCERRMSK_REG 0x1ac
3225 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3227 * This is a quirk for masking VT-d spec-defined errors to platform error
3228 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3229 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3230 * on the RAS config settings of the platform) when a VT-d fault happens.
3231 * The resulting SMI caused the system to hang.
3233 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3234 * need to report the same error through other channels.
3236 static void vtd_mask_spec_errors(struct pci_dev *dev)
3240 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3241 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3243 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3244 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3247 static void fixup_ti816x_class(struct pci_dev *dev)
3249 u32 class = dev->class;
3251 /* TI 816x devices do not have class code set when in PCIe boot mode */
3252 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3253 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3256 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3257 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3260 * Some PCIe devices do not work reliably with the claimed maximum
3261 * payload size supported.
3263 static void fixup_mpss_256(struct pci_dev *dev)
3265 dev->pcie_mpss = 1; /* 256 bytes */
3267 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3268 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3269 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3270 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3271 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3272 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3273 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3276 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3277 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3278 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3279 * until all of the devices are discovered and buses walked, read completion
3280 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3281 * it is possible to hotplug a device with MPS of 256B.
3283 static void quirk_intel_mc_errata(struct pci_dev *dev)
3288 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3289 pcie_bus_config == PCIE_BUS_DEFAULT)
3293 * Intel erratum specifies bits to change but does not say what
3294 * they are. Keeping them magical until such time as the registers
3295 * and values can be explained.
3297 err = pci_read_config_word(dev, 0x48, &rcc);
3299 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3303 if (!(rcc & (1 << 10)))
3308 err = pci_write_config_word(dev, 0x48, rcc);
3310 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3314 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3316 /* Intel 5000 series memory controllers and ports 2-7 */
3317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3331 /* Intel 5100 series memory controllers and ports 2-7 */
3332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3345 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3346 * To work around this, query the size it should be configured to by the
3347 * device and modify the resource end to correspond to this new size.
3349 static void quirk_intel_ntb(struct pci_dev *dev)
3354 rc = pci_read_config_byte(dev, 0x00D0, &val);
3358 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3360 rc = pci_read_config_byte(dev, 0x00D1, &val);
3364 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3370 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3371 * though no one is handling them (e.g., if the i915 driver is never
3372 * loaded). Additionally the interrupt destination is not set up properly
3373 * and the interrupt ends up -somewhere-.
3375 * These spurious interrupts are "sticky" and the kernel disables the
3376 * (shared) interrupt line after 100,000+ generated interrupts.
3378 * Fix it by disabling the still enabled interrupts. This resolves crashes
3379 * often seen on monitor unplug.
3381 #define I915_DEIER_REG 0x4400c
3382 static void disable_igfx_irq(struct pci_dev *dev)
3384 void __iomem *regs = pci_iomap(dev, 0, 0);
3386 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3390 /* Check if any interrupt line is still enabled */
3391 if (readl(regs + I915_DEIER_REG) != 0) {
3392 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3394 writel(0, regs + I915_DEIER_REG);
3397 pci_iounmap(dev, regs);
3399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3408 * PCI devices which are on Intel chips can skip the 10ms delay
3409 * before entering D3 mode.
3411 static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3413 dev->d3hot_delay = 0;
3415 /* C600 Series devices do not need 10ms d3hot_delay */
3416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3419 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3431 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3443 * Some devices may pass our check in pci_intx_mask_supported() if
3444 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3445 * support this feature.
3447 static void quirk_broken_intx_masking(struct pci_dev *dev)
3449 dev->broken_intx_masking = 1;
3451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3452 quirk_broken_intx_masking);
3453 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3454 quirk_broken_intx_masking);
3455 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3456 quirk_broken_intx_masking);
3459 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3460 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3462 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3465 quirk_broken_intx_masking);
3468 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3469 * DisINTx can be set but the interrupt status bit is non-functional.
3471 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3472 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3473 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3474 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3475 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3477 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3488 static u16 mellanox_broken_intx_devs[] = {
3489 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3490 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3491 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3492 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3493 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3494 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3495 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3496 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3497 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3498 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3499 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3500 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3501 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3502 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3505 #define CONNECTX_4_CURR_MAX_MINOR 99
3506 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3509 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3510 * If so, don't mark it as broken.
3511 * FW minor > 99 means older FW version format and no INTx masking support.
3512 * FW minor < 14 means new FW version format and no INTx masking support.
3514 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3516 __be32 __iomem *fw_ver;
3524 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3525 if (pdev->device == mellanox_broken_intx_devs[i]) {
3526 pdev->broken_intx_masking = 1;
3532 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3533 * support so shouldn't be checked further
3535 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3538 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3539 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3542 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3543 if (pci_enable_device_mem(pdev)) {
3544 pci_warn(pdev, "Can't enable device memory\n");
3548 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3550 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3554 /* Reading from resource space should be 32b aligned */
3555 fw_maj_min = ioread32be(fw_ver);
3556 fw_sub_min = ioread32be(fw_ver + 1);
3557 fw_major = fw_maj_min & 0xffff;
3558 fw_minor = fw_maj_min >> 16;
3559 fw_subminor = fw_sub_min & 0xffff;
3560 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3561 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3562 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3563 fw_major, fw_minor, fw_subminor, pdev->device ==
3564 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3565 pdev->broken_intx_masking = 1;
3571 pci_disable_device(pdev);
3573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3574 mellanox_check_broken_intx_masking);
3576 static void quirk_no_bus_reset(struct pci_dev *dev)
3578 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3582 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3583 * prevented for those affected devices.
3585 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3587 if ((dev->device & 0xffc0) == 0x2340)
3588 quirk_no_bus_reset(dev);
3590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3591 quirk_nvidia_no_bus_reset);
3594 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3595 * The device will throw a Link Down error on AER-capable systems and
3596 * regardless of AER, config space of the device is never accessible again
3597 * and typically causes the system to hang or reset when access is attempted.
3598 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3608 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3609 * reset when used with certain child devices. After the reset, config
3610 * accesses to the child may fail.
3612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3615 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3616 * automatically disables LTSSM when Secondary Bus Reset is received and
3617 * the device stops working. Prevent bus reset for these devices. With
3618 * this change, the device can be assigned to VMs with VFIO, but it will
3619 * leak state between VMs. Reference
3620 * https://e2e.ti.com/support/processors/f/791/t/954382
3622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3624 static void quirk_no_pm_reset(struct pci_dev *dev)
3627 * We can't do a bus reset on root bus devices, but an ineffective
3628 * PM reset may be better than nothing.
3630 if (!pci_is_root_bus(dev->bus))
3631 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3635 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3636 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3637 * to have no effect on the device: it retains the framebuffer contents and
3638 * monitor sync. Advertising this support makes other layers, like VFIO,
3639 * assume pci_reset_function() is viable for this device. Mark it as
3640 * unavailable to skip it when testing reset methods.
3642 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3643 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3646 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset
3647 * (i.e., they advertise NoSoftRst-). However, this transition does not have
3648 * any effect on the device: It continues to be operational and network ports
3649 * remain up. Advertising this support makes it seem as if a PM reset is viable
3650 * for these devices. Mark it as unavailable to skip it when testing reset
3653 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset);
3654 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset);
3655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset);
3656 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset);
3659 * Thunderbolt controllers with broken MSI hotplug signaling:
3660 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3661 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3663 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3665 if (pdev->is_hotplug_bridge &&
3666 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3667 pdev->revision <= 1))
3670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3671 quirk_thunderbolt_hotplug_msi);
3672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3673 quirk_thunderbolt_hotplug_msi);
3674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3675 quirk_thunderbolt_hotplug_msi);
3676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3677 quirk_thunderbolt_hotplug_msi);
3678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3679 quirk_thunderbolt_hotplug_msi);
3683 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3685 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3686 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3687 * be present after resume if a device was plugged in before suspend.
3689 * The Thunderbolt controller consists of a PCIe switch with downstream
3690 * bridges leading to the NHI and to the tunnel PCI bridges.
3692 * This quirk cuts power to the whole chip. Therefore we have to apply it
3693 * during suspend_noirq of the upstream bridge.
3695 * Power is automagically restored before resume. No action is needed.
3697 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3699 acpi_handle bridge, SXIO, SXFP, SXLV;
3701 if (!x86_apple_machine)
3703 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3707 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3708 * We don't know how to turn it back on again, but firmware does,
3709 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3712 if (!pm_suspend_via_firmware())
3715 bridge = ACPI_HANDLE(&dev->dev);
3720 * SXIO and SXLV are present only on machines requiring this quirk.
3721 * Thunderbolt bridges in external devices might have the same
3722 * device ID as those on the host, but they will not have the
3723 * associated ACPI methods. This implicitly checks that we are at
3726 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3727 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3728 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3730 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3732 /* magic sequence */
3733 acpi_execute_simple_method(SXIO, NULL, 1);
3734 acpi_execute_simple_method(SXFP, NULL, 0);
3736 acpi_execute_simple_method(SXLV, NULL, 0);
3737 acpi_execute_simple_method(SXIO, NULL, 0);
3738 acpi_execute_simple_method(SXLV, NULL, 0);
3740 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3741 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3742 quirk_apple_poweroff_thunderbolt);
3746 * Following are device-specific reset methods which can be used to
3747 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3750 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3753 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3755 * The 82599 supports FLR on VFs, but FLR support is reported only
3756 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3757 * Thus we must call pcie_flr() directly without first checking if it is
3765 #define SOUTH_CHICKEN2 0xc2004
3766 #define PCH_PP_STATUS 0xc7200
3767 #define PCH_PP_CONTROL 0xc7204
3768 #define MSG_CTL 0x45010
3769 #define NSDE_PWR_STATE 0xd0100
3770 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3772 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3774 void __iomem *mmio_base;
3775 unsigned long timeout;
3781 mmio_base = pci_iomap(dev, 0, 0);
3785 iowrite32(0x00000002, mmio_base + MSG_CTL);
3788 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3789 * driver loaded sets the right bits. However, this's a reset and
3790 * the bits have been set by i915 previously, so we clobber
3791 * SOUTH_CHICKEN2 register directly here.
3793 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3795 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3796 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3798 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3800 val = ioread32(mmio_base + PCH_PP_STATUS);
3801 if ((val & 0xb0000000) == 0)
3802 goto reset_complete;
3804 } while (time_before(jiffies, timeout));
3805 pci_warn(dev, "timeout during reset\n");
3808 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3810 pci_iounmap(dev, mmio_base);
3814 /* Device-specific reset method for Chelsio T4-based adapters */
3815 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3821 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3822 * that we have no device-specific reset method.
3824 if ((dev->device & 0xf000) != 0x4000)
3828 * If this is the "probe" phase, return 0 indicating that we can
3829 * reset this device.
3835 * T4 can wedge if there are DMAs in flight within the chip and Bus
3836 * Master has been disabled. We need to have it on till the Function
3837 * Level Reset completes. (BUS_MASTER is disabled in
3838 * pci_reset_function()).
3840 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3841 pci_write_config_word(dev, PCI_COMMAND,
3842 old_command | PCI_COMMAND_MASTER);
3845 * Perform the actual device function reset, saving and restoring
3846 * configuration information around the reset.
3848 pci_save_state(dev);
3851 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3852 * are disabled when an MSI-X interrupt message needs to be delivered.
3853 * So we briefly re-enable MSI-X interrupts for the duration of the
3854 * FLR. The pci_restore_state() below will restore the original
3857 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3858 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3859 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3861 PCI_MSIX_FLAGS_ENABLE |
3862 PCI_MSIX_FLAGS_MASKALL);
3867 * Restore the configuration information (BAR values, etc.) including
3868 * the original PCI Configuration Space Command word, and return
3871 pci_restore_state(dev);
3872 pci_write_config_word(dev, PCI_COMMAND, old_command);
3876 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3877 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3878 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3881 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3882 * FLR where config space reads from the device return -1. We seem to be
3883 * able to avoid this condition if we disable the NVMe controller prior to
3884 * FLR. This quirk is generic for any NVMe class device requiring similar
3885 * assistance to quiesce the device prior to FLR.
3887 * NVMe specification: https://nvmexpress.org/resources/specifications/
3889 * Chapter 2: Required and optional PCI config registers
3890 * Chapter 3: NVMe control registers
3891 * Chapter 7.3: Reset behavior
3893 static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3899 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3900 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3906 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3910 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3911 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3913 cfg = readl(bar + NVME_REG_CC);
3915 /* Disable controller if enabled */
3916 if (cfg & NVME_CC_ENABLE) {
3917 u32 cap = readl(bar + NVME_REG_CAP);
3918 unsigned long timeout;
3921 * Per nvme_disable_ctrl() skip shutdown notification as it
3922 * could complete commands to the admin queue. We only intend
3923 * to quiesce the device before reset.
3925 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3927 writel(cfg, bar + NVME_REG_CC);
3930 * Some controllers require an additional delay here, see
3931 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3932 * supported by this quirk.
3935 /* Cap register provides max timeout in 500ms increments */
3936 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3939 u32 status = readl(bar + NVME_REG_CSTS);
3941 /* Ready status becomes zero on disable complete */
3942 if (!(status & NVME_CSTS_RDY))
3947 if (time_after(jiffies, timeout)) {
3948 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3954 pci_iounmap(dev, bar);
3962 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3963 * to change after NVMe enable if the driver starts interacting with the
3964 * device too soon after FLR. A 250ms delay after FLR has heuristically
3965 * proven to produce reliably working results for device assignment cases.
3967 static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3969 if (!pcie_has_flr(dev))
3982 #define PCI_DEVICE_ID_HINIC_VF 0x375E
3983 #define HINIC_VF_FLR_TYPE 0x1000
3984 #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
3985 #define HINIC_VF_OP 0xE80
3986 #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
3987 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
3989 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3990 static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe)
3992 unsigned long timeout;
3999 bar = pci_iomap(pdev, 0, 0);
4003 /* Get and check firmware capabilities */
4004 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4005 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4006 pci_iounmap(pdev, bar);
4010 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
4011 val = ioread32be(bar + HINIC_VF_OP);
4012 val = val | HINIC_VF_FLR_PROC_BIT;
4013 iowrite32be(val, bar + HINIC_VF_OP);
4018 * The device must recapture its Bus and Device Numbers after FLR
4019 * in order generate Completions. Issue a config write to let the
4020 * device capture this information.
4022 pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
4024 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
4025 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
4027 val = ioread32be(bar + HINIC_VF_OP);
4028 if (!(val & HINIC_VF_FLR_PROC_BIT))
4029 goto reset_complete;
4031 } while (time_before(jiffies, timeout));
4033 val = ioread32be(bar + HINIC_VF_OP);
4034 if (!(val & HINIC_VF_FLR_PROC_BIT))
4035 goto reset_complete;
4037 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
4040 pci_iounmap(pdev, bar);
4045 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4046 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4047 reset_intel_82599_sfp_virtfn },
4048 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4050 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4052 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4053 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4054 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4055 reset_chelsio_generic_dev },
4056 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4057 reset_hinic_vf_dev },
4062 * These device-specific reset methods are here rather than in a driver
4063 * because when a host assigns a device to a guest VM, the host may need
4064 * to reset the device but probably doesn't have a driver for it.
4066 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
4068 const struct pci_dev_reset_methods *i;
4070 for (i = pci_dev_reset_methods; i->reset; i++) {
4071 if ((i->vendor == dev->vendor ||
4072 i->vendor == (u16)PCI_ANY_ID) &&
4073 (i->device == dev->device ||
4074 i->device == (u16)PCI_ANY_ID))
4075 return i->reset(dev, probe);
4081 static void quirk_dma_func0_alias(struct pci_dev *dev)
4083 if (PCI_FUNC(dev->devfn) != 0)
4084 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4088 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4090 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4095 static void quirk_dma_func1_alias(struct pci_dev *dev)
4097 if (PCI_FUNC(dev->devfn) != 1)
4098 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4102 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4103 * SKUs function 1 is present and is a legacy IDE controller, in other
4104 * SKUs this function is not present, making this a ghost requester.
4105 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4108 quirk_dma_func1_alias);
4109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4110 quirk_dma_func1_alias);
4111 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4113 quirk_dma_func1_alias);
4114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4115 quirk_dma_func1_alias);
4116 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4118 quirk_dma_func1_alias);
4119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4120 quirk_dma_func1_alias);
4121 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4123 quirk_dma_func1_alias);
4124 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4126 quirk_dma_func1_alias);
4127 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4129 quirk_dma_func1_alias);
4130 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4132 quirk_dma_func1_alias);
4133 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4135 quirk_dma_func1_alias);
4136 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4138 quirk_dma_func1_alias);
4139 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4141 quirk_dma_func1_alias);
4142 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4144 quirk_dma_func1_alias);
4145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4146 quirk_dma_func1_alias);
4147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4148 quirk_dma_func1_alias);
4149 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4150 quirk_dma_func1_alias);
4151 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4153 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4154 quirk_dma_func1_alias);
4155 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4156 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4157 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4158 quirk_dma_func1_alias);
4161 * Some devices DMA with the wrong devfn, not just the wrong function.
4162 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4163 * the alias is "fixed" and independent of the device devfn.
4165 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4166 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4167 * single device on the secondary bus. In reality, the single exposed
4168 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4169 * that provides a bridge to the internal bus of the I/O processor. The
4170 * controller supports private devices, which can be hidden from PCI config
4171 * space. In the case of the Adaptec 3405, a private device at 01.0
4172 * appears to be the DMA engine, which therefore needs to become a DMA
4173 * alias for the device.
4175 static const struct pci_device_id fixed_dma_alias_tbl[] = {
4176 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4177 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4178 .driver_data = PCI_DEVFN(1, 0) },
4179 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4180 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4181 .driver_data = PCI_DEVFN(1, 0) },
4185 static void quirk_fixed_dma_alias(struct pci_dev *dev)
4187 const struct pci_device_id *id;
4189 id = pci_match_id(fixed_dma_alias_tbl, dev);
4191 pci_add_dma_alias(dev, id->driver_data, 1);
4193 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4196 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4197 * using the wrong DMA alias for the device. Some of these devices can be
4198 * used as either forward or reverse bridges, so we need to test whether the
4199 * device is operating in the correct mode. We could probably apply this
4200 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4201 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4202 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4204 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4206 if (!pci_is_root_bus(pdev->bus) &&
4207 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4208 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4209 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4210 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4212 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4214 quirk_use_pcie_bridge_dma_alias);
4215 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4216 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4217 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4218 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4219 /* ITE 8893 has the same problem as the 8892 */
4220 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4221 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4222 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4225 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4226 * be added as aliases to the DMA device in order to allow buffer access
4227 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4228 * programmed in the EEPROM.
4230 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4232 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4233 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4234 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4240 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4241 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4243 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4244 * when IOMMU is enabled. These aliases allow computational unit access to
4245 * host memory. These aliases mark the whole VCA device as one IOMMU
4248 * All possible slot numbers (0x20) are used, since we are unable to tell
4249 * what slot is used on other side. This quirk is intended for both host
4250 * and computational unit sides. The VCA devices have up to five functions
4251 * (four for DMA channels and one additional).
4253 static void quirk_pex_vca_alias(struct pci_dev *pdev)
4255 const unsigned int num_pci_slots = 0x20;
4258 for (slot = 0; slot < num_pci_slots; slot++)
4259 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4269 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4270 * associated not at the root bus, but at a bridge below. This quirk avoids
4271 * generating invalid DMA aliases.
4273 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4275 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4278 quirk_bridge_cavm_thrx2_pcie_root);
4279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4280 quirk_bridge_cavm_thrx2_pcie_root);
4283 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4284 * class code. Fix it.
4286 static void quirk_tw686x_class(struct pci_dev *pdev)
4288 u32 class = pdev->class;
4290 /* Use "Multimedia controller" class */
4291 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4292 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4293 class, pdev->class);
4295 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4296 quirk_tw686x_class);
4297 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4298 quirk_tw686x_class);
4299 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4300 quirk_tw686x_class);
4301 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4302 quirk_tw686x_class);
4305 * Some devices have problems with Transaction Layer Packets with the Relaxed
4306 * Ordering Attribute set. Such devices should mark themselves and other
4307 * device drivers should check before sending TLPs with RO set.
4309 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4311 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4312 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4316 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4317 * Complex have a Flow Control Credit issue which can cause performance
4318 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4320 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4321 quirk_relaxedordering_disable);
4322 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4323 quirk_relaxedordering_disable);
4324 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4325 quirk_relaxedordering_disable);
4326 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4327 quirk_relaxedordering_disable);
4328 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4329 quirk_relaxedordering_disable);
4330 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4331 quirk_relaxedordering_disable);
4332 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4333 quirk_relaxedordering_disable);
4334 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4335 quirk_relaxedordering_disable);
4336 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4337 quirk_relaxedordering_disable);
4338 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4339 quirk_relaxedordering_disable);
4340 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4341 quirk_relaxedordering_disable);
4342 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4343 quirk_relaxedordering_disable);
4344 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4345 quirk_relaxedordering_disable);
4346 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4347 quirk_relaxedordering_disable);
4348 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4349 quirk_relaxedordering_disable);
4350 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4351 quirk_relaxedordering_disable);
4352 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4353 quirk_relaxedordering_disable);
4354 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4355 quirk_relaxedordering_disable);
4356 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4357 quirk_relaxedordering_disable);
4358 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4359 quirk_relaxedordering_disable);
4360 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4361 quirk_relaxedordering_disable);
4362 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4363 quirk_relaxedordering_disable);
4364 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4365 quirk_relaxedordering_disable);
4366 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4367 quirk_relaxedordering_disable);
4368 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4369 quirk_relaxedordering_disable);
4370 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4371 quirk_relaxedordering_disable);
4372 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4373 quirk_relaxedordering_disable);
4374 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4375 quirk_relaxedordering_disable);
4378 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4379 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4380 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4381 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4382 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4383 * November 10, 2010). As a result, on this platform we can't use Relaxed
4384 * Ordering for Upstream TLPs.
4386 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4387 quirk_relaxedordering_disable);
4388 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4389 quirk_relaxedordering_disable);
4390 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4391 quirk_relaxedordering_disable);
4394 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4395 * values for the Attribute as were supplied in the header of the
4396 * corresponding Request, except as explicitly allowed when IDO is used."
4398 * If a non-compliant device generates a completion with a different
4399 * attribute than the request, the receiver may accept it (which itself
4400 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4401 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4402 * device access timeout.
4404 * If the non-compliant device generates completions with zero attributes
4405 * (instead of copying the attributes from the request), we can work around
4406 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4407 * upstream devices so they always generate requests with zero attributes.
4409 * This affects other devices under the same Root Port, but since these
4410 * attributes are performance hints, there should be no functional problem.
4412 * Note that Configuration Space accesses are never supposed to have TLP
4413 * Attributes, so we're safe waiting till after any Configuration Space
4414 * accesses to do the Root Port fixup.
4416 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4418 struct pci_dev *root_port = pcie_find_root_port(pdev);
4421 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4425 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4426 dev_name(&pdev->dev));
4427 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4428 PCI_EXP_DEVCTL_RELAX_EN |
4429 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4433 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4434 * Completion it generates.
4436 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4439 * This mask/compare operation selects for Physical Function 4 on a
4440 * T5. We only need to fix up the Root Port once for any of the
4441 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4442 * 0x54xx so we use that one.
4444 if ((pdev->device & 0xff00) == 0x5400)
4445 quirk_disable_root_port_attributes(pdev);
4447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4448 quirk_chelsio_T5_disable_root_port_attributes);
4451 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4453 * @acs_ctrl_req: Bitmask of desired ACS controls
4454 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4455 * the hardware design
4457 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4458 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4459 * caller desires. Return 0 otherwise.
4461 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4463 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4469 * AMD has indicated that the devices below do not support peer-to-peer
4470 * in any system where they are found in the southbridge with an AMD
4471 * IOMMU in the system. Multifunction devices that do not support
4472 * peer-to-peer between functions can claim to support a subset of ACS.
4473 * Such devices effectively enable request redirect (RR) and completion
4474 * redirect (CR) since all transactions are redirected to the upstream
4477 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4478 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4479 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4481 * 1002:4385 SBx00 SMBus Controller
4482 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4483 * 1002:4383 SBx00 Azalia (Intel HDA)
4484 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4485 * 1002:4384 SBx00 PCI to PCI Bridge
4486 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4488 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4490 * 1022:780f [AMD] FCH PCI Bridge
4491 * 1022:7809 [AMD] FCH USB OHCI Controller
4493 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4496 struct acpi_table_header *header = NULL;
4499 /* Targeting multifunction devices on the SB (appears on root bus) */
4500 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4503 /* The IVRS table describes the AMD IOMMU */
4504 status = acpi_get_table("IVRS", 0, &header);
4505 if (ACPI_FAILURE(status))
4508 acpi_put_table(header);
4510 /* Filter out flags not applicable to multifunction */
4511 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4513 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4519 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4521 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4524 switch (dev->device) {
4526 * Effectively selects all downstream ports for whole ThunderX1
4527 * (which represents 8 SoCs).
4529 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4530 case 0xaf84: /* ThunderX2 */
4531 case 0xb884: /* ThunderX3 */
4538 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4540 if (!pci_quirk_cavium_acs_match(dev))
4544 * Cavium Root Ports don't advertise an ACS capability. However,
4545 * the RTL internally implements similar protection as if ACS had
4546 * Source Validation, Request Redirection, Completion Redirection,
4547 * and Upstream Forwarding features enabled. Assert that the
4548 * hardware implements and enables equivalent ACS functionality for
4551 return pci_acs_ctrl_enabled(acs_flags,
4552 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4555 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4558 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4559 * transactions with others, allowing masking out these bits as if they
4560 * were unimplemented in the ACS capability.
4562 return pci_acs_ctrl_enabled(acs_flags,
4563 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4567 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4568 * But the implementation could block peer-to-peer transactions between them
4569 * and provide ACS-like functionality.
4571 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4573 if (!pci_is_pcie(dev) ||
4574 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4575 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4579 * Future Zhaoxin Root Ports and Switch Downstream Ports will
4580 * implement ACS capability in accordance with the PCIe Spec.
4582 switch (dev->device) {
4583 case 0x0710 ... 0x071e:
4585 case 0x0723 ... 0x0752:
4586 return pci_acs_ctrl_enabled(acs_flags,
4587 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4594 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4595 * transactions and validate bus numbers in requests, but do not provide an
4596 * actual PCIe ACS capability. This is the list of device IDs known to fall
4597 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4599 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4601 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4602 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4603 /* Cougarpoint PCH */
4604 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4605 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4606 /* Pantherpoint PCH */
4607 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4608 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4609 /* Lynxpoint-H PCH */
4610 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4611 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4612 /* Lynxpoint-LP PCH */
4613 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4614 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4616 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4617 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4618 /* Patsburg (X79) PCH */
4619 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4620 /* Wellsburg (X99) PCH */
4621 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4622 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4623 /* Lynx Point (9 series) PCH */
4624 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4627 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4631 /* Filter out a few obvious non-matches first */
4632 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4635 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4636 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4642 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4644 if (!pci_quirk_intel_pch_acs_match(dev))
4647 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4648 return pci_acs_ctrl_enabled(acs_flags,
4649 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4651 return pci_acs_ctrl_enabled(acs_flags, 0);
4655 * These QCOM Root Ports do provide ACS-like features to disable peer
4656 * transactions and validate bus numbers in requests, but do not provide an
4657 * actual PCIe ACS capability. Hardware supports source validation but it
4658 * will report the issue as Completer Abort instead of ACS Violation.
4659 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4660 * Complex with unique segment numbers. It is not possible for one Root
4661 * Port to pass traffic to another Root Port. All PCIe transactions are
4662 * terminated inside the Root Port.
4664 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4666 return pci_acs_ctrl_enabled(acs_flags,
4667 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4671 * Each of these NXP Root Ports is in a Root Complex with a unique segment
4672 * number and does provide isolation features to disable peer transactions
4673 * and validate bus numbers in requests, but does not provide an ACS
4676 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4678 return pci_acs_ctrl_enabled(acs_flags,
4679 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4682 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4684 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4688 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4689 * but do include ACS-like functionality. The hardware doesn't support
4690 * peer-to-peer transactions via the root port and each has a unique
4693 * Additionally, the root ports cannot send traffic to each other.
4695 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4697 return acs_flags ? 0 : 1;
4701 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4702 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4703 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4704 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4705 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4706 * control register is at offset 8 instead of 6 and we should probably use
4707 * dword accesses to them. This applies to the following PCI Device IDs, as
4708 * found in volume 1 of the datasheet[2]:
4710 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4711 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4713 * N.B. This doesn't fix what lspci shows.
4715 * The 100 series chipset specification update includes this as errata #23[3].
4717 * The 200 series chipset (Union Point) has the same bug according to the
4718 * specification update (Intel 200 Series Chipset Family Platform Controller
4719 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4720 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4723 * 0xa290-0xa29f PCI Express Root port #{0-16}
4724 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4726 * Mobile chipsets are also affected, 7th & 8th Generation
4727 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4728 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4729 * Processor Family I/O for U Quad Core Platforms Specification Update,
4730 * August 2017, Revision 002, Document#: 334660-002)[6]
4731 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4732 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4733 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4735 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4737 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4738 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4739 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4740 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4741 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4742 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4743 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4745 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4747 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4750 switch (dev->device) {
4751 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4752 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4753 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4760 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4762 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4767 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4774 /* see pci_acs_flags_enabled() */
4775 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4776 acs_flags &= (cap | PCI_ACS_EC);
4778 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4780 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4783 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4786 * SV, TB, and UF are not relevant to multifunction endpoints.
4788 * Multifunction devices are only required to implement RR, CR, and DT
4789 * in their ACS capability if they support peer-to-peer transactions.
4790 * Devices matching this quirk have been verified by the vendor to not
4791 * perform peer-to-peer with other functions, allowing us to mask out
4792 * these bits as if they were unimplemented in the ACS capability.
4794 return pci_acs_ctrl_enabled(acs_flags,
4795 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4796 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4799 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4802 * Intel RCiEP's are required to allow p2p only on translated
4803 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4804 * "Root-Complex Peer to Peer Considerations".
4806 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4809 return pci_acs_ctrl_enabled(acs_flags,
4810 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4813 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4816 * iProc PAXB Root Ports don't advertise an ACS capability, but
4817 * they do not allow peer-to-peer transactions between Root Ports.
4818 * Allow each Root Port to be in a separate IOMMU group by masking
4821 return pci_acs_ctrl_enabled(acs_flags,
4822 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4826 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4827 * devices, peer-to-peer transactions are not be used between the functions.
4828 * So add an ACS quirk for below devices to isolate functions.
4829 * SFxxx 1G NICs(em).
4830 * RP1000/RP2000 10G NICs(sp).
4832 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
4834 switch (dev->device) {
4835 case 0x0100 ... 0x010F:
4838 return pci_acs_ctrl_enabled(acs_flags,
4839 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4845 static const struct pci_dev_acs_enabled {
4848 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4849 } pci_dev_acs_enabled[] = {
4850 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4851 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4852 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4853 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4854 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4855 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4856 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4857 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4858 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4859 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4860 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4861 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4862 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4863 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4864 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4865 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4866 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4867 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4868 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4869 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4870 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4871 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4872 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4873 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4874 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4875 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4876 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4877 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4878 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4879 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4880 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4882 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4883 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4884 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4885 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4886 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4887 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4888 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4890 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4891 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4892 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4893 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4894 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4895 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4896 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4897 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4899 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4900 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4901 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4903 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4904 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4905 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4906 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4907 /* 82571 (Quads omitted due to non-ACS switch) */
4908 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4909 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4910 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4911 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4913 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4914 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4915 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4916 /* QCOM QDF2xxx root ports */
4917 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4918 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4919 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4920 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4921 /* Intel PCH root ports */
4922 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4923 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4924 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4925 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4926 /* Cavium ThunderX */
4927 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4928 /* Cavium multi-function devices */
4929 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4930 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4931 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4933 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4934 /* Ampere Computing */
4935 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4936 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4937 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4938 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4939 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4940 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4941 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4942 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4943 /* Broadcom multi-function device */
4944 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4945 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
4946 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
4947 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
4948 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4949 /* Amazon Annapurna Labs */
4950 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4951 /* Zhaoxin multi-function devices */
4952 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4953 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4954 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4955 /* NXP root ports, xx=16, 12, or 08 cores */
4956 /* LX2xx0A : without security features + CAN-FD */
4957 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
4958 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
4959 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
4960 /* LX2xx0C : security features + CAN-FD */
4961 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
4962 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
4963 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
4964 /* LX2xx0E : security features + CAN */
4965 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
4966 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
4967 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
4968 /* LX2xx0N : without security features + CAN */
4969 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
4970 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
4971 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
4972 /* LX2xx2A : without security features + CAN-FD */
4973 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
4974 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
4975 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
4976 /* LX2xx2C : security features + CAN-FD */
4977 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
4978 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
4979 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
4980 /* LX2xx2E : security features + CAN */
4981 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
4982 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
4983 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
4984 /* LX2xx2N : without security features + CAN */
4985 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
4986 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
4987 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
4988 /* Zhaoxin Root/Downstream Ports */
4989 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
4991 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
4996 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4998 * @acs_flags: Bitmask of desired ACS controls
5001 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5002 * device provides the desired controls
5003 * 0: Device does not provide all the desired controls
5004 * >0: Device provides all the controls in @acs_flags
5006 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
5008 const struct pci_dev_acs_enabled *i;
5012 * Allow devices that do not expose standard PCIe ACS capabilities
5013 * or control to indicate their support here. Multi-function express
5014 * devices which do not allow internal peer-to-peer between functions,
5015 * but do not implement PCIe ACS may wish to return true here.
5017 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
5018 if ((i->vendor == dev->vendor ||
5019 i->vendor == (u16)PCI_ANY_ID) &&
5020 (i->device == dev->device ||
5021 i->device == (u16)PCI_ANY_ID)) {
5022 ret = i->acs_enabled(dev, acs_flags);
5031 /* Config space offset of Root Complex Base Address register */
5032 #define INTEL_LPC_RCBA_REG 0xf0
5033 /* 31:14 RCBA address */
5034 #define INTEL_LPC_RCBA_MASK 0xffffc000
5036 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5038 /* Backbone Scratch Pad Register */
5039 #define INTEL_BSPR_REG 0x1104
5040 /* Backbone Peer Non-Posted Disable */
5041 #define INTEL_BSPR_REG_BPNPD (1 << 8)
5042 /* Backbone Peer Posted Disable */
5043 #define INTEL_BSPR_REG_BPPD (1 << 9)
5045 /* Upstream Peer Decode Configuration Register */
5046 #define INTEL_UPDCR_REG 0x1014
5047 /* 5:0 Peer Decode Enable bits */
5048 #define INTEL_UPDCR_REG_MASK 0x3f
5050 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
5052 u32 rcba, bspr, updcr;
5053 void __iomem *rcba_mem;
5056 * Read the RCBA register from the LPC (D31:F0). PCH root ports
5057 * are D28:F* and therefore get probed before LPC, thus we can't
5058 * use pci_get_slot()/pci_read_config_dword() here.
5060 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
5061 INTEL_LPC_RCBA_REG, &rcba);
5062 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
5065 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
5066 PAGE_ALIGN(INTEL_UPDCR_REG));
5071 * The BSPR can disallow peer cycles, but it's set by soft strap and
5072 * therefore read-only. If both posted and non-posted peer cycles are
5073 * disallowed, we're ok. If either are allowed, then we need to use
5074 * the UPDCR to disable peer decodes for each port. This provides the
5075 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5077 bspr = readl(rcba_mem + INTEL_BSPR_REG);
5078 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5079 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5080 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
5081 if (updcr & INTEL_UPDCR_REG_MASK) {
5082 pci_info(dev, "Disabling UPDCR peer decodes\n");
5083 updcr &= ~INTEL_UPDCR_REG_MASK;
5084 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
5092 /* Miscellaneous Port Configuration register */
5093 #define INTEL_MPC_REG 0xd8
5094 /* MPC: Invalid Receive Bus Number Check Enable */
5095 #define INTEL_MPC_REG_IRBNCE (1 << 26)
5097 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5102 * When enabled, the IRBNCE bit of the MPC register enables the
5103 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5104 * ensures that requester IDs fall within the bus number range
5105 * of the bridge. Enable if not already.
5107 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
5108 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5109 pci_info(dev, "Enabling MPC IRBNCE\n");
5110 mpc |= INTEL_MPC_REG_IRBNCE;
5111 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
5116 * Currently this quirk does the equivalent of
5117 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5119 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5120 * if dev->external_facing || dev->untrusted
5122 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5124 if (!pci_quirk_intel_pch_acs_match(dev))
5127 if (pci_quirk_enable_intel_lpc_acs(dev)) {
5128 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5132 pci_quirk_enable_intel_rp_mpc_acs(dev);
5134 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5136 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5141 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5146 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5153 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5154 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5156 ctrl |= (cap & PCI_ACS_SV);
5157 ctrl |= (cap & PCI_ACS_RR);
5158 ctrl |= (cap & PCI_ACS_CR);
5159 ctrl |= (cap & PCI_ACS_UF);
5161 if (dev->external_facing || dev->untrusted)
5162 ctrl |= (cap & PCI_ACS_TB);
5164 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5166 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5171 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5176 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5183 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5184 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5186 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5188 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5190 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5195 static const struct pci_dev_acs_ops {
5198 int (*enable_acs)(struct pci_dev *dev);
5199 int (*disable_acs_redir)(struct pci_dev *dev);
5200 } pci_dev_acs_ops[] = {
5201 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5202 .enable_acs = pci_quirk_enable_intel_pch_acs,
5204 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5205 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5206 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5210 int pci_dev_specific_enable_acs(struct pci_dev *dev)
5212 const struct pci_dev_acs_ops *p;
5215 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5216 p = &pci_dev_acs_ops[i];
5217 if ((p->vendor == dev->vendor ||
5218 p->vendor == (u16)PCI_ANY_ID) &&
5219 (p->device == dev->device ||
5220 p->device == (u16)PCI_ANY_ID) &&
5222 ret = p->enable_acs(dev);
5231 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5233 const struct pci_dev_acs_ops *p;
5236 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5237 p = &pci_dev_acs_ops[i];
5238 if ((p->vendor == dev->vendor ||
5239 p->vendor == (u16)PCI_ANY_ID) &&
5240 (p->device == dev->device ||
5241 p->device == (u16)PCI_ANY_ID) &&
5242 p->disable_acs_redir) {
5243 ret = p->disable_acs_redir(dev);
5253 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5254 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5255 * Next Capability pointer in the MSI Capability Structure should point to
5256 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5259 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5264 struct pci_cap_saved_state *state;
5266 /* Bail if the hardware bug is fixed */
5267 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5270 /* Bail if MSI Capability Structure is not found for some reason */
5271 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5276 * Bail if Next Capability pointer in the MSI Capability Structure
5277 * is not the expected incorrect 0x00.
5279 pci_read_config_byte(pdev, pos + 1, &next_cap);
5284 * PCIe Capability Structure is expected to be at 0x50 and should
5285 * terminate the list (Next Capability pointer is 0x00). Verify
5286 * Capability Id and Next Capability pointer is as expected.
5287 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5288 * to correctly set kernel data structures which have already been
5289 * set incorrectly due to the hardware bug.
5292 pci_read_config_word(pdev, pos, ®16);
5293 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5295 #ifndef PCI_EXP_SAVE_REGS
5296 #define PCI_EXP_SAVE_REGS 7
5298 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5300 pdev->pcie_cap = pos;
5301 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5302 pdev->pcie_flags_reg = reg16;
5303 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5304 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5306 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5307 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5308 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5309 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5311 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5315 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5319 state->cap.cap_nr = PCI_CAP_ID_EXP;
5320 state->cap.cap_extended = 0;
5321 state->cap.size = size;
5322 cap = (u16 *)&state->cap.data[0];
5323 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5324 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5325 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5326 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5327 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5328 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5329 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5330 hlist_add_head(&state->next, &pdev->saved_cap_space);
5333 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5336 * FLR may cause the following to devices to hang:
5338 * AMD Starship/Matisse HD Audio Controller 0x1487
5339 * AMD Starship USB 3.0 Host Controller 0x148c
5340 * AMD Matisse USB 3.0 Host Controller 0x149c
5341 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5342 * Intel 82579V Gigabit Ethernet Controller 0x1503
5345 static void quirk_no_flr(struct pci_dev *dev)
5347 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5349 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5350 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5351 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5352 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5353 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5354 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5356 static void quirk_no_ext_tags(struct pci_dev *pdev)
5358 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5363 bridge->no_ext_tags = 1;
5364 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5366 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5368 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags);
5369 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5370 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5371 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5372 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5373 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5374 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5375 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5377 #ifdef CONFIG_PCI_ATS
5378 static void quirk_no_ats(struct pci_dev *pdev)
5380 pci_info(pdev, "disabling ATS\n");
5385 * Some devices require additional driver setup to enable ATS. Don't use
5386 * ATS for those devices as ATS will be enabled before the driver has had a
5387 * chance to load and configure the device.
5389 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5391 if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
5392 (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
5393 (pdev->device == 0x7341 && pdev->revision != 0x00))
5399 /* AMD Stoney platform GPU */
5400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5401 /* AMD Iceland dGPU */
5402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5403 /* AMD Navi10 dGPU */
5404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5405 /* AMD Navi14 dGPU */
5406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5410 * Intel IPU E2000 revisions before C0 implement incorrect endianness
5411 * in ATS Invalidate Request message body. Disable ATS for those devices.
5413 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)
5415 if (pdev->revision < 0x20)
5418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
5419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
5420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
5421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
5422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
5423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
5424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
5425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
5426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
5427 #endif /* CONFIG_PCI_ATS */
5429 /* Freescale PCIe doesn't support MSI in RC mode */
5430 static void quirk_fsl_no_msi(struct pci_dev *pdev)
5432 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5438 * Although not allowed by the spec, some multi-function devices have
5439 * dependencies of one function (consumer) on another (supplier). For the
5440 * consumer to work in D0, the supplier must also be in D0. Create a
5441 * device link from the consumer to the supplier to enforce this
5442 * dependency. Runtime PM is allowed by default on the consumer to prevent
5443 * it from permanently keeping the supplier awake.
5445 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5446 unsigned int supplier, unsigned int class,
5447 unsigned int class_shift)
5449 struct pci_dev *supplier_pdev;
5451 if (PCI_FUNC(pdev->devfn) != consumer)
5454 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5456 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5457 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5458 pci_dev_put(supplier_pdev);
5462 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5463 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5464 pci_info(pdev, "D0 power state depends on %s\n",
5465 pci_name(supplier_pdev));
5467 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5468 pci_name(supplier_pdev));
5470 pm_runtime_allow(&pdev->dev);
5471 pci_dev_put(supplier_pdev);
5475 * Create device link for GPUs with integrated HDA controller for streaming
5476 * audio to attached displays.
5478 static void quirk_gpu_hda(struct pci_dev *hda)
5480 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5482 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5483 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5484 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5485 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5486 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5487 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5490 * Create device link for GPUs with integrated USB xHCI Host
5491 * controller to VGA.
5493 static void quirk_gpu_usb(struct pci_dev *usb)
5495 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5497 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5498 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5499 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5500 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5503 * Create device link for GPUs with integrated Type-C UCSI controller
5504 * to VGA. Currently there is no class code defined for UCSI device over PCI
5505 * so using UNKNOWN class for now and it will be updated when UCSI
5506 * over PCI gets a class code.
5508 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5509 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5511 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5513 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5514 PCI_CLASS_SERIAL_UNKNOWN, 8,
5515 quirk_gpu_usb_typec_ucsi);
5516 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5517 PCI_CLASS_SERIAL_UNKNOWN, 8,
5518 quirk_gpu_usb_typec_ucsi);
5521 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5522 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5524 static void quirk_nvidia_hda(struct pci_dev *gpu)
5529 /* There was no integrated HDA controller before MCP89 */
5530 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5533 /* Bit 25 at offset 0x488 enables the HDA controller */
5534 pci_read_config_dword(gpu, 0x488, &val);
5538 pci_info(gpu, "Enabling HDA controller\n");
5539 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5541 /* The GPU becomes a multi-function device when the HDA is enabled */
5542 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5543 gpu->multifunction = !!(hdr_type & 0x80);
5545 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5546 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5547 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5548 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5551 * Some IDT switches incorrectly flag an ACS Source Validation error on
5552 * completions for config read requests even though PCIe r4.0, sec
5553 * 6.12.1.1, says that completions are never affected by ACS Source
5554 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5556 * Item #36 - Downstream port applies ACS Source Validation to Completions
5557 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5558 * completions are never affected by ACS Source Validation. However,
5559 * completions received by a downstream port of the PCIe switch from a
5560 * device that has not yet captured a PCIe bus number are incorrectly
5561 * dropped by ACS Source Validation by the switch downstream port.
5563 * The workaround suggested by IDT is to issue a config write to the
5564 * downstream device before issuing the first config read. This allows the
5565 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5566 * sec 2.2.9), thus avoiding the ACS error on the completion.
5568 * However, we don't know when the device is ready to accept the config
5569 * write, so we do config reads until we receive a non-Config Request Retry
5570 * Status, then do the config write.
5572 * To avoid hitting the erratum when doing the config reads, we disable ACS
5573 * SV around this process.
5575 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5580 struct pci_dev *bridge = bus->self;
5582 pos = bridge->acs_cap;
5584 /* Disable ACS SV before initial config reads */
5586 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5587 if (ctrl & PCI_ACS_SV)
5588 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5589 ctrl & ~PCI_ACS_SV);
5592 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5594 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5596 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5598 /* Re-enable ACS_SV if it was previously enabled */
5599 if (ctrl & PCI_ACS_SV)
5600 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5606 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5607 * NT endpoints via the internal switch fabric. These IDs replace the
5608 * originating requestor ID TLPs which access host memory on peer NTB
5609 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5610 * to permit access when the IOMMU is turned on.
5612 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5615 struct ntb_info_regs __iomem *mmio_ntb;
5616 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5621 if (pci_enable_device(pdev)) {
5622 pci_err(pdev, "Cannot enable Switchtec device\n");
5626 mmio = pci_iomap(pdev, 0, 0);
5628 pci_disable_device(pdev);
5629 pci_err(pdev, "Cannot iomap Switchtec device\n");
5633 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5635 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5636 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5638 partition = ioread8(&mmio_ntb->partition_id);
5640 partition_map = ioread32(&mmio_ntb->ep_map);
5641 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5642 partition_map &= ~(1ULL << partition);
5644 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5645 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5649 if (!(partition_map & (1ULL << pp)))
5652 pci_dbg(pdev, "Processing partition %d\n", pp);
5654 mmio_peer_ctrl = &mmio_ctrl[pp];
5656 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5658 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5662 if (table_sz > 512) {
5664 "Invalid Switchtec partition %d table_sz %d\n",
5669 for (te = 0; te < table_sz; te++) {
5673 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5674 devfn = (rid_entry >> 1) & 0xFF;
5676 "Aliasing Partition %d Proxy ID %02x.%d\n",
5677 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5678 pci_add_dma_alias(pdev, devfn, 1);
5682 pci_iounmap(pdev, mmio);
5683 pci_disable_device(pdev);
5685 #define SWITCHTEC_QUIRK(vid) \
5686 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5687 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5689 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5690 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5691 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5692 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5693 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5694 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5695 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5696 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5697 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5698 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5699 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5700 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5701 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5702 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5703 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5704 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5705 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5706 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5707 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5708 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5709 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5710 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5711 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5712 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5713 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5714 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5715 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5716 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5717 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5718 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5719 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5720 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5721 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5722 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5723 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5724 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5725 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5726 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5727 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5728 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5729 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5730 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5731 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5732 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5733 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5734 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5735 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5736 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5739 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5740 * These IDs are used to forward responses to the originator on the other
5741 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5742 * the IOMMU is turned on.
5744 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5746 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5747 /* PLX NTB may use all 256 devfns */
5748 pci_add_dma_alias(pdev, 0, 256);
5750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5751 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5754 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5755 * not always reset the secondary Nvidia GPU between reboots if the system
5756 * is configured to use Hybrid Graphics mode. This results in the GPU
5757 * being left in whatever state it was in during the *previous* boot, which
5758 * causes spurious interrupts from the GPU, which in turn causes us to
5759 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5760 * this also completely breaks nouveau.
5762 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5763 * clean state and fixes all these issues.
5765 * When the machine is configured in Dedicated display mode, the issue
5766 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5767 * mode, so we can detect that and avoid resetting it.
5769 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5774 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5775 pdev->subsystem_device != 0x222e ||
5779 if (pci_enable_device_mem(pdev))
5783 * Based on nvkm_device_ctor() in
5784 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5786 map = pci_iomap(pdev, 0, 0x23000);
5788 pci_err(pdev, "Can't map MMIO space\n");
5793 * Make sure the GPU looks like it's been POSTed before resetting
5796 if (ioread32(map + 0x2240c) & 0x2) {
5797 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5798 ret = pci_reset_bus(pdev);
5800 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5805 pci_disable_device(pdev);
5807 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5808 PCI_CLASS_DISPLAY_VGA, 8,
5809 quirk_reset_lenovo_thinkpad_p50_nvgpu);
5812 * Device [1b21:2142]
5813 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5815 static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5817 pci_info(dev, "PME# does not work under D0, disabling it\n");
5818 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5823 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5825 * These devices advertise PME# support in all power states but don't
5826 * reliably assert it.
5828 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5829 * says "The MSI Function is not implemented on this device" in chapters
5830 * 7.3.27, 7.3.29-7.3.31.
5832 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
5834 #ifdef CONFIG_PCI_MSI
5835 pci_info(dev, "MSI is not implemented on this device, disabling it\n");
5838 pci_info(dev, "PME# is unreliable, disabling it\n");
5839 dev->pme_support = 0;
5841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
5842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
5844 static void apex_pci_fixup_class(struct pci_dev *pdev)
5846 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5848 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5849 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
5851 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
5853 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
5855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
5857 static void rom_bar_overlap_defect(struct pci_dev *dev)
5859 pci_info(dev, "working around ROM BAR overlap defect\n");
5860 dev->rom_bar_overlap = 1;
5862 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
5863 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
5864 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
5865 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
5867 #ifdef CONFIG_PCIEASPM
5869 * Several Intel DG2 graphics devices advertise that they can only tolerate
5870 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1
5871 * from being enabled. But in fact these devices can tolerate unlimited
5872 * latency. Override their Device Capabilities value to allow ASPM L1 to
5875 static void aspm_l1_acceptable_latency(struct pci_dev *dev)
5877 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap);
5880 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7);
5881 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n",
5885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
5886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
5887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
5888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
5889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
5890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
5891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
5892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
5893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
5894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
5895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
5896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
5897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
5898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
5899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
5900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
5901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
5902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
5903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
5904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
5905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
5906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
5907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
5908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
5909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
5910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
5913 #ifdef CONFIG_PCIE_DPC
5915 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears
5916 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root
5919 static void dpc_log_size(struct pci_dev *dev)
5923 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
5927 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
5928 if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
5931 if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
5932 pci_info(dev, "Overriding RP PIO Log Size to 4\n");
5933 dev->dpc_rp_log_size = 4;
5936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
5937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
5938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
5939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
5940 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
5941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
5942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
5943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
5944 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
5945 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
5946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
5947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
5948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
5949 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
5950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
5951 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
5952 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size);
5953 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);