1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/ktime.h>
27 #include <linux/nvme.h>
28 #include <linux/platform_data/x86/apple.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/suspend.h>
31 #include <linux/switchtec.h>
32 #include <asm/dma.h> /* isa_dma_bridge_buggy */
35 static ktime_t fixup_debug_start(struct pci_dev *dev,
36 void (*fn)(struct pci_dev *dev))
39 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
44 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
45 void (*fn)(struct pci_dev *dev))
47 ktime_t delta, rettime;
48 unsigned long long duration;
50 rettime = ktime_get();
51 delta = ktime_sub(rettime, calltime);
52 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
53 if (initcall_debug || duration > 10000)
54 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
57 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
58 struct pci_fixup *end)
63 if ((f->class == (u32) (dev->class >> f->class_shift) ||
64 f->class == (u32) PCI_ANY_ID) &&
65 (f->vendor == dev->vendor ||
66 f->vendor == (u16) PCI_ANY_ID) &&
67 (f->device == dev->device ||
68 f->device == (u16) PCI_ANY_ID)) {
69 void (*hook)(struct pci_dev *dev);
70 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
71 hook = offset_to_ptr(&f->hook_offset);
75 calltime = fixup_debug_start(dev, hook);
77 fixup_debug_report(dev, calltime, hook);
81 extern struct pci_fixup __start_pci_fixups_early[];
82 extern struct pci_fixup __end_pci_fixups_early[];
83 extern struct pci_fixup __start_pci_fixups_header[];
84 extern struct pci_fixup __end_pci_fixups_header[];
85 extern struct pci_fixup __start_pci_fixups_final[];
86 extern struct pci_fixup __end_pci_fixups_final[];
87 extern struct pci_fixup __start_pci_fixups_enable[];
88 extern struct pci_fixup __end_pci_fixups_enable[];
89 extern struct pci_fixup __start_pci_fixups_resume[];
90 extern struct pci_fixup __end_pci_fixups_resume[];
91 extern struct pci_fixup __start_pci_fixups_resume_early[];
92 extern struct pci_fixup __end_pci_fixups_resume_early[];
93 extern struct pci_fixup __start_pci_fixups_suspend[];
94 extern struct pci_fixup __end_pci_fixups_suspend[];
95 extern struct pci_fixup __start_pci_fixups_suspend_late[];
96 extern struct pci_fixup __end_pci_fixups_suspend_late[];
98 static bool pci_apply_fixup_final_quirks;
100 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
102 struct pci_fixup *start, *end;
105 case pci_fixup_early:
106 start = __start_pci_fixups_early;
107 end = __end_pci_fixups_early;
110 case pci_fixup_header:
111 start = __start_pci_fixups_header;
112 end = __end_pci_fixups_header;
115 case pci_fixup_final:
116 if (!pci_apply_fixup_final_quirks)
118 start = __start_pci_fixups_final;
119 end = __end_pci_fixups_final;
122 case pci_fixup_enable:
123 start = __start_pci_fixups_enable;
124 end = __end_pci_fixups_enable;
127 case pci_fixup_resume:
128 start = __start_pci_fixups_resume;
129 end = __end_pci_fixups_resume;
132 case pci_fixup_resume_early:
133 start = __start_pci_fixups_resume_early;
134 end = __end_pci_fixups_resume_early;
137 case pci_fixup_suspend:
138 start = __start_pci_fixups_suspend;
139 end = __end_pci_fixups_suspend;
142 case pci_fixup_suspend_late:
143 start = __start_pci_fixups_suspend_late;
144 end = __end_pci_fixups_suspend_late;
148 /* stupid compiler warning, you would think with an enum... */
151 pci_do_fixups(dev, start, end);
153 EXPORT_SYMBOL(pci_fixup_device);
155 static int __init pci_apply_final_quirks(void)
157 struct pci_dev *dev = NULL;
161 if (pci_cache_line_size)
162 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
164 pci_apply_fixup_final_quirks = true;
165 for_each_pci_dev(dev) {
166 pci_fixup_device(pci_fixup_final, dev);
168 * If arch hasn't set it explicitly yet, use the CLS
169 * value shared by all PCI devices. If there's a
170 * mismatch, fall back to the default value.
172 if (!pci_cache_line_size) {
173 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
176 if (!tmp || cls == tmp)
179 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
181 pci_dfl_cache_line_size << 2);
182 pci_cache_line_size = pci_dfl_cache_line_size;
186 if (!pci_cache_line_size) {
187 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
188 pci_dfl_cache_line_size << 2);
189 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
194 fs_initcall_sync(pci_apply_final_quirks);
197 * Decoding should be disabled for a PCI device during BAR sizing to avoid
198 * conflict. But doing so may cause problems on host bridge and perhaps other
199 * key system devices. For devices that need to have mmio decoding always-on,
200 * we need to set the dev->mmio_always_on bit.
202 static void quirk_mmio_always_on(struct pci_dev *dev)
204 dev->mmio_always_on = 1;
206 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
207 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
210 * The Mellanox Tavor device gives false positive parity errors. Mark this
211 * device with a broken_parity_status to allow PCI scanning code to "skip"
212 * this now blacklisted device.
214 static void quirk_mellanox_tavor(struct pci_dev *dev)
216 dev->broken_parity_status = 1; /* This device gives false positives */
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
222 * Deal with broken BIOSes that neglect to enable passive release,
223 * which can cause problems in combination with the 82441FX/PPro MTRRs
225 static void quirk_passive_release(struct pci_dev *dev)
227 struct pci_dev *d = NULL;
231 * We have to make sure a particular bit is set in the PIIX3
232 * ISA bridge, so we have to go out and find it.
234 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
235 pci_read_config_byte(d, 0x82, &dlc);
237 pci_info(d, "PIIX3: Enabling Passive Release\n");
239 pci_write_config_byte(d, 0x82, dlc);
243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
244 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
247 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
248 * workaround but VIA don't answer queries. If you happen to have good
249 * contacts at VIA ask them for me please -- Alan
251 * This appears to be BIOS not version dependent. So presumably there is a
254 static void quirk_isa_dma_hangs(struct pci_dev *dev)
256 if (!isa_dma_bridge_buggy) {
257 isa_dma_bridge_buggy = 1;
258 pci_info(dev, "Activating ISA DMA hang workarounds\n");
262 * It's not totally clear which chipsets are the problematic ones. We know
263 * 82C586 and 82C596 variants are affected.
265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
274 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
275 * for some HT machines to use C4 w/o hanging.
277 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
282 pci_read_config_dword(dev, 0x40, &pmbase);
283 pmbase = pmbase & 0xff80;
287 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
293 /* Chipsets where PCI->PCI transfers vanish or hang */
294 static void quirk_nopcipci(struct pci_dev *dev)
296 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
297 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
298 pci_pci_problems |= PCIPCI_FAIL;
301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
304 static void quirk_nopciamd(struct pci_dev *dev)
307 pci_read_config_byte(dev, 0x08, &rev);
310 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
311 pci_pci_problems |= PCIAGP_FAIL;
314 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
316 /* Triton requires workarounds to be used by the drivers */
317 static void quirk_triton(struct pci_dev *dev)
319 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
320 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
321 pci_pci_problems |= PCIPCI_TRITON;
324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
330 * VIA Apollo KT133 needs PCI latency patch
331 * Made according to a Windows driver-based patch by George E. Breese;
332 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
333 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
334 * which Mr Breese based his work.
336 * Updated based on further information from the site and also on
337 * information provided by VIA
339 static void quirk_vialatency(struct pci_dev *dev)
345 * Ok, we have a potential problem chipset here. Now see if we have
346 * a buggy southbridge.
348 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
352 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
354 * Check for buggy part revisions
356 if (p->revision < 0x40 || p->revision > 0x42)
359 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
360 if (p == NULL) /* No problem parts */
363 /* Check for buggy part revisions */
364 if (p->revision < 0x10 || p->revision > 0x12)
369 * Ok we have the problem. Now set the PCI master grant to occur
370 * every master grant. The apparent bug is that under high PCI load
371 * (quite common in Linux of course) you can get data loss when the
372 * CPU is held off the bus for 3 bus master requests. This happens
373 * to include the IDE controllers....
375 * VIA only apply this fix when an SB Live! is present but under
376 * both Linux and Windows this isn't enough, and we have seen
377 * corruption without SB Live! but with things like 3 UDMA IDE
378 * controllers. So we ignore that bit of the VIA recommendation..
380 pci_read_config_byte(dev, 0x76, &busarb);
383 * Set bit 4 and bit 5 of byte 76 to 0x01
384 * "Master priority rotation on every PCI master grant"
388 pci_write_config_byte(dev, 0x76, busarb);
389 pci_info(dev, "Applying VIA southbridge workaround\n");
393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
396 /* Must restore this on a resume from RAM */
397 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
398 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
399 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
401 /* VIA Apollo VP3 needs ETBF on BT848/878 */
402 static void quirk_viaetbf(struct pci_dev *dev)
404 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
405 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
406 pci_pci_problems |= PCIPCI_VIAETBF;
409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
411 static void quirk_vsfx(struct pci_dev *dev)
413 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
414 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
415 pci_pci_problems |= PCIPCI_VSFX;
418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
421 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
422 * space. Latency must be set to 0xA and Triton workaround applied too.
423 * [Info kindly provided by ALi]
425 static void quirk_alimagik(struct pci_dev *dev)
427 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
428 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
429 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
435 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
436 static void quirk_natoma(struct pci_dev *dev)
438 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
439 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
440 pci_pci_problems |= PCIPCI_NATOMA;
443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
451 * This chip can cause PCI parity errors if config register 0xA0 is read
452 * while DMAs are occurring.
454 static void quirk_citrine(struct pci_dev *dev)
456 dev->cfg_size = 0xA0;
458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
461 * This chip can cause bus lockups if config addresses above 0x600
462 * are read or written.
464 static void quirk_nfp6000(struct pci_dev *dev)
466 dev->cfg_size = 0x600;
468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
473 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
474 static void quirk_extend_bar_to_page(struct pci_dev *dev)
478 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
479 struct resource *r = &dev->resource[i];
481 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
482 r->end = PAGE_SIZE - 1;
484 r->flags |= IORESOURCE_UNSET;
485 pci_info(dev, "expanded BAR %d to page size: %pR\n",
490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
493 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
494 * If it's needed, re-allocate the region.
496 static void quirk_s3_64M(struct pci_dev *dev)
498 struct resource *r = &dev->resource[0];
500 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
501 r->flags |= IORESOURCE_UNSET;
506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
509 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
513 struct pci_bus_region bus_region;
514 struct resource *res = dev->resource + pos;
516 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
521 res->name = pci_name(dev);
522 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
524 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
525 region &= ~(size - 1);
527 /* Convert from PCI bus to resource space */
528 bus_region.start = region;
529 bus_region.end = region + size - 1;
530 pcibios_bus_to_resource(dev->bus, res, &bus_region);
532 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
533 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
537 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
538 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
539 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
540 * (which conflicts w/ BAR1's memory range).
542 * CS553x's ISA PCI BARs may also be read-only (ref:
543 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
545 static void quirk_cs5536_vsa(struct pci_dev *dev)
547 static char *name = "CS5536 ISA bridge";
549 if (pci_resource_len(dev, 0) != 8) {
550 quirk_io(dev, 0, 8, name); /* SMB */
551 quirk_io(dev, 1, 256, name); /* GPIO */
552 quirk_io(dev, 2, 64, name); /* MFGPT */
553 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
557 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
559 static void quirk_io_region(struct pci_dev *dev, int port,
560 unsigned size, int nr, const char *name)
563 struct pci_bus_region bus_region;
564 struct resource *res = dev->resource + nr;
566 pci_read_config_word(dev, port, ®ion);
567 region &= ~(size - 1);
572 res->name = pci_name(dev);
573 res->flags = IORESOURCE_IO;
575 /* Convert from PCI bus to resource space */
576 bus_region.start = region;
577 bus_region.end = region + size - 1;
578 pcibios_bus_to_resource(dev->bus, res, &bus_region);
580 if (!pci_claim_resource(dev, nr))
581 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
585 * ATI Northbridge setups MCE the processor if you even read somewhere
586 * between 0x3b0->0x3bb or read 0x3d3
588 static void quirk_ati_exploding_mce(struct pci_dev *dev)
590 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
591 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
592 request_region(0x3b0, 0x0C, "RadeonIGP");
593 request_region(0x3d3, 0x01, "RadeonIGP");
595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
598 * In the AMD NL platform, this device ([1022:7912]) has a class code of
599 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
602 * But the dwc3 driver is a more specific driver for this device, and we'd
603 * prefer to use it instead of xhci. To prevent xhci from claiming the
604 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
605 * defines as "USB device (not host controller)". The dwc3 driver can then
606 * claim it based on its Vendor and Device ID.
608 static void quirk_amd_nl_class(struct pci_dev *pdev)
610 u32 class = pdev->class;
612 /* Use "USB Device (not host controller)" class */
613 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
614 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
621 * Synopsys USB 3.x host HAPS platform has a class code of
622 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
623 * devices should use dwc3-haps driver. Change these devices' class code to
624 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
627 static void quirk_synopsys_haps(struct pci_dev *pdev)
629 u32 class = pdev->class;
631 switch (pdev->device) {
632 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
633 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
634 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
635 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
636 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
641 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
642 PCI_CLASS_SERIAL_USB_XHCI, 0,
643 quirk_synopsys_haps);
646 * Let's make the southbridge information explicit instead of having to
647 * worry about people probing the ACPI areas, for example.. (Yes, it
648 * happens, and if you read the wrong ACPI register it will put the machine
649 * to sleep with no way of waking it up again. Bummer).
651 * ALI M7101: Two IO regions pointed to by words at
652 * 0xE0 (64 bytes of ACPI registers)
653 * 0xE2 (32 bytes of SMB registers)
655 static void quirk_ali7101_acpi(struct pci_dev *dev)
657 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
658 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
662 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
665 u32 mask, size, base;
667 pci_read_config_dword(dev, port, &devres);
668 if ((devres & enable) != enable)
670 mask = (devres >> 16) & 15;
671 base = devres & 0xffff;
674 unsigned bit = size >> 1;
675 if ((bit & mask) == bit)
680 * For now we only print it out. Eventually we'll want to
681 * reserve it (at least if it's in the 0x1000+ range), but
682 * let's get enough confirmation reports first.
685 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
688 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
691 u32 mask, size, base;
693 pci_read_config_dword(dev, port, &devres);
694 if ((devres & enable) != enable)
696 base = devres & 0xffff0000;
697 mask = (devres & 0x3f) << 16;
700 unsigned bit = size >> 1;
701 if ((bit & mask) == bit)
707 * For now we only print it out. Eventually we'll want to
708 * reserve it, but let's get enough confirmation reports first.
711 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
715 * PIIX4 ACPI: Two IO regions pointed to by longwords at
716 * 0x40 (64 bytes of ACPI registers)
717 * 0x90 (16 bytes of SMB registers)
718 * and a few strange programmable PIIX4 device resources.
720 static void quirk_piix4_acpi(struct pci_dev *dev)
724 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
725 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
727 /* Device resource A has enables for some of the other ones */
728 pci_read_config_dword(dev, 0x5c, &res_a);
730 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
731 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
733 /* Device resource D is just bitfields for static resources */
735 /* Device 12 enabled? */
736 if (res_a & (1 << 29)) {
737 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
738 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
740 /* Device 13 enabled? */
741 if (res_a & (1 << 30)) {
742 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
743 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
745 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
746 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
749 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
751 #define ICH_PMBASE 0x40
752 #define ICH_ACPI_CNTL 0x44
753 #define ICH4_ACPI_EN 0x10
754 #define ICH6_ACPI_EN 0x80
755 #define ICH4_GPIOBASE 0x58
756 #define ICH4_GPIO_CNTL 0x5c
757 #define ICH4_GPIO_EN 0x10
758 #define ICH6_GPIOBASE 0x48
759 #define ICH6_GPIO_CNTL 0x4c
760 #define ICH6_GPIO_EN 0x10
763 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
764 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
765 * 0x58 (64 bytes of GPIO I/O space)
767 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
772 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
773 * with low legacy (and fixed) ports. We don't know the decoding
774 * priority and can't tell whether the legacy device or the one created
775 * here is really at that address. This happens on boards with broken
778 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
779 if (enable & ICH4_ACPI_EN)
780 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
781 "ICH4 ACPI/GPIO/TCO");
783 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
784 if (enable & ICH4_GPIO_EN)
785 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
795 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
797 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
799 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
803 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
804 if (enable & ICH6_ACPI_EN)
805 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
806 "ICH6 ACPI/GPIO/TCO");
808 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
809 if (enable & ICH6_GPIO_EN)
810 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
814 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
815 const char *name, int dynsize)
820 pci_read_config_dword(dev, reg, &val);
828 * This is not correct. It is 16, 32 or 64 bytes depending on
829 * register D31:F0:ADh bits 5:4.
831 * But this gets us at least _part_ of it.
840 * Just print it out for now. We should reserve it after more
843 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
846 static void quirk_ich6_lpc(struct pci_dev *dev)
848 /* Shared ACPI/GPIO decode with all ICH6+ */
849 ich6_lpc_acpi_gpio(dev);
851 /* ICH6-specific generic IO decode */
852 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
853 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
858 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
864 pci_read_config_dword(dev, reg, &val);
870 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
872 mask = (val >> 16) & 0xfc;
876 * Just print it out for now. We should reserve it after more
879 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
882 /* ICH7-10 has the same common LPC generic IO decode registers */
883 static void quirk_ich7_lpc(struct pci_dev *dev)
885 /* We share the common ACPI/GPIO decode with ICH6 */
886 ich6_lpc_acpi_gpio(dev);
888 /* And have 4 ICH7+ generic decodes */
889 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
890 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
891 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
892 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
909 * VIA ACPI: One IO region pointed to by longword at
910 * 0x48 or 0x20 (256 bytes of ACPI registers)
912 static void quirk_vt82c586_acpi(struct pci_dev *dev)
914 if (dev->revision & 0x10)
915 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
921 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
922 * 0x48 (256 bytes of ACPI registers)
923 * 0x70 (128 bytes of hardware monitoring register)
924 * 0x90 (16 bytes of SMB registers)
926 static void quirk_vt82c686_acpi(struct pci_dev *dev)
928 quirk_vt82c586_acpi(dev);
930 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
933 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
938 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
939 * 0x88 (128 bytes of power management registers)
940 * 0xd0 (16 bytes of SMB registers)
942 static void quirk_vt8235_acpi(struct pci_dev *dev)
944 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
945 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
950 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
951 * back-to-back: Disable fast back-to-back on the secondary bus segment
953 static void quirk_xio2000a(struct pci_dev *dev)
955 struct pci_dev *pdev;
958 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
959 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
960 pci_read_config_word(pdev, PCI_COMMAND, &command);
961 if (command & PCI_COMMAND_FAST_BACK)
962 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
968 #ifdef CONFIG_X86_IO_APIC
970 #include <asm/io_apic.h>
973 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
974 * devices to the external APIC.
976 * TODO: When we have device-specific interrupt routers, this code will go
979 static void quirk_via_ioapic(struct pci_dev *dev)
984 tmp = 0; /* nothing routed to external APIC */
986 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
988 pci_info(dev, "%sbling VIA external APIC routing\n",
989 tmp == 0 ? "Disa" : "Ena");
991 /* Offset 0x58: External APIC IRQ output control */
992 pci_write_config_byte(dev, 0x58, tmp);
994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
995 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
998 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
999 * This leads to doubled level interrupt rates.
1000 * Set this bit to get rid of cycle wastage.
1001 * Otherwise uncritical.
1003 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1006 #define BYPASS_APIC_DEASSERT 8
1008 pci_read_config_byte(dev, 0x5B, &misc_control2);
1009 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1010 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1011 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1015 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1018 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1019 * We check all revs >= B0 (yet not in the pre production!) as the bug
1020 * is currently marked NoFix
1022 * We have multiple reports of hangs with this chipset that went away with
1023 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1024 * of course. However the advice is demonstrably good even if so.
1026 static void quirk_amd_ioapic(struct pci_dev *dev)
1028 if (dev->revision >= 0x02) {
1029 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1030 pci_warn(dev, " : booting with the \"noapic\" option\n");
1033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1034 #endif /* CONFIG_X86_IO_APIC */
1036 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1038 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1040 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1041 if (dev->subsystem_device == 0xa118)
1042 dev->sriov->link = dev->devfn;
1044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1048 * Some settings of MMRBC can lead to data corruption so block changes.
1049 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1051 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1053 if (dev->subordinate && dev->revision <= 0x12) {
1054 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1056 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1062 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1063 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1064 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1065 * of the ACPI SCI interrupt is only done for convenience.
1068 static void quirk_via_acpi(struct pci_dev *d)
1072 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1073 pci_read_config_byte(d, 0x42, &irq);
1075 if (irq && (irq != 2))
1078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1081 /* VIA bridges which have VLink */
1082 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1084 static void quirk_via_bridge(struct pci_dev *dev)
1086 /* See what bridge we have and find the device ranges */
1087 switch (dev->device) {
1088 case PCI_DEVICE_ID_VIA_82C686:
1090 * The VT82C686 is special; it attaches to PCI and can have
1091 * any device number. All its subdevices are functions of
1092 * that single device.
1094 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1095 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1097 case PCI_DEVICE_ID_VIA_8237:
1098 case PCI_DEVICE_ID_VIA_8237A:
1099 via_vlink_dev_lo = 15;
1101 case PCI_DEVICE_ID_VIA_8235:
1102 via_vlink_dev_lo = 16;
1104 case PCI_DEVICE_ID_VIA_8231:
1105 case PCI_DEVICE_ID_VIA_8233_0:
1106 case PCI_DEVICE_ID_VIA_8233A:
1107 case PCI_DEVICE_ID_VIA_8233C_0:
1108 via_vlink_dev_lo = 17;
1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1122 * quirk_via_vlink - VIA VLink IRQ number update
1125 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1126 * the IRQ line register which usually is not relevant for PCI cards, is
1127 * actually written so that interrupts get sent to the right place.
1129 * We only do this on systems where a VIA south bridge was detected, and
1130 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1132 static void quirk_via_vlink(struct pci_dev *dev)
1136 /* Check if we have VLink at all */
1137 if (via_vlink_dev_lo == -1)
1142 /* Don't quirk interrupts outside the legacy IRQ range */
1143 if (!new_irq || new_irq > 15)
1146 /* Internal device ? */
1147 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1148 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1152 * This is an internal VLink device on a PIC interrupt. The BIOS
1153 * ought to have set this but may not have, so we redo it.
1155 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1156 if (new_irq != irq) {
1157 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1159 udelay(15); /* unknown if delay really needed */
1160 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1163 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1166 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1167 * of VT82C597 for backward compatibility. We need to switch it off to be
1168 * able to recognize the real type of the chip.
1170 static void quirk_vt82c598_id(struct pci_dev *dev)
1172 pci_write_config_byte(dev, 0xfc, 0);
1173 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1178 * CardBus controllers have a legacy base address that enables them to
1179 * respond as i82365 pcmcia controllers. We don't want them to do this
1180 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1181 * driver does not (and should not) handle CardBus.
1183 static void quirk_cardbus_legacy(struct pci_dev *dev)
1185 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1187 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1188 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1189 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1190 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1193 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1194 * what the designers were smoking but let's not inhale...
1196 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1199 static void quirk_amd_ordering(struct pci_dev *dev)
1202 pci_read_config_dword(dev, 0x4C, &pcic);
1203 if ((pcic & 6) != 6) {
1205 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1206 pci_write_config_dword(dev, 0x4C, pcic);
1207 pci_read_config_dword(dev, 0x84, &pcic);
1208 pcic |= (1 << 23); /* Required in this mode */
1209 pci_write_config_dword(dev, 0x84, pcic);
1212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1213 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1216 * DreamWorks-provided workaround for Dunord I-3000 problem
1218 * This card decodes and responds to addresses not apparently assigned to
1219 * it. We force a larger allocation to ensure that nothing gets put too
1222 static void quirk_dunord(struct pci_dev *dev)
1224 struct resource *r = &dev->resource[1];
1226 r->flags |= IORESOURCE_UNSET;
1230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1233 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1234 * decoding (transparent), and does indicate this in the ProgIf.
1235 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1237 static void quirk_transparent_bridge(struct pci_dev *dev)
1239 dev->transparent = 1;
1241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1245 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1246 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1247 * found at http://www.national.com/analog for info on what these bits do.
1248 * <christer@weinigel.se>
1250 static void quirk_mediagx_master(struct pci_dev *dev)
1254 pci_read_config_byte(dev, 0x41, ®);
1257 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1259 pci_write_config_byte(dev, 0x41, reg);
1262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1263 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1266 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1267 * in the odd case it is not the results are corruption hence the presence
1270 static void quirk_disable_pxb(struct pci_dev *pdev)
1274 if (pdev->revision != 0x04) /* Only C0 requires this */
1276 pci_read_config_word(pdev, 0x40, &config);
1277 if (config & (1<<6)) {
1279 pci_write_config_word(pdev, 0x40, config);
1280 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1284 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1286 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1288 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1291 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1293 pci_read_config_byte(pdev, 0x40, &tmp);
1294 pci_write_config_byte(pdev, 0x40, tmp|1);
1295 pci_write_config_byte(pdev, 0x9, 1);
1296 pci_write_config_byte(pdev, 0xa, 6);
1297 pci_write_config_byte(pdev, 0x40, tmp);
1299 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1300 pci_info(pdev, "set SATA to AHCI mode\n");
1303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1304 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1306 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1308 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1310 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1312 /* Serverworks CSB5 IDE does not fully support native mode */
1313 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1316 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1320 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1321 /* PCI layer will sort out resources */
1324 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1326 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1327 static void quirk_ide_samemode(struct pci_dev *pdev)
1331 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1333 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1334 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1337 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1340 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1342 /* Some ATA devices break if put into D3 */
1343 static void quirk_no_ata_d3(struct pci_dev *pdev)
1345 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1347 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1348 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1349 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1350 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1351 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1352 /* ALi loses some register settings that we cannot then restore */
1353 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1354 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1355 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1356 occur when mode detecting */
1357 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1358 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1361 * This was originally an Alpha-specific thing, but it really fits here.
1362 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1364 static void quirk_eisa_bridge(struct pci_dev *dev)
1366 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1371 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1372 * is not activated. The myth is that Asus said that they do not want the
1373 * users to be irritated by just another PCI Device in the Win98 device
1374 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1375 * package 2.7.0 for details)
1377 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1378 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1379 * becomes necessary to do this tweak in two steps -- the chosen trigger
1380 * is either the Host bridge (preferred) or on-board VGA controller.
1382 * Note that we used to unhide the SMBus that way on Toshiba laptops
1383 * (Satellite A40 and Tecra M2) but then found that the thermal management
1384 * was done by SMM code, which could cause unsynchronized concurrent
1385 * accesses to the SMBus registers, with potentially bad effects. Thus you
1386 * should be very careful when adding new entries: if SMM is accessing the
1387 * Intel SMBus, this is a very good reason to leave it hidden.
1389 * Likewise, many recent laptops use ACPI for thermal management. If the
1390 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1391 * natively, and keeping the SMBus hidden is the right thing to do. If you
1392 * are about to add an entry in the table below, please first disassemble
1393 * the DSDT and double-check that there is no code accessing the SMBus.
1395 static int asus_hides_smbus;
1397 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1399 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1400 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1401 switch (dev->subsystem_device) {
1402 case 0x8025: /* P4B-LX */
1403 case 0x8070: /* P4B */
1404 case 0x8088: /* P4B533 */
1405 case 0x1626: /* L3C notebook */
1406 asus_hides_smbus = 1;
1408 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1409 switch (dev->subsystem_device) {
1410 case 0x80b1: /* P4GE-V */
1411 case 0x80b2: /* P4PE */
1412 case 0x8093: /* P4B533-V */
1413 asus_hides_smbus = 1;
1415 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1416 switch (dev->subsystem_device) {
1417 case 0x8030: /* P4T533 */
1418 asus_hides_smbus = 1;
1420 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1421 switch (dev->subsystem_device) {
1422 case 0x8070: /* P4G8X Deluxe */
1423 asus_hides_smbus = 1;
1425 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1426 switch (dev->subsystem_device) {
1427 case 0x80c9: /* PU-DLS */
1428 asus_hides_smbus = 1;
1430 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1431 switch (dev->subsystem_device) {
1432 case 0x1751: /* M2N notebook */
1433 case 0x1821: /* M5N notebook */
1434 case 0x1897: /* A6L notebook */
1435 asus_hides_smbus = 1;
1437 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1438 switch (dev->subsystem_device) {
1439 case 0x184b: /* W1N notebook */
1440 case 0x186a: /* M6Ne notebook */
1441 asus_hides_smbus = 1;
1443 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1444 switch (dev->subsystem_device) {
1445 case 0x80f2: /* P4P800-X */
1446 asus_hides_smbus = 1;
1448 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1449 switch (dev->subsystem_device) {
1450 case 0x1882: /* M6V notebook */
1451 case 0x1977: /* A6VA notebook */
1452 asus_hides_smbus = 1;
1454 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1455 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1456 switch (dev->subsystem_device) {
1457 case 0x088C: /* HP Compaq nc8000 */
1458 case 0x0890: /* HP Compaq nc6000 */
1459 asus_hides_smbus = 1;
1461 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1462 switch (dev->subsystem_device) {
1463 case 0x12bc: /* HP D330L */
1464 case 0x12bd: /* HP D530 */
1465 case 0x006a: /* HP Compaq nx9500 */
1466 asus_hides_smbus = 1;
1468 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1469 switch (dev->subsystem_device) {
1470 case 0x12bf: /* HP xw4100 */
1471 asus_hides_smbus = 1;
1473 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1474 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1475 switch (dev->subsystem_device) {
1476 case 0xC00C: /* Samsung P35 notebook */
1477 asus_hides_smbus = 1;
1479 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1480 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1481 switch (dev->subsystem_device) {
1482 case 0x0058: /* Compaq Evo N620c */
1483 asus_hides_smbus = 1;
1485 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1486 switch (dev->subsystem_device) {
1487 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1488 /* Motherboard doesn't have Host bridge
1489 * subvendor/subdevice IDs, therefore checking
1490 * its on-board VGA controller */
1491 asus_hides_smbus = 1;
1493 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1494 switch (dev->subsystem_device) {
1495 case 0x00b8: /* Compaq Evo D510 CMT */
1496 case 0x00b9: /* Compaq Evo D510 SFF */
1497 case 0x00ba: /* Compaq Evo D510 USDT */
1498 /* Motherboard doesn't have Host bridge
1499 * subvendor/subdevice IDs and on-board VGA
1500 * controller is disabled if an AGP card is
1501 * inserted, therefore checking USB UHCI
1503 asus_hides_smbus = 1;
1505 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1506 switch (dev->subsystem_device) {
1507 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1508 /* Motherboard doesn't have host bridge
1509 * subvendor/subdevice IDs, therefore checking
1510 * its on-board VGA controller */
1511 asus_hides_smbus = 1;
1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1530 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1534 if (likely(!asus_hides_smbus))
1537 pci_read_config_word(dev, 0xF2, &val);
1539 pci_write_config_word(dev, 0xF2, val & (~0x8));
1540 pci_read_config_word(dev, 0xF2, &val);
1542 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1545 pci_info(dev, "Enabled i801 SMBus device\n");
1548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1556 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1557 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1558 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1559 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1560 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1561 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1563 /* It appears we just have one such device. If not, we have a warning */
1564 static void __iomem *asus_rcba_base;
1565 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1569 if (likely(!asus_hides_smbus))
1571 WARN_ON(asus_rcba_base);
1573 pci_read_config_dword(dev, 0xF0, &rcba);
1574 /* use bits 31:14, 16 kB aligned */
1575 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1576 if (asus_rcba_base == NULL)
1580 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1584 if (likely(!asus_hides_smbus || !asus_rcba_base))
1587 /* read the Function Disable register, dword mode only */
1588 val = readl(asus_rcba_base + 0x3418);
1590 /* enable the SMBus device */
1591 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1594 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1596 if (likely(!asus_hides_smbus || !asus_rcba_base))
1599 iounmap(asus_rcba_base);
1600 asus_rcba_base = NULL;
1601 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1604 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1606 asus_hides_smbus_lpc_ich6_suspend(dev);
1607 asus_hides_smbus_lpc_ich6_resume_early(dev);
1608 asus_hides_smbus_lpc_ich6_resume(dev);
1610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1611 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1612 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1613 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1615 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1616 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1619 pci_read_config_byte(dev, 0x77, &val);
1621 pci_info(dev, "Enabling SiS 96x SMBus\n");
1622 pci_write_config_byte(dev, 0x77, val & ~0x10);
1625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1629 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1630 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1631 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1632 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1635 * ... This is further complicated by the fact that some SiS96x south
1636 * bridges pretend to be 85C503/5513 instead. In that case see if we
1637 * spotted a compatible north bridge to make sure.
1638 * (pci_find_device() doesn't work yet)
1640 * We can also enable the sis96x bit in the discovery register..
1642 #define SIS_DETECT_REGISTER 0x40
1644 static void quirk_sis_503(struct pci_dev *dev)
1649 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1650 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1651 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1652 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1653 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1658 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1659 * it has already been processed. (Depends on link order, which is
1660 * apparently not guaranteed)
1662 dev->device = devid;
1663 quirk_sis_96x_smbus(dev);
1665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1666 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1669 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1670 * and MC97 modem controller are disabled when a second PCI soundcard is
1671 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1674 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1677 int asus_hides_ac97 = 0;
1679 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1680 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1681 asus_hides_ac97 = 1;
1684 if (!asus_hides_ac97)
1687 pci_read_config_byte(dev, 0x50, &val);
1689 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1690 pci_read_config_byte(dev, 0x50, &val);
1692 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1695 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1699 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1701 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1704 * If we are using libata we can drive this chip properly but must do this
1705 * early on to make the additional device appear during the PCI scanning.
1707 static void quirk_jmicron_ata(struct pci_dev *pdev)
1709 u32 conf1, conf5, class;
1712 /* Only poke fn 0 */
1713 if (PCI_FUNC(pdev->devfn))
1716 pci_read_config_dword(pdev, 0x40, &conf1);
1717 pci_read_config_dword(pdev, 0x80, &conf5);
1719 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1720 conf5 &= ~(1 << 24); /* Clear bit 24 */
1722 switch (pdev->device) {
1723 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1724 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1725 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1726 /* The controller should be in single function ahci mode */
1727 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1730 case PCI_DEVICE_ID_JMICRON_JMB365:
1731 case PCI_DEVICE_ID_JMICRON_JMB366:
1732 /* Redirect IDE second PATA port to the right spot */
1735 case PCI_DEVICE_ID_JMICRON_JMB361:
1736 case PCI_DEVICE_ID_JMICRON_JMB363:
1737 case PCI_DEVICE_ID_JMICRON_JMB369:
1738 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1739 /* Set the class codes correctly and then direct IDE 0 */
1740 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1743 case PCI_DEVICE_ID_JMICRON_JMB368:
1744 /* The controller should be in single function IDE mode */
1745 conf1 |= 0x00C00000; /* Set 22, 23 */
1749 pci_write_config_dword(pdev, 0x40, conf1);
1750 pci_write_config_dword(pdev, 0x80, conf5);
1752 /* Update pdev accordingly */
1753 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1754 pdev->hdr_type = hdr & 0x7f;
1755 pdev->multifunction = !!(hdr & 0x80);
1757 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1758 pdev->class = class >> 8;
1760 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1764 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1765 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1766 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1768 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1769 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1771 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1773 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1774 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1775 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1776 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1777 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1781 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1783 if (dev->multifunction) {
1784 device_disable_async_suspend(&dev->dev);
1785 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1788 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1789 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1793 #ifdef CONFIG_X86_IO_APIC
1794 static void quirk_alder_ioapic(struct pci_dev *pdev)
1798 if ((pdev->class >> 8) != 0xff00)
1802 * The first BAR is the location of the IO-APIC... we must
1803 * not touch this (and it's already covered by the fixmap), so
1804 * forcibly insert it into the resource tree.
1806 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1807 insert_resource(&iomem_resource, &pdev->resource[0]);
1810 * The next five BARs all seem to be rubbish, so just clean
1813 for (i = 1; i < 6; i++)
1814 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1816 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1819 static void quirk_pcie_mch(struct pci_dev *pdev)
1823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1827 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1830 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1831 * together on certain PXH-based systems.
1833 static void quirk_pcie_pxh(struct pci_dev *dev)
1836 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1838 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1839 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1840 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1841 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1842 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1845 * Some Intel PCI Express chipsets have trouble with downstream device
1848 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1850 pci_pm_d3_delay = 120;
1853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1875 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1877 if (dev->d3_delay >= delay)
1880 dev->d3_delay = delay;
1881 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1885 static void quirk_radeon_pm(struct pci_dev *dev)
1887 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1888 dev->subsystem_device == 0x00e2)
1889 quirk_d3hot_delay(dev, 20);
1891 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1894 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1895 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1897 * The kernel attempts to transition these devices to D3cold, but that seems
1898 * to be ineffective on the platforms in question; the PCI device appears to
1899 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1900 * extended delay in order to succeed.
1902 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1904 quirk_d3hot_delay(dev, 20);
1906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
1910 #ifdef CONFIG_X86_IO_APIC
1911 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1913 noioapicreroute = 1;
1914 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1919 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1921 * Systems to exclude from boot interrupt reroute quirks
1924 .callback = dmi_disable_ioapicreroute,
1925 .ident = "ASUSTek Computer INC. M2N-LR",
1927 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1928 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1935 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1936 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1937 * that a PCI device's interrupt handler is installed on the boot interrupt
1940 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1942 dmi_check_system(boot_interrupt_dmi_table);
1943 if (noioapicquirk || noioapicreroute)
1946 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1947 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1948 dev->vendor, dev->device);
1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1958 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1959 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1960 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1961 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1962 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1963 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1964 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1965 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1968 * On some chipsets we can disable the generation of legacy INTx boot
1973 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1974 * 300641-004US, section 5.7.3.
1976 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1977 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1978 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1979 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1980 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1981 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1982 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1983 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1984 * Core IO on Xeon Scalable, see Intel order no 610950.
1986 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
1987 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1989 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
1990 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
1992 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1994 u16 pci_config_word;
1995 u32 pci_config_dword;
2000 switch (dev->device) {
2001 case PCI_DEVICE_ID_INTEL_ESB_10:
2002 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2004 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2005 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2008 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2009 case 0x0e28: /* Xeon E5/E7 V2 */
2010 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2011 case 0x6f28: /* Xeon D-1500 */
2012 case 0x2034: /* Xeon Scalable Family */
2013 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2015 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2016 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2022 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2023 dev->vendor, dev->device);
2026 * Device 29 Func 5 Device IDs of IO-APIC
2027 * containing ABAR—APIC1 Alternate Base Address Register
2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2030 quirk_disable_intel_boot_interrupt);
2031 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2032 quirk_disable_intel_boot_interrupt);
2035 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2036 * containing Coherent Interface Protocol Interrupt Control
2038 * Device IDs obtained from volume 2 datasheets of commented
2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2042 quirk_disable_intel_boot_interrupt);
2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2044 quirk_disable_intel_boot_interrupt);
2045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2046 quirk_disable_intel_boot_interrupt);
2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2048 quirk_disable_intel_boot_interrupt);
2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2050 quirk_disable_intel_boot_interrupt);
2051 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2052 quirk_disable_intel_boot_interrupt);
2053 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2054 quirk_disable_intel_boot_interrupt);
2055 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2056 quirk_disable_intel_boot_interrupt);
2057 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2058 quirk_disable_intel_boot_interrupt);
2059 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2060 quirk_disable_intel_boot_interrupt);
2062 /* Disable boot interrupts on HT-1000 */
2063 #define BC_HT1000_FEATURE_REG 0x64
2064 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2065 #define BC_HT1000_MAP_IDX 0xC00
2066 #define BC_HT1000_MAP_DATA 0xC01
2068 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2070 u32 pci_config_dword;
2076 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2077 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2078 BC_HT1000_PIC_REGS_ENABLE);
2080 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2081 outb(irq, BC_HT1000_MAP_IDX);
2082 outb(0x00, BC_HT1000_MAP_DATA);
2085 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2087 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2088 dev->vendor, dev->device);
2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2091 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2093 /* Disable boot interrupts on AMD and ATI chipsets */
2096 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2097 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2098 * (due to an erratum).
2100 #define AMD_813X_MISC 0x40
2101 #define AMD_813X_NOIOAMODE (1<<0)
2102 #define AMD_813X_REV_B1 0x12
2103 #define AMD_813X_REV_B2 0x13
2105 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2107 u32 pci_config_dword;
2111 if ((dev->revision == AMD_813X_REV_B1) ||
2112 (dev->revision == AMD_813X_REV_B2))
2115 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2116 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2117 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2119 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2120 dev->vendor, dev->device);
2122 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2123 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2125 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2127 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2129 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2131 u16 pci_config_word;
2136 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2137 if (!pci_config_word) {
2138 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2139 dev->vendor, dev->device);
2142 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2143 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2144 dev->vendor, dev->device);
2146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2147 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2148 #endif /* CONFIG_X86_IO_APIC */
2151 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2152 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2153 * Re-allocate the region if needed...
2155 static void quirk_tc86c001_ide(struct pci_dev *dev)
2157 struct resource *r = &dev->resource[0];
2159 if (r->start & 0x8) {
2160 r->flags |= IORESOURCE_UNSET;
2165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2166 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2167 quirk_tc86c001_ide);
2170 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2171 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2172 * being read correctly if bit 7 of the base address is set.
2173 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2174 * Re-allocate the regions to a 256-byte boundary if necessary.
2176 static void quirk_plx_pci9050(struct pci_dev *dev)
2180 /* Fixed in revision 2 (PCI 9052). */
2181 if (dev->revision >= 2)
2183 for (bar = 0; bar <= 1; bar++)
2184 if (pci_resource_len(dev, bar) == 0x80 &&
2185 (pci_resource_start(dev, bar) & 0x80)) {
2186 struct resource *r = &dev->resource[bar];
2187 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2189 r->flags |= IORESOURCE_UNSET;
2194 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2197 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2198 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2199 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2200 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2202 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2205 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2206 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2208 static void quirk_netmos(struct pci_dev *dev)
2210 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2211 unsigned int num_serial = dev->subsystem_device & 0xf;
2214 * These Netmos parts are multiport serial devices with optional
2215 * parallel ports. Even when parallel ports are present, they
2216 * are identified as class SERIAL, which means the serial driver
2217 * will claim them. To prevent this, mark them as class OTHER.
2218 * These combo devices should be claimed by parport_serial.
2220 * The subdevice ID is of the form 0x00PS, where <P> is the number
2221 * of parallel ports and <S> is the number of serial ports.
2223 switch (dev->device) {
2224 case PCI_DEVICE_ID_NETMOS_9835:
2225 /* Well, this rule doesn't hold for the following 9835 device */
2226 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2227 dev->subsystem_device == 0x0299)
2229 /* else, fall through */
2230 case PCI_DEVICE_ID_NETMOS_9735:
2231 case PCI_DEVICE_ID_NETMOS_9745:
2232 case PCI_DEVICE_ID_NETMOS_9845:
2233 case PCI_DEVICE_ID_NETMOS_9855:
2235 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2236 dev->device, num_parallel, num_serial);
2237 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2238 (dev->class & 0xff);
2242 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2243 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2245 static void quirk_e100_interrupt(struct pci_dev *dev)
2251 switch (dev->device) {
2252 /* PCI IDs taken from drivers/net/e100.c */
2254 case 0x1030 ... 0x1034:
2255 case 0x1038 ... 0x103E:
2256 case 0x1050 ... 0x1057:
2258 case 0x1064 ... 0x106B:
2259 case 0x1091 ... 0x1095:
2272 * Some firmware hands off the e100 with interrupts enabled,
2273 * which can cause a flood of interrupts if packets are
2274 * received before the driver attaches to the device. So
2275 * disable all e100 interrupts here. The driver will
2276 * re-enable them when it's ready.
2278 pci_read_config_word(dev, PCI_COMMAND, &command);
2280 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2284 * Check that the device is in the D0 power state. If it's not,
2285 * there is no point to look any further.
2288 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2289 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2293 /* Convert from PCI bus to resource space. */
2294 csr = ioremap(pci_resource_start(dev, 0), 8);
2296 pci_warn(dev, "Can't map e100 registers\n");
2300 cmd_hi = readb(csr + 3);
2302 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2308 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2309 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2312 * The 82575 and 82598 may experience data corruption issues when transitioning
2313 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2315 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2317 pci_info(dev, "Disabling L0s\n");
2318 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2330 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2332 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2333 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2335 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2337 pci_info(dev, "Disabling ASPM L0s/L1\n");
2338 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2342 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2343 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2344 * disable both L0s and L1 for now to be safe.
2346 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2349 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2350 * Link bit cleared after starting the link retrain process to allow this
2351 * process to finish.
2353 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2354 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2356 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2358 dev->clear_retrain_link = 1;
2359 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2361 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2362 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2363 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2365 static void fixup_rev1_53c810(struct pci_dev *dev)
2367 u32 class = dev->class;
2370 * rev 1 ncr53c810 chips don't set the class at all which means
2371 * they don't get their resources remapped. Fix that here.
2376 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2377 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2380 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2382 /* Enable 1k I/O space granularity on the Intel P64H2 */
2383 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2387 pci_read_config_word(dev, 0x40, &en1k);
2390 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2391 dev->io_window_1k = 1;
2394 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2397 * Under some circumstances, AER is not linked with extended capabilities.
2398 * Force it to be linked by setting the corresponding control bit in the
2401 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2405 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2407 pci_write_config_byte(dev, 0xf41, b | 0x20);
2408 pci_info(dev, "Linking AER extended capability\n");
2412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2413 quirk_nvidia_ck804_pcie_aer_ext_cap);
2414 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2415 quirk_nvidia_ck804_pcie_aer_ext_cap);
2417 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2420 * Disable PCI Bus Parking and PCI Master read caching on CX700
2421 * which causes unspecified timing errors with a VT6212L on the PCI
2422 * bus leading to USB2.0 packet loss.
2424 * This quirk is only enabled if a second (on the external PCI bus)
2425 * VT6212L is found -- the CX700 core itself also contains a USB
2426 * host controller with the same PCI ID as the VT6212L.
2429 /* Count VT6212L instances */
2430 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2431 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2435 * p should contain the first (internal) VT6212L -- see if we have
2436 * an external one by searching again.
2438 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2443 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2445 /* Turn off PCI Bus Parking */
2446 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2448 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2452 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2454 /* Turn off PCI Master read caching */
2455 pci_write_config_byte(dev, 0x72, 0x0);
2457 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2458 pci_write_config_byte(dev, 0x75, 0x1);
2460 /* Disable "Read FIFO Timer" */
2461 pci_write_config_byte(dev, 0x77, 0x0);
2463 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2469 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2473 pci_read_config_dword(dev, 0xf4, &rev);
2475 /* Only CAP the MRRS if the device is a 5719 A0 */
2476 if (rev == 0x05719000) {
2477 int readrq = pcie_get_readrq(dev);
2479 pcie_set_readrq(dev, 2048);
2482 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2483 PCI_DEVICE_ID_TIGON3_5719,
2484 quirk_brcm_5719_limit_mrrs);
2487 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2488 * hide device 6 which configures the overflow device access containing the
2489 * DRBs - this is where we expose device 6.
2490 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2492 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2496 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2497 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2498 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2501 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2502 quirk_unhide_mch_dev6);
2503 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2504 quirk_unhide_mch_dev6);
2506 #ifdef CONFIG_PCI_MSI
2508 * Some chipsets do not support MSI. We cannot easily rely on setting
2509 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2510 * other buses controlled by the chipset even if Linux is not aware of it.
2511 * Instead of setting the flag on all buses in the machine, simply disable
2514 static void quirk_disable_all_msi(struct pci_dev *dev)
2517 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2521 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2523 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2525 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2526 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2528 /* Disable MSI on chipsets that are known to not support it */
2529 static void quirk_disable_msi(struct pci_dev *dev)
2531 if (dev->subordinate) {
2532 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2533 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2541 * The APC bridge device in AMD 780 family northbridges has some random
2542 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2543 * we use the possible vendor/device IDs of the host bridge for the
2544 * declared quirk, and search for the APC bridge by slot number.
2546 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2548 struct pci_dev *apc_bridge;
2550 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2552 if (apc_bridge->device == 0x9602)
2553 quirk_disable_msi(apc_bridge);
2554 pci_dev_put(apc_bridge);
2557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2561 * Go through the list of HyperTransport capabilities and return 1 if a HT
2562 * MSI capability is found and enabled.
2564 static int msi_ht_cap_enabled(struct pci_dev *dev)
2566 int pos, ttl = PCI_FIND_CAP_TTL;
2568 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2569 while (pos && ttl--) {
2572 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2574 pci_info(dev, "Found %s HT MSI Mapping\n",
2575 flags & HT_MSI_FLAGS_ENABLE ?
2576 "enabled" : "disabled");
2577 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2580 pos = pci_find_next_ht_capability(dev, pos,
2581 HT_CAPTYPE_MSI_MAPPING);
2586 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2587 static void quirk_msi_ht_cap(struct pci_dev *dev)
2589 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2590 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2591 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2598 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2599 * if the MSI capability is set in any of these mappings.
2601 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2603 struct pci_dev *pdev;
2605 if (!dev->subordinate)
2609 * Check HT MSI cap on this chipset and the root one. A single one
2610 * having MSI is enough to be sure that MSI is supported.
2612 pdev = pci_get_slot(dev->bus, 0);
2615 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2616 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2617 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2622 quirk_nvidia_ck804_msi_ht_cap);
2624 /* Force enable MSI mapping capability on HT bridges */
2625 static void ht_enable_msi_mapping(struct pci_dev *dev)
2627 int pos, ttl = PCI_FIND_CAP_TTL;
2629 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2630 while (pos && ttl--) {
2633 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2635 pci_info(dev, "Enabling HT MSI Mapping\n");
2637 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2638 flags | HT_MSI_FLAGS_ENABLE);
2640 pos = pci_find_next_ht_capability(dev, pos,
2641 HT_CAPTYPE_MSI_MAPPING);
2644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2645 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2646 ht_enable_msi_mapping);
2647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2648 ht_enable_msi_mapping);
2651 * The P5N32-SLI motherboards from Asus have a problem with MSI
2652 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2653 * also affects other devices. As for now, turn off MSI for this device.
2655 static void nvenet_msi_disable(struct pci_dev *dev)
2657 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2660 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2661 strstr(board_name, "P5N32-E SLI"))) {
2662 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2666 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2667 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2668 nvenet_msi_disable);
2671 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2672 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2673 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2674 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2675 * for other events, since PCIe specificiation doesn't support using a mix of
2676 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2677 * service drivers registering their respective ISRs for MSIs.
2679 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2683 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2684 PCI_CLASS_BRIDGE_PCI, 8,
2685 pci_quirk_nvidia_tegra_disable_rp_msi);
2686 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2687 PCI_CLASS_BRIDGE_PCI, 8,
2688 pci_quirk_nvidia_tegra_disable_rp_msi);
2689 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2690 PCI_CLASS_BRIDGE_PCI, 8,
2691 pci_quirk_nvidia_tegra_disable_rp_msi);
2692 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2693 PCI_CLASS_BRIDGE_PCI, 8,
2694 pci_quirk_nvidia_tegra_disable_rp_msi);
2695 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2696 PCI_CLASS_BRIDGE_PCI, 8,
2697 pci_quirk_nvidia_tegra_disable_rp_msi);
2698 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2699 PCI_CLASS_BRIDGE_PCI, 8,
2700 pci_quirk_nvidia_tegra_disable_rp_msi);
2701 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2702 PCI_CLASS_BRIDGE_PCI, 8,
2703 pci_quirk_nvidia_tegra_disable_rp_msi);
2704 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2705 PCI_CLASS_BRIDGE_PCI, 8,
2706 pci_quirk_nvidia_tegra_disable_rp_msi);
2707 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2708 PCI_CLASS_BRIDGE_PCI, 8,
2709 pci_quirk_nvidia_tegra_disable_rp_msi);
2710 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2711 PCI_CLASS_BRIDGE_PCI, 8,
2712 pci_quirk_nvidia_tegra_disable_rp_msi);
2713 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2714 PCI_CLASS_BRIDGE_PCI, 8,
2715 pci_quirk_nvidia_tegra_disable_rp_msi);
2716 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2717 PCI_CLASS_BRIDGE_PCI, 8,
2718 pci_quirk_nvidia_tegra_disable_rp_msi);
2719 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2720 PCI_CLASS_BRIDGE_PCI, 8,
2721 pci_quirk_nvidia_tegra_disable_rp_msi);
2724 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2725 * config register. This register controls the routing of legacy
2726 * interrupts from devices that route through the MCP55. If this register
2727 * is misprogrammed, interrupts are only sent to the BSP, unlike
2728 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2729 * having this register set properly prevents kdump from booting up
2730 * properly, so let's make sure that we have it set correctly.
2731 * Note that this is an undocumented register.
2733 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2737 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2740 pci_read_config_dword(dev, 0x74, &cfg);
2742 if (cfg & ((1 << 2) | (1 << 15))) {
2743 pr_info("Rewriting IRQ routing register on MCP55\n");
2744 cfg &= ~((1 << 2) | (1 << 15));
2745 pci_write_config_dword(dev, 0x74, cfg);
2748 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2749 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2750 nvbridge_check_legacy_irq_routing);
2751 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2752 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2753 nvbridge_check_legacy_irq_routing);
2755 static int ht_check_msi_mapping(struct pci_dev *dev)
2757 int pos, ttl = PCI_FIND_CAP_TTL;
2760 /* Check if there is HT MSI cap or enabled on this device */
2761 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2762 while (pos && ttl--) {
2767 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2769 if (flags & HT_MSI_FLAGS_ENABLE) {
2776 pos = pci_find_next_ht_capability(dev, pos,
2777 HT_CAPTYPE_MSI_MAPPING);
2783 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2785 struct pci_dev *dev;
2790 dev_no = host_bridge->devfn >> 3;
2791 for (i = dev_no + 1; i < 0x20; i++) {
2792 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2796 /* found next host bridge? */
2797 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2803 if (ht_check_msi_mapping(dev)) {
2814 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2815 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2817 static int is_end_of_ht_chain(struct pci_dev *dev)
2823 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2828 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2830 ctrl_off = ((flags >> 10) & 1) ?
2831 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2832 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2834 if (ctrl & (1 << 6))
2841 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2843 struct pci_dev *host_bridge;
2848 dev_no = dev->devfn >> 3;
2849 for (i = dev_no; i >= 0; i--) {
2850 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2854 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2859 pci_dev_put(host_bridge);
2865 /* don't enable end_device/host_bridge with leaf directly here */
2866 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2867 host_bridge_with_leaf(host_bridge))
2870 /* root did that ! */
2871 if (msi_ht_cap_enabled(host_bridge))
2874 ht_enable_msi_mapping(dev);
2877 pci_dev_put(host_bridge);
2880 static void ht_disable_msi_mapping(struct pci_dev *dev)
2882 int pos, ttl = PCI_FIND_CAP_TTL;
2884 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2885 while (pos && ttl--) {
2888 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2890 pci_info(dev, "Disabling HT MSI Mapping\n");
2892 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2893 flags & ~HT_MSI_FLAGS_ENABLE);
2895 pos = pci_find_next_ht_capability(dev, pos,
2896 HT_CAPTYPE_MSI_MAPPING);
2900 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2902 struct pci_dev *host_bridge;
2906 if (!pci_msi_enabled())
2909 /* check if there is HT MSI cap or enabled on this device */
2910 found = ht_check_msi_mapping(dev);
2917 * HT MSI mapping should be disabled on devices that are below
2918 * a non-Hypertransport host bridge. Locate the host bridge...
2920 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2922 if (host_bridge == NULL) {
2923 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2927 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2929 /* Host bridge is to HT */
2931 /* it is not enabled, try to enable it */
2933 ht_enable_msi_mapping(dev);
2935 nv_ht_enable_msi_mapping(dev);
2940 /* HT MSI is not enabled */
2944 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2945 ht_disable_msi_mapping(dev);
2948 pci_dev_put(host_bridge);
2951 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2953 return __nv_msi_ht_cap_quirk(dev, 1);
2955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2956 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2958 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2960 return __nv_msi_ht_cap_quirk(dev, 0);
2962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2963 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2965 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2967 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2970 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2975 * SB700 MSI issue will be fixed at HW level from revision A21;
2976 * we need check PCI REVISION ID of SMBus controller to get SB700
2979 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2984 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2985 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2989 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2991 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2992 if (dev->revision < 0x18) {
2993 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2994 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2998 PCI_DEVICE_ID_TIGON3_5780,
2999 quirk_msi_intx_disable_bug);
3000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3001 PCI_DEVICE_ID_TIGON3_5780S,
3002 quirk_msi_intx_disable_bug);
3003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3004 PCI_DEVICE_ID_TIGON3_5714,
3005 quirk_msi_intx_disable_bug);
3006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3007 PCI_DEVICE_ID_TIGON3_5714S,
3008 quirk_msi_intx_disable_bug);
3009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3010 PCI_DEVICE_ID_TIGON3_5715,
3011 quirk_msi_intx_disable_bug);
3012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3013 PCI_DEVICE_ID_TIGON3_5715S,
3014 quirk_msi_intx_disable_bug);
3016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3017 quirk_msi_intx_disable_ati_bug);
3018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3019 quirk_msi_intx_disable_ati_bug);
3020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3021 quirk_msi_intx_disable_ati_bug);
3022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3023 quirk_msi_intx_disable_ati_bug);
3024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3025 quirk_msi_intx_disable_ati_bug);
3027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3028 quirk_msi_intx_disable_bug);
3029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3030 quirk_msi_intx_disable_bug);
3031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3032 quirk_msi_intx_disable_bug);
3034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3035 quirk_msi_intx_disable_bug);
3036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3037 quirk_msi_intx_disable_bug);
3038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3039 quirk_msi_intx_disable_bug);
3040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3041 quirk_msi_intx_disable_bug);
3042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3043 quirk_msi_intx_disable_bug);
3044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3045 quirk_msi_intx_disable_bug);
3046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3047 quirk_msi_intx_disable_qca_bug);
3048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3049 quirk_msi_intx_disable_qca_bug);
3050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3051 quirk_msi_intx_disable_qca_bug);
3052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3053 quirk_msi_intx_disable_qca_bug);
3054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3055 quirk_msi_intx_disable_qca_bug);
3058 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3059 * should be disabled on platforms where the device (mistakenly) advertises it.
3061 * Notice that this quirk also disables MSI (which may work, but hasn't been
3062 * tested), since currently there is no standard way to disable only MSI-X.
3064 * The 0031 device id is reused for other non Root Port device types,
3065 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3067 static void quirk_al_msi_disable(struct pci_dev *dev)
3070 pci_warn(dev, "Disabling MSI/MSI-X\n");
3072 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3073 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3074 #endif /* CONFIG_PCI_MSI */
3077 * Allow manual resource allocation for PCI hotplug bridges via
3078 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3079 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3080 * allocate resources when hotplug device is inserted and PCI bus is
3083 static void quirk_hotplug_bridge(struct pci_dev *dev)
3085 dev->is_hotplug_bridge = 1;
3087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3090 * This is a quirk for the Ricoh MMC controller found as a part of some
3091 * multifunction chips.
3093 * This is very similar and based on the ricoh_mmc driver written by
3094 * Philip Langdale. Thank you for these magic sequences.
3096 * These chips implement the four main memory card controllers (SD, MMC,
3097 * MS, xD) and one or both of CardBus or FireWire.
3099 * It happens that they implement SD and MMC support as separate
3100 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3101 * cards but the chip detects MMC cards in hardware and directs them to the
3102 * MMC controller - so the SDHCI driver never sees them.
3104 * To get around this, we must disable the useless MMC controller. At that
3105 * point, the SDHCI controller will start seeing them. It seems to be the
3106 * case that the relevant PCI registers to deactivate the MMC controller
3107 * live on PCI function 0, which might be the CardBus controller or the
3108 * FireWire controller, depending on the particular chip in question
3110 * This has to be done early, because as soon as we disable the MMC controller
3111 * other PCI functions shift up one level, e.g. function #2 becomes function
3112 * #1, and this will confuse the PCI core.
3114 #ifdef CONFIG_MMC_RICOH_MMC
3115 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3122 * Disable via CardBus interface
3124 * This must be done via function #0
3126 if (PCI_FUNC(dev->devfn))
3129 pci_read_config_byte(dev, 0xB7, &disable);
3133 pci_read_config_byte(dev, 0x8E, &write_enable);
3134 pci_write_config_byte(dev, 0x8E, 0xAA);
3135 pci_read_config_byte(dev, 0x8D, &write_target);
3136 pci_write_config_byte(dev, 0x8D, 0xB7);
3137 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3138 pci_write_config_byte(dev, 0x8E, write_enable);
3139 pci_write_config_byte(dev, 0x8D, write_target);
3141 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3142 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3144 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3145 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3147 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3153 * Disable via FireWire interface
3155 * This must be done via function #0
3157 if (PCI_FUNC(dev->devfn))
3160 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3161 * certain types of SD/MMC cards. Lowering the SD base clock
3162 * frequency from 200Mhz to 50Mhz fixes this issue.
3164 * 0x150 - SD2.0 mode enable for changing base clock
3165 * frequency to 50Mhz
3166 * 0xe1 - Base clock frequency
3167 * 0x32 - 50Mhz new clock frequency
3168 * 0xf9 - Key register for 0x150
3169 * 0xfc - key register for 0xe1
3171 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3172 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3173 pci_write_config_byte(dev, 0xf9, 0xfc);
3174 pci_write_config_byte(dev, 0x150, 0x10);
3175 pci_write_config_byte(dev, 0xf9, 0x00);
3176 pci_write_config_byte(dev, 0xfc, 0x01);
3177 pci_write_config_byte(dev, 0xe1, 0x32);
3178 pci_write_config_byte(dev, 0xfc, 0x00);
3180 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3183 pci_read_config_byte(dev, 0xCB, &disable);
3188 pci_read_config_byte(dev, 0xCA, &write_enable);
3189 pci_write_config_byte(dev, 0xCA, 0x57);
3190 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3191 pci_write_config_byte(dev, 0xCA, write_enable);
3193 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3194 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3197 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3198 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3199 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3200 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3201 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3202 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3203 #endif /*CONFIG_MMC_RICOH_MMC*/
3205 #ifdef CONFIG_DMAR_TABLE
3206 #define VTUNCERRMSK_REG 0x1ac
3207 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3209 * This is a quirk for masking VT-d spec-defined errors to platform error
3210 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3211 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3212 * on the RAS config settings of the platform) when a VT-d fault happens.
3213 * The resulting SMI caused the system to hang.
3215 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3216 * need to report the same error through other channels.
3218 static void vtd_mask_spec_errors(struct pci_dev *dev)
3222 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3223 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3225 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3226 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3229 static void fixup_ti816x_class(struct pci_dev *dev)
3231 u32 class = dev->class;
3233 /* TI 816x devices do not have class code set when in PCIe boot mode */
3234 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3235 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3238 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3239 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3242 * Some PCIe devices do not work reliably with the claimed maximum
3243 * payload size supported.
3245 static void fixup_mpss_256(struct pci_dev *dev)
3247 dev->pcie_mpss = 1; /* 256 bytes */
3249 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3250 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3251 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3252 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3253 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3254 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3255 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3258 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3259 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3260 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3261 * until all of the devices are discovered and buses walked, read completion
3262 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3263 * it is possible to hotplug a device with MPS of 256B.
3265 static void quirk_intel_mc_errata(struct pci_dev *dev)
3270 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3271 pcie_bus_config == PCIE_BUS_DEFAULT)
3275 * Intel erratum specifies bits to change but does not say what
3276 * they are. Keeping them magical until such time as the registers
3277 * and values can be explained.
3279 err = pci_read_config_word(dev, 0x48, &rcc);
3281 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3285 if (!(rcc & (1 << 10)))
3290 err = pci_write_config_word(dev, 0x48, rcc);
3292 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3296 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3298 /* Intel 5000 series memory controllers and ports 2-7 */
3299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3313 /* Intel 5100 series memory controllers and ports 2-7 */
3314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3327 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3328 * To work around this, query the size it should be configured to by the
3329 * device and modify the resource end to correspond to this new size.
3331 static void quirk_intel_ntb(struct pci_dev *dev)
3336 rc = pci_read_config_byte(dev, 0x00D0, &val);
3340 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3342 rc = pci_read_config_byte(dev, 0x00D1, &val);
3346 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3352 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3353 * though no one is handling them (e.g., if the i915 driver is never
3354 * loaded). Additionally the interrupt destination is not set up properly
3355 * and the interrupt ends up -somewhere-.
3357 * These spurious interrupts are "sticky" and the kernel disables the
3358 * (shared) interrupt line after 100,000+ generated interrupts.
3360 * Fix it by disabling the still enabled interrupts. This resolves crashes
3361 * often seen on monitor unplug.
3363 #define I915_DEIER_REG 0x4400c
3364 static void disable_igfx_irq(struct pci_dev *dev)
3366 void __iomem *regs = pci_iomap(dev, 0, 0);
3368 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3372 /* Check if any interrupt line is still enabled */
3373 if (readl(regs + I915_DEIER_REG) != 0) {
3374 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3376 writel(0, regs + I915_DEIER_REG);
3379 pci_iounmap(dev, regs);
3381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3390 * PCI devices which are on Intel chips can skip the 10ms delay
3391 * before entering D3 mode.
3393 static void quirk_remove_d3_delay(struct pci_dev *dev)
3397 /* C600 Series devices do not need 10ms d3_delay */
3398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3401 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3413 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3425 * Some devices may pass our check in pci_intx_mask_supported() if
3426 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3427 * support this feature.
3429 static void quirk_broken_intx_masking(struct pci_dev *dev)
3431 dev->broken_intx_masking = 1;
3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3434 quirk_broken_intx_masking);
3435 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3436 quirk_broken_intx_masking);
3437 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3438 quirk_broken_intx_masking);
3441 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3442 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3444 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3447 quirk_broken_intx_masking);
3450 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3451 * DisINTx can be set but the interrupt status bit is non-functional.
3453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3455 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3456 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3457 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3458 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3463 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3466 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3468 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3470 static u16 mellanox_broken_intx_devs[] = {
3471 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3472 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3473 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3474 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3475 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3476 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3477 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3478 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3479 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3480 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3481 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3482 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3483 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3484 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3487 #define CONNECTX_4_CURR_MAX_MINOR 99
3488 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3491 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3492 * If so, don't mark it as broken.
3493 * FW minor > 99 means older FW version format and no INTx masking support.
3494 * FW minor < 14 means new FW version format and no INTx masking support.
3496 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3498 __be32 __iomem *fw_ver;
3506 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3507 if (pdev->device == mellanox_broken_intx_devs[i]) {
3508 pdev->broken_intx_masking = 1;
3514 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3515 * support so shouldn't be checked further
3517 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3520 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3521 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3524 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3525 if (pci_enable_device_mem(pdev)) {
3526 pci_warn(pdev, "Can't enable device memory\n");
3530 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3532 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3536 /* Reading from resource space should be 32b aligned */
3537 fw_maj_min = ioread32be(fw_ver);
3538 fw_sub_min = ioread32be(fw_ver + 1);
3539 fw_major = fw_maj_min & 0xffff;
3540 fw_minor = fw_maj_min >> 16;
3541 fw_subminor = fw_sub_min & 0xffff;
3542 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3543 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3544 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3545 fw_major, fw_minor, fw_subminor, pdev->device ==
3546 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3547 pdev->broken_intx_masking = 1;
3553 pci_disable_device(pdev);
3555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3556 mellanox_check_broken_intx_masking);
3558 static void quirk_no_bus_reset(struct pci_dev *dev)
3560 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3564 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3565 * prevented for those affected devices.
3567 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3569 if ((dev->device & 0xffc0) == 0x2340)
3570 quirk_no_bus_reset(dev);
3572 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3573 quirk_nvidia_no_bus_reset);
3576 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3577 * The device will throw a Link Down error on AER-capable systems and
3578 * regardless of AER, config space of the device is never accessible again
3579 * and typically causes the system to hang or reset when access is attempted.
3580 * http://www.spinics.net/lists/linux-pci/msg34797.html
3582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3584 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3590 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3591 * reset when used with certain child devices. After the reset, config
3592 * accesses to the child may fail.
3594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3597 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3598 * automatically disables LTSSM when Secondary Bus Reset is received and
3599 * the device stops working. Prevent bus reset for these devices. With
3600 * this change, the device can be assigned to VMs with VFIO, but it will
3601 * leak state between VMs. Reference
3602 * https://e2e.ti.com/support/processors/f/791/t/954382
3604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3606 static void quirk_no_pm_reset(struct pci_dev *dev)
3609 * We can't do a bus reset on root bus devices, but an ineffective
3610 * PM reset may be better than nothing.
3612 if (!pci_is_root_bus(dev->bus))
3613 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3617 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3618 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3619 * to have no effect on the device: it retains the framebuffer contents and
3620 * monitor sync. Advertising this support makes other layers, like VFIO,
3621 * assume pci_reset_function() is viable for this device. Mark it as
3622 * unavailable to skip it when testing reset methods.
3624 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3625 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3628 * Thunderbolt controllers with broken MSI hotplug signaling:
3629 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3630 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3632 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3634 if (pdev->is_hotplug_bridge &&
3635 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3636 pdev->revision <= 1))
3639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3640 quirk_thunderbolt_hotplug_msi);
3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3642 quirk_thunderbolt_hotplug_msi);
3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3644 quirk_thunderbolt_hotplug_msi);
3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3646 quirk_thunderbolt_hotplug_msi);
3647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3648 quirk_thunderbolt_hotplug_msi);
3652 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3654 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3655 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3656 * be present after resume if a device was plugged in before suspend.
3658 * The Thunderbolt controller consists of a PCIe switch with downstream
3659 * bridges leading to the NHI and to the tunnel PCI bridges.
3661 * This quirk cuts power to the whole chip. Therefore we have to apply it
3662 * during suspend_noirq of the upstream bridge.
3664 * Power is automagically restored before resume. No action is needed.
3666 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3668 acpi_handle bridge, SXIO, SXFP, SXLV;
3670 if (!x86_apple_machine)
3672 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3676 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3677 * We don't know how to turn it back on again, but firmware does,
3678 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3681 if (!pm_suspend_via_firmware())
3684 bridge = ACPI_HANDLE(&dev->dev);
3689 * SXIO and SXLV are present only on machines requiring this quirk.
3690 * Thunderbolt bridges in external devices might have the same
3691 * device ID as those on the host, but they will not have the
3692 * associated ACPI methods. This implicitly checks that we are at
3695 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3696 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3697 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3699 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3701 /* magic sequence */
3702 acpi_execute_simple_method(SXIO, NULL, 1);
3703 acpi_execute_simple_method(SXFP, NULL, 0);
3705 acpi_execute_simple_method(SXLV, NULL, 0);
3706 acpi_execute_simple_method(SXIO, NULL, 0);
3707 acpi_execute_simple_method(SXLV, NULL, 0);
3709 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3710 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3711 quirk_apple_poweroff_thunderbolt);
3714 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3716 * During suspend the Thunderbolt controller is reset and all PCI
3717 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3718 * during resume. We have to manually wait for the NHI since there is
3719 * no parent child relationship between the NHI and the tunneled
3722 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3724 struct pci_dev *sibling = NULL;
3725 struct pci_dev *nhi = NULL;
3727 if (!x86_apple_machine)
3729 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3733 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3734 * host controller and not on a Thunderbolt endpoint.
3736 sibling = pci_get_slot(dev->bus, 0x0);
3738 goto out; /* we are the downstream bridge to the NHI */
3739 if (!sibling || !sibling->subordinate)
3741 nhi = pci_get_slot(sibling->subordinate, 0x0);
3744 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3745 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3746 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3747 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3748 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3749 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3751 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3752 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3755 pci_dev_put(sibling);
3757 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3758 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3759 quirk_apple_wait_for_thunderbolt);
3760 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3761 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3762 quirk_apple_wait_for_thunderbolt);
3763 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3764 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3765 quirk_apple_wait_for_thunderbolt);
3766 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3767 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3768 quirk_apple_wait_for_thunderbolt);
3772 * Following are device-specific reset methods which can be used to
3773 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3776 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3779 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3781 * The 82599 supports FLR on VFs, but FLR support is reported only
3782 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3783 * Thus we must call pcie_flr() directly without first checking if it is
3791 #define SOUTH_CHICKEN2 0xc2004
3792 #define PCH_PP_STATUS 0xc7200
3793 #define PCH_PP_CONTROL 0xc7204
3794 #define MSG_CTL 0x45010
3795 #define NSDE_PWR_STATE 0xd0100
3796 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3798 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3800 void __iomem *mmio_base;
3801 unsigned long timeout;
3807 mmio_base = pci_iomap(dev, 0, 0);
3811 iowrite32(0x00000002, mmio_base + MSG_CTL);
3814 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3815 * driver loaded sets the right bits. However, this's a reset and
3816 * the bits have been set by i915 previously, so we clobber
3817 * SOUTH_CHICKEN2 register directly here.
3819 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3821 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3822 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3824 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3826 val = ioread32(mmio_base + PCH_PP_STATUS);
3827 if ((val & 0xb0000000) == 0)
3828 goto reset_complete;
3830 } while (time_before(jiffies, timeout));
3831 pci_warn(dev, "timeout during reset\n");
3834 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3836 pci_iounmap(dev, mmio_base);
3840 /* Device-specific reset method for Chelsio T4-based adapters */
3841 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3847 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3848 * that we have no device-specific reset method.
3850 if ((dev->device & 0xf000) != 0x4000)
3854 * If this is the "probe" phase, return 0 indicating that we can
3855 * reset this device.
3861 * T4 can wedge if there are DMAs in flight within the chip and Bus
3862 * Master has been disabled. We need to have it on till the Function
3863 * Level Reset completes. (BUS_MASTER is disabled in
3864 * pci_reset_function()).
3866 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3867 pci_write_config_word(dev, PCI_COMMAND,
3868 old_command | PCI_COMMAND_MASTER);
3871 * Perform the actual device function reset, saving and restoring
3872 * configuration information around the reset.
3874 pci_save_state(dev);
3877 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3878 * are disabled when an MSI-X interrupt message needs to be delivered.
3879 * So we briefly re-enable MSI-X interrupts for the duration of the
3880 * FLR. The pci_restore_state() below will restore the original
3883 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3884 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3885 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3887 PCI_MSIX_FLAGS_ENABLE |
3888 PCI_MSIX_FLAGS_MASKALL);
3893 * Restore the configuration information (BAR values, etc.) including
3894 * the original PCI Configuration Space Command word, and return
3897 pci_restore_state(dev);
3898 pci_write_config_word(dev, PCI_COMMAND, old_command);
3902 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3903 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3904 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3907 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3908 * FLR where config space reads from the device return -1. We seem to be
3909 * able to avoid this condition if we disable the NVMe controller prior to
3910 * FLR. This quirk is generic for any NVMe class device requiring similar
3911 * assistance to quiesce the device prior to FLR.
3913 * NVMe specification: https://nvmexpress.org/resources/specifications/
3915 * Chapter 2: Required and optional PCI config registers
3916 * Chapter 3: NVMe control registers
3917 * Chapter 7.3: Reset behavior
3919 static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3925 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3926 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3932 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3936 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3937 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3939 cfg = readl(bar + NVME_REG_CC);
3941 /* Disable controller if enabled */
3942 if (cfg & NVME_CC_ENABLE) {
3943 u32 cap = readl(bar + NVME_REG_CAP);
3944 unsigned long timeout;
3947 * Per nvme_disable_ctrl() skip shutdown notification as it
3948 * could complete commands to the admin queue. We only intend
3949 * to quiesce the device before reset.
3951 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3953 writel(cfg, bar + NVME_REG_CC);
3956 * Some controllers require an additional delay here, see
3957 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3958 * supported by this quirk.
3961 /* Cap register provides max timeout in 500ms increments */
3962 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3965 u32 status = readl(bar + NVME_REG_CSTS);
3967 /* Ready status becomes zero on disable complete */
3968 if (!(status & NVME_CSTS_RDY))
3973 if (time_after(jiffies, timeout)) {
3974 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3980 pci_iounmap(dev, bar);
3988 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3989 * to change after NVMe enable if the driver starts interacting with the
3990 * device too soon after FLR. A 250ms delay after FLR has heuristically
3991 * proven to produce reliably working results for device assignment cases.
3993 static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3995 if (!pcie_has_flr(dev))
4008 #define PCI_DEVICE_ID_HINIC_VF 0x375E
4009 #define HINIC_VF_FLR_TYPE 0x1000
4010 #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
4011 #define HINIC_VF_OP 0xE80
4012 #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
4013 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
4015 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4016 static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe)
4018 unsigned long timeout;
4025 bar = pci_iomap(pdev, 0, 0);
4029 /* Get and check firmware capabilities */
4030 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4031 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4032 pci_iounmap(pdev, bar);
4036 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
4037 val = ioread32be(bar + HINIC_VF_OP);
4038 val = val | HINIC_VF_FLR_PROC_BIT;
4039 iowrite32be(val, bar + HINIC_VF_OP);
4044 * The device must recapture its Bus and Device Numbers after FLR
4045 * in order generate Completions. Issue a config write to let the
4046 * device capture this information.
4048 pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
4050 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
4051 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
4053 val = ioread32be(bar + HINIC_VF_OP);
4054 if (!(val & HINIC_VF_FLR_PROC_BIT))
4055 goto reset_complete;
4057 } while (time_before(jiffies, timeout));
4059 val = ioread32be(bar + HINIC_VF_OP);
4060 if (!(val & HINIC_VF_FLR_PROC_BIT))
4061 goto reset_complete;
4063 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
4066 pci_iounmap(pdev, bar);
4071 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4072 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4073 reset_intel_82599_sfp_virtfn },
4074 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4076 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4078 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4079 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4080 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4081 reset_chelsio_generic_dev },
4082 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4083 reset_hinic_vf_dev },
4088 * These device-specific reset methods are here rather than in a driver
4089 * because when a host assigns a device to a guest VM, the host may need
4090 * to reset the device but probably doesn't have a driver for it.
4092 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
4094 const struct pci_dev_reset_methods *i;
4096 for (i = pci_dev_reset_methods; i->reset; i++) {
4097 if ((i->vendor == dev->vendor ||
4098 i->vendor == (u16)PCI_ANY_ID) &&
4099 (i->device == dev->device ||
4100 i->device == (u16)PCI_ANY_ID))
4101 return i->reset(dev, probe);
4107 static void quirk_dma_func0_alias(struct pci_dev *dev)
4109 if (PCI_FUNC(dev->devfn) != 0)
4110 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4114 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4116 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4121 static void quirk_dma_func1_alias(struct pci_dev *dev)
4123 if (PCI_FUNC(dev->devfn) != 1)
4124 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4128 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4129 * SKUs function 1 is present and is a legacy IDE controller, in other
4130 * SKUs this function is not present, making this a ghost requester.
4131 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4134 quirk_dma_func1_alias);
4135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4136 quirk_dma_func1_alias);
4137 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4139 quirk_dma_func1_alias);
4140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4141 quirk_dma_func1_alias);
4142 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4144 quirk_dma_func1_alias);
4145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4146 quirk_dma_func1_alias);
4147 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4149 quirk_dma_func1_alias);
4150 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4152 quirk_dma_func1_alias);
4153 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4155 quirk_dma_func1_alias);
4156 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4158 quirk_dma_func1_alias);
4159 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4161 quirk_dma_func1_alias);
4162 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4164 quirk_dma_func1_alias);
4165 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4167 quirk_dma_func1_alias);
4168 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4170 quirk_dma_func1_alias);
4171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4172 quirk_dma_func1_alias);
4173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4174 quirk_dma_func1_alias);
4175 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4177 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4178 quirk_dma_func1_alias);
4179 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4180 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4181 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4182 quirk_dma_func1_alias);
4185 * Some devices DMA with the wrong devfn, not just the wrong function.
4186 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4187 * the alias is "fixed" and independent of the device devfn.
4189 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4190 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4191 * single device on the secondary bus. In reality, the single exposed
4192 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4193 * that provides a bridge to the internal bus of the I/O processor. The
4194 * controller supports private devices, which can be hidden from PCI config
4195 * space. In the case of the Adaptec 3405, a private device at 01.0
4196 * appears to be the DMA engine, which therefore needs to become a DMA
4197 * alias for the device.
4199 static const struct pci_device_id fixed_dma_alias_tbl[] = {
4200 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4201 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4202 .driver_data = PCI_DEVFN(1, 0) },
4203 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4204 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4205 .driver_data = PCI_DEVFN(1, 0) },
4209 static void quirk_fixed_dma_alias(struct pci_dev *dev)
4211 const struct pci_device_id *id;
4213 id = pci_match_id(fixed_dma_alias_tbl, dev);
4215 pci_add_dma_alias(dev, id->driver_data, 1);
4218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4221 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4222 * using the wrong DMA alias for the device. Some of these devices can be
4223 * used as either forward or reverse bridges, so we need to test whether the
4224 * device is operating in the correct mode. We could probably apply this
4225 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4226 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4227 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4229 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4231 if (!pci_is_root_bus(pdev->bus) &&
4232 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4233 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4234 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4235 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4237 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4239 quirk_use_pcie_bridge_dma_alias);
4240 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4241 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4242 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4243 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4244 /* ITE 8893 has the same problem as the 8892 */
4245 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4246 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4247 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4250 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4251 * be added as aliases to the DMA device in order to allow buffer access
4252 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4253 * programmed in the EEPROM.
4255 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4257 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4258 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4259 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4265 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4266 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4268 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4269 * when IOMMU is enabled. These aliases allow computational unit access to
4270 * host memory. These aliases mark the whole VCA device as one IOMMU
4273 * All possible slot numbers (0x20) are used, since we are unable to tell
4274 * what slot is used on other side. This quirk is intended for both host
4275 * and computational unit sides. The VCA devices have up to five functions
4276 * (four for DMA channels and one additional).
4278 static void quirk_pex_vca_alias(struct pci_dev *pdev)
4280 const unsigned int num_pci_slots = 0x20;
4283 for (slot = 0; slot < num_pci_slots; slot++)
4284 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4294 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4295 * associated not at the root bus, but at a bridge below. This quirk avoids
4296 * generating invalid DMA aliases.
4298 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4300 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4303 quirk_bridge_cavm_thrx2_pcie_root);
4304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4305 quirk_bridge_cavm_thrx2_pcie_root);
4308 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4309 * class code. Fix it.
4311 static void quirk_tw686x_class(struct pci_dev *pdev)
4313 u32 class = pdev->class;
4315 /* Use "Multimedia controller" class */
4316 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4317 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4318 class, pdev->class);
4320 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4321 quirk_tw686x_class);
4322 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4323 quirk_tw686x_class);
4324 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4325 quirk_tw686x_class);
4326 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4327 quirk_tw686x_class);
4330 * Some devices have problems with Transaction Layer Packets with the Relaxed
4331 * Ordering Attribute set. Such devices should mark themselves and other
4332 * device drivers should check before sending TLPs with RO set.
4334 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4336 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4337 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4341 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4342 * Complex have a Flow Control Credit issue which can cause performance
4343 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4345 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4346 quirk_relaxedordering_disable);
4347 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4348 quirk_relaxedordering_disable);
4349 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4350 quirk_relaxedordering_disable);
4351 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4352 quirk_relaxedordering_disable);
4353 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4354 quirk_relaxedordering_disable);
4355 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4356 quirk_relaxedordering_disable);
4357 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4358 quirk_relaxedordering_disable);
4359 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4360 quirk_relaxedordering_disable);
4361 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4362 quirk_relaxedordering_disable);
4363 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4364 quirk_relaxedordering_disable);
4365 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4366 quirk_relaxedordering_disable);
4367 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4368 quirk_relaxedordering_disable);
4369 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4370 quirk_relaxedordering_disable);
4371 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4372 quirk_relaxedordering_disable);
4373 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4374 quirk_relaxedordering_disable);
4375 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4376 quirk_relaxedordering_disable);
4377 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4378 quirk_relaxedordering_disable);
4379 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4380 quirk_relaxedordering_disable);
4381 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4382 quirk_relaxedordering_disable);
4383 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4384 quirk_relaxedordering_disable);
4385 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4386 quirk_relaxedordering_disable);
4387 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4388 quirk_relaxedordering_disable);
4389 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4390 quirk_relaxedordering_disable);
4391 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4392 quirk_relaxedordering_disable);
4393 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4394 quirk_relaxedordering_disable);
4395 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4396 quirk_relaxedordering_disable);
4397 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4398 quirk_relaxedordering_disable);
4399 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4400 quirk_relaxedordering_disable);
4403 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4404 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4405 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4406 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4407 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4408 * November 10, 2010). As a result, on this platform we can't use Relaxed
4409 * Ordering for Upstream TLPs.
4411 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4412 quirk_relaxedordering_disable);
4413 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4414 quirk_relaxedordering_disable);
4415 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4416 quirk_relaxedordering_disable);
4419 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4420 * values for the Attribute as were supplied in the header of the
4421 * corresponding Request, except as explicitly allowed when IDO is used."
4423 * If a non-compliant device generates a completion with a different
4424 * attribute than the request, the receiver may accept it (which itself
4425 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4426 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4427 * device access timeout.
4429 * If the non-compliant device generates completions with zero attributes
4430 * (instead of copying the attributes from the request), we can work around
4431 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4432 * upstream devices so they always generate requests with zero attributes.
4434 * This affects other devices under the same Root Port, but since these
4435 * attributes are performance hints, there should be no functional problem.
4437 * Note that Configuration Space accesses are never supposed to have TLP
4438 * Attributes, so we're safe waiting till after any Configuration Space
4439 * accesses to do the Root Port fixup.
4441 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4443 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4446 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4450 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4451 dev_name(&pdev->dev));
4452 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4453 PCI_EXP_DEVCTL_RELAX_EN |
4454 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4458 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4459 * Completion it generates.
4461 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4464 * This mask/compare operation selects for Physical Function 4 on a
4465 * T5. We only need to fix up the Root Port once for any of the
4466 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4467 * 0x54xx so we use that one.
4469 if ((pdev->device & 0xff00) == 0x5400)
4470 quirk_disable_root_port_attributes(pdev);
4472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4473 quirk_chelsio_T5_disable_root_port_attributes);
4476 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4478 * @acs_ctrl_req: Bitmask of desired ACS controls
4479 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4480 * the hardware design
4482 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4483 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4484 * caller desires. Return 0 otherwise.
4486 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4488 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4494 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4495 * But the implementation could block peer-to-peer transactions between them
4496 * and provide ACS-like functionality.
4498 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4500 if (!pci_is_pcie(dev) ||
4501 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4502 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4505 switch (dev->device) {
4506 case 0x0710 ... 0x071e:
4508 case 0x0723 ... 0x0732:
4509 return pci_acs_ctrl_enabled(acs_flags,
4510 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4517 * AMD has indicated that the devices below do not support peer-to-peer
4518 * in any system where they are found in the southbridge with an AMD
4519 * IOMMU in the system. Multifunction devices that do not support
4520 * peer-to-peer between functions can claim to support a subset of ACS.
4521 * Such devices effectively enable request redirect (RR) and completion
4522 * redirect (CR) since all transactions are redirected to the upstream
4525 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4526 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4527 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4529 * 1002:4385 SBx00 SMBus Controller
4530 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4531 * 1002:4383 SBx00 Azalia (Intel HDA)
4532 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4533 * 1002:4384 SBx00 PCI to PCI Bridge
4534 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4536 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4538 * 1022:780f [AMD] FCH PCI Bridge
4539 * 1022:7809 [AMD] FCH USB OHCI Controller
4541 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4544 struct acpi_table_header *header = NULL;
4547 /* Targeting multifunction devices on the SB (appears on root bus) */
4548 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4551 /* The IVRS table describes the AMD IOMMU */
4552 status = acpi_get_table("IVRS", 0, &header);
4553 if (ACPI_FAILURE(status))
4556 acpi_put_table(header);
4558 /* Filter out flags not applicable to multifunction */
4559 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4561 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4567 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4569 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4572 switch (dev->device) {
4574 * Effectively selects all downstream ports for whole ThunderX1
4575 * (which represents 8 SoCs).
4577 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4578 case 0xaf84: /* ThunderX2 */
4579 case 0xb884: /* ThunderX3 */
4586 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4588 if (!pci_quirk_cavium_acs_match(dev))
4592 * Cavium Root Ports don't advertise an ACS capability. However,
4593 * the RTL internally implements similar protection as if ACS had
4594 * Source Validation, Request Redirection, Completion Redirection,
4595 * and Upstream Forwarding features enabled. Assert that the
4596 * hardware implements and enables equivalent ACS functionality for
4599 return pci_acs_ctrl_enabled(acs_flags,
4600 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4603 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4606 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4607 * transactions with others, allowing masking out these bits as if they
4608 * were unimplemented in the ACS capability.
4610 return pci_acs_ctrl_enabled(acs_flags,
4611 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4615 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4616 * transactions and validate bus numbers in requests, but do not provide an
4617 * actual PCIe ACS capability. This is the list of device IDs known to fall
4618 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4620 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4622 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4623 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4624 /* Cougarpoint PCH */
4625 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4626 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4627 /* Pantherpoint PCH */
4628 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4629 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4630 /* Lynxpoint-H PCH */
4631 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4632 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4633 /* Lynxpoint-LP PCH */
4634 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4635 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4637 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4638 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4639 /* Patsburg (X79) PCH */
4640 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4641 /* Wellsburg (X99) PCH */
4642 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4643 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4644 /* Lynx Point (9 series) PCH */
4645 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4648 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4652 /* Filter out a few obvious non-matches first */
4653 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4656 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4657 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4663 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4665 if (!pci_quirk_intel_pch_acs_match(dev))
4668 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4669 return pci_acs_ctrl_enabled(acs_flags,
4670 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4672 return pci_acs_ctrl_enabled(acs_flags, 0);
4676 * These QCOM Root Ports do provide ACS-like features to disable peer
4677 * transactions and validate bus numbers in requests, but do not provide an
4678 * actual PCIe ACS capability. Hardware supports source validation but it
4679 * will report the issue as Completer Abort instead of ACS Violation.
4680 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4681 * Complex with unique segment numbers. It is not possible for one Root
4682 * Port to pass traffic to another Root Port. All PCIe transactions are
4683 * terminated inside the Root Port.
4685 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4687 return pci_acs_ctrl_enabled(acs_flags,
4688 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4692 * Each of these NXP Root Ports is in a Root Complex with a unique segment
4693 * number and does provide isolation features to disable peer transactions
4694 * and validate bus numbers in requests, but does not provide an ACS
4697 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4699 return pci_acs_ctrl_enabled(acs_flags,
4700 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4703 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4705 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4709 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4710 * but do include ACS-like functionality. The hardware doesn't support
4711 * peer-to-peer transactions via the root port and each has a unique
4714 * Additionally, the root ports cannot send traffic to each other.
4716 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4718 return acs_flags ? 0 : 1;
4722 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4723 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4724 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4725 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4726 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4727 * control register is at offset 8 instead of 6 and we should probably use
4728 * dword accesses to them. This applies to the following PCI Device IDs, as
4729 * found in volume 1 of the datasheet[2]:
4731 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4732 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4734 * N.B. This doesn't fix what lspci shows.
4736 * The 100 series chipset specification update includes this as errata #23[3].
4738 * The 200 series chipset (Union Point) has the same bug according to the
4739 * specification update (Intel 200 Series Chipset Family Platform Controller
4740 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4741 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4744 * 0xa290-0xa29f PCI Express Root port #{0-16}
4745 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4747 * Mobile chipsets are also affected, 7th & 8th Generation
4748 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4749 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4750 * Processor Family I/O for U Quad Core Platforms Specification Update,
4751 * August 2017, Revision 002, Document#: 334660-002)[6]
4752 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4753 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4754 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4756 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4758 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4759 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4760 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4761 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4762 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4763 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4764 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4766 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4768 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4771 switch (dev->device) {
4772 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4773 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4774 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4781 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4783 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4788 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4791 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4795 /* see pci_acs_flags_enabled() */
4796 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4797 acs_flags &= (cap | PCI_ACS_EC);
4799 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4801 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4804 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4807 * SV, TB, and UF are not relevant to multifunction endpoints.
4809 * Multifunction devices are only required to implement RR, CR, and DT
4810 * in their ACS capability if they support peer-to-peer transactions.
4811 * Devices matching this quirk have been verified by the vendor to not
4812 * perform peer-to-peer with other functions, allowing us to mask out
4813 * these bits as if they were unimplemented in the ACS capability.
4815 return pci_acs_ctrl_enabled(acs_flags,
4816 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4817 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4820 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4823 * Intel RCiEP's are required to allow p2p only on translated
4824 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4825 * "Root-Complex Peer to Peer Considerations".
4827 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4830 return pci_acs_ctrl_enabled(acs_flags,
4831 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4834 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4837 * iProc PAXB Root Ports don't advertise an ACS capability, but
4838 * they do not allow peer-to-peer transactions between Root Ports.
4839 * Allow each Root Port to be in a separate IOMMU group by masking
4842 return pci_acs_ctrl_enabled(acs_flags,
4843 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4847 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4848 * devices, peer-to-peer transactions are not be used between the functions.
4849 * So add an ACS quirk for below devices to isolate functions.
4850 * SFxxx 1G NICs(em).
4851 * RP1000/RP2000 10G NICs(sp).
4853 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
4855 switch (dev->device) {
4856 case 0x0100 ... 0x010F:
4859 return pci_acs_ctrl_enabled(acs_flags,
4860 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4866 static const struct pci_dev_acs_enabled {
4869 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4870 } pci_dev_acs_enabled[] = {
4871 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4872 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4873 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4874 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4875 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4876 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4877 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4878 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4879 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4880 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4881 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4882 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4883 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4884 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4885 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4886 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4887 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4888 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4889 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4890 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4891 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4892 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4893 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4894 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4895 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4896 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4897 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4898 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4899 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4900 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4901 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4903 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4904 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4905 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4906 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4907 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4908 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4909 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4911 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4912 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4913 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4914 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4915 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4916 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4917 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4918 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4920 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4921 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4922 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4924 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4925 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4926 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4927 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4928 /* 82571 (Quads omitted due to non-ACS switch) */
4929 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4930 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4931 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4932 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4934 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4935 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4936 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4937 /* QCOM QDF2xxx root ports */
4938 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4939 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4940 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4941 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4942 /* Intel PCH root ports */
4943 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4944 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4945 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4946 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4947 /* Cavium ThunderX */
4948 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4949 /* Cavium multi-function devices */
4950 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4951 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4952 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4954 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4955 /* Ampere Computing */
4956 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4957 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4958 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4959 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4960 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4961 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4962 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4963 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4964 /* Broadcom multi-function device */
4965 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4966 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
4967 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
4968 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
4969 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4970 /* Amazon Annapurna Labs */
4971 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4972 /* Zhaoxin multi-function devices */
4973 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4974 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4975 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4976 /* NXP root ports, xx=16, 12, or 08 cores */
4977 /* LX2xx0A : without security features + CAN-FD */
4978 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
4979 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
4980 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
4981 /* LX2xx0C : security features + CAN-FD */
4982 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
4983 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
4984 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
4985 /* LX2xx0E : security features + CAN */
4986 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
4987 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
4988 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
4989 /* LX2xx0N : without security features + CAN */
4990 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
4991 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
4992 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
4993 /* LX2xx2A : without security features + CAN-FD */
4994 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
4995 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
4996 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
4997 /* LX2xx2C : security features + CAN-FD */
4998 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
4999 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
5000 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
5001 /* LX2xx2E : security features + CAN */
5002 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
5003 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
5004 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
5005 /* LX2xx2N : without security features + CAN */
5006 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
5007 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
5008 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
5009 /* Zhaoxin Root/Downstream Ports */
5010 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
5012 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
5017 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5019 * @acs_flags: Bitmask of desired ACS controls
5022 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5023 * device provides the desired controls
5024 * 0: Device does not provide all the desired controls
5025 * >0: Device provides all the controls in @acs_flags
5027 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
5029 const struct pci_dev_acs_enabled *i;
5033 * Allow devices that do not expose standard PCIe ACS capabilities
5034 * or control to indicate their support here. Multi-function express
5035 * devices which do not allow internal peer-to-peer between functions,
5036 * but do not implement PCIe ACS may wish to return true here.
5038 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
5039 if ((i->vendor == dev->vendor ||
5040 i->vendor == (u16)PCI_ANY_ID) &&
5041 (i->device == dev->device ||
5042 i->device == (u16)PCI_ANY_ID)) {
5043 ret = i->acs_enabled(dev, acs_flags);
5052 /* Config space offset of Root Complex Base Address register */
5053 #define INTEL_LPC_RCBA_REG 0xf0
5054 /* 31:14 RCBA address */
5055 #define INTEL_LPC_RCBA_MASK 0xffffc000
5057 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5059 /* Backbone Scratch Pad Register */
5060 #define INTEL_BSPR_REG 0x1104
5061 /* Backbone Peer Non-Posted Disable */
5062 #define INTEL_BSPR_REG_BPNPD (1 << 8)
5063 /* Backbone Peer Posted Disable */
5064 #define INTEL_BSPR_REG_BPPD (1 << 9)
5066 /* Upstream Peer Decode Configuration Register */
5067 #define INTEL_UPDCR_REG 0x1014
5068 /* 5:0 Peer Decode Enable bits */
5069 #define INTEL_UPDCR_REG_MASK 0x3f
5071 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
5073 u32 rcba, bspr, updcr;
5074 void __iomem *rcba_mem;
5077 * Read the RCBA register from the LPC (D31:F0). PCH root ports
5078 * are D28:F* and therefore get probed before LPC, thus we can't
5079 * use pci_get_slot()/pci_read_config_dword() here.
5081 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
5082 INTEL_LPC_RCBA_REG, &rcba);
5083 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
5086 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
5087 PAGE_ALIGN(INTEL_UPDCR_REG));
5092 * The BSPR can disallow peer cycles, but it's set by soft strap and
5093 * therefore read-only. If both posted and non-posted peer cycles are
5094 * disallowed, we're ok. If either are allowed, then we need to use
5095 * the UPDCR to disable peer decodes for each port. This provides the
5096 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5098 bspr = readl(rcba_mem + INTEL_BSPR_REG);
5099 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5100 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5101 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
5102 if (updcr & INTEL_UPDCR_REG_MASK) {
5103 pci_info(dev, "Disabling UPDCR peer decodes\n");
5104 updcr &= ~INTEL_UPDCR_REG_MASK;
5105 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
5113 /* Miscellaneous Port Configuration register */
5114 #define INTEL_MPC_REG 0xd8
5115 /* MPC: Invalid Receive Bus Number Check Enable */
5116 #define INTEL_MPC_REG_IRBNCE (1 << 26)
5118 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5123 * When enabled, the IRBNCE bit of the MPC register enables the
5124 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5125 * ensures that requester IDs fall within the bus number range
5126 * of the bridge. Enable if not already.
5128 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
5129 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5130 pci_info(dev, "Enabling MPC IRBNCE\n");
5131 mpc |= INTEL_MPC_REG_IRBNCE;
5132 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
5136 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5138 if (!pci_quirk_intel_pch_acs_match(dev))
5141 if (pci_quirk_enable_intel_lpc_acs(dev)) {
5142 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5146 pci_quirk_enable_intel_rp_mpc_acs(dev);
5148 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5150 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5155 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5160 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5163 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
5167 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5168 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5170 ctrl |= (cap & PCI_ACS_SV);
5171 ctrl |= (cap & PCI_ACS_RR);
5172 ctrl |= (cap & PCI_ACS_CR);
5173 ctrl |= (cap & PCI_ACS_UF);
5175 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5177 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5182 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5187 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5190 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
5194 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5195 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5197 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5199 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5201 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5206 static const struct pci_dev_acs_ops {
5209 int (*enable_acs)(struct pci_dev *dev);
5210 int (*disable_acs_redir)(struct pci_dev *dev);
5211 } pci_dev_acs_ops[] = {
5212 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5213 .enable_acs = pci_quirk_enable_intel_pch_acs,
5215 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5216 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5217 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5221 int pci_dev_specific_enable_acs(struct pci_dev *dev)
5223 const struct pci_dev_acs_ops *p;
5226 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5227 p = &pci_dev_acs_ops[i];
5228 if ((p->vendor == dev->vendor ||
5229 p->vendor == (u16)PCI_ANY_ID) &&
5230 (p->device == dev->device ||
5231 p->device == (u16)PCI_ANY_ID) &&
5233 ret = p->enable_acs(dev);
5242 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5244 const struct pci_dev_acs_ops *p;
5247 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5248 p = &pci_dev_acs_ops[i];
5249 if ((p->vendor == dev->vendor ||
5250 p->vendor == (u16)PCI_ANY_ID) &&
5251 (p->device == dev->device ||
5252 p->device == (u16)PCI_ANY_ID) &&
5253 p->disable_acs_redir) {
5254 ret = p->disable_acs_redir(dev);
5264 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5265 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5266 * Next Capability pointer in the MSI Capability Structure should point to
5267 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5270 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5275 struct pci_cap_saved_state *state;
5277 /* Bail if the hardware bug is fixed */
5278 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5281 /* Bail if MSI Capability Structure is not found for some reason */
5282 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5287 * Bail if Next Capability pointer in the MSI Capability Structure
5288 * is not the expected incorrect 0x00.
5290 pci_read_config_byte(pdev, pos + 1, &next_cap);
5295 * PCIe Capability Structure is expected to be at 0x50 and should
5296 * terminate the list (Next Capability pointer is 0x00). Verify
5297 * Capability Id and Next Capability pointer is as expected.
5298 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5299 * to correctly set kernel data structures which have already been
5300 * set incorrectly due to the hardware bug.
5303 pci_read_config_word(pdev, pos, ®16);
5304 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5306 #ifndef PCI_EXP_SAVE_REGS
5307 #define PCI_EXP_SAVE_REGS 7
5309 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5311 pdev->pcie_cap = pos;
5312 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5313 pdev->pcie_flags_reg = reg16;
5314 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5315 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5317 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5318 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5319 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5320 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5322 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5326 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5330 state->cap.cap_nr = PCI_CAP_ID_EXP;
5331 state->cap.cap_extended = 0;
5332 state->cap.size = size;
5333 cap = (u16 *)&state->cap.data[0];
5334 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5335 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5336 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5337 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5338 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5339 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5340 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5341 hlist_add_head(&state->next, &pdev->saved_cap_space);
5344 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5347 * FLR may cause the following to devices to hang:
5349 * AMD Starship/Matisse HD Audio Controller 0x1487
5350 * AMD Starship USB 3.0 Host Controller 0x148c
5351 * AMD Matisse USB 3.0 Host Controller 0x149c
5352 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5353 * Intel 82579V Gigabit Ethernet Controller 0x1503
5356 static void quirk_no_flr(struct pci_dev *dev)
5358 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5360 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5361 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5362 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5363 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5364 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5365 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5367 static void quirk_no_ext_tags(struct pci_dev *pdev)
5369 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5374 bridge->no_ext_tags = 1;
5375 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5377 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5379 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5380 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5381 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5382 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5383 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5384 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5385 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5387 #ifdef CONFIG_PCI_ATS
5389 * Some devices require additional driver setup to enable ATS. Don't use
5390 * ATS for those devices as ATS will be enabled before the driver has had a
5391 * chance to load and configure the device.
5393 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5395 if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
5396 (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
5397 (pdev->device == 0x7341 && pdev->revision != 0x00))
5400 pci_info(pdev, "disabling ATS\n");
5404 /* AMD Stoney platform GPU */
5405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5406 /* AMD Iceland dGPU */
5407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5408 /* AMD Navi10 dGPU */
5409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5410 /* AMD Navi14 dGPU */
5411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5413 #endif /* CONFIG_PCI_ATS */
5415 /* Freescale PCIe doesn't support MSI in RC mode */
5416 static void quirk_fsl_no_msi(struct pci_dev *pdev)
5418 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5424 * Although not allowed by the spec, some multi-function devices have
5425 * dependencies of one function (consumer) on another (supplier). For the
5426 * consumer to work in D0, the supplier must also be in D0. Create a
5427 * device link from the consumer to the supplier to enforce this
5428 * dependency. Runtime PM is allowed by default on the consumer to prevent
5429 * it from permanently keeping the supplier awake.
5431 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5432 unsigned int supplier, unsigned int class,
5433 unsigned int class_shift)
5435 struct pci_dev *supplier_pdev;
5437 if (PCI_FUNC(pdev->devfn) != consumer)
5440 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5442 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5443 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5444 pci_dev_put(supplier_pdev);
5448 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5449 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5450 pci_info(pdev, "D0 power state depends on %s\n",
5451 pci_name(supplier_pdev));
5453 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5454 pci_name(supplier_pdev));
5456 pm_runtime_allow(&pdev->dev);
5457 pci_dev_put(supplier_pdev);
5461 * Create device link for GPUs with integrated HDA controller for streaming
5462 * audio to attached displays.
5464 static void quirk_gpu_hda(struct pci_dev *hda)
5466 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5468 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5469 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5470 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5471 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5472 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5473 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5476 * Create device link for GPUs with integrated USB xHCI Host
5477 * controller to VGA.
5479 static void quirk_gpu_usb(struct pci_dev *usb)
5481 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5483 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5484 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5485 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5486 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5489 * Create device link for GPUs with integrated Type-C UCSI controller
5490 * to VGA. Currently there is no class code defined for UCSI device over PCI
5491 * so using UNKNOWN class for now and it will be updated when UCSI
5492 * over PCI gets a class code.
5494 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5495 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5497 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5499 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5500 PCI_CLASS_SERIAL_UNKNOWN, 8,
5501 quirk_gpu_usb_typec_ucsi);
5502 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5503 PCI_CLASS_SERIAL_UNKNOWN, 8,
5504 quirk_gpu_usb_typec_ucsi);
5507 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5508 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5510 static void quirk_nvidia_hda(struct pci_dev *gpu)
5515 /* There was no integrated HDA controller before MCP89 */
5516 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5519 /* Bit 25 at offset 0x488 enables the HDA controller */
5520 pci_read_config_dword(gpu, 0x488, &val);
5524 pci_info(gpu, "Enabling HDA controller\n");
5525 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5527 /* The GPU becomes a multi-function device when the HDA is enabled */
5528 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5529 gpu->multifunction = !!(hdr_type & 0x80);
5531 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5532 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5533 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5534 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5537 * Some IDT switches incorrectly flag an ACS Source Validation error on
5538 * completions for config read requests even though PCIe r4.0, sec
5539 * 6.12.1.1, says that completions are never affected by ACS Source
5540 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5542 * Item #36 - Downstream port applies ACS Source Validation to Completions
5543 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5544 * completions are never affected by ACS Source Validation. However,
5545 * completions received by a downstream port of the PCIe switch from a
5546 * device that has not yet captured a PCIe bus number are incorrectly
5547 * dropped by ACS Source Validation by the switch downstream port.
5549 * The workaround suggested by IDT is to issue a config write to the
5550 * downstream device before issuing the first config read. This allows the
5551 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5552 * sec 2.2.9), thus avoiding the ACS error on the completion.
5554 * However, we don't know when the device is ready to accept the config
5555 * write, so we do config reads until we receive a non-Config Request Retry
5556 * Status, then do the config write.
5558 * To avoid hitting the erratum when doing the config reads, we disable ACS
5559 * SV around this process.
5561 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5566 struct pci_dev *bridge = bus->self;
5568 pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
5570 /* Disable ACS SV before initial config reads */
5572 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5573 if (ctrl & PCI_ACS_SV)
5574 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5575 ctrl & ~PCI_ACS_SV);
5578 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5580 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5582 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5584 /* Re-enable ACS_SV if it was previously enabled */
5585 if (ctrl & PCI_ACS_SV)
5586 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5592 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5593 * NT endpoints via the internal switch fabric. These IDs replace the
5594 * originating requestor ID TLPs which access host memory on peer NTB
5595 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5596 * to permit access when the IOMMU is turned on.
5598 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5601 struct ntb_info_regs __iomem *mmio_ntb;
5602 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5607 if (pci_enable_device(pdev)) {
5608 pci_err(pdev, "Cannot enable Switchtec device\n");
5612 mmio = pci_iomap(pdev, 0, 0);
5614 pci_disable_device(pdev);
5615 pci_err(pdev, "Cannot iomap Switchtec device\n");
5619 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5621 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5622 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5624 partition = ioread8(&mmio_ntb->partition_id);
5626 partition_map = ioread32(&mmio_ntb->ep_map);
5627 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5628 partition_map &= ~(1ULL << partition);
5630 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5631 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5635 if (!(partition_map & (1ULL << pp)))
5638 pci_dbg(pdev, "Processing partition %d\n", pp);
5640 mmio_peer_ctrl = &mmio_ctrl[pp];
5642 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5644 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5648 if (table_sz > 512) {
5650 "Invalid Switchtec partition %d table_sz %d\n",
5655 for (te = 0; te < table_sz; te++) {
5659 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5660 devfn = (rid_entry >> 1) & 0xFF;
5662 "Aliasing Partition %d Proxy ID %02x.%d\n",
5663 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5664 pci_add_dma_alias(pdev, devfn, 1);
5668 pci_iounmap(pdev, mmio);
5669 pci_disable_device(pdev);
5671 #define SWITCHTEC_QUIRK(vid) \
5672 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5673 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5675 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5676 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5677 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5678 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5679 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5680 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5681 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5682 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5683 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5684 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5685 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5686 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5687 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5688 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5689 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5690 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5691 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5692 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5693 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5694 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5695 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5696 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5697 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5698 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5699 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5700 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5701 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5702 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5703 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5704 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5707 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5708 * These IDs are used to forward responses to the originator on the other
5709 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5710 * the IOMMU is turned on.
5712 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5714 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5715 /* PLX NTB may use all 256 devfns */
5716 pci_add_dma_alias(pdev, 0, 256);
5718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5722 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5723 * not always reset the secondary Nvidia GPU between reboots if the system
5724 * is configured to use Hybrid Graphics mode. This results in the GPU
5725 * being left in whatever state it was in during the *previous* boot, which
5726 * causes spurious interrupts from the GPU, which in turn causes us to
5727 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5728 * this also completely breaks nouveau.
5730 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5731 * clean state and fixes all these issues.
5733 * When the machine is configured in Dedicated display mode, the issue
5734 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5735 * mode, so we can detect that and avoid resetting it.
5737 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5742 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5743 pdev->subsystem_device != 0x222e ||
5747 if (pci_enable_device_mem(pdev))
5751 * Based on nvkm_device_ctor() in
5752 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5754 map = pci_iomap(pdev, 0, 0x23000);
5756 pci_err(pdev, "Can't map MMIO space\n");
5761 * Make sure the GPU looks like it's been POSTed before resetting
5764 if (ioread32(map + 0x2240c) & 0x2) {
5765 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5766 ret = pci_reset_bus(pdev);
5768 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5773 pci_disable_device(pdev);
5775 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5776 PCI_CLASS_DISPLAY_VGA, 8,
5777 quirk_reset_lenovo_thinkpad_p50_nvgpu);
5780 * Device [1b21:2142]
5781 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5783 static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5785 pci_info(dev, "PME# does not work under D0, disabling it\n");
5786 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5788 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5791 * Device [12d8:0x400e] and [12d8:0x400f]
5792 * These devices advertise PME# support in all power states but don't
5793 * reliably assert it.
5795 static void pci_fixup_no_pme(struct pci_dev *dev)
5797 pci_info(dev, "PME# is unreliable, disabling it\n");
5798 dev->pme_support = 0;
5800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_pme);
5801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_pme);
5803 static void apex_pci_fixup_class(struct pci_dev *pdev)
5805 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5807 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5808 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
5810 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
5812 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
5814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);