2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/irqdomain.h>
19 #include <linux/pm_runtime.h>
22 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23 #define CARDBUS_RESERVE_BUSNR 3
25 static struct resource busn_resource = {
29 .flags = IORESOURCE_BUS,
32 /* Ugh. Need to stop exporting this to modules. */
33 LIST_HEAD(pci_root_buses);
34 EXPORT_SYMBOL(pci_root_buses);
36 static LIST_HEAD(pci_domain_busn_res_list);
38 struct pci_domain_busn_res {
39 struct list_head list;
44 static struct resource *get_pci_domain_busn_res(int domain_nr)
46 struct pci_domain_busn_res *r;
48 list_for_each_entry(r, &pci_domain_busn_res_list, list)
49 if (r->domain_nr == domain_nr)
52 r = kzalloc(sizeof(*r), GFP_KERNEL);
56 r->domain_nr = domain_nr;
59 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
61 list_add_tail(&r->list, &pci_domain_busn_res_list);
66 static int find_anything(struct device *dev, void *data)
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
74 * is no device to be found on the pci_bus_type.
76 int no_pci_devices(void)
81 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
82 no_devices = (dev == NULL);
86 EXPORT_SYMBOL(no_pci_devices);
91 static void release_pcibus_dev(struct device *dev)
93 struct pci_bus *pci_bus = to_pci_bus(dev);
95 put_device(pci_bus->bridge);
96 pci_bus_remove_resources(pci_bus);
97 pci_release_bus_of_node(pci_bus);
101 static struct class pcibus_class = {
103 .dev_release = &release_pcibus_dev,
104 .dev_groups = pcibus_groups,
107 static int __init pcibus_class_init(void)
109 return class_register(&pcibus_class);
111 postcore_initcall(pcibus_class_init);
113 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
115 u64 size = mask & maxbase; /* Find the significant bits */
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size = (size & ~(size-1)) - 1;
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base == maxbase && ((base | size) & mask) != mask)
131 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
158 /* mem unknown type treated as 32-bit BAR */
164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
178 u32 l = 0, sz = 0, mask;
179 u64 l64, sz64, mask64;
181 struct pci_bus_region region, inverted_region;
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
194 res->name = pci_name(dev);
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 if (sz == 0xffffffff)
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = PCI_ROM_ADDRESS_MASK;
237 if (res->flags & IORESOURCE_MEM_64) {
238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
245 mask64 |= ((u64)~0 << 32);
248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
254 sz64 = pci_size(l64, sz64, mask64);
256 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
261 if (res->flags & IORESOURCE_MEM_64) {
262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
267 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
273 /* Above 32-bit boundary; try to reallocate */
274 res->flags |= IORESOURCE_UNSET;
277 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
284 region.end = l64 + sz64;
286 pcibios_bus_to_resource(dev->bus, res, ®ion);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
295 * resource_to_bus(bus_to_resource(A)) == A
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
300 if (inverted_region.start != region.start) {
301 res->flags |= IORESOURCE_UNSET;
303 res->end = region.end - region.start;
304 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
315 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
320 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322 unsigned int pos, reg;
324 if (dev->non_compliant_bars)
327 for (pos = 0; pos < howmany; pos++) {
328 struct resource *res = &dev->resource[pos];
329 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
330 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
334 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
335 dev->rom_base_reg = rom;
336 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
337 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
338 __pci_read_base(dev, pci_bar_mem32, res, rom);
342 static void pci_read_bridge_io(struct pci_bus *child)
344 struct pci_dev *dev = child->self;
345 u8 io_base_lo, io_limit_lo;
346 unsigned long io_mask, io_granularity, base, limit;
347 struct pci_bus_region region;
348 struct resource *res;
350 io_mask = PCI_IO_RANGE_MASK;
351 io_granularity = 0x1000;
352 if (dev->io_window_1k) {
353 /* Support 1K I/O space granularity */
354 io_mask = PCI_IO_1K_RANGE_MASK;
355 io_granularity = 0x400;
358 res = child->resource[0];
359 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
360 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
361 base = (io_base_lo & io_mask) << 8;
362 limit = (io_limit_lo & io_mask) << 8;
364 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
365 u16 io_base_hi, io_limit_hi;
367 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
368 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
369 base |= ((unsigned long) io_base_hi << 16);
370 limit |= ((unsigned long) io_limit_hi << 16);
374 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
376 region.end = limit + io_granularity - 1;
377 pcibios_bus_to_resource(dev->bus, res, ®ion);
378 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
382 static void pci_read_bridge_mmio(struct pci_bus *child)
384 struct pci_dev *dev = child->self;
385 u16 mem_base_lo, mem_limit_lo;
386 unsigned long base, limit;
387 struct pci_bus_region region;
388 struct resource *res;
390 res = child->resource[1];
391 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
392 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
393 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
396 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
398 region.end = limit + 0xfffff;
399 pcibios_bus_to_resource(dev->bus, res, ®ion);
400 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
404 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
406 struct pci_dev *dev = child->self;
407 u16 mem_base_lo, mem_limit_lo;
409 pci_bus_addr_t base, limit;
410 struct pci_bus_region region;
411 struct resource *res;
413 res = child->resource[2];
414 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
415 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
416 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
417 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
419 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
420 u32 mem_base_hi, mem_limit_hi;
422 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
423 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
426 * Some bridges set the base > limit by default, and some
427 * (broken) BIOSes do not initialize them. If we find
428 * this, just assume they are not being used.
430 if (mem_base_hi <= mem_limit_hi) {
431 base64 |= (u64) mem_base_hi << 32;
432 limit64 |= (u64) mem_limit_hi << 32;
436 base = (pci_bus_addr_t) base64;
437 limit = (pci_bus_addr_t) limit64;
439 if (base != base64) {
440 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
441 (unsigned long long) base64);
446 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
447 IORESOURCE_MEM | IORESOURCE_PREFETCH;
448 if (res->flags & PCI_PREF_RANGE_TYPE_64)
449 res->flags |= IORESOURCE_MEM_64;
451 region.end = limit + 0xfffff;
452 pcibios_bus_to_resource(dev->bus, res, ®ion);
453 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
457 void pci_read_bridge_bases(struct pci_bus *child)
459 struct pci_dev *dev = child->self;
460 struct resource *res;
463 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
466 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
468 dev->transparent ? " (subtractive decode)" : "");
470 pci_bus_remove_resources(child);
471 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
472 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
474 pci_read_bridge_io(child);
475 pci_read_bridge_mmio(child);
476 pci_read_bridge_mmio_pref(child);
478 if (dev->transparent) {
479 pci_bus_for_each_resource(child->parent, res, i) {
480 if (res && res->flags) {
481 pci_bus_add_resource(child, res,
482 PCI_SUBTRACTIVE_DECODE);
483 dev_printk(KERN_DEBUG, &dev->dev,
484 " bridge window %pR (subtractive decode)\n",
491 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
495 b = kzalloc(sizeof(*b), GFP_KERNEL);
499 INIT_LIST_HEAD(&b->node);
500 INIT_LIST_HEAD(&b->children);
501 INIT_LIST_HEAD(&b->devices);
502 INIT_LIST_HEAD(&b->slots);
503 INIT_LIST_HEAD(&b->resources);
504 b->max_bus_speed = PCI_SPEED_UNKNOWN;
505 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
506 #ifdef CONFIG_PCI_DOMAINS_GENERIC
508 b->domain_nr = parent->domain_nr;
513 static void devm_pci_release_host_bridge_dev(struct device *dev)
515 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
517 if (bridge->release_fn)
518 bridge->release_fn(bridge);
520 pci_free_resource_list(&bridge->windows);
523 static void pci_release_host_bridge_dev(struct device *dev)
525 devm_pci_release_host_bridge_dev(dev);
526 kfree(to_pci_host_bridge(dev));
529 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
531 struct pci_host_bridge *bridge;
533 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
537 INIT_LIST_HEAD(&bridge->windows);
538 bridge->dev.release = pci_release_host_bridge_dev;
542 EXPORT_SYMBOL(pci_alloc_host_bridge);
544 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
547 struct pci_host_bridge *bridge;
549 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
553 INIT_LIST_HEAD(&bridge->windows);
554 bridge->dev.release = devm_pci_release_host_bridge_dev;
558 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
560 void pci_free_host_bridge(struct pci_host_bridge *bridge)
562 pci_free_resource_list(&bridge->windows);
566 EXPORT_SYMBOL(pci_free_host_bridge);
568 static const unsigned char pcix_bus_speed[] = {
569 PCI_SPEED_UNKNOWN, /* 0 */
570 PCI_SPEED_66MHz_PCIX, /* 1 */
571 PCI_SPEED_100MHz_PCIX, /* 2 */
572 PCI_SPEED_133MHz_PCIX, /* 3 */
573 PCI_SPEED_UNKNOWN, /* 4 */
574 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
575 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
576 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
577 PCI_SPEED_UNKNOWN, /* 8 */
578 PCI_SPEED_66MHz_PCIX_266, /* 9 */
579 PCI_SPEED_100MHz_PCIX_266, /* A */
580 PCI_SPEED_133MHz_PCIX_266, /* B */
581 PCI_SPEED_UNKNOWN, /* C */
582 PCI_SPEED_66MHz_PCIX_533, /* D */
583 PCI_SPEED_100MHz_PCIX_533, /* E */
584 PCI_SPEED_133MHz_PCIX_533 /* F */
587 const unsigned char pcie_link_speed[] = {
588 PCI_SPEED_UNKNOWN, /* 0 */
589 PCIE_SPEED_2_5GT, /* 1 */
590 PCIE_SPEED_5_0GT, /* 2 */
591 PCIE_SPEED_8_0GT, /* 3 */
592 PCI_SPEED_UNKNOWN, /* 4 */
593 PCI_SPEED_UNKNOWN, /* 5 */
594 PCI_SPEED_UNKNOWN, /* 6 */
595 PCI_SPEED_UNKNOWN, /* 7 */
596 PCI_SPEED_UNKNOWN, /* 8 */
597 PCI_SPEED_UNKNOWN, /* 9 */
598 PCI_SPEED_UNKNOWN, /* A */
599 PCI_SPEED_UNKNOWN, /* B */
600 PCI_SPEED_UNKNOWN, /* C */
601 PCI_SPEED_UNKNOWN, /* D */
602 PCI_SPEED_UNKNOWN, /* E */
603 PCI_SPEED_UNKNOWN /* F */
606 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
608 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
610 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
612 static unsigned char agp_speeds[] = {
620 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
626 else if (agpstat & 2)
628 else if (agpstat & 1)
640 return agp_speeds[index];
643 static void pci_set_bus_speed(struct pci_bus *bus)
645 struct pci_dev *bridge = bus->self;
648 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
650 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
654 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
655 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
657 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
658 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
661 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
664 enum pci_bus_speed max;
666 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
669 if (status & PCI_X_SSTATUS_533MHZ) {
670 max = PCI_SPEED_133MHz_PCIX_533;
671 } else if (status & PCI_X_SSTATUS_266MHZ) {
672 max = PCI_SPEED_133MHz_PCIX_266;
673 } else if (status & PCI_X_SSTATUS_133MHZ) {
674 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
675 max = PCI_SPEED_133MHz_PCIX_ECC;
677 max = PCI_SPEED_133MHz_PCIX;
679 max = PCI_SPEED_66MHz_PCIX;
682 bus->max_bus_speed = max;
683 bus->cur_bus_speed = pcix_bus_speed[
684 (status & PCI_X_SSTATUS_FREQ) >> 6];
689 if (pci_is_pcie(bridge)) {
693 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
694 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
696 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
697 pcie_update_link_speed(bus, linksta);
701 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
703 struct irq_domain *d;
706 * Any firmware interface that can resolve the msi_domain
707 * should be called from here.
709 d = pci_host_bridge_of_msi_domain(bus);
711 d = pci_host_bridge_acpi_msi_domain(bus);
713 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
715 * If no IRQ domain was found via the OF tree, try looking it up
716 * directly through the fwnode_handle.
719 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
722 d = irq_find_matching_fwnode(fwnode,
730 static void pci_set_bus_msi_domain(struct pci_bus *bus)
732 struct irq_domain *d;
736 * The bus can be a root bus, a subordinate bus, or a virtual bus
737 * created by an SR-IOV device. Walk up to the first bridge device
738 * found or derive the domain from the host bridge.
740 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
742 d = dev_get_msi_domain(&b->self->dev);
746 d = pci_host_bridge_msi_domain(b);
748 dev_set_msi_domain(&bus->dev, d);
751 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
753 struct device *parent = bridge->dev.parent;
754 struct resource_entry *window, *n;
755 struct pci_bus *bus, *b;
756 resource_size_t offset;
757 LIST_HEAD(resources);
758 struct resource *res;
763 bus = pci_alloc_bus(NULL);
769 /* temporarily move resources off the list */
770 list_splice_init(&bridge->windows, &resources);
771 bus->sysdata = bridge->sysdata;
772 bus->msi = bridge->msi;
773 bus->ops = bridge->ops;
774 bus->number = bus->busn_res.start = bridge->busnr;
775 #ifdef CONFIG_PCI_DOMAINS_GENERIC
776 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
779 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
781 /* If we already got to this bus through a different bridge, ignore it */
782 dev_dbg(&b->dev, "bus already known\n");
787 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
790 err = pcibios_root_bridge_prepare(bridge);
794 err = device_register(&bridge->dev);
796 put_device(&bridge->dev);
799 bus->bridge = get_device(&bridge->dev);
800 device_enable_async_suspend(bus->bridge);
801 pci_set_bus_of_node(bus);
802 pci_set_bus_msi_domain(bus);
805 set_dev_node(bus->bridge, pcibus_to_node(bus));
807 bus->dev.class = &pcibus_class;
808 bus->dev.parent = bus->bridge;
810 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
811 name = dev_name(&bus->dev);
813 err = device_register(&bus->dev);
817 pcibios_add_bus(bus);
819 /* Create legacy_io and legacy_mem files for this bus */
820 pci_create_legacy_files(bus);
823 dev_info(parent, "PCI host bridge to bus %s\n", name);
825 pr_info("PCI host bridge to bus %s\n", name);
827 /* Add initial resources to the bus */
828 resource_list_for_each_entry_safe(window, n, &resources) {
829 list_move_tail(&window->node, &bridge->windows);
830 offset = window->offset;
833 if (res->flags & IORESOURCE_BUS)
834 pci_bus_insert_busn_res(bus, bus->number, res->end);
836 pci_bus_add_resource(bus, res, 0);
839 if (resource_type(res) == IORESOURCE_IO)
840 fmt = " (bus address [%#06llx-%#06llx])";
842 fmt = " (bus address [%#010llx-%#010llx])";
844 snprintf(addr, sizeof(addr), fmt,
845 (unsigned long long)(res->start - offset),
846 (unsigned long long)(res->end - offset));
850 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
853 down_write(&pci_bus_sem);
854 list_add_tail(&bus->node, &pci_root_buses);
855 up_write(&pci_bus_sem);
860 put_device(&bridge->dev);
861 device_unregister(&bridge->dev);
868 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
869 struct pci_dev *bridge, int busnr)
871 struct pci_bus *child;
876 * Allocate a new bus, and inherit stuff from the parent..
878 child = pci_alloc_bus(parent);
882 child->parent = parent;
883 child->ops = parent->ops;
884 child->msi = parent->msi;
885 child->sysdata = parent->sysdata;
886 child->bus_flags = parent->bus_flags;
888 /* initialize some portions of the bus device, but don't register it
889 * now as the parent is not properly set up yet.
891 child->dev.class = &pcibus_class;
892 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
895 * Set up the primary, secondary and subordinate
898 child->number = child->busn_res.start = busnr;
899 child->primary = parent->busn_res.start;
900 child->busn_res.end = 0xff;
903 child->dev.parent = parent->bridge;
907 child->self = bridge;
908 child->bridge = get_device(&bridge->dev);
909 child->dev.parent = child->bridge;
910 pci_set_bus_of_node(child);
911 pci_set_bus_speed(child);
913 /* Set up default resource pointers and names.. */
914 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
915 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
916 child->resource[i]->name = child->name;
918 bridge->subordinate = child;
921 pci_set_bus_msi_domain(child);
922 ret = device_register(&child->dev);
925 pcibios_add_bus(child);
927 if (child->ops->add_bus) {
928 ret = child->ops->add_bus(child);
929 if (WARN_ON(ret < 0))
930 dev_err(&child->dev, "failed to add bus: %d\n", ret);
933 /* Create legacy_io and legacy_mem files for this bus */
934 pci_create_legacy_files(child);
939 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
942 struct pci_bus *child;
944 child = pci_alloc_child_bus(parent, dev, busnr);
946 down_write(&pci_bus_sem);
947 list_add_tail(&child->node, &parent->children);
948 up_write(&pci_bus_sem);
952 EXPORT_SYMBOL(pci_add_new_bus);
954 static void pci_enable_crs(struct pci_dev *pdev)
958 /* Enable CRS Software Visibility if supported */
959 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
960 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
961 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
962 PCI_EXP_RTCTL_CRSSVE);
966 * If it's a bridge, configure it and scan the bus behind it.
967 * For CardBus bridges, we don't scan behind as the devices will
968 * be handled by the bridge driver itself.
970 * We need to process bridges in two passes -- first we scan those
971 * already configured by the BIOS and after we are done with all of
972 * them, we proceed to assigning numbers to the remaining buses in
973 * order to avoid overlaps between old and new bus numbers.
975 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
977 struct pci_bus *child;
978 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
981 u8 primary, secondary, subordinate;
985 * Make sure the bridge is powered on to be able to access config
986 * space of devices below it.
988 pm_runtime_get_sync(&dev->dev);
990 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
991 primary = buses & 0xFF;
992 secondary = (buses >> 8) & 0xFF;
993 subordinate = (buses >> 16) & 0xFF;
995 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
996 secondary, subordinate, pass);
998 if (!primary && (primary != bus->number) && secondary && subordinate) {
999 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
1000 primary = bus->number;
1003 /* Check if setup is sensible at all */
1005 (primary != bus->number || secondary <= bus->number ||
1006 secondary > subordinate)) {
1007 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1008 secondary, subordinate);
1012 /* Disable MasterAbortMode during probing to avoid reporting
1013 of bus errors (in some architectures) */
1014 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1015 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1016 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1018 pci_enable_crs(dev);
1020 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1021 !is_cardbus && !broken) {
1024 * Bus already configured by firmware, process it in the first
1025 * pass and just note the configuration.
1031 * The bus might already exist for two reasons: Either we are
1032 * rescanning the bus or the bus is reachable through more than
1033 * one bridge. The second case can happen with the i450NX
1036 child = pci_find_bus(pci_domain_nr(bus), secondary);
1038 child = pci_add_new_bus(bus, dev, secondary);
1041 child->primary = primary;
1042 pci_bus_insert_busn_res(child, secondary, subordinate);
1043 child->bridge_ctl = bctl;
1046 cmax = pci_scan_child_bus(child);
1047 if (cmax > subordinate)
1048 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
1050 /* subordinate should equal child->busn_res.end */
1051 if (subordinate > max)
1055 * We need to assign a number to this bus which we always
1056 * do in the second pass.
1059 if (pcibios_assign_all_busses() || broken || is_cardbus)
1060 /* Temporarily disable forwarding of the
1061 configuration cycles on all bridges in
1062 this bus segment to avoid possible
1063 conflicts in the second pass between two
1064 bridges programmed with overlapping
1066 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1072 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1074 /* Prevent assigning a bus number that already exists.
1075 * This can happen when a bridge is hot-plugged, so in
1076 * this case we only re-scan this bus. */
1077 child = pci_find_bus(pci_domain_nr(bus), max+1);
1079 child = pci_add_new_bus(bus, dev, max+1);
1082 pci_bus_insert_busn_res(child, max+1,
1086 buses = (buses & 0xff000000)
1087 | ((unsigned int)(child->primary) << 0)
1088 | ((unsigned int)(child->busn_res.start) << 8)
1089 | ((unsigned int)(child->busn_res.end) << 16);
1092 * yenta.c forces a secondary latency timer of 176.
1093 * Copy that behaviour here.
1096 buses &= ~0xff000000;
1097 buses |= CARDBUS_LATENCY_TIMER << 24;
1101 * We need to blast all three values with a single write.
1103 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1106 child->bridge_ctl = bctl;
1107 max = pci_scan_child_bus(child);
1110 * For CardBus bridges, we leave 4 bus numbers
1111 * as cards with a PCI-to-PCI bridge can be
1114 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1115 struct pci_bus *parent = bus;
1116 if (pci_find_bus(pci_domain_nr(bus),
1119 while (parent->parent) {
1120 if ((!pcibios_assign_all_busses()) &&
1121 (parent->busn_res.end > max) &&
1122 (parent->busn_res.end <= max+i)) {
1125 parent = parent->parent;
1129 * Often, there are two cardbus bridges
1130 * -- try to leave one valid bus number
1140 * Set the subordinate bus number to its real value.
1142 pci_bus_update_busn_res_end(child, max);
1143 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1146 sprintf(child->name,
1147 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1148 pci_domain_nr(bus), child->number);
1150 /* Has only triggered on CardBus, fixup is in yenta_socket */
1151 while (bus->parent) {
1152 if ((child->busn_res.end > bus->busn_res.end) ||
1153 (child->number > bus->busn_res.end) ||
1154 (child->number < bus->number) ||
1155 (child->busn_res.end < bus->number)) {
1156 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1158 (bus->number > child->busn_res.end &&
1159 bus->busn_res.end < child->number) ?
1160 "wholly" : "partially",
1161 bus->self->transparent ? " transparent" : "",
1162 dev_name(&bus->dev),
1169 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1171 pm_runtime_put(&dev->dev);
1175 EXPORT_SYMBOL(pci_scan_bridge);
1178 * Read interrupt line and base address registers.
1179 * The architecture-dependent code can tweak these, of course.
1181 static void pci_read_irq(struct pci_dev *dev)
1185 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1188 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1192 void set_pcie_port_type(struct pci_dev *pdev)
1197 struct pci_dev *parent;
1199 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1203 pdev->pcie_cap = pos;
1204 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1205 pdev->pcie_flags_reg = reg16;
1206 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1207 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1210 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1211 * of a Link. No PCIe component has two Links. Two Links are
1212 * connected by a Switch that has a Port on each Link and internal
1213 * logic to connect the two Ports.
1215 type = pci_pcie_type(pdev);
1216 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1217 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1218 pdev->has_secondary_link = 1;
1219 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1220 type == PCI_EXP_TYPE_DOWNSTREAM) {
1221 parent = pci_upstream_bridge(pdev);
1224 * Usually there's an upstream device (Root Port or Switch
1225 * Downstream Port), but we can't assume one exists.
1227 if (parent && !parent->has_secondary_link)
1228 pdev->has_secondary_link = 1;
1232 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1236 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1237 if (reg32 & PCI_EXP_SLTCAP_HPC)
1238 pdev->is_hotplug_bridge = 1;
1241 static void set_pcie_thunderbolt(struct pci_dev *dev)
1246 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1247 PCI_EXT_CAP_ID_VNDR))) {
1248 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1250 /* Is the device part of a Thunderbolt controller? */
1251 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1252 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1253 dev->is_thunderbolt = 1;
1260 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1263 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1264 * when forwarding a type1 configuration request the bridge must check that
1265 * the extended register address field is zero. The bridge is not permitted
1266 * to forward the transactions and must handle it as an Unsupported Request.
1267 * Some bridges do not follow this rule and simply drop the extended register
1268 * bits, resulting in the standard config space being aliased, every 256
1269 * bytes across the entire configuration space. Test for this condition by
1270 * comparing the first dword of each potential alias to the vendor/device ID.
1272 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1273 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1275 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1277 #ifdef CONFIG_PCI_QUIRKS
1281 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1283 for (pos = PCI_CFG_SPACE_SIZE;
1284 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1285 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1297 * pci_cfg_space_size - get the configuration space size of the PCI device.
1300 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1301 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1302 * access it. Maybe we don't have a way to generate extended config space
1303 * accesses, or the device is behind a reverse Express bridge. So we try
1304 * reading the dword at 0x100 which must either be 0 or a valid extended
1305 * capability header.
1307 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1310 int pos = PCI_CFG_SPACE_SIZE;
1312 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1313 return PCI_CFG_SPACE_SIZE;
1314 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1315 return PCI_CFG_SPACE_SIZE;
1317 return PCI_CFG_SPACE_EXP_SIZE;
1320 int pci_cfg_space_size(struct pci_dev *dev)
1326 class = dev->class >> 8;
1327 if (class == PCI_CLASS_BRIDGE_HOST)
1328 return pci_cfg_space_size_ext(dev);
1330 if (pci_is_pcie(dev))
1331 return pci_cfg_space_size_ext(dev);
1333 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1335 return PCI_CFG_SPACE_SIZE;
1337 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1338 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1339 return pci_cfg_space_size_ext(dev);
1341 return PCI_CFG_SPACE_SIZE;
1344 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1346 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1349 * Disable the MSI hardware to avoid screaming interrupts
1350 * during boot. This is the power on reset default so
1351 * usually this should be a noop.
1353 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1355 pci_msi_set_enable(dev, 0);
1357 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1359 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1363 * pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability
1366 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1367 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1369 static int pci_intx_mask_broken(struct pci_dev *dev)
1371 u16 orig, toggle, new;
1373 pci_read_config_word(dev, PCI_COMMAND, &orig);
1374 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1375 pci_write_config_word(dev, PCI_COMMAND, toggle);
1376 pci_read_config_word(dev, PCI_COMMAND, &new);
1378 pci_write_config_word(dev, PCI_COMMAND, orig);
1381 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1382 * r2.3, so strictly speaking, a device is not *broken* if it's not
1383 * writable. But we'll live with the misnomer for now.
1391 * pci_setup_device - fill in class and map information of a device
1392 * @dev: the device structure to fill
1394 * Initialize the device structure with information about the device's
1395 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1396 * Called at initialisation of the PCI subsystem and by CardBus services.
1397 * Returns 0 on success and negative if unknown type of device (not normal,
1398 * bridge or CardBus).
1400 int pci_setup_device(struct pci_dev *dev)
1406 struct pci_bus_region region;
1407 struct resource *res;
1409 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1412 dev->sysdata = dev->bus->sysdata;
1413 dev->dev.parent = dev->bus->bridge;
1414 dev->dev.bus = &pci_bus_type;
1415 dev->hdr_type = hdr_type & 0x7f;
1416 dev->multifunction = !!(hdr_type & 0x80);
1417 dev->error_state = pci_channel_io_normal;
1418 set_pcie_port_type(dev);
1420 pci_dev_assign_slot(dev);
1421 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1422 set this higher, assuming the system even supports it. */
1423 dev->dma_mask = 0xffffffff;
1425 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1426 dev->bus->number, PCI_SLOT(dev->devfn),
1427 PCI_FUNC(dev->devfn));
1429 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1430 dev->revision = class & 0xff;
1431 dev->class = class >> 8; /* upper 3 bytes */
1433 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1434 dev->vendor, dev->device, dev->hdr_type, dev->class);
1436 /* need to have dev->class ready */
1437 dev->cfg_size = pci_cfg_space_size(dev);
1439 /* need to have dev->cfg_size ready */
1440 set_pcie_thunderbolt(dev);
1442 /* "Unknown power state" */
1443 dev->current_state = PCI_UNKNOWN;
1445 /* Early fixups, before probing the BARs */
1446 pci_fixup_device(pci_fixup_early, dev);
1447 /* device class may be changed after fixup */
1448 class = dev->class >> 8;
1450 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1451 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1452 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1453 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1454 cmd &= ~PCI_COMMAND_IO;
1455 cmd &= ~PCI_COMMAND_MEMORY;
1456 pci_write_config_word(dev, PCI_COMMAND, cmd);
1460 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1462 switch (dev->hdr_type) { /* header type */
1463 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1464 if (class == PCI_CLASS_BRIDGE_PCI)
1467 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1468 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1469 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1472 * Do the ugly legacy mode stuff here rather than broken chip
1473 * quirk code. Legacy mode ATA controllers have fixed
1474 * addresses. These are not always echoed in BAR0-3, and
1475 * BAR0-3 in a few cases contain junk!
1477 if (class == PCI_CLASS_STORAGE_IDE) {
1479 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1480 if ((progif & 1) == 0) {
1481 region.start = 0x1F0;
1483 res = &dev->resource[0];
1484 res->flags = LEGACY_IO_RESOURCE;
1485 pcibios_bus_to_resource(dev->bus, res, ®ion);
1486 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1488 region.start = 0x3F6;
1490 res = &dev->resource[1];
1491 res->flags = LEGACY_IO_RESOURCE;
1492 pcibios_bus_to_resource(dev->bus, res, ®ion);
1493 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1496 if ((progif & 4) == 0) {
1497 region.start = 0x170;
1499 res = &dev->resource[2];
1500 res->flags = LEGACY_IO_RESOURCE;
1501 pcibios_bus_to_resource(dev->bus, res, ®ion);
1502 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1504 region.start = 0x376;
1506 res = &dev->resource[3];
1507 res->flags = LEGACY_IO_RESOURCE;
1508 pcibios_bus_to_resource(dev->bus, res, ®ion);
1509 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1515 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1516 if (class != PCI_CLASS_BRIDGE_PCI)
1518 /* The PCI-to-PCI bridge spec requires that subtractive
1519 decoding (i.e. transparent) bridge must have programming
1520 interface code of 0x01. */
1522 dev->transparent = ((dev->class & 0xff) == 1);
1523 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1524 set_pcie_hotplug_bridge(dev);
1525 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1527 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1528 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1532 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1533 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1536 pci_read_bases(dev, 1, 0);
1537 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1538 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1541 default: /* unknown header */
1542 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1547 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1548 dev->class, dev->hdr_type);
1549 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1552 /* We found a fine healthy device, go go go... */
1556 static void pci_configure_mps(struct pci_dev *dev)
1558 struct pci_dev *bridge = pci_upstream_bridge(dev);
1561 if (!pci_is_pcie(dev))
1564 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1569 * For Root Complex Integrated Endpoints, program the maximum
1570 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
1572 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
1573 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1576 mps = 128 << dev->pcie_mpss;
1577 rc = pcie_set_mps(dev, mps);
1579 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1585 if (!bridge || !pci_is_pcie(bridge))
1588 mps = pcie_get_mps(dev);
1589 p_mps = pcie_get_mps(bridge);
1594 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1595 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1596 mps, pci_name(bridge), p_mps);
1601 * Fancier MPS configuration is done later by
1602 * pcie_bus_configure_settings()
1604 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1607 rc = pcie_set_mps(dev, p_mps);
1609 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1614 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1615 p_mps, mps, 128 << dev->pcie_mpss);
1618 static struct hpp_type0 pci_default_type0 = {
1620 .cache_line_size = 8,
1621 .latency_timer = 0x40,
1626 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1628 u16 pci_cmd, pci_bctl;
1631 hpp = &pci_default_type0;
1633 if (hpp->revision > 1) {
1635 "PCI settings rev %d not supported; using defaults\n",
1637 hpp = &pci_default_type0;
1640 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1641 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1642 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1643 if (hpp->enable_serr)
1644 pci_cmd |= PCI_COMMAND_SERR;
1645 if (hpp->enable_perr)
1646 pci_cmd |= PCI_COMMAND_PARITY;
1647 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1649 /* Program bridge control value */
1650 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1651 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1652 hpp->latency_timer);
1653 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1654 if (hpp->enable_serr)
1655 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1656 if (hpp->enable_perr)
1657 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1658 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1662 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1669 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1673 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1676 static bool pcie_root_rcb_set(struct pci_dev *dev)
1678 struct pci_dev *rp = pcie_find_root_port(dev);
1684 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1685 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1691 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1699 if (!pci_is_pcie(dev))
1702 if (hpp->revision > 1) {
1703 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1709 * Don't allow _HPX to change MPS or MRRS settings. We manage
1710 * those to make sure they're consistent with the rest of the
1713 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1714 PCI_EXP_DEVCTL_READRQ;
1715 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1716 PCI_EXP_DEVCTL_READRQ);
1718 /* Initialize Device Control Register */
1719 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1720 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1722 /* Initialize Link Control Register */
1723 if (pcie_cap_has_lnkctl(dev)) {
1726 * If the Root Port supports Read Completion Boundary of
1727 * 128, set RCB to 128. Otherwise, clear it.
1729 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1730 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1731 if (pcie_root_rcb_set(dev))
1732 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1734 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1735 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1738 /* Find Advanced Error Reporting Enhanced Capability */
1739 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1743 /* Initialize Uncorrectable Error Mask Register */
1744 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1745 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1746 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1748 /* Initialize Uncorrectable Error Severity Register */
1749 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1750 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1751 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1753 /* Initialize Correctable Error Mask Register */
1754 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1755 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1756 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1758 /* Initialize Advanced Error Capabilities and Control Register */
1759 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1760 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1761 /* Don't enable ECRC generation or checking if unsupported */
1762 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
1763 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
1764 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
1765 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
1766 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1769 * FIXME: The following two registers are not supported yet.
1771 * o Secondary Uncorrectable Error Severity Register
1772 * o Secondary Uncorrectable Error Mask Register
1776 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1778 struct pci_host_bridge *host;
1783 if (!pci_is_pcie(dev))
1786 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1790 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1793 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1797 host = pci_find_host_bridge(dev->bus);
1802 * If some device in the hierarchy doesn't handle Extended Tags
1803 * correctly, make sure they're disabled.
1805 if (host->no_ext_tags) {
1806 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1807 dev_info(&dev->dev, "disabling Extended Tags\n");
1808 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1809 PCI_EXP_DEVCTL_EXT_TAG);
1814 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1815 dev_info(&dev->dev, "enabling Extended Tags\n");
1816 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1817 PCI_EXP_DEVCTL_EXT_TAG);
1823 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
1824 * @dev: PCI device to query
1826 * Returns true if the device has enabled relaxed ordering attribute.
1828 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1832 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1834 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1836 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1838 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
1840 struct pci_dev *root;
1842 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
1846 if (!pcie_relaxed_ordering_enabled(dev))
1850 * For now, we only deal with Relaxed Ordering issues with Root
1851 * Ports. Peer-to-Peer DMA is another can of worms.
1853 root = pci_find_pcie_root_port(dev);
1857 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
1858 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1859 PCI_EXP_DEVCTL_RELAX_EN);
1860 dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n");
1864 static void pci_configure_device(struct pci_dev *dev)
1866 struct hotplug_params hpp;
1869 pci_configure_mps(dev);
1870 pci_configure_extended_tags(dev, NULL);
1871 pci_configure_relaxed_ordering(dev);
1873 memset(&hpp, 0, sizeof(hpp));
1874 ret = pci_get_hp_params(dev, &hpp);
1878 program_hpp_type2(dev, hpp.t2);
1879 program_hpp_type1(dev, hpp.t1);
1880 program_hpp_type0(dev, hpp.t0);
1883 static void pci_release_capabilities(struct pci_dev *dev)
1885 pci_vpd_release(dev);
1886 pci_iov_release(dev);
1887 pci_free_cap_save_buffers(dev);
1891 * pci_release_dev - free a pci device structure when all users of it are finished.
1892 * @dev: device that's been disconnected
1894 * Will be called only by the device core when all users of this pci device are
1897 static void pci_release_dev(struct device *dev)
1899 struct pci_dev *pci_dev;
1901 pci_dev = to_pci_dev(dev);
1902 pci_release_capabilities(pci_dev);
1903 pci_release_of_node(pci_dev);
1904 pcibios_release_device(pci_dev);
1905 pci_bus_put(pci_dev->bus);
1906 kfree(pci_dev->driver_override);
1907 kfree(pci_dev->dma_alias_mask);
1911 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1913 struct pci_dev *dev;
1915 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1919 INIT_LIST_HEAD(&dev->bus_list);
1920 dev->dev.type = &pci_dev_type;
1921 dev->bus = pci_bus_get(bus);
1925 EXPORT_SYMBOL(pci_alloc_dev);
1927 static bool pci_bus_crs_vendor_id(u32 l)
1929 return (l & 0xffff) == 0x0001;
1932 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
1937 if (!pci_bus_crs_vendor_id(*l))
1938 return true; /* not a CRS completion */
1941 return false; /* CRS, but caller doesn't want to wait */
1944 * We got the reserved Vendor ID that indicates a completion with
1945 * Configuration Request Retry Status (CRS). Retry until we get a
1946 * valid Vendor ID or we time out.
1948 while (pci_bus_crs_vendor_id(*l)) {
1949 if (delay > timeout) {
1950 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
1951 pci_domain_nr(bus), bus->number,
1952 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
1957 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
1958 pci_domain_nr(bus), bus->number,
1959 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
1964 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1969 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
1970 pci_domain_nr(bus), bus->number,
1971 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
1976 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1979 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1982 /* some broken boards return 0 or ~0 if a slot is empty: */
1983 if (*l == 0xffffffff || *l == 0x00000000 ||
1984 *l == 0x0000ffff || *l == 0xffff0000)
1987 if (pci_bus_crs_vendor_id(*l))
1988 return pci_bus_wait_crs(bus, devfn, l, timeout);
1992 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1995 * Read the config data for a PCI device, sanity-check it
1996 * and fill in the dev structure...
1998 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2000 struct pci_dev *dev;
2003 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2006 dev = pci_alloc_dev(bus);
2011 dev->vendor = l & 0xffff;
2012 dev->device = (l >> 16) & 0xffff;
2014 pci_set_of_node(dev);
2016 if (pci_setup_device(dev)) {
2017 pci_release_of_node(dev);
2018 pci_bus_put(dev->bus);
2026 static void pci_init_capabilities(struct pci_dev *dev)
2028 /* Enhanced Allocation */
2031 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2032 pci_msi_setup_pci_dev(dev);
2034 /* Buffers for saving PCIe and PCI-X capabilities */
2035 pci_allocate_cap_save_buffers(dev);
2037 /* Power Management */
2040 /* Vital Product Data */
2043 /* Alternative Routing-ID Forwarding */
2044 pci_configure_ari(dev);
2046 /* Single Root I/O Virtualization */
2049 /* Address Translation Services */
2052 /* Enable ACS P2P upstream forwarding */
2053 pci_enable_acs(dev);
2055 /* Precision Time Measurement */
2058 /* Advanced Error Reporting */
2063 * This is the equivalent of pci_host_bridge_msi_domain that acts on
2064 * devices. Firmware interfaces that can select the MSI domain on a
2065 * per-device basis should be called from here.
2067 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2069 struct irq_domain *d;
2072 * If a domain has been set through the pcibios_add_device
2073 * callback, then this is the one (platform code knows best).
2075 d = dev_get_msi_domain(&dev->dev);
2080 * Let's see if we have a firmware interface able to provide
2083 d = pci_msi_get_device_domain(dev);
2090 static void pci_set_msi_domain(struct pci_dev *dev)
2092 struct irq_domain *d;
2095 * If the platform or firmware interfaces cannot supply a
2096 * device-specific MSI domain, then inherit the default domain
2097 * from the host bridge itself.
2099 d = pci_dev_msi_domain(dev);
2101 d = dev_get_msi_domain(&dev->bus->dev);
2103 dev_set_msi_domain(&dev->dev, d);
2106 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2110 pci_configure_device(dev);
2112 device_initialize(&dev->dev);
2113 dev->dev.release = pci_release_dev;
2115 set_dev_node(&dev->dev, pcibus_to_node(bus));
2116 dev->dev.dma_mask = &dev->dma_mask;
2117 dev->dev.dma_parms = &dev->dma_parms;
2118 dev->dev.coherent_dma_mask = 0xffffffffull;
2120 pci_set_dma_max_seg_size(dev, 65536);
2121 pci_set_dma_seg_boundary(dev, 0xffffffff);
2123 /* Fix up broken headers */
2124 pci_fixup_device(pci_fixup_header, dev);
2126 /* moved out from quirk header fixup code */
2127 pci_reassigndev_resource_alignment(dev);
2129 /* Clear the state_saved flag. */
2130 dev->state_saved = false;
2132 /* Initialize various capabilities */
2133 pci_init_capabilities(dev);
2136 * Add the device to our list of discovered devices
2137 * and the bus list for fixup functions, etc.
2139 down_write(&pci_bus_sem);
2140 list_add_tail(&dev->bus_list, &bus->devices);
2141 up_write(&pci_bus_sem);
2143 ret = pcibios_add_device(dev);
2146 /* Setup MSI irq domain */
2147 pci_set_msi_domain(dev);
2149 /* Notifier could use PCI capabilities */
2150 dev->match_driver = false;
2151 ret = device_add(&dev->dev);
2155 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2157 struct pci_dev *dev;
2159 dev = pci_get_slot(bus, devfn);
2165 dev = pci_scan_device(bus, devfn);
2169 pci_device_add(dev, bus);
2173 EXPORT_SYMBOL(pci_scan_single_device);
2175 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2181 if (pci_ari_enabled(bus)) {
2184 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2188 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2189 next_fn = PCI_ARI_CAP_NFN(cap);
2191 return 0; /* protect against malformed list */
2196 /* dev may be NULL for non-contiguous multifunction devices */
2197 if (!dev || dev->multifunction)
2198 return (fn + 1) % 8;
2203 static int only_one_child(struct pci_bus *bus)
2205 struct pci_dev *parent = bus->self;
2207 if (!parent || !pci_is_pcie(parent))
2209 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
2213 * PCIe downstream ports are bridges that normally lead to only a
2214 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
2215 * possible devices, not just device 0. See PCIe spec r3.0,
2218 if (parent->has_secondary_link &&
2219 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2225 * pci_scan_slot - scan a PCI slot on a bus for devices.
2226 * @bus: PCI bus to scan
2227 * @devfn: slot number to scan (must have zero function.)
2229 * Scan a PCI slot on the specified PCI bus for devices, adding
2230 * discovered devices to the @bus->devices list. New devices
2231 * will not have is_added set.
2233 * Returns the number of new devices found.
2235 int pci_scan_slot(struct pci_bus *bus, int devfn)
2237 unsigned fn, nr = 0;
2238 struct pci_dev *dev;
2240 if (only_one_child(bus) && (devfn > 0))
2241 return 0; /* Already scanned the entire slot */
2243 dev = pci_scan_single_device(bus, devfn);
2249 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2250 dev = pci_scan_single_device(bus, devfn + fn);
2254 dev->multifunction = 1;
2258 /* only one slot has pcie device */
2259 if (bus->self && nr)
2260 pcie_aspm_init_link_state(bus->self);
2264 EXPORT_SYMBOL(pci_scan_slot);
2266 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2270 if (!pci_is_pcie(dev))
2274 * We don't have a way to change MPS settings on devices that have
2275 * drivers attached. A hot-added device might support only the minimum
2276 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2277 * where devices may be hot-added, we limit the fabric MPS to 128 so
2278 * hot-added devices will work correctly.
2280 * However, if we hot-add a device to a slot directly below a Root
2281 * Port, it's impossible for there to be other existing devices below
2282 * the port. We don't limit the MPS in this case because we can
2283 * reconfigure MPS on both the Root Port and the hot-added device,
2284 * and there are no other devices involved.
2286 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2288 if (dev->is_hotplug_bridge &&
2289 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2292 if (*smpss > dev->pcie_mpss)
2293 *smpss = dev->pcie_mpss;
2298 static void pcie_write_mps(struct pci_dev *dev, int mps)
2302 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2303 mps = 128 << dev->pcie_mpss;
2305 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2307 /* For "Performance", the assumption is made that
2308 * downstream communication will never be larger than
2309 * the MRRS. So, the MPS only needs to be configured
2310 * for the upstream communication. This being the case,
2311 * walk from the top down and set the MPS of the child
2312 * to that of the parent bus.
2314 * Configure the device MPS with the smaller of the
2315 * device MPSS or the bridge MPS (which is assumed to be
2316 * properly configured at this point to the largest
2317 * allowable MPS based on its parent bus).
2319 mps = min(mps, pcie_get_mps(dev->bus->self));
2322 rc = pcie_set_mps(dev, mps);
2324 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
2327 static void pcie_write_mrrs(struct pci_dev *dev)
2331 /* In the "safe" case, do not configure the MRRS. There appear to be
2332 * issues with setting MRRS to 0 on a number of devices.
2334 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2337 /* For Max performance, the MRRS must be set to the largest supported
2338 * value. However, it cannot be configured larger than the MPS the
2339 * device or the bus can support. This should already be properly
2340 * configured by a prior call to pcie_write_mps.
2342 mrrs = pcie_get_mps(dev);
2344 /* MRRS is a R/W register. Invalid values can be written, but a
2345 * subsequent read will verify if the value is acceptable or not.
2346 * If the MRRS value provided is not acceptable (e.g., too large),
2347 * shrink the value until it is acceptable to the HW.
2349 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2350 rc = pcie_set_readrq(dev, mrrs);
2354 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2359 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2362 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2366 if (!pci_is_pcie(dev))
2369 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2370 pcie_bus_config == PCIE_BUS_DEFAULT)
2373 mps = 128 << *(u8 *)data;
2374 orig_mps = pcie_get_mps(dev);
2376 pcie_write_mps(dev, mps);
2377 pcie_write_mrrs(dev);
2379 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2380 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2381 orig_mps, pcie_get_readrq(dev));
2386 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2387 * parents then children fashion. If this changes, then this code will not
2390 void pcie_bus_configure_settings(struct pci_bus *bus)
2397 if (!pci_is_pcie(bus->self))
2400 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2401 * to be aware of the MPS of the destination. To work around this,
2402 * simply force the MPS of the entire system to the smallest possible.
2404 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2407 if (pcie_bus_config == PCIE_BUS_SAFE) {
2408 smpss = bus->self->pcie_mpss;
2410 pcie_find_smpss(bus->self, &smpss);
2411 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2414 pcie_bus_configure_set(bus->self, &smpss);
2415 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2417 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2420 * Called after each bus is probed, but before its children are examined. This
2421 * is marked as __weak because multiple architectures define it.
2423 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2425 /* nothing to do, expected to be removed in the future */
2428 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2430 unsigned int devfn, pass, max = bus->busn_res.start;
2431 struct pci_dev *dev;
2433 dev_dbg(&bus->dev, "scanning bus\n");
2435 /* Go find them, Rover! */
2436 for (devfn = 0; devfn < 0x100; devfn += 8)
2437 pci_scan_slot(bus, devfn);
2439 /* Reserve buses for SR-IOV capability. */
2440 max += pci_iov_bus_range(bus);
2443 * After performing arch-dependent fixup of the bus, look behind
2444 * all PCI-to-PCI bridges on this bus.
2446 if (!bus->is_added) {
2447 dev_dbg(&bus->dev, "fixups for bus\n");
2448 pcibios_fixup_bus(bus);
2452 for (pass = 0; pass < 2; pass++)
2453 list_for_each_entry(dev, &bus->devices, bus_list) {
2454 if (pci_is_bridge(dev))
2455 max = pci_scan_bridge(bus, dev, max, pass);
2459 * Make sure a hotplug bridge has at least the minimum requested
2462 if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
2463 if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
2464 max = bus->busn_res.start + pci_hotplug_bus_size - 1;
2466 /* Do not allocate more buses than we have room left */
2467 if (max > bus->busn_res.end)
2468 max = bus->busn_res.end;
2472 * We've scanned the bus and so we know all about what's on
2473 * the other side of any bridges that may be on this bus plus
2476 * Return how far we've got finding sub-buses.
2478 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2481 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2484 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2485 * @bridge: Host bridge to set up.
2487 * Default empty implementation. Replace with an architecture-specific setup
2488 * routine, if necessary.
2490 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2495 void __weak pcibios_add_bus(struct pci_bus *bus)
2499 void __weak pcibios_remove_bus(struct pci_bus *bus)
2503 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2504 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2507 struct pci_host_bridge *bridge;
2509 bridge = pci_alloc_host_bridge(0);
2513 bridge->dev.parent = parent;
2515 list_splice_init(resources, &bridge->windows);
2516 bridge->sysdata = sysdata;
2517 bridge->busnr = bus;
2520 error = pci_register_host_bridge(bridge);
2530 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2532 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2534 struct resource *res = &b->busn_res;
2535 struct resource *parent_res, *conflict;
2539 res->flags = IORESOURCE_BUS;
2541 if (!pci_is_root_bus(b))
2542 parent_res = &b->parent->busn_res;
2544 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2545 res->flags |= IORESOURCE_PCI_FIXED;
2548 conflict = request_resource_conflict(parent_res, res);
2551 dev_printk(KERN_DEBUG, &b->dev,
2552 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2553 res, pci_is_root_bus(b) ? "domain " : "",
2554 parent_res, conflict->name, conflict);
2556 return conflict == NULL;
2559 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2561 struct resource *res = &b->busn_res;
2562 struct resource old_res = *res;
2563 resource_size_t size;
2566 if (res->start > bus_max)
2569 size = bus_max - res->start + 1;
2570 ret = adjust_resource(res, res->start, size);
2571 dev_printk(KERN_DEBUG, &b->dev,
2572 "busn_res: %pR end %s updated to %02x\n",
2573 &old_res, ret ? "can not be" : "is", bus_max);
2575 if (!ret && !res->parent)
2576 pci_bus_insert_busn_res(b, res->start, res->end);
2581 void pci_bus_release_busn_res(struct pci_bus *b)
2583 struct resource *res = &b->busn_res;
2586 if (!res->flags || !res->parent)
2589 ret = release_resource(res);
2590 dev_printk(KERN_DEBUG, &b->dev,
2591 "busn_res: %pR %s released\n",
2592 res, ret ? "can not be" : "is");
2595 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
2597 struct resource_entry *window;
2605 resource_list_for_each_entry(window, &bridge->windows)
2606 if (window->res->flags & IORESOURCE_BUS) {
2611 ret = pci_register_host_bridge(bridge);
2616 bus = bridge->busnr;
2620 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2622 pci_bus_insert_busn_res(b, bus, 255);
2625 max = pci_scan_child_bus(b);
2628 pci_bus_update_busn_res_end(b, max);
2632 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
2634 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2635 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2637 struct resource_entry *window;
2642 resource_list_for_each_entry(window, resources)
2643 if (window->res->flags & IORESOURCE_BUS) {
2648 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2654 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2656 pci_bus_insert_busn_res(b, bus, 255);
2659 max = pci_scan_child_bus(b);
2662 pci_bus_update_busn_res_end(b, max);
2666 EXPORT_SYMBOL(pci_scan_root_bus);
2668 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2671 LIST_HEAD(resources);
2674 pci_add_resource(&resources, &ioport_resource);
2675 pci_add_resource(&resources, &iomem_resource);
2676 pci_add_resource(&resources, &busn_resource);
2677 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2679 pci_scan_child_bus(b);
2681 pci_free_resource_list(&resources);
2685 EXPORT_SYMBOL(pci_scan_bus);
2688 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2689 * @bridge: PCI bridge for the bus to scan
2691 * Scan a PCI bus and child buses for new devices, add them,
2692 * and enable them, resizing bridge mmio/io resource if necessary
2693 * and possible. The caller must ensure the child devices are already
2694 * removed for resizing to occur.
2696 * Returns the max number of subordinate bus discovered.
2698 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2701 struct pci_bus *bus = bridge->subordinate;
2703 max = pci_scan_child_bus(bus);
2705 pci_assign_unassigned_bridge_resources(bridge);
2707 pci_bus_add_devices(bus);
2713 * pci_rescan_bus - scan a PCI bus for devices.
2714 * @bus: PCI bus to scan
2716 * Scan a PCI bus and child buses for new devices, adds them,
2719 * Returns the max number of subordinate bus discovered.
2721 unsigned int pci_rescan_bus(struct pci_bus *bus)
2725 max = pci_scan_child_bus(bus);
2726 pci_assign_unassigned_bus_resources(bus);
2727 pci_bus_add_devices(bus);
2731 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2734 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2735 * routines should always be executed under this mutex.
2737 static DEFINE_MUTEX(pci_rescan_remove_lock);
2739 void pci_lock_rescan_remove(void)
2741 mutex_lock(&pci_rescan_remove_lock);
2743 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2745 void pci_unlock_rescan_remove(void)
2747 mutex_unlock(&pci_rescan_remove_lock);
2749 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2751 static int __init pci_sort_bf_cmp(const struct device *d_a,
2752 const struct device *d_b)
2754 const struct pci_dev *a = to_pci_dev(d_a);
2755 const struct pci_dev *b = to_pci_dev(d_b);
2757 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2758 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2760 if (a->bus->number < b->bus->number) return -1;
2761 else if (a->bus->number > b->bus->number) return 1;
2763 if (a->devfn < b->devfn) return -1;
2764 else if (a->devfn > b->devfn) return 1;
2769 void __init pci_sort_breadthfirst(void)
2771 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);