1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Express Precision Time Measurement
4 * Copyright (c) 2016, Intel Corporation.
7 #include <linux/module.h>
8 #include <linux/init.h>
12 static void pci_ptm_info(struct pci_dev *dev)
16 switch (dev->ptm_granularity) {
18 snprintf(clock_desc, sizeof(clock_desc), "unknown");
21 snprintf(clock_desc, sizeof(clock_desc), ">254ns");
24 snprintf(clock_desc, sizeof(clock_desc), "%uns",
25 dev->ptm_granularity);
28 pci_info(dev, "PTM enabled%s, %s granularity\n",
29 dev->ptm_root ? " (root)" : "", clock_desc);
32 void pci_ptm_init(struct pci_dev *dev)
39 if (!pci_is_pcie(dev))
43 * Enable PTM only on interior devices (root ports, switch ports,
44 * etc.) on the assumption that it causes no link traffic until an
45 * endpoint enables it.
47 if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
48 pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
52 * Switch Downstream Ports are not permitted to have a PTM
53 * capability; their PTM behavior is controlled by the Upstream
54 * Port (PCIe r5.0, sec 7.9.16).
56 ups = pci_upstream_bridge(dev);
57 if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM &&
58 ups && ups->ptm_enabled) {
59 dev->ptm_granularity = ups->ptm_granularity;
64 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
68 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
69 local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
72 * There's no point in enabling PTM unless it's enabled in the
73 * upstream device or this device can be a PTM Root itself. Per
74 * the spec recommendation (PCIe r3.1, sec 7.32.3), select the
75 * furthest upstream Time Source as the PTM Root.
77 if (ups && ups->ptm_enabled) {
78 ctrl = PCI_PTM_CTRL_ENABLE;
79 if (ups->ptm_granularity == 0)
80 dev->ptm_granularity = 0;
81 else if (ups->ptm_granularity > local_clock)
82 dev->ptm_granularity = ups->ptm_granularity;
84 if (cap & PCI_PTM_CAP_ROOT) {
85 ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
87 dev->ptm_granularity = local_clock;
92 ctrl |= dev->ptm_granularity << 8;
93 pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
99 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
105 if (!pci_is_pcie(dev))
108 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
112 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
113 if (!(cap & PCI_PTM_CAP_REQ))
117 * For a PCIe Endpoint, PTM is only useful if the endpoint can
118 * issue PTM requests to upstream devices that have PTM enabled.
120 * For Root Complex Integrated Endpoints, there is no upstream
121 * device, so there must be some implementation-specific way to
122 * associate the endpoint with a time source.
124 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
125 ups = pci_upstream_bridge(dev);
126 if (!ups || !ups->ptm_enabled)
129 dev->ptm_granularity = ups->ptm_granularity;
130 } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
131 dev->ptm_granularity = 0;
135 ctrl = PCI_PTM_CTRL_ENABLE;
136 ctrl |= dev->ptm_granularity << 8;
137 pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
138 dev->ptm_enabled = 1;
143 *granularity = dev->ptm_granularity;
146 EXPORT_SYMBOL(pci_enable_ptm);