2 * PCI Express Precision Time Measurement
3 * Copyright (c) 2016, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/pci.h>
20 static void pci_ptm_info(struct pci_dev *dev)
24 switch (dev->ptm_granularity) {
26 snprintf(clock_desc, sizeof(clock_desc), "unknown");
29 snprintf(clock_desc, sizeof(clock_desc), ">254ns");
32 snprintf(clock_desc, sizeof(clock_desc), "%uns",
33 dev->ptm_granularity);
36 dev_info(&dev->dev, "PTM enabled%s, %s granularity\n",
37 dev->ptm_root ? " (root)" : "", clock_desc);
40 void pci_ptm_init(struct pci_dev *dev)
47 if (!pci_is_pcie(dev))
51 * Enable PTM only on interior devices (root ports, switch ports,
52 * etc.) on the assumption that it causes no link traffic until an
53 * endpoint enables it.
55 if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
56 pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
60 * Switch Downstream Ports are not permitted to have a PTM
61 * capability; their PTM behavior is controlled by the Upstream
62 * Port (PCIe r5.0, sec 7.9.16).
64 ups = pci_upstream_bridge(dev);
65 if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM &&
66 ups && ups->ptm_enabled) {
67 dev->ptm_granularity = ups->ptm_granularity;
72 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
76 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
77 local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
80 * There's no point in enabling PTM unless it's enabled in the
81 * upstream device or this device can be a PTM Root itself. Per
82 * the spec recommendation (PCIe r3.1, sec 7.32.3), select the
83 * furthest upstream Time Source as the PTM Root.
85 if (ups && ups->ptm_enabled) {
86 ctrl = PCI_PTM_CTRL_ENABLE;
87 if (ups->ptm_granularity == 0)
88 dev->ptm_granularity = 0;
89 else if (ups->ptm_granularity > local_clock)
90 dev->ptm_granularity = ups->ptm_granularity;
92 if (cap & PCI_PTM_CAP_ROOT) {
93 ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
95 dev->ptm_granularity = local_clock;
100 ctrl |= dev->ptm_granularity << 8;
101 pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
102 dev->ptm_enabled = 1;
107 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
113 if (!pci_is_pcie(dev))
116 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
120 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
121 if (!(cap & PCI_PTM_CAP_REQ))
125 * For a PCIe Endpoint, PTM is only useful if the endpoint can
126 * issue PTM requests to upstream devices that have PTM enabled.
128 * For Root Complex Integrated Endpoints, there is no upstream
129 * device, so there must be some implementation-specific way to
130 * associate the endpoint with a time source.
132 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
133 ups = pci_upstream_bridge(dev);
134 if (!ups || !ups->ptm_enabled)
137 dev->ptm_granularity = ups->ptm_granularity;
138 } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
139 dev->ptm_granularity = 0;
143 ctrl = PCI_PTM_CTRL_ENABLE;
144 ctrl |= dev->ptm_granularity << 8;
145 pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
146 dev->ptm_enabled = 1;
151 *granularity = dev->ptm_granularity;
154 EXPORT_SYMBOL(pci_enable_ptm);