1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
23 #ifdef MODULE_PARAM_PREFIX
24 #undef MODULE_PARAM_PREFIX
26 #define MODULE_PARAM_PREFIX "pcie_aspm."
28 /* Note: those are not register definitions */
29 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
30 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
31 #define ASPM_STATE_L1 (4) /* L1 state */
32 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
34 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
35 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
36 #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
37 #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
38 #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
40 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
41 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
45 u32 l0s; /* L0s latency (nsec) */
46 u32 l1; /* L1 latency (nsec) */
49 struct pcie_link_state {
50 struct pci_dev *pdev; /* Upstream component of the Link */
51 struct pci_dev *downstream; /* Downstream component, function 0 */
52 struct pcie_link_state *root; /* pointer to the root port link */
53 struct pcie_link_state *parent; /* pointer to the parent Link state */
54 struct list_head sibling; /* node in link_list */
57 u32 aspm_support:7; /* Supported ASPM state */
58 u32 aspm_enabled:7; /* Enabled ASPM state */
59 u32 aspm_capable:7; /* Capable ASPM state with latency */
60 u32 aspm_default:7; /* Default ASPM state by BIOS */
61 u32 aspm_disable:7; /* Disabled ASPM state */
64 u32 clkpm_capable:1; /* Clock PM capable? */
65 u32 clkpm_enabled:1; /* Current Clock PM state */
66 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
67 u32 clkpm_disable:1; /* Clock PM disabled */
70 struct aspm_latency latency_up; /* Upstream direction exit latency */
71 struct aspm_latency latency_dw; /* Downstream direction exit latency */
73 * Endpoint acceptable latencies. A pcie downstream port only
74 * has one slot under it, so at most there are 8 functions.
76 struct aspm_latency acceptable[8];
79 static int aspm_disabled, aspm_force;
80 static bool aspm_support_enabled = true;
81 static DEFINE_MUTEX(aspm_lock);
82 static LIST_HEAD(link_list);
84 #define POLICY_DEFAULT 0 /* BIOS default setting */
85 #define POLICY_PERFORMANCE 1 /* high performance */
86 #define POLICY_POWERSAVE 2 /* high power saving */
87 #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
89 #ifdef CONFIG_PCIEASPM_PERFORMANCE
90 static int aspm_policy = POLICY_PERFORMANCE;
91 #elif defined CONFIG_PCIEASPM_POWERSAVE
92 static int aspm_policy = POLICY_POWERSAVE;
93 #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
94 static int aspm_policy = POLICY_POWER_SUPERSAVE;
96 static int aspm_policy;
99 static const char *policy_str[] = {
100 [POLICY_DEFAULT] = "default",
101 [POLICY_PERFORMANCE] = "performance",
102 [POLICY_POWERSAVE] = "powersave",
103 [POLICY_POWER_SUPERSAVE] = "powersupersave"
106 #define LINK_RETRAIN_TIMEOUT HZ
108 static int policy_to_aspm_state(struct pcie_link_state *link)
110 switch (aspm_policy) {
111 case POLICY_PERFORMANCE:
112 /* Disable ASPM and Clock PM */
114 case POLICY_POWERSAVE:
115 /* Enable ASPM L0s/L1 */
116 return (ASPM_STATE_L0S | ASPM_STATE_L1);
117 case POLICY_POWER_SUPERSAVE:
118 /* Enable Everything */
119 return ASPM_STATE_ALL;
121 return link->aspm_default;
126 static int policy_to_clkpm_state(struct pcie_link_state *link)
128 switch (aspm_policy) {
129 case POLICY_PERFORMANCE:
130 /* Disable ASPM and Clock PM */
132 case POLICY_POWERSAVE:
133 case POLICY_POWER_SUPERSAVE:
134 /* Enable Clock PM */
137 return link->clkpm_default;
142 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
144 struct pci_dev *child;
145 struct pci_bus *linkbus = link->pdev->subordinate;
146 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
148 list_for_each_entry(child, &linkbus->devices, bus_list)
149 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
150 PCI_EXP_LNKCTL_CLKREQ_EN,
152 link->clkpm_enabled = !!enable;
155 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
158 * Don't enable Clock PM if the link is not Clock PM capable
159 * or Clock PM is disabled
161 if (!link->clkpm_capable || link->clkpm_disable)
163 /* Need nothing if the specified equals to current state */
164 if (link->clkpm_enabled == enable)
166 pcie_set_clkpm_nocheck(link, enable);
169 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
171 int capable = 1, enabled = 1;
174 struct pci_dev *child;
175 struct pci_bus *linkbus = link->pdev->subordinate;
177 /* All functions should have the same cap and state, take the worst */
178 list_for_each_entry(child, &linkbus->devices, bus_list) {
179 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
180 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
185 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
186 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
189 link->clkpm_enabled = enabled;
190 link->clkpm_default = enabled;
191 link->clkpm_capable = capable;
192 link->clkpm_disable = blacklist ? 1 : 0;
195 static bool pcie_retrain_link(struct pcie_link_state *link)
197 struct pci_dev *parent = link->pdev;
198 unsigned long end_jiffies;
201 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
202 reg16 |= PCI_EXP_LNKCTL_RL;
203 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
204 if (parent->clear_retrain_link) {
206 * Due to an erratum in some devices the Retrain Link bit
207 * needs to be cleared again manually to allow the link
208 * training to succeed.
210 reg16 &= ~PCI_EXP_LNKCTL_RL;
211 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
214 /* Wait for link training end. Break out after waiting for timeout */
215 end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
217 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
218 if (!(reg16 & PCI_EXP_LNKSTA_LT))
221 } while (time_before(jiffies, end_jiffies));
222 return !(reg16 & PCI_EXP_LNKSTA_LT);
226 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
227 * could use common clock. If they are, configure them to use the
228 * common clock. That will reduce the ASPM state exit latency.
230 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
233 u16 reg16, parent_reg, child_reg[8];
234 struct pci_dev *child, *parent = link->pdev;
235 struct pci_bus *linkbus = parent->subordinate;
237 * All functions of a slot should have the same Slot Clock
238 * Configuration, so just check one function
240 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
241 BUG_ON(!pci_is_pcie(child));
243 /* Check downstream component if bit Slot Clock Configuration is 1 */
244 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
245 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
248 /* Check upstream component if bit Slot Clock Configuration is 1 */
249 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
250 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
253 /* Port might be already in common clock mode */
254 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
255 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
256 bool consistent = true;
258 list_for_each_entry(child, &linkbus->devices, bus_list) {
259 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
261 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
268 pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
271 /* Configure downstream component, all functions */
272 list_for_each_entry(child, &linkbus->devices, bus_list) {
273 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
274 child_reg[PCI_FUNC(child->devfn)] = reg16;
276 reg16 |= PCI_EXP_LNKCTL_CCC;
278 reg16 &= ~PCI_EXP_LNKCTL_CCC;
279 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
282 /* Configure upstream component */
283 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
286 reg16 |= PCI_EXP_LNKCTL_CCC;
288 reg16 &= ~PCI_EXP_LNKCTL_CCC;
289 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
291 if (pcie_retrain_link(link))
294 /* Training failed. Restore common clock configurations */
295 pci_err(parent, "ASPM: Could not configure common clock\n");
296 list_for_each_entry(child, &linkbus->devices, bus_list)
297 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
298 child_reg[PCI_FUNC(child->devfn)]);
299 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
302 /* Convert L0s latency encoding to ns */
303 static u32 calc_l0s_latency(u32 lnkcap)
305 u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
308 return (5 * 1000); /* > 4us */
309 return (64 << encoding);
312 /* Convert L0s acceptable latency encoding to ns */
313 static u32 calc_l0s_acceptable(u32 encoding)
317 return (64 << encoding);
320 /* Convert L1 latency encoding to ns */
321 static u32 calc_l1_latency(u32 lnkcap)
323 u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
326 return (65 * 1000); /* > 64us */
327 return (1000 << encoding);
330 /* Convert L1 acceptable latency encoding to ns */
331 static u32 calc_l1_acceptable(u32 encoding)
335 return (1000 << encoding);
338 /* Convert L1SS T_pwr encoding to usec */
339 static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
349 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
353 static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
355 u32 threshold_ns = threshold_us * 1000;
357 /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
358 if (threshold_ns < 32) {
360 *value = threshold_ns;
361 } else if (threshold_ns < 1024) {
363 *value = threshold_ns >> 5;
364 } else if (threshold_ns < 32768) {
366 *value = threshold_ns >> 10;
367 } else if (threshold_ns < 1048576) {
369 *value = threshold_ns >> 15;
370 } else if (threshold_ns < 33554432) {
372 *value = threshold_ns >> 20;
375 *value = threshold_ns >> 25;
379 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
381 u32 latency, l1_switch_latency = 0;
382 struct aspm_latency *acceptable;
383 struct pcie_link_state *link;
385 /* Device not in D0 doesn't need latency check */
386 if ((endpoint->current_state != PCI_D0) &&
387 (endpoint->current_state != PCI_UNKNOWN))
390 link = endpoint->bus->self->link_state;
391 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
394 /* Check upstream direction L0s latency */
395 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
396 (link->latency_up.l0s > acceptable->l0s))
397 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
399 /* Check downstream direction L0s latency */
400 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
401 (link->latency_dw.l0s > acceptable->l0s))
402 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
405 * Every switch on the path to root complex need 1
406 * more microsecond for L1. Spec doesn't mention L0s.
408 * The exit latencies for L1 substates are not advertised
409 * by a device. Since the spec also doesn't mention a way
410 * to determine max latencies introduced by enabling L1
411 * substates on the components, it is not clear how to do
412 * a L1 substate exit latency check. We assume that the
413 * L1 exit latencies advertised by a device include L1
414 * substate latencies (and hence do not do any check).
416 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
417 if ((link->aspm_capable & ASPM_STATE_L1) &&
418 (latency + l1_switch_latency > acceptable->l1))
419 link->aspm_capable &= ~ASPM_STATE_L1;
420 l1_switch_latency += 1000;
427 * The L1 PM substate capability is only implemented in function 0 in a
428 * multi function device.
430 static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
432 struct pci_dev *child;
434 list_for_each_entry(child, &linkbus->devices, bus_list)
435 if (PCI_FUNC(child->devfn) == 0)
440 static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
445 pci_read_config_dword(pdev, pos, &val);
448 pci_write_config_dword(pdev, pos, val);
451 /* Calculate L1.2 PM substate timing parameters */
452 static void aspm_calc_l1ss_info(struct pcie_link_state *link,
453 u32 parent_l1ss_cap, u32 child_l1ss_cap)
455 struct pci_dev *child = link->downstream, *parent = link->pdev;
456 u32 val1, val2, scale1, scale2;
457 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
458 u32 ctl1 = 0, ctl2 = 0;
459 u32 pctl1, pctl2, cctl1, cctl2;
460 u32 pl1_2_enables, cl1_2_enables;
462 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
465 /* Choose the greater of the two Port Common_Mode_Restore_Times */
466 val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
467 val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
468 t_common_mode = max(val1, val2);
470 /* Choose the greater of the two Port T_POWER_ON times */
471 val1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
472 scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
473 val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
474 scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
476 if (calc_l1ss_pwron(parent, scale1, val1) >
477 calc_l1ss_pwron(child, scale2, val2)) {
478 ctl2 |= scale1 | (val1 << 3);
479 t_power_on = calc_l1ss_pwron(parent, scale1, val1);
481 ctl2 |= scale2 | (val2 << 3);
482 t_power_on = calc_l1ss_pwron(child, scale2, val2);
486 * Set LTR_L1.2_THRESHOLD to the time required to transition the
487 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
488 * downstream devices report (via LTR) that they can tolerate at
489 * least that much latency.
491 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
492 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
495 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
496 encode_l12_threshold(l1_2_threshold, &scale, &value);
497 ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
499 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
500 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
501 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
502 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
504 if (ctl1 == pctl1 && ctl1 == cctl1 &&
505 ctl2 == pctl2 && ctl2 == cctl2)
508 /* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
509 pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
510 cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
512 if (pl1_2_enables || cl1_2_enables) {
513 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
514 PCI_L1SS_CTL1_L1_2_MASK, 0);
515 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
516 PCI_L1SS_CTL1_L1_2_MASK, 0);
519 /* Program T_POWER_ON times in both ports */
520 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
521 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
523 /* Program Common_Mode_Restore_Time in upstream device */
524 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
525 PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
527 /* Program LTR_L1.2_THRESHOLD time in both ports */
528 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
529 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
530 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
531 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
532 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
533 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
535 if (pl1_2_enables || cl1_2_enables) {
536 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
538 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
543 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
545 struct pci_dev *child = link->downstream, *parent = link->pdev;
546 u32 parent_lnkcap, child_lnkcap;
547 u16 parent_lnkctl, child_lnkctl;
548 u32 parent_l1ss_cap, child_l1ss_cap;
549 u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
550 struct pci_bus *linkbus = parent->subordinate;
553 /* Set enabled/disable so that we will disable ASPM later */
554 link->aspm_enabled = ASPM_STATE_ALL;
555 link->aspm_disable = ASPM_STATE_ALL;
560 * If ASPM not supported, don't mess with the clocks and link,
563 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
564 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
565 if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
568 /* Configure common clock before checking latencies */
569 pcie_aspm_configure_common_clock(link);
572 * Re-read upstream/downstream components' register state after
573 * clock configuration. L0s & L1 exit latencies in the otherwise
574 * read-only Link Capabilities may change depending on common clock
575 * configuration (PCIe r5.0, sec 7.5.3.6).
577 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
578 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
579 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
580 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
585 * Note that we must not enable L0s in either direction on a
586 * given link unless components on both sides of the link each
589 if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
590 link->aspm_support |= ASPM_STATE_L0S;
592 if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
593 link->aspm_enabled |= ASPM_STATE_L0S_UP;
594 if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
595 link->aspm_enabled |= ASPM_STATE_L0S_DW;
596 link->latency_up.l0s = calc_l0s_latency(parent_lnkcap);
597 link->latency_dw.l0s = calc_l0s_latency(child_lnkcap);
600 if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
601 link->aspm_support |= ASPM_STATE_L1;
603 if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
604 link->aspm_enabled |= ASPM_STATE_L1;
605 link->latency_up.l1 = calc_l1_latency(parent_lnkcap);
606 link->latency_dw.l1 = calc_l1_latency(child_lnkcap);
608 /* Setup L1 substate */
609 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
611 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
614 if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
616 if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
620 * If we don't have LTR for the entire path from the Root Complex
621 * to this device, we can't use ASPM L1.2 because it relies on the
622 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
624 if (!child->ltr_path)
625 child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
627 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
628 link->aspm_support |= ASPM_STATE_L1_1;
629 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
630 link->aspm_support |= ASPM_STATE_L1_2;
631 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
632 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
633 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
634 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
637 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
640 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
643 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
644 link->aspm_enabled |= ASPM_STATE_L1_1;
645 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
646 link->aspm_enabled |= ASPM_STATE_L1_2;
647 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
648 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
649 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
650 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
652 if (link->aspm_support & ASPM_STATE_L1SS)
653 aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);
655 /* Save default state */
656 link->aspm_default = link->aspm_enabled;
658 /* Setup initial capable state. Will be updated later */
659 link->aspm_capable = link->aspm_support;
661 /* Get and check endpoint acceptable latencies */
662 list_for_each_entry(child, &linkbus->devices, bus_list) {
664 struct aspm_latency *acceptable =
665 &link->acceptable[PCI_FUNC(child->devfn)];
667 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
668 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
671 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
672 /* Calculate endpoint L0s acceptable latency */
673 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
674 acceptable->l0s = calc_l0s_acceptable(encoding);
675 /* Calculate endpoint L1 acceptable latency */
676 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
677 acceptable->l1 = calc_l1_acceptable(encoding);
679 pcie_aspm_check_latency(child);
683 /* Configure the ASPM L1 substates */
684 static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
687 struct pci_dev *child = link->downstream, *parent = link->pdev;
689 enable_req = (link->aspm_enabled ^ state) & state;
692 * Here are the rules specified in the PCIe spec for enabling L1SS:
693 * - When enabling L1.x, enable bit at parent first, then at child
694 * - When disabling L1.x, disable bit at child first, then at parent
695 * - When enabling ASPM L1.x, need to disable L1
696 * (at child followed by parent).
697 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
700 * To keep it simple, disable all L1SS bits first, and later enable
704 /* Disable all L1 substates */
705 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
706 PCI_L1SS_CTL1_L1SS_MASK, 0);
707 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
708 PCI_L1SS_CTL1_L1SS_MASK, 0);
710 * If needed, disable L1, and it gets enabled later
711 * in pcie_config_aspm_link().
713 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
714 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
715 PCI_EXP_LNKCTL_ASPM_L1, 0);
716 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
717 PCI_EXP_LNKCTL_ASPM_L1, 0);
721 if (state & ASPM_STATE_L1_1)
722 val |= PCI_L1SS_CTL1_ASPM_L1_1;
723 if (state & ASPM_STATE_L1_2)
724 val |= PCI_L1SS_CTL1_ASPM_L1_2;
725 if (state & ASPM_STATE_L1_1_PCIPM)
726 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
727 if (state & ASPM_STATE_L1_2_PCIPM)
728 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
730 /* Enable what we need to enable */
731 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
732 PCI_L1SS_CTL1_L1SS_MASK, val);
733 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
734 PCI_L1SS_CTL1_L1SS_MASK, val);
737 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
739 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
740 PCI_EXP_LNKCTL_ASPMC, val);
743 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
745 u32 upstream = 0, dwstream = 0;
746 struct pci_dev *child = link->downstream, *parent = link->pdev;
747 struct pci_bus *linkbus = parent->subordinate;
749 /* Enable only the states that were not explicitly disabled */
750 state &= (link->aspm_capable & ~link->aspm_disable);
752 /* Can't enable any substates if L1 is not enabled */
753 if (!(state & ASPM_STATE_L1))
754 state &= ~ASPM_STATE_L1SS;
756 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
757 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
758 state &= ~ASPM_STATE_L1_SS_PCIPM;
759 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
762 /* Nothing to do if the link is already in the requested state */
763 if (link->aspm_enabled == state)
765 /* Convert ASPM state to upstream/downstream ASPM register state */
766 if (state & ASPM_STATE_L0S_UP)
767 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
768 if (state & ASPM_STATE_L0S_DW)
769 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
770 if (state & ASPM_STATE_L1) {
771 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
772 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
775 if (link->aspm_capable & ASPM_STATE_L1SS)
776 pcie_config_aspm_l1ss(link, state);
779 * Spec 2.0 suggests all functions should be configured the
780 * same setting for ASPM. Enabling ASPM L1 should be done in
781 * upstream component first and then downstream, and vice
782 * versa for disabling ASPM L1. Spec doesn't mention L0S.
784 if (state & ASPM_STATE_L1)
785 pcie_config_aspm_dev(parent, upstream);
786 list_for_each_entry(child, &linkbus->devices, bus_list)
787 pcie_config_aspm_dev(child, dwstream);
788 if (!(state & ASPM_STATE_L1))
789 pcie_config_aspm_dev(parent, upstream);
791 link->aspm_enabled = state;
794 static void pcie_config_aspm_path(struct pcie_link_state *link)
797 pcie_config_aspm_link(link, policy_to_aspm_state(link));
802 static void free_link_state(struct pcie_link_state *link)
804 link->pdev->link_state = NULL;
808 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
810 struct pci_dev *child;
814 * Some functions in a slot might not all be PCIe functions,
815 * very strange. Disable ASPM for the whole slot
817 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
818 if (!pci_is_pcie(child))
822 * If ASPM is disabled then we're not going to change
823 * the BIOS state. It's safe to continue even if it's a
831 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
832 * RBER bit to determine if a function is 1.1 version device
834 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
835 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
836 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
843 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
845 struct pcie_link_state *link;
847 link = kzalloc(sizeof(*link), GFP_KERNEL);
851 INIT_LIST_HEAD(&link->sibling);
853 link->downstream = pci_function_0(pdev->subordinate);
856 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
857 * hierarchies. Note that some PCIe host implementations omit
858 * the root ports entirely, in which case a downstream port on
859 * a switch may become the root of the link state chain for all
860 * its subordinate endpoints.
862 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
863 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
864 !pdev->bus->parent->self) {
867 struct pcie_link_state *parent;
869 parent = pdev->bus->parent->self->link_state;
875 link->parent = parent;
876 link->root = link->parent->root;
879 list_add(&link->sibling, &link_list);
880 pdev->link_state = link;
884 static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)
886 struct pci_dev *child;
888 list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
889 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group);
893 * pcie_aspm_init_link_state: Initiate PCI express link state.
894 * It is called after the pcie and its children devices are scanned.
895 * @pdev: the root port or switch downstream port
897 void pcie_aspm_init_link_state(struct pci_dev *pdev)
899 struct pcie_link_state *link;
900 int blacklist = !!pcie_aspm_sanity_check(pdev);
902 if (!aspm_support_enabled)
905 if (pdev->link_state)
909 * We allocate pcie_link_state for the component on the upstream
910 * end of a Link, so there's nothing to do unless this device is
913 if (!pcie_downstream_port(pdev))
916 /* VIA has a strange chipset, root port is under a bridge */
917 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
921 down_read(&pci_bus_sem);
922 if (list_empty(&pdev->subordinate->devices))
925 mutex_lock(&aspm_lock);
926 link = alloc_pcie_link_state(pdev);
930 * Setup initial ASPM state. Note that we need to configure
931 * upstream links also because capable state of them can be
932 * update through pcie_aspm_cap_init().
934 pcie_aspm_cap_init(link, blacklist);
936 /* Setup initial Clock PM state */
937 pcie_clkpm_cap_init(link, blacklist);
940 * At this stage drivers haven't had an opportunity to change the
941 * link policy setting. Enabling ASPM on broken hardware can cripple
942 * it even before the driver has had a chance to disable ASPM, so
943 * default to a safe level right now. If we're enabling ASPM beyond
944 * the BIOS's expectation, we'll do so once pci_enable_device() is
947 if (aspm_policy != POLICY_POWERSAVE &&
948 aspm_policy != POLICY_POWER_SUPERSAVE) {
949 pcie_config_aspm_path(link);
950 pcie_set_clkpm(link, policy_to_clkpm_state(link));
953 pcie_aspm_update_sysfs_visibility(pdev);
956 mutex_unlock(&aspm_lock);
958 up_read(&pci_bus_sem);
961 /* Recheck latencies and update aspm_capable for links under the root */
962 static void pcie_update_aspm_capable(struct pcie_link_state *root)
964 struct pcie_link_state *link;
965 BUG_ON(root->parent);
966 list_for_each_entry(link, &link_list, sibling) {
967 if (link->root != root)
969 link->aspm_capable = link->aspm_support;
971 list_for_each_entry(link, &link_list, sibling) {
972 struct pci_dev *child;
973 struct pci_bus *linkbus = link->pdev->subordinate;
974 if (link->root != root)
976 list_for_each_entry(child, &linkbus->devices, bus_list) {
977 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
978 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
980 pcie_aspm_check_latency(child);
985 /* @pdev: the endpoint device */
986 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
988 struct pci_dev *parent = pdev->bus->self;
989 struct pcie_link_state *link, *root, *parent_link;
991 if (!parent || !parent->link_state)
994 down_read(&pci_bus_sem);
995 mutex_lock(&aspm_lock);
997 * All PCIe functions are in one slot, remove one function will remove
998 * the whole slot, so just wait until we are the last function left.
1000 if (!list_empty(&parent->subordinate->devices))
1003 link = parent->link_state;
1005 parent_link = link->parent;
1007 /* All functions are removed, so just disable ASPM for the link */
1008 pcie_config_aspm_link(link, 0);
1009 list_del(&link->sibling);
1010 /* Clock PM is for endpoint device */
1011 free_link_state(link);
1013 /* Recheck latencies and configure upstream links */
1015 pcie_update_aspm_capable(root);
1016 pcie_config_aspm_path(parent_link);
1019 mutex_unlock(&aspm_lock);
1020 up_read(&pci_bus_sem);
1023 /* @pdev: the root port or switch downstream port */
1024 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
1026 struct pcie_link_state *link = pdev->link_state;
1028 if (aspm_disabled || !link)
1031 * Devices changed PM state, we should recheck if latency
1032 * meets all functions' requirement
1034 down_read(&pci_bus_sem);
1035 mutex_lock(&aspm_lock);
1036 pcie_update_aspm_capable(link->root);
1037 pcie_config_aspm_path(link);
1038 mutex_unlock(&aspm_lock);
1039 up_read(&pci_bus_sem);
1042 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1044 struct pcie_link_state *link = pdev->link_state;
1046 if (aspm_disabled || !link)
1049 if (aspm_policy != POLICY_POWERSAVE &&
1050 aspm_policy != POLICY_POWER_SUPERSAVE)
1053 down_read(&pci_bus_sem);
1054 mutex_lock(&aspm_lock);
1055 pcie_config_aspm_path(link);
1056 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1057 mutex_unlock(&aspm_lock);
1058 up_read(&pci_bus_sem);
1061 static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
1063 struct pci_dev *bridge;
1065 if (!pci_is_pcie(pdev))
1068 bridge = pci_upstream_bridge(pdev);
1069 if (!bridge || !pci_is_pcie(bridge))
1072 return bridge->link_state;
1075 static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1077 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1082 * A driver requested that ASPM be disabled on this device, but
1083 * if we don't have permission to manage ASPM (e.g., on ACPI
1084 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1085 * the _OSC method), we can't honor that request. Windows has
1086 * a similar mechanism using "PciASPMOptOut", which is also
1087 * ignored in this situation.
1089 if (aspm_disabled) {
1090 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1095 down_read(&pci_bus_sem);
1096 mutex_lock(&aspm_lock);
1097 if (state & PCIE_LINK_STATE_L0S)
1098 link->aspm_disable |= ASPM_STATE_L0S;
1099 if (state & PCIE_LINK_STATE_L1)
1100 /* L1 PM substates require L1 */
1101 link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
1102 if (state & PCIE_LINK_STATE_L1_1)
1103 link->aspm_disable |= ASPM_STATE_L1_1;
1104 if (state & PCIE_LINK_STATE_L1_2)
1105 link->aspm_disable |= ASPM_STATE_L1_2;
1106 if (state & PCIE_LINK_STATE_L1_1_PCIPM)
1107 link->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
1108 if (state & PCIE_LINK_STATE_L1_2_PCIPM)
1109 link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
1110 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1112 if (state & PCIE_LINK_STATE_CLKPM)
1113 link->clkpm_disable = 1;
1114 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1115 mutex_unlock(&aspm_lock);
1117 up_read(&pci_bus_sem);
1122 int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1124 return __pci_disable_link_state(pdev, state, false);
1126 EXPORT_SYMBOL(pci_disable_link_state_locked);
1129 * pci_disable_link_state - Disable device's link state, so the link will
1130 * never enter specific states. Note that if the BIOS didn't grant ASPM
1131 * control to the OS, this does nothing because we can't touch the LNKCTL
1132 * register. Returns 0 or a negative errno.
1135 * @state: ASPM link state to disable
1137 int pci_disable_link_state(struct pci_dev *pdev, int state)
1139 return __pci_disable_link_state(pdev, state, true);
1141 EXPORT_SYMBOL(pci_disable_link_state);
1143 static int pcie_aspm_set_policy(const char *val,
1144 const struct kernel_param *kp)
1147 struct pcie_link_state *link;
1151 i = sysfs_match_string(policy_str, val);
1154 if (i == aspm_policy)
1157 down_read(&pci_bus_sem);
1158 mutex_lock(&aspm_lock);
1160 list_for_each_entry(link, &link_list, sibling) {
1161 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1162 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1164 mutex_unlock(&aspm_lock);
1165 up_read(&pci_bus_sem);
1169 static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1172 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1173 if (i == aspm_policy)
1174 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1176 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1177 cnt += sprintf(buffer + cnt, "\n");
1181 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1185 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1186 * @pdev: Target device.
1188 * Relies on the upstream bridge's link_state being valid. The link_state
1189 * is deallocated only when the last child of the bridge (i.e., @pdev or a
1190 * sibling) is removed, and the caller should be holding a reference to
1191 * @pdev, so this should be safe.
1193 bool pcie_aspm_enabled(struct pci_dev *pdev)
1195 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1200 return link->aspm_enabled;
1202 EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1204 static ssize_t aspm_attr_show_common(struct device *dev,
1205 struct device_attribute *attr,
1206 char *buf, u8 state)
1208 struct pci_dev *pdev = to_pci_dev(dev);
1209 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1211 return sprintf(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0);
1214 static ssize_t aspm_attr_store_common(struct device *dev,
1215 struct device_attribute *attr,
1216 const char *buf, size_t len, u8 state)
1218 struct pci_dev *pdev = to_pci_dev(dev);
1219 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1222 if (strtobool(buf, &state_enable) < 0)
1225 down_read(&pci_bus_sem);
1226 mutex_lock(&aspm_lock);
1229 link->aspm_disable &= ~state;
1230 /* need to enable L1 for substates */
1231 if (state & ASPM_STATE_L1SS)
1232 link->aspm_disable &= ~ASPM_STATE_L1;
1234 link->aspm_disable |= state;
1237 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1239 mutex_unlock(&aspm_lock);
1240 up_read(&pci_bus_sem);
1245 #define ASPM_ATTR(_f, _s) \
1246 static ssize_t _f##_show(struct device *dev, \
1247 struct device_attribute *attr, char *buf) \
1248 { return aspm_attr_show_common(dev, attr, buf, ASPM_STATE_##_s); } \
1250 static ssize_t _f##_store(struct device *dev, \
1251 struct device_attribute *attr, \
1252 const char *buf, size_t len) \
1253 { return aspm_attr_store_common(dev, attr, buf, len, ASPM_STATE_##_s); }
1255 ASPM_ATTR(l0s_aspm, L0S)
1256 ASPM_ATTR(l1_aspm, L1)
1257 ASPM_ATTR(l1_1_aspm, L1_1)
1258 ASPM_ATTR(l1_2_aspm, L1_2)
1259 ASPM_ATTR(l1_1_pcipm, L1_1_PCIPM)
1260 ASPM_ATTR(l1_2_pcipm, L1_2_PCIPM)
1262 static ssize_t clkpm_show(struct device *dev,
1263 struct device_attribute *attr, char *buf)
1265 struct pci_dev *pdev = to_pci_dev(dev);
1266 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1268 return sprintf(buf, "%d\n", link->clkpm_enabled);
1271 static ssize_t clkpm_store(struct device *dev,
1272 struct device_attribute *attr,
1273 const char *buf, size_t len)
1275 struct pci_dev *pdev = to_pci_dev(dev);
1276 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1279 if (strtobool(buf, &state_enable) < 0)
1282 down_read(&pci_bus_sem);
1283 mutex_lock(&aspm_lock);
1285 link->clkpm_disable = !state_enable;
1286 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1288 mutex_unlock(&aspm_lock);
1289 up_read(&pci_bus_sem);
1294 static DEVICE_ATTR_RW(clkpm);
1295 static DEVICE_ATTR_RW(l0s_aspm);
1296 static DEVICE_ATTR_RW(l1_aspm);
1297 static DEVICE_ATTR_RW(l1_1_aspm);
1298 static DEVICE_ATTR_RW(l1_2_aspm);
1299 static DEVICE_ATTR_RW(l1_1_pcipm);
1300 static DEVICE_ATTR_RW(l1_2_pcipm);
1302 static struct attribute *aspm_ctrl_attrs[] = {
1303 &dev_attr_clkpm.attr,
1304 &dev_attr_l0s_aspm.attr,
1305 &dev_attr_l1_aspm.attr,
1306 &dev_attr_l1_1_aspm.attr,
1307 &dev_attr_l1_2_aspm.attr,
1308 &dev_attr_l1_1_pcipm.attr,
1309 &dev_attr_l1_2_pcipm.attr,
1313 static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
1314 struct attribute *a, int n)
1316 struct device *dev = kobj_to_dev(kobj);
1317 struct pci_dev *pdev = to_pci_dev(dev);
1318 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1319 static const u8 aspm_state_map[] = {
1324 ASPM_STATE_L1_1_PCIPM,
1325 ASPM_STATE_L1_2_PCIPM,
1328 if (aspm_disabled || !link)
1332 return link->clkpm_capable ? a->mode : 0;
1334 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
1337 const struct attribute_group aspm_ctrl_attr_group = {
1339 .attrs = aspm_ctrl_attrs,
1340 .is_visible = aspm_ctrl_attrs_are_visible,
1343 static int __init pcie_aspm_disable(char *str)
1345 if (!strcmp(str, "off")) {
1346 aspm_policy = POLICY_DEFAULT;
1348 aspm_support_enabled = false;
1349 printk(KERN_INFO "PCIe ASPM is disabled\n");
1350 } else if (!strcmp(str, "force")) {
1352 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1357 __setup("pcie_aspm=", pcie_aspm_disable);
1359 void pcie_no_aspm(void)
1362 * Disabling ASPM is intended to prevent the kernel from modifying
1363 * existing hardware state, not to clear existing state. To that end:
1364 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1365 * (b) prevent userspace from changing policy
1368 aspm_policy = POLICY_DEFAULT;
1373 bool pcie_aspm_support_enabled(void)
1375 return aspm_support_enabled;
1377 EXPORT_SYMBOL(pcie_aspm_support_enabled);