2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 /* Note: those are not register definitions */
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
34 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
37 u32 l0s; /* L0s latency (nsec) */
38 u32 l1; /* L1 latency (nsec) */
41 struct pcie_link_state {
42 struct pci_dev *pdev; /* Upstream component of the Link */
43 struct pcie_link_state *root; /* pointer to the root port link */
44 struct pcie_link_state *parent; /* pointer to the parent Link state */
45 struct list_head sibling; /* node in link_list */
46 struct list_head children; /* list of child link states */
47 struct list_head link; /* node in parent's children list */
50 u32 aspm_support:3; /* Supported ASPM state */
51 u32 aspm_enabled:3; /* Enabled ASPM state */
52 u32 aspm_capable:3; /* Capable ASPM state with latency */
53 u32 aspm_default:3; /* Default ASPM state by BIOS */
54 u32 aspm_disable:3; /* Disabled ASPM state */
57 u32 clkpm_capable:1; /* Clock PM capable? */
58 u32 clkpm_enabled:1; /* Current Clock PM state */
59 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
60 u32 clkpm_disable:1; /* Clock PM disabled */
63 struct aspm_latency latency_up; /* Upstream direction exit latency */
64 struct aspm_latency latency_dw; /* Downstream direction exit latency */
66 * Endpoint acceptable latencies. A pcie downstream port only
67 * has one slot under it, so at most there are 8 functions.
69 struct aspm_latency acceptable[8];
72 static int aspm_disabled, aspm_force;
73 static bool aspm_support_enabled = true;
74 static DEFINE_MUTEX(aspm_lock);
75 static LIST_HEAD(link_list);
77 #define POLICY_DEFAULT 0 /* BIOS default setting */
78 #define POLICY_PERFORMANCE 1 /* high performance */
79 #define POLICY_POWERSAVE 2 /* high power saving */
81 #ifdef CONFIG_PCIEASPM_PERFORMANCE
82 static int aspm_policy = POLICY_PERFORMANCE;
83 #elif defined CONFIG_PCIEASPM_POWERSAVE
84 static int aspm_policy = POLICY_POWERSAVE;
86 static int aspm_policy;
89 static const char *policy_str[] = {
90 [POLICY_DEFAULT] = "default",
91 [POLICY_PERFORMANCE] = "performance",
92 [POLICY_POWERSAVE] = "powersave"
95 #define LINK_RETRAIN_TIMEOUT HZ
97 static int policy_to_aspm_state(struct pcie_link_state *link)
99 switch (aspm_policy) {
100 case POLICY_PERFORMANCE:
101 /* Disable ASPM and Clock PM */
103 case POLICY_POWERSAVE:
104 /* Enable ASPM L0s/L1 */
105 return ASPM_STATE_ALL;
107 return link->aspm_default;
112 static int policy_to_clkpm_state(struct pcie_link_state *link)
114 switch (aspm_policy) {
115 case POLICY_PERFORMANCE:
116 /* Disable ASPM and Clock PM */
118 case POLICY_POWERSAVE:
119 /* Disable Clock PM */
122 return link->clkpm_default;
127 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
129 struct pci_dev *child;
130 struct pci_bus *linkbus = link->pdev->subordinate;
131 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
133 list_for_each_entry(child, &linkbus->devices, bus_list)
134 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
135 PCI_EXP_LNKCTL_CLKREQ_EN,
137 link->clkpm_enabled = !!enable;
140 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
143 * Don't enable Clock PM if the link is not Clock PM capable
144 * or Clock PM is disabled
146 if (!link->clkpm_capable || link->clkpm_disable)
148 /* Need nothing if the specified equals to current state */
149 if (link->clkpm_enabled == enable)
151 pcie_set_clkpm_nocheck(link, enable);
154 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
156 int capable = 1, enabled = 1;
159 struct pci_dev *child;
160 struct pci_bus *linkbus = link->pdev->subordinate;
162 /* All functions should have the same cap and state, take the worst */
163 list_for_each_entry(child, &linkbus->devices, bus_list) {
164 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
165 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
170 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
171 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
174 link->clkpm_enabled = enabled;
175 link->clkpm_default = enabled;
176 link->clkpm_capable = capable;
177 link->clkpm_disable = blacklist ? 1 : 0;
180 static bool pcie_retrain_link(struct pcie_link_state *link)
182 struct pci_dev *parent = link->pdev;
183 unsigned long start_jiffies;
186 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
187 reg16 |= PCI_EXP_LNKCTL_RL;
188 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
189 if (parent->clear_retrain_link) {
191 * Due to an erratum in some devices the Retrain Link bit
192 * needs to be cleared again manually to allow the link
193 * training to succeed.
195 reg16 &= ~PCI_EXP_LNKCTL_RL;
196 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
199 /* Wait for link training end. Break out after waiting for timeout */
200 start_jiffies = jiffies;
202 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
203 if (!(reg16 & PCI_EXP_LNKSTA_LT))
205 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
209 return !(reg16 & PCI_EXP_LNKSTA_LT);
213 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
214 * could use common clock. If they are, configure them to use the
215 * common clock. That will reduce the ASPM state exit latency.
217 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
220 u16 reg16, parent_reg, child_reg[8];
221 struct pci_dev *child, *parent = link->pdev;
222 struct pci_bus *linkbus = parent->subordinate;
224 * All functions of a slot should have the same Slot Clock
225 * Configuration, so just check one function
227 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
228 BUG_ON(!pci_is_pcie(child));
230 /* Check downstream component if bit Slot Clock Configuration is 1 */
231 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
232 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
235 /* Check upstream component if bit Slot Clock Configuration is 1 */
236 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
237 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
240 /* Configure downstream component, all functions */
241 list_for_each_entry(child, &linkbus->devices, bus_list) {
242 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
243 child_reg[PCI_FUNC(child->devfn)] = reg16;
245 reg16 |= PCI_EXP_LNKCTL_CCC;
247 reg16 &= ~PCI_EXP_LNKCTL_CCC;
248 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
251 /* Configure upstream component */
252 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
255 reg16 |= PCI_EXP_LNKCTL_CCC;
257 reg16 &= ~PCI_EXP_LNKCTL_CCC;
258 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
260 if (pcie_retrain_link(link))
263 /* Training failed. Restore common clock configurations */
264 dev_err(&parent->dev, "ASPM: Could not configure common clock\n");
265 list_for_each_entry(child, &linkbus->devices, bus_list)
266 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
267 child_reg[PCI_FUNC(child->devfn)]);
268 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
271 /* Convert L0s latency encoding to ns */
272 static u32 calc_l0s_latency(u32 encoding)
275 return (5 * 1000); /* > 4us */
276 return (64 << encoding);
279 /* Convert L0s acceptable latency encoding to ns */
280 static u32 calc_l0s_acceptable(u32 encoding)
284 return (64 << encoding);
287 /* Convert L1 latency encoding to ns */
288 static u32 calc_l1_latency(u32 encoding)
291 return (65 * 1000); /* > 64us */
292 return (1000 << encoding);
295 /* Convert L1 acceptable latency encoding to ns */
296 static u32 calc_l1_acceptable(u32 encoding)
300 return (1000 << encoding);
303 struct aspm_register_info {
306 u32 latency_encoding_l0s;
307 u32 latency_encoding_l1;
310 static void pcie_get_aspm_reg(struct pci_dev *pdev,
311 struct aspm_register_info *info)
316 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
317 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
318 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
319 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
320 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
321 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
324 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
326 u32 latency, l1_switch_latency = 0;
327 struct aspm_latency *acceptable;
328 struct pcie_link_state *link;
330 /* Device not in D0 doesn't need latency check */
331 if ((endpoint->current_state != PCI_D0) &&
332 (endpoint->current_state != PCI_UNKNOWN))
335 link = endpoint->bus->self->link_state;
336 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
339 /* Check upstream direction L0s latency */
340 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
341 (link->latency_up.l0s > acceptable->l0s))
342 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
344 /* Check downstream direction L0s latency */
345 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
346 (link->latency_dw.l0s > acceptable->l0s))
347 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
350 * Every switch on the path to root complex need 1
351 * more microsecond for L1. Spec doesn't mention L0s.
353 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
354 if ((link->aspm_capable & ASPM_STATE_L1) &&
355 (latency + l1_switch_latency > acceptable->l1))
356 link->aspm_capable &= ~ASPM_STATE_L1;
357 l1_switch_latency += 1000;
363 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
365 struct pci_dev *child, *parent = link->pdev;
366 struct pci_bus *linkbus = parent->subordinate;
367 struct aspm_register_info upreg, dwreg;
370 /* Set enabled/disable so that we will disable ASPM later */
371 link->aspm_enabled = ASPM_STATE_ALL;
372 link->aspm_disable = ASPM_STATE_ALL;
376 /* Configure common clock before checking latencies */
377 pcie_aspm_configure_common_clock(link);
379 /* Get upstream/downstream components' register state */
380 pcie_get_aspm_reg(parent, &upreg);
381 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
382 pcie_get_aspm_reg(child, &dwreg);
387 * Note that we must not enable L0s in either direction on a
388 * given link unless components on both sides of the link each
391 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
392 link->aspm_support |= ASPM_STATE_L0S;
393 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
394 link->aspm_enabled |= ASPM_STATE_L0S_UP;
395 if (upreg.enabled & PCIE_LINK_STATE_L0S)
396 link->aspm_enabled |= ASPM_STATE_L0S_DW;
397 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
398 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
401 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
402 link->aspm_support |= ASPM_STATE_L1;
403 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
404 link->aspm_enabled |= ASPM_STATE_L1;
405 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
406 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
408 /* Save default state */
409 link->aspm_default = link->aspm_enabled;
411 /* Setup initial capable state. Will be updated later */
412 link->aspm_capable = link->aspm_support;
414 /* Get and check endpoint acceptable latencies */
415 list_for_each_entry(child, &linkbus->devices, bus_list) {
417 struct aspm_latency *acceptable =
418 &link->acceptable[PCI_FUNC(child->devfn)];
420 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
421 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
424 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
425 /* Calculate endpoint L0s acceptable latency */
426 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
427 acceptable->l0s = calc_l0s_acceptable(encoding);
428 /* Calculate endpoint L1 acceptable latency */
429 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
430 acceptable->l1 = calc_l1_acceptable(encoding);
432 pcie_aspm_check_latency(child);
436 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
438 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
439 PCI_EXP_LNKCTL_ASPMC, val);
442 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
444 u32 upstream = 0, dwstream = 0;
445 struct pci_dev *child, *parent = link->pdev;
446 struct pci_bus *linkbus = parent->subordinate;
448 /* Nothing to do if the link is already in the requested state */
449 state &= (link->aspm_capable & ~link->aspm_disable);
450 if (link->aspm_enabled == state)
452 /* Convert ASPM state to upstream/downstream ASPM register state */
453 if (state & ASPM_STATE_L0S_UP)
454 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
455 if (state & ASPM_STATE_L0S_DW)
456 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
457 if (state & ASPM_STATE_L1) {
458 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
459 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
462 * Spec 2.0 suggests all functions should be configured the
463 * same setting for ASPM. Enabling ASPM L1 should be done in
464 * upstream component first and then downstream, and vice
465 * versa for disabling ASPM L1. Spec doesn't mention L0S.
467 if (state & ASPM_STATE_L1)
468 pcie_config_aspm_dev(parent, upstream);
469 list_for_each_entry(child, &linkbus->devices, bus_list)
470 pcie_config_aspm_dev(child, dwstream);
471 if (!(state & ASPM_STATE_L1))
472 pcie_config_aspm_dev(parent, upstream);
474 link->aspm_enabled = state;
477 static void pcie_config_aspm_path(struct pcie_link_state *link)
480 pcie_config_aspm_link(link, policy_to_aspm_state(link));
485 static void free_link_state(struct pcie_link_state *link)
487 link->pdev->link_state = NULL;
491 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
493 struct pci_dev *child;
497 * Some functions in a slot might not all be PCIe functions,
498 * very strange. Disable ASPM for the whole slot
500 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
501 if (!pci_is_pcie(child))
505 * If ASPM is disabled then we're not going to change
506 * the BIOS state. It's safe to continue even if it's a
514 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
515 * RBER bit to determine if a function is 1.1 version device
517 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
518 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
519 dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
526 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
528 struct pcie_link_state *link;
530 link = kzalloc(sizeof(*link), GFP_KERNEL);
534 INIT_LIST_HEAD(&link->sibling);
535 INIT_LIST_HEAD(&link->children);
536 INIT_LIST_HEAD(&link->link);
540 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
541 * hierarchies. Note that some PCIe host implementations omit
542 * the root ports entirely, in which case a downstream port on
543 * a switch may become the root of the link state chain for all
544 * its subordinate endpoints.
546 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
547 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
548 !pdev->bus->parent->self) {
551 struct pcie_link_state *parent;
553 parent = pdev->bus->parent->self->link_state;
559 link->parent = parent;
560 link->root = link->parent->root;
561 list_add(&link->link, &parent->children);
564 list_add(&link->sibling, &link_list);
565 pdev->link_state = link;
570 * pcie_aspm_init_link_state: Initiate PCI express link state.
571 * It is called after the pcie and its children devices are scanned.
572 * @pdev: the root port or switch downstream port
574 void pcie_aspm_init_link_state(struct pci_dev *pdev)
576 struct pcie_link_state *link;
577 int blacklist = !!pcie_aspm_sanity_check(pdev);
579 if (!aspm_support_enabled)
582 if (pdev->link_state)
586 * We allocate pcie_link_state for the component on the upstream
587 * end of a Link, so there's nothing to do unless this device has a
588 * Link on its secondary side.
590 if (!pdev->has_secondary_link)
593 /* VIA has a strange chipset, root port is under a bridge */
594 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
598 down_read(&pci_bus_sem);
599 if (list_empty(&pdev->subordinate->devices))
602 mutex_lock(&aspm_lock);
603 link = alloc_pcie_link_state(pdev);
607 * Setup initial ASPM state. Note that we need to configure
608 * upstream links also because capable state of them can be
609 * update through pcie_aspm_cap_init().
611 pcie_aspm_cap_init(link, blacklist);
613 /* Setup initial Clock PM state */
614 pcie_clkpm_cap_init(link, blacklist);
617 * At this stage drivers haven't had an opportunity to change the
618 * link policy setting. Enabling ASPM on broken hardware can cripple
619 * it even before the driver has had a chance to disable ASPM, so
620 * default to a safe level right now. If we're enabling ASPM beyond
621 * the BIOS's expectation, we'll do so once pci_enable_device() is
624 if (aspm_policy != POLICY_POWERSAVE) {
625 pcie_config_aspm_path(link);
626 pcie_set_clkpm(link, policy_to_clkpm_state(link));
630 mutex_unlock(&aspm_lock);
632 up_read(&pci_bus_sem);
635 /* Recheck latencies and update aspm_capable for links under the root */
636 static void pcie_update_aspm_capable(struct pcie_link_state *root)
638 struct pcie_link_state *link;
639 BUG_ON(root->parent);
640 list_for_each_entry(link, &link_list, sibling) {
641 if (link->root != root)
643 link->aspm_capable = link->aspm_support;
645 list_for_each_entry(link, &link_list, sibling) {
646 struct pci_dev *child;
647 struct pci_bus *linkbus = link->pdev->subordinate;
648 if (link->root != root)
650 list_for_each_entry(child, &linkbus->devices, bus_list) {
651 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
652 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
654 pcie_aspm_check_latency(child);
659 /* @pdev: the endpoint device */
660 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
662 struct pci_dev *parent = pdev->bus->self;
663 struct pcie_link_state *link, *root, *parent_link;
665 if (!parent || !parent->link_state)
668 down_read(&pci_bus_sem);
669 mutex_lock(&aspm_lock);
671 * All PCIe functions are in one slot, remove one function will remove
672 * the whole slot, so just wait until we are the last function left.
674 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
677 link = parent->link_state;
679 parent_link = link->parent;
681 /* All functions are removed, so just disable ASPM for the link */
682 pcie_config_aspm_link(link, 0);
683 list_del(&link->sibling);
684 list_del(&link->link);
685 /* Clock PM is for endpoint device */
686 free_link_state(link);
688 /* Recheck latencies and configure upstream links */
690 pcie_update_aspm_capable(root);
691 pcie_config_aspm_path(parent_link);
694 mutex_unlock(&aspm_lock);
695 up_read(&pci_bus_sem);
698 /* @pdev: the root port or switch downstream port */
699 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
701 struct pcie_link_state *link = pdev->link_state;
703 if (aspm_disabled || !link)
706 * Devices changed PM state, we should recheck if latency
707 * meets all functions' requirement
709 down_read(&pci_bus_sem);
710 mutex_lock(&aspm_lock);
711 pcie_update_aspm_capable(link->root);
712 pcie_config_aspm_path(link);
713 mutex_unlock(&aspm_lock);
714 up_read(&pci_bus_sem);
717 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
719 struct pcie_link_state *link = pdev->link_state;
721 if (aspm_disabled || !link)
724 if (aspm_policy != POLICY_POWERSAVE)
727 down_read(&pci_bus_sem);
728 mutex_lock(&aspm_lock);
729 pcie_config_aspm_path(link);
730 pcie_set_clkpm(link, policy_to_clkpm_state(link));
731 mutex_unlock(&aspm_lock);
732 up_read(&pci_bus_sem);
735 static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
737 struct pci_dev *parent = pdev->bus->self;
738 struct pcie_link_state *link;
740 if (!pci_is_pcie(pdev))
743 if (pdev->has_secondary_link)
745 if (!parent || !parent->link_state)
749 * A driver requested that ASPM be disabled on this device, but
750 * if we don't have permission to manage ASPM (e.g., on ACPI
751 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
752 * the _OSC method), we can't honor that request. Windows has
753 * a similar mechanism using "PciASPMOptOut", which is also
754 * ignored in this situation.
757 dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n");
762 down_read(&pci_bus_sem);
763 mutex_lock(&aspm_lock);
764 link = parent->link_state;
765 if (state & PCIE_LINK_STATE_L0S)
766 link->aspm_disable |= ASPM_STATE_L0S;
767 if (state & PCIE_LINK_STATE_L1)
768 link->aspm_disable |= ASPM_STATE_L1;
769 pcie_config_aspm_link(link, policy_to_aspm_state(link));
771 if (state & PCIE_LINK_STATE_CLKPM)
772 link->clkpm_disable = 1;
773 pcie_set_clkpm(link, policy_to_clkpm_state(link));
774 mutex_unlock(&aspm_lock);
776 up_read(&pci_bus_sem);
779 void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
781 __pci_disable_link_state(pdev, state, false);
783 EXPORT_SYMBOL(pci_disable_link_state_locked);
786 * pci_disable_link_state - Disable device's link state, so the link will
787 * never enter specific states. Note that if the BIOS didn't grant ASPM
788 * control to the OS, this does nothing because we can't touch the LNKCTL
792 * @state: ASPM link state to disable
794 void pci_disable_link_state(struct pci_dev *pdev, int state)
796 __pci_disable_link_state(pdev, state, true);
798 EXPORT_SYMBOL(pci_disable_link_state);
800 static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
803 struct pcie_link_state *link;
807 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
808 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
810 if (i >= ARRAY_SIZE(policy_str))
812 if (i == aspm_policy)
815 down_read(&pci_bus_sem);
816 mutex_lock(&aspm_lock);
818 list_for_each_entry(link, &link_list, sibling) {
819 pcie_config_aspm_link(link, policy_to_aspm_state(link));
820 pcie_set_clkpm(link, policy_to_clkpm_state(link));
822 mutex_unlock(&aspm_lock);
823 up_read(&pci_bus_sem);
827 static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
830 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
831 if (i == aspm_policy)
832 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
834 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
835 cnt += sprintf(buffer + cnt, "\n");
839 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
842 #ifdef CONFIG_PCIEASPM_DEBUG
843 static ssize_t link_state_show(struct device *dev,
844 struct device_attribute *attr,
847 struct pci_dev *pci_device = to_pci_dev(dev);
848 struct pcie_link_state *link_state = pci_device->link_state;
850 return sprintf(buf, "%d\n", link_state->aspm_enabled);
853 static ssize_t link_state_store(struct device *dev,
854 struct device_attribute *attr,
858 struct pci_dev *pdev = to_pci_dev(dev);
859 struct pcie_link_state *link, *root = pdev->link_state->root;
865 if (kstrtouint(buf, 10, &state))
867 if ((state & ~ASPM_STATE_ALL) != 0)
870 down_read(&pci_bus_sem);
871 mutex_lock(&aspm_lock);
872 list_for_each_entry(link, &link_list, sibling) {
873 if (link->root != root)
875 pcie_config_aspm_link(link, state);
877 mutex_unlock(&aspm_lock);
878 up_read(&pci_bus_sem);
882 static ssize_t clk_ctl_show(struct device *dev,
883 struct device_attribute *attr,
886 struct pci_dev *pci_device = to_pci_dev(dev);
887 struct pcie_link_state *link_state = pci_device->link_state;
889 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
892 static ssize_t clk_ctl_store(struct device *dev,
893 struct device_attribute *attr,
897 struct pci_dev *pdev = to_pci_dev(dev);
900 if (strtobool(buf, &state))
903 down_read(&pci_bus_sem);
904 mutex_lock(&aspm_lock);
905 pcie_set_clkpm_nocheck(pdev->link_state, state);
906 mutex_unlock(&aspm_lock);
907 up_read(&pci_bus_sem);
912 static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
913 static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
915 static char power_group[] = "power";
916 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
918 struct pcie_link_state *link_state = pdev->link_state;
923 if (link_state->aspm_support)
924 sysfs_add_file_to_group(&pdev->dev.kobj,
925 &dev_attr_link_state.attr, power_group);
926 if (link_state->clkpm_capable)
927 sysfs_add_file_to_group(&pdev->dev.kobj,
928 &dev_attr_clk_ctl.attr, power_group);
931 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
933 struct pcie_link_state *link_state = pdev->link_state;
938 if (link_state->aspm_support)
939 sysfs_remove_file_from_group(&pdev->dev.kobj,
940 &dev_attr_link_state.attr, power_group);
941 if (link_state->clkpm_capable)
942 sysfs_remove_file_from_group(&pdev->dev.kobj,
943 &dev_attr_clk_ctl.attr, power_group);
947 static int __init pcie_aspm_disable(char *str)
949 if (!strcmp(str, "off")) {
950 aspm_policy = POLICY_DEFAULT;
952 aspm_support_enabled = false;
953 printk(KERN_INFO "PCIe ASPM is disabled\n");
954 } else if (!strcmp(str, "force")) {
956 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
961 __setup("pcie_aspm=", pcie_aspm_disable);
963 void pcie_no_aspm(void)
966 * Disabling ASPM is intended to prevent the kernel from modifying
967 * existing hardware state, not to clear existing state. To that end:
968 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
969 * (b) prevent userspace from changing policy
972 aspm_policy = POLICY_DEFAULT;
977 bool pcie_aspm_support_enabled(void)
979 return aspm_support_enabled;
981 EXPORT_SYMBOL(pcie_aspm_support_enabled);