1 // SPDX-License-Identifier: GPL-2.0
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
15 #define pr_fmt(fmt) "AER: " fmt
16 #define dev_fmt pr_fmt
18 #include <linux/bitops.h>
19 #include <linux/cper.h>
20 #include <linux/pci.h>
21 #include <linux/pci-acpi.h>
22 #include <linux/sched.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/kfifo.h>
30 #include <linux/slab.h>
31 #include <acpi/apei.h>
32 #include <ras/ras_event.h>
37 #define AER_ERROR_SOURCES_MAX 128
39 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
40 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
42 struct aer_err_source {
48 struct pci_dev *rpd; /* Root Port device */
49 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
52 /* AER stats for the device */
56 * Fields for all AER capable devices. They indicate the errors
57 * "as seen by this device". Note that this may mean that if an
58 * end point is causing problems, the AER counters may increment
59 * at its link partner (e.g. root port) because the errors will be
60 * "seen" by the link partner and not the the problematic end point
61 * itself (which may report all counters as 0 as it never saw any
64 /* Counters for different type of correctable errors */
65 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
66 /* Counters for different type of fatal uncorrectable errors */
67 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
68 /* Counters for different type of nonfatal uncorrectable errors */
69 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
70 /* Total number of ERR_COR sent by this device */
71 u64 dev_total_cor_errs;
72 /* Total number of ERR_FATAL sent by this device */
73 u64 dev_total_fatal_errs;
74 /* Total number of ERR_NONFATAL sent by this device */
75 u64 dev_total_nonfatal_errs;
78 * Fields for Root ports & root complex event collectors only, these
79 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
80 * messages received by the root port / event collector, INCLUDING the
81 * ones that are generated internally (by the rootport itself)
83 u64 rootport_total_cor_errs;
84 u64 rootport_total_fatal_errs;
85 u64 rootport_total_nonfatal_errs;
88 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
91 PCI_ERR_UNC_COMP_ABORT| \
92 PCI_ERR_UNC_UNX_COMP| \
95 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
96 PCI_EXP_RTCTL_SENFEE| \
98 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
99 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
100 PCI_ERR_ROOT_CMD_FATAL_EN)
101 #define ERR_COR_ID(d) (d & 0xffff)
102 #define ERR_UNCOR_ID(d) (d >> 16)
104 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \
105 PCI_ERR_ROOT_COR_RCV | \
106 PCI_ERR_ROOT_MULTI_COR_RCV | \
107 PCI_ERR_ROOT_MULTI_UNCOR_RCV)
109 static int pcie_aer_disable;
110 static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
112 void pci_no_aer(void)
114 pcie_aer_disable = 1;
117 bool pci_aer_available(void)
119 return !pcie_aer_disable && pci_msi_enabled();
122 #ifdef CONFIG_PCIE_ECRC
124 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
125 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
126 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
128 static int ecrc_policy = ECRC_POLICY_DEFAULT;
130 static const char * const ecrc_policy_str[] = {
131 [ECRC_POLICY_DEFAULT] = "bios",
132 [ECRC_POLICY_OFF] = "off",
133 [ECRC_POLICY_ON] = "on"
137 * enable_ercr_checking - enable PCIe ECRC checking for a device
138 * @dev: the PCI device
140 * Returns 0 on success, or negative on failure.
142 static int enable_ecrc_checking(struct pci_dev *dev)
144 int aer = dev->aer_cap;
150 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
151 if (reg32 & PCI_ERR_CAP_ECRC_GENC)
152 reg32 |= PCI_ERR_CAP_ECRC_GENE;
153 if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
154 reg32 |= PCI_ERR_CAP_ECRC_CHKE;
155 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
161 * disable_ercr_checking - disables PCIe ECRC checking for a device
162 * @dev: the PCI device
164 * Returns 0 on success, or negative on failure.
166 static int disable_ecrc_checking(struct pci_dev *dev)
168 int aer = dev->aer_cap;
174 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
175 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
176 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
182 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
183 * @dev: the PCI device
185 void pcie_set_ecrc_checking(struct pci_dev *dev)
187 switch (ecrc_policy) {
188 case ECRC_POLICY_DEFAULT:
190 case ECRC_POLICY_OFF:
191 disable_ecrc_checking(dev);
194 enable_ecrc_checking(dev);
202 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
203 * @str: ECRC policy from kernel command line to use
205 void pcie_ecrc_get_policy(char *str)
209 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
215 #endif /* CONFIG_PCIE_ECRC */
217 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
218 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
220 int pcie_aer_is_native(struct pci_dev *dev)
222 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
227 return pcie_ports_native || host->native_aer;
230 int pci_enable_pcie_error_reporting(struct pci_dev *dev)
234 if (!pcie_aer_is_native(dev))
237 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
238 return pcibios_err_to_errno(rc);
240 EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
242 int pci_disable_pcie_error_reporting(struct pci_dev *dev)
246 if (!pcie_aer_is_native(dev))
249 rc = pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
250 return pcibios_err_to_errno(rc);
252 EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
254 int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
256 int aer = dev->aer_cap;
259 if (!pcie_aer_is_native(dev))
262 /* Clear status bits for ERR_NONFATAL errors only */
263 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
264 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
267 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
271 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
273 void pci_aer_clear_fatal_status(struct pci_dev *dev)
275 int aer = dev->aer_cap;
278 if (!pcie_aer_is_native(dev))
281 /* Clear status bits for ERR_FATAL errors only */
282 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
283 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
286 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
290 * pci_aer_raw_clear_status - Clear AER error registers.
291 * @dev: the PCI device
293 * Clearing AER error status registers unconditionally, regardless of
294 * whether they're owned by firmware or the OS.
296 * Returns 0 on success, or negative on failure.
298 int pci_aer_raw_clear_status(struct pci_dev *dev)
300 int aer = dev->aer_cap;
307 port_type = pci_pcie_type(dev);
308 if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
309 port_type == PCI_EXP_TYPE_RC_EC) {
310 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
311 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
314 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
315 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
317 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
318 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
323 int pci_aer_clear_status(struct pci_dev *dev)
325 if (!pcie_aer_is_native(dev))
328 return pci_aer_raw_clear_status(dev);
331 void pci_save_aer_state(struct pci_dev *dev)
333 int aer = dev->aer_cap;
334 struct pci_cap_saved_state *save_state;
340 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
344 cap = &save_state->cap.data[0];
345 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
346 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
347 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
348 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
349 if (pcie_cap_has_rtctl(dev))
350 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
353 void pci_restore_aer_state(struct pci_dev *dev)
355 int aer = dev->aer_cap;
356 struct pci_cap_saved_state *save_state;
362 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
366 cap = &save_state->cap.data[0];
367 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
368 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
369 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
370 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
371 if (pcie_cap_has_rtctl(dev))
372 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
375 void pci_aer_init(struct pci_dev *dev)
379 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
383 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
386 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
387 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
388 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
391 n = pcie_cap_has_rtctl(dev) ? 5 : 4;
392 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
394 pci_aer_clear_status(dev);
397 void pci_aer_exit(struct pci_dev *dev)
399 kfree(dev->aer_stats);
400 dev->aer_stats = NULL;
403 #define AER_AGENT_RECEIVER 0
404 #define AER_AGENT_REQUESTER 1
405 #define AER_AGENT_COMPLETER 2
406 #define AER_AGENT_TRANSMITTER 3
408 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
409 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
410 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
411 0 : PCI_ERR_UNC_COMP_ABORT)
412 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
413 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
415 #define AER_GET_AGENT(t, e) \
416 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
417 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
418 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
421 #define AER_PHYSICAL_LAYER_ERROR 0
422 #define AER_DATA_LINK_LAYER_ERROR 1
423 #define AER_TRANSACTION_LAYER_ERROR 2
425 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
426 PCI_ERR_COR_RCVR : 0)
427 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
428 (PCI_ERR_COR_BAD_TLP| \
429 PCI_ERR_COR_BAD_DLLP| \
430 PCI_ERR_COR_REP_ROLL| \
431 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
433 #define AER_GET_LAYER_ERROR(t, e) \
434 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
435 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
436 AER_TRANSACTION_LAYER_ERROR)
441 static const char *aer_error_severity_string[] = {
442 "Uncorrected (Non-Fatal)",
443 "Uncorrected (Fatal)",
447 static const char *aer_error_layer[] = {
453 static const char *aer_correctable_error_string[] = {
454 "RxErr", /* Bit Position 0 */
460 "BadTLP", /* Bit Position 6 */
461 "BadDLLP", /* Bit Position 7 */
462 "Rollover", /* Bit Position 8 */
466 "Timeout", /* Bit Position 12 */
467 "NonFatalErr", /* Bit Position 13 */
468 "CorrIntErr", /* Bit Position 14 */
469 "HeaderOF", /* Bit Position 15 */
470 NULL, /* Bit Position 16 */
471 NULL, /* Bit Position 17 */
472 NULL, /* Bit Position 18 */
473 NULL, /* Bit Position 19 */
474 NULL, /* Bit Position 20 */
475 NULL, /* Bit Position 21 */
476 NULL, /* Bit Position 22 */
477 NULL, /* Bit Position 23 */
478 NULL, /* Bit Position 24 */
479 NULL, /* Bit Position 25 */
480 NULL, /* Bit Position 26 */
481 NULL, /* Bit Position 27 */
482 NULL, /* Bit Position 28 */
483 NULL, /* Bit Position 29 */
484 NULL, /* Bit Position 30 */
485 NULL, /* Bit Position 31 */
488 static const char *aer_uncorrectable_error_string[] = {
489 "Undefined", /* Bit Position 0 */
493 "DLP", /* Bit Position 4 */
494 "SDES", /* Bit Position 5 */
501 "TLP", /* Bit Position 12 */
502 "FCP", /* Bit Position 13 */
503 "CmpltTO", /* Bit Position 14 */
504 "CmpltAbrt", /* Bit Position 15 */
505 "UnxCmplt", /* Bit Position 16 */
506 "RxOF", /* Bit Position 17 */
507 "MalfTLP", /* Bit Position 18 */
508 "ECRC", /* Bit Position 19 */
509 "UnsupReq", /* Bit Position 20 */
510 "ACSViol", /* Bit Position 21 */
511 "UncorrIntErr", /* Bit Position 22 */
512 "BlockedTLP", /* Bit Position 23 */
513 "AtomicOpBlocked", /* Bit Position 24 */
514 "TLPBlockedErr", /* Bit Position 25 */
515 "PoisonTLPBlocked", /* Bit Position 26 */
516 NULL, /* Bit Position 27 */
517 NULL, /* Bit Position 28 */
518 NULL, /* Bit Position 29 */
519 NULL, /* Bit Position 30 */
520 NULL, /* Bit Position 31 */
523 static const char *aer_agent_string[] = {
530 #define aer_stats_dev_attr(name, stats_array, strings_array, \
531 total_string, total_field) \
533 name##_show(struct device *dev, struct device_attribute *attr, \
538 struct pci_dev *pdev = to_pci_dev(dev); \
539 u64 *stats = pdev->aer_stats->stats_array; \
541 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\
542 if (strings_array[i]) \
543 str += sprintf(str, "%s %llu\n", \
544 strings_array[i], stats[i]); \
546 str += sprintf(str, #stats_array "_bit[%d] %llu\n",\
549 str += sprintf(str, "TOTAL_%s %llu\n", total_string, \
550 pdev->aer_stats->total_field); \
553 static DEVICE_ATTR_RO(name)
555 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
556 aer_correctable_error_string, "ERR_COR",
558 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
559 aer_uncorrectable_error_string, "ERR_FATAL",
560 dev_total_fatal_errs);
561 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
562 aer_uncorrectable_error_string, "ERR_NONFATAL",
563 dev_total_nonfatal_errs);
565 #define aer_stats_rootport_attr(name, field) \
567 name##_show(struct device *dev, struct device_attribute *attr, \
570 struct pci_dev *pdev = to_pci_dev(dev); \
571 return sprintf(buf, "%llu\n", pdev->aer_stats->field); \
573 static DEVICE_ATTR_RO(name)
575 aer_stats_rootport_attr(aer_rootport_total_err_cor,
576 rootport_total_cor_errs);
577 aer_stats_rootport_attr(aer_rootport_total_err_fatal,
578 rootport_total_fatal_errs);
579 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
580 rootport_total_nonfatal_errs);
582 static struct attribute *aer_stats_attrs[] __ro_after_init = {
583 &dev_attr_aer_dev_correctable.attr,
584 &dev_attr_aer_dev_fatal.attr,
585 &dev_attr_aer_dev_nonfatal.attr,
586 &dev_attr_aer_rootport_total_err_cor.attr,
587 &dev_attr_aer_rootport_total_err_fatal.attr,
588 &dev_attr_aer_rootport_total_err_nonfatal.attr,
592 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
593 struct attribute *a, int n)
595 struct device *dev = kobj_to_dev(kobj);
596 struct pci_dev *pdev = to_pci_dev(dev);
598 if (!pdev->aer_stats)
601 if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
602 a == &dev_attr_aer_rootport_total_err_fatal.attr ||
603 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
604 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
605 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC)))
611 const struct attribute_group aer_stats_attr_group = {
612 .attrs = aer_stats_attrs,
613 .is_visible = aer_stats_attrs_are_visible,
616 static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
617 struct aer_err_info *info)
619 unsigned long status = info->status & ~info->mask;
622 struct aer_stats *aer_stats = pdev->aer_stats;
627 switch (info->severity) {
628 case AER_CORRECTABLE:
629 aer_stats->dev_total_cor_errs++;
630 counter = &aer_stats->dev_cor_errs[0];
631 max = AER_MAX_TYPEOF_COR_ERRS;
634 aer_stats->dev_total_nonfatal_errs++;
635 counter = &aer_stats->dev_nonfatal_errs[0];
636 max = AER_MAX_TYPEOF_UNCOR_ERRS;
639 aer_stats->dev_total_fatal_errs++;
640 counter = &aer_stats->dev_fatal_errs[0];
641 max = AER_MAX_TYPEOF_UNCOR_ERRS;
645 for_each_set_bit(i, &status, max)
649 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
650 struct aer_err_source *e_src)
652 struct aer_stats *aer_stats = pdev->aer_stats;
657 if (e_src->status & PCI_ERR_ROOT_COR_RCV)
658 aer_stats->rootport_total_cor_errs++;
660 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
661 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
662 aer_stats->rootport_total_fatal_errs++;
664 aer_stats->rootport_total_nonfatal_errs++;
668 static void __print_tlp_header(struct pci_dev *dev,
669 struct aer_header_log_regs *t)
671 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
672 t->dw0, t->dw1, t->dw2, t->dw3);
675 static void __aer_print_error(struct pci_dev *dev,
676 struct aer_err_info *info)
678 const char **strings;
679 unsigned long status = info->status & ~info->mask;
680 const char *level, *errmsg;
683 if (info->severity == AER_CORRECTABLE) {
684 strings = aer_correctable_error_string;
685 level = KERN_WARNING;
687 strings = aer_uncorrectable_error_string;
691 for_each_set_bit(i, &status, 32) {
694 errmsg = "Unknown Error Bit";
696 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
697 info->first_error == i ? " (First)" : "");
699 pci_dev_aer_stats_incr(dev, info);
702 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
705 int id = ((dev->bus->number << 8) | dev->devfn);
709 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
710 aer_error_severity_string[info->severity]);
714 layer = AER_GET_LAYER_ERROR(info->severity, info->status);
715 agent = AER_GET_AGENT(info->severity, info->status);
717 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
719 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
720 aer_error_severity_string[info->severity],
721 aer_error_layer[layer], aer_agent_string[agent]);
723 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
724 dev->vendor, dev->device, info->status, info->mask);
726 __aer_print_error(dev, info);
728 if (info->tlp_header_valid)
729 __print_tlp_header(dev, &info->tlp);
732 if (info->id && info->error_dev_num > 1 && info->id == id)
733 pci_err(dev, " Error of this Agent is reported first\n");
735 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
736 info->severity, info->tlp_header_valid, &info->tlp);
739 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
741 u8 bus = info->id >> 8;
742 u8 devfn = info->id & 0xff;
744 pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n",
745 info->multi_error_valid ? "Multiple " : "",
746 aer_error_severity_string[info->severity],
747 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
751 #ifdef CONFIG_ACPI_APEI_PCIEAER
752 int cper_severity_to_aer(int cper_severity)
754 switch (cper_severity) {
755 case CPER_SEV_RECOVERABLE:
760 return AER_CORRECTABLE;
763 EXPORT_SYMBOL_GPL(cper_severity_to_aer);
765 void cper_print_aer(struct pci_dev *dev, int aer_severity,
766 struct aer_capability_regs *aer)
768 int layer, agent, tlp_header_valid = 0;
770 struct aer_err_info info;
772 if (aer_severity == AER_CORRECTABLE) {
773 status = aer->cor_status;
774 mask = aer->cor_mask;
776 status = aer->uncor_status;
777 mask = aer->uncor_mask;
778 tlp_header_valid = status & AER_LOG_TLP_MASKS;
781 layer = AER_GET_LAYER_ERROR(aer_severity, status);
782 agent = AER_GET_AGENT(aer_severity, status);
784 memset(&info, 0, sizeof(info));
785 info.severity = aer_severity;
786 info.status = status;
788 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
790 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
791 __aer_print_error(dev, &info);
792 pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
793 aer_error_layer[layer], aer_agent_string[agent]);
795 if (aer_severity != AER_CORRECTABLE)
796 pci_err(dev, "aer_uncor_severity: 0x%08x\n",
797 aer->uncor_severity);
799 if (tlp_header_valid)
800 __print_tlp_header(dev, &aer->header_log);
802 trace_aer_event(dev_name(&dev->dev), (status & ~mask),
803 aer_severity, tlp_header_valid, &aer->header_log);
808 * add_error_device - list device to be handled
809 * @e_info: pointer to error info
810 * @dev: pointer to pci_dev to be added
812 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
814 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
815 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev);
816 e_info->error_dev_num++;
823 * is_error_source - check whether the device is source of reported error
824 * @dev: pointer to pci_dev to be checked
825 * @e_info: pointer to reported error info
827 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
829 int aer = dev->aer_cap;
834 * When bus id is equal to 0, it might be a bad id
835 * reported by root port.
837 if ((PCI_BUS_NUM(e_info->id) != 0) &&
838 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
839 /* Device ID match? */
840 if (e_info->id == ((dev->bus->number << 8) | dev->devfn))
843 /* Continue id comparing if there is no multiple error */
844 if (!e_info->multi_error_valid)
850 * 1) bus id is equal to 0. Some ports might lose the bus
851 * id of error source id;
852 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
853 * 3) There are multiple errors and prior ID comparing fails;
854 * We check AER status registers to find possible reporter.
856 if (atomic_read(&dev->enable_cnt) == 0)
859 /* Check if AER is enabled */
860 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
861 if (!(reg16 & PCI_EXP_AER_FLAGS))
867 /* Check if error is recorded */
868 if (e_info->severity == AER_CORRECTABLE) {
869 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
870 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
872 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
873 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
881 static int find_device_iter(struct pci_dev *dev, void *data)
883 struct aer_err_info *e_info = (struct aer_err_info *)data;
885 if (is_error_source(dev, e_info)) {
886 /* List this device */
887 if (add_error_device(e_info, dev)) {
888 /* We cannot handle more... Stop iteration */
889 /* TODO: Should print error message here? */
893 /* If there is only a single error, stop iteration */
894 if (!e_info->multi_error_valid)
901 * find_source_device - search through device hierarchy for source device
902 * @parent: pointer to Root Port pci_dev data structure
903 * @e_info: including detailed error information such like id
905 * Return true if found.
907 * Invoked by DPC when error is detected at the Root Port.
908 * Caller of this function must set id, severity, and multi_error_valid of
909 * struct aer_err_info pointed by @e_info properly. This function must fill
910 * e_info->error_dev_num and e_info->dev[], based on the given information.
912 static bool find_source_device(struct pci_dev *parent,
913 struct aer_err_info *e_info)
915 struct pci_dev *dev = parent;
918 /* Must reset in this function */
919 e_info->error_dev_num = 0;
921 /* Is Root Port an agent that sends error message? */
922 result = find_device_iter(dev, e_info);
926 pci_walk_bus(parent->subordinate, find_device_iter, e_info);
928 if (!e_info->error_dev_num) {
929 pci_info(parent, "can't find device of ID%04x\n", e_info->id);
936 * handle_error_source - handle logging error into an event log
937 * @dev: pointer to pci_dev data structure of error source device
938 * @info: comprehensive error information
940 * Invoked when an error being detected by Root Port.
942 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
944 int aer = dev->aer_cap;
946 if (info->severity == AER_CORRECTABLE) {
948 * Correctable error does not need software intervention.
949 * No need to go through error recovery process.
952 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
954 if (pcie_aer_is_native(dev))
955 pcie_clear_device_status(dev);
956 } else if (info->severity == AER_NONFATAL)
957 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
958 else if (info->severity == AER_FATAL)
959 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
963 #ifdef CONFIG_ACPI_APEI_PCIEAER
965 #define AER_RECOVER_RING_ORDER 4
966 #define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
968 struct aer_recover_entry {
973 struct aer_capability_regs *regs;
976 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
977 AER_RECOVER_RING_SIZE);
979 static void aer_recover_work_func(struct work_struct *work)
981 struct aer_recover_entry entry;
982 struct pci_dev *pdev;
984 while (kfifo_get(&aer_recover_ring, &entry)) {
985 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
988 pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
989 entry.domain, entry.bus,
990 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
993 cper_print_aer(pdev, entry.severity, entry.regs);
994 if (entry.severity == AER_NONFATAL)
995 pcie_do_recovery(pdev, pci_channel_io_normal,
997 else if (entry.severity == AER_FATAL)
998 pcie_do_recovery(pdev, pci_channel_io_frozen,
1005 * Mutual exclusion for writers of aer_recover_ring, reader side don't
1006 * need lock, because there is only one reader and lock is not needed
1007 * between reader and writer.
1009 static DEFINE_SPINLOCK(aer_recover_ring_lock);
1010 static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
1012 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
1013 int severity, struct aer_capability_regs *aer_regs)
1015 struct aer_recover_entry entry = {
1019 .severity = severity,
1023 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
1024 &aer_recover_ring_lock))
1025 schedule_work(&aer_recover_work);
1027 pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
1028 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1030 EXPORT_SYMBOL_GPL(aer_recover_queue);
1034 * aer_get_device_error_info - read error status from dev and store it to info
1035 * @dev: pointer to the device expected to have a error record
1036 * @info: pointer to structure to store the error record
1038 * Return 1 on success, 0 on error.
1040 * Note that @info is reused among all error devices. Clear fields properly.
1042 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
1044 int type = pci_pcie_type(dev);
1045 int aer = dev->aer_cap;
1048 /* Must reset in this function */
1050 info->tlp_header_valid = 0;
1052 /* The device might not support AER */
1056 if (info->severity == AER_CORRECTABLE) {
1057 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1059 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
1061 if (!(info->status & ~info->mask))
1063 } else if (type == PCI_EXP_TYPE_ROOT_PORT ||
1064 type == PCI_EXP_TYPE_DOWNSTREAM ||
1065 info->severity == AER_NONFATAL) {
1067 /* Link is still healthy for IO reads */
1068 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
1070 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
1072 if (!(info->status & ~info->mask))
1075 /* Get First Error Pointer */
1076 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
1077 info->first_error = PCI_ERR_CAP_FEP(temp);
1079 if (info->status & AER_LOG_TLP_MASKS) {
1080 info->tlp_header_valid = 1;
1081 pci_read_config_dword(dev,
1082 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
1083 pci_read_config_dword(dev,
1084 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
1085 pci_read_config_dword(dev,
1086 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
1087 pci_read_config_dword(dev,
1088 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
1095 static inline void aer_process_err_devices(struct aer_err_info *e_info)
1099 /* Report all before handle them, not to lost records by reset etc. */
1100 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1101 if (aer_get_device_error_info(e_info->dev[i], e_info))
1102 aer_print_error(e_info->dev[i], e_info);
1104 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1105 if (aer_get_device_error_info(e_info->dev[i], e_info))
1106 handle_error_source(e_info->dev[i], e_info);
1111 * aer_isr_one_error - consume an error detected by root port
1112 * @rpc: pointer to the root port which holds an error
1113 * @e_src: pointer to an error source
1115 static void aer_isr_one_error(struct aer_rpc *rpc,
1116 struct aer_err_source *e_src)
1118 struct pci_dev *pdev = rpc->rpd;
1119 struct aer_err_info e_info;
1121 pci_rootport_aer_stats_incr(pdev, e_src);
1124 * There is a possibility that both correctable error and
1125 * uncorrectable error being logged. Report correctable error first.
1127 if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
1128 e_info.id = ERR_COR_ID(e_src->id);
1129 e_info.severity = AER_CORRECTABLE;
1131 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
1132 e_info.multi_error_valid = 1;
1134 e_info.multi_error_valid = 0;
1135 aer_print_port_info(pdev, &e_info);
1137 if (find_source_device(pdev, &e_info))
1138 aer_process_err_devices(&e_info);
1141 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
1142 e_info.id = ERR_UNCOR_ID(e_src->id);
1144 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
1145 e_info.severity = AER_FATAL;
1147 e_info.severity = AER_NONFATAL;
1149 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
1150 e_info.multi_error_valid = 1;
1152 e_info.multi_error_valid = 0;
1154 aer_print_port_info(pdev, &e_info);
1156 if (find_source_device(pdev, &e_info))
1157 aer_process_err_devices(&e_info);
1162 * aer_isr - consume errors detected by root port
1163 * @irq: IRQ assigned to Root Port
1164 * @context: pointer to Root Port data structure
1166 * Invoked, as DPC, when root port records new detected error
1168 static irqreturn_t aer_isr(int irq, void *context)
1170 struct pcie_device *dev = (struct pcie_device *)context;
1171 struct aer_rpc *rpc = get_service_data(dev);
1172 struct aer_err_source e_src;
1174 if (kfifo_is_empty(&rpc->aer_fifo))
1177 while (kfifo_get(&rpc->aer_fifo, &e_src))
1178 aer_isr_one_error(rpc, &e_src);
1183 * aer_irq - Root Port's ISR
1184 * @irq: IRQ assigned to Root Port
1185 * @context: pointer to Root Port data structure
1187 * Invoked when Root Port detects AER messages.
1189 static irqreturn_t aer_irq(int irq, void *context)
1191 struct pcie_device *pdev = (struct pcie_device *)context;
1192 struct aer_rpc *rpc = get_service_data(pdev);
1193 struct pci_dev *rp = rpc->rpd;
1194 int aer = rp->aer_cap;
1195 struct aer_err_source e_src = {};
1197 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
1198 if (!(e_src.status & AER_ERR_STATUS_MASK))
1201 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
1202 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
1204 if (!kfifo_put(&rpc->aer_fifo, e_src))
1207 return IRQ_WAKE_THREAD;
1210 static int set_device_error_reporting(struct pci_dev *dev, void *data)
1212 bool enable = *((bool *)data);
1213 int type = pci_pcie_type(dev);
1215 if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
1216 (type == PCI_EXP_TYPE_RC_EC) ||
1217 (type == PCI_EXP_TYPE_UPSTREAM) ||
1218 (type == PCI_EXP_TYPE_DOWNSTREAM)) {
1220 pci_enable_pcie_error_reporting(dev);
1222 pci_disable_pcie_error_reporting(dev);
1226 pcie_set_ecrc_checking(dev);
1232 * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
1233 * @dev: pointer to root port's pci_dev data structure
1234 * @enable: true = enable error reporting, false = disable error reporting.
1236 static void set_downstream_devices_error_reporting(struct pci_dev *dev,
1239 set_device_error_reporting(dev, &enable);
1241 if (!dev->subordinate)
1243 pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable);
1247 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1248 * @rpc: pointer to a Root Port data structure
1250 * Invoked when PCIe bus loads AER service driver.
1252 static void aer_enable_rootport(struct aer_rpc *rpc)
1254 struct pci_dev *pdev = rpc->rpd;
1255 int aer = pdev->aer_cap;
1259 /* Clear PCIe Capability's Device Status */
1260 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16);
1261 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
1263 /* Disable system error generation in response to error messages */
1264 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
1265 SYSTEM_ERROR_INTR_ON_MESG_MASK);
1267 /* Clear error status */
1268 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1269 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1270 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32);
1271 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
1272 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32);
1273 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
1276 * Enable error reporting for the root port device and downstream port
1279 set_downstream_devices_error_reporting(pdev, true);
1281 /* Enable Root Port's interrupt in response to error messages */
1282 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1283 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1284 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1288 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1289 * @rpc: pointer to a Root Port data structure
1291 * Invoked when PCIe bus unloads AER service driver.
1293 static void aer_disable_rootport(struct aer_rpc *rpc)
1295 struct pci_dev *pdev = rpc->rpd;
1296 int aer = pdev->aer_cap;
1300 * Disable error reporting for the root port device and downstream port
1303 set_downstream_devices_error_reporting(pdev, false);
1305 /* Disable Root's interrupt in response to error messages */
1306 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1307 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1308 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1310 /* Clear Root's error status reg */
1311 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1312 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1316 * aer_remove - clean up resources
1317 * @dev: pointer to the pcie_dev data structure
1319 * Invoked when PCI Express bus unloads or AER probe fails.
1321 static void aer_remove(struct pcie_device *dev)
1323 struct aer_rpc *rpc = get_service_data(dev);
1325 aer_disable_rootport(rpc);
1329 * aer_probe - initialize resources
1330 * @dev: pointer to the pcie_dev data structure
1332 * Invoked when PCI Express bus loads AER service driver.
1334 static int aer_probe(struct pcie_device *dev)
1337 struct aer_rpc *rpc;
1338 struct device *device = &dev->device;
1339 struct pci_dev *port = dev->port;
1341 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) <
1342 AER_MAX_TYPEOF_COR_ERRS);
1343 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) <
1344 AER_MAX_TYPEOF_UNCOR_ERRS);
1346 /* Limit to Root Ports or Root Complex Event Collectors */
1347 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) &&
1348 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT))
1351 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
1356 INIT_KFIFO(rpc->aer_fifo);
1357 set_service_data(dev, rpc);
1359 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
1360 IRQF_SHARED, "aerdrv", dev);
1362 pci_err(port, "request AER IRQ %d failed\n", dev->irq);
1366 aer_enable_rootport(rpc);
1367 pci_info(port, "enabled with IRQ %d\n", dev->irq);
1372 * aer_root_reset - reset Root Port hierarchy or RCEC
1373 * @dev: pointer to Root Port or RCEC
1375 * Invoked by Port Bus driver when performing reset.
1377 static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
1379 int type = pci_pcie_type(dev);
1380 struct pci_dev *root;
1382 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
1386 root = dev; /* device with Root Error registers */
1387 aer = root->aer_cap;
1389 if ((host->native_aer || pcie_ports_native) && aer) {
1390 /* Disable Root's interrupt in response to error messages */
1391 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32);
1392 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1393 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);
1396 if (type == PCI_EXP_TYPE_RC_EC) {
1397 if (pcie_has_flr(dev)) {
1399 pci_info(dev, "has been reset (%d)\n", rc);
1401 pci_info(dev, "not reset (no FLR support)\n");
1405 rc = pci_bus_error_reset(dev);
1406 pci_info(dev, "Root Port link has been reset (%d)\n", rc);
1409 if ((host->native_aer || pcie_ports_native) && aer) {
1410 /* Clear Root Error Status */
1411 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32);
1412 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32);
1414 /* Enable Root Port's interrupt in response to error messages */
1415 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32);
1416 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1417 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);
1420 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1423 static struct pcie_port_service_driver aerdriver = {
1425 .port_type = PCIE_ANY_PORT,
1426 .service = PCIE_PORT_SERVICE_AER,
1429 .remove = aer_remove,
1433 * aer_service_init - register AER root service driver
1435 * Invoked when AER root service driver is loaded.
1437 int __init pcie_aer_init(void)
1439 if (!pci_aer_available())
1441 return pcie_port_service_register(&aerdriver);