1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
10 #define PCI_FIND_CAP_TTL 48
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14 extern const unsigned char pcie_link_speed[];
15 extern bool pci_early_dump;
17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
20 /* Functions internal to the PCI core code */
22 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
24 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
25 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
27 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
30 void pci_create_firmware_label_files(struct pci_dev *pdev);
31 void pci_remove_firmware_label_files(struct pci_dev *pdev);
33 void pci_cleanup_rom(struct pci_dev *dev);
36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
39 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
40 enum pci_mmap_api mmap_api);
42 int pci_probe_reset_function(struct pci_dev *dev);
43 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
44 int pci_bus_error_reset(struct pci_dev *dev);
46 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
47 #define PCI_PM_D3HOT_WAIT 10 /* msec */
48 #define PCI_PM_D3COLD_WAIT 100 /* msec */
51 * Following exit from Conventional Reset, devices must be ready within 1 sec
52 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
53 * Reset (PCIe r6.0 sec 5.8).
55 #define PCI_RESET_WAIT 1000 /* msec */
57 * Devices may extend the 1 sec period through Request Retry Status completions
58 * (PCIe r6.0 sec 2.3.1). The spec does not provide an upper limit, but 60 sec
59 * ought to be enough for any device to become responsive.
61 #define PCIE_RESET_READY_POLL_MS 60000 /* msec */
64 * struct pci_platform_pm_ops - Firmware PM callbacks
66 * @bridge_d3: Does the bridge allow entering into D3
68 * @is_manageable: returns 'true' if given device is power manageable by the
71 * @set_state: invokes the platform firmware to set the device's power state
73 * @get_state: queries the platform firmware for a device's current power state
75 * @refresh_state: asks the platform to refresh the device's power state data
77 * @choose_state: returns PCI power state of given device preferred by the
78 * platform; to be used during system-wide transitions from a
79 * sleeping state to the working state and vice versa
81 * @set_wakeup: enables/disables wakeup capability for the device
83 * @need_resume: returns 'true' if the given device (which is currently
84 * suspended) needs to be resumed to be configured for system
87 * If given platform is generally capable of power managing PCI devices, all of
88 * these callbacks are mandatory.
90 struct pci_platform_pm_ops {
91 bool (*bridge_d3)(struct pci_dev *dev);
92 bool (*is_manageable)(struct pci_dev *dev);
93 int (*set_state)(struct pci_dev *dev, pci_power_t state);
94 pci_power_t (*get_state)(struct pci_dev *dev);
95 void (*refresh_state)(struct pci_dev *dev);
96 pci_power_t (*choose_state)(struct pci_dev *dev);
97 int (*set_wakeup)(struct pci_dev *dev, bool enable);
98 bool (*need_resume)(struct pci_dev *dev);
101 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
102 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
103 void pci_refresh_power_state(struct pci_dev *dev);
104 int pci_power_up(struct pci_dev *dev);
105 void pci_disable_enabled_device(struct pci_dev *dev);
106 int pci_finish_runtime_suspend(struct pci_dev *dev);
107 void pcie_clear_device_status(struct pci_dev *dev);
108 void pcie_clear_root_pme_status(struct pci_dev *dev);
109 bool pci_check_pme_status(struct pci_dev *dev);
110 void pci_pme_wakeup_bus(struct pci_bus *bus);
111 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
112 void pci_pme_restore(struct pci_dev *dev);
113 bool pci_dev_need_resume(struct pci_dev *dev);
114 void pci_dev_adjust_pme(struct pci_dev *dev);
115 void pci_dev_complete_resume(struct pci_dev *pci_dev);
116 void pci_config_pm_runtime_get(struct pci_dev *dev);
117 void pci_config_pm_runtime_put(struct pci_dev *dev);
118 void pci_pm_init(struct pci_dev *dev);
119 void pci_ea_init(struct pci_dev *dev);
120 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
121 void pci_free_cap_save_buffers(struct pci_dev *dev);
122 bool pci_bridge_d3_possible(struct pci_dev *dev);
123 void pci_bridge_d3_update(struct pci_dev *dev);
124 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
127 static inline void pci_wakeup_event(struct pci_dev *dev)
129 /* Wait 100 ms before the system can be put into a sleep state. */
130 pm_wakeup_event(&dev->dev, 100);
133 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
135 return !!(pci_dev->subordinate);
138 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
141 * Currently we allow normal PCI devices and PCI bridges transition
142 * into D3 if their bridge_d3 is set.
144 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
147 static inline bool pcie_downstream_port(const struct pci_dev *dev)
149 int type = pci_pcie_type(dev);
151 return type == PCI_EXP_TYPE_ROOT_PORT ||
152 type == PCI_EXP_TYPE_DOWNSTREAM ||
153 type == PCI_EXP_TYPE_PCIE_BRIDGE;
156 int pci_vpd_init(struct pci_dev *dev);
157 void pci_vpd_release(struct pci_dev *dev);
158 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
159 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
161 /* PCI Virtual Channel */
162 int pci_save_vc_state(struct pci_dev *dev);
163 void pci_restore_vc_state(struct pci_dev *dev);
164 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
166 /* PCI /proc functions */
167 #ifdef CONFIG_PROC_FS
168 int pci_proc_attach_device(struct pci_dev *dev);
169 int pci_proc_detach_device(struct pci_dev *dev);
170 int pci_proc_detach_bus(struct pci_bus *bus);
172 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
173 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
174 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
177 /* Functions for PCI Hotplug drivers to use */
178 int pci_hp_add_bridge(struct pci_dev *dev);
180 #ifdef HAVE_PCI_LEGACY
181 void pci_create_legacy_files(struct pci_bus *bus);
182 void pci_remove_legacy_files(struct pci_bus *bus);
184 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
185 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
188 /* Lock for read/write access to pci device and bus lists */
189 extern struct rw_semaphore pci_bus_sem;
190 extern struct mutex pci_slot_mutex;
192 extern raw_spinlock_t pci_lock;
194 extern unsigned int pci_pm_d3hot_delay;
196 #ifdef CONFIG_PCI_MSI
197 void pci_no_msi(void);
199 static inline void pci_no_msi(void) { }
202 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
206 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
207 control &= ~PCI_MSI_FLAGS_ENABLE;
209 control |= PCI_MSI_FLAGS_ENABLE;
210 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
213 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
217 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
220 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
223 void pci_realloc_get_opt(char *);
225 static inline int pci_no_d1d2(struct pci_dev *dev)
227 unsigned int parent_dstates = 0;
230 parent_dstates = dev->bus->self->no_d1d2;
231 return (dev->no_d1d2 || parent_dstates);
234 extern const struct attribute_group *pci_dev_groups[];
235 extern const struct attribute_group *pcibus_groups[];
236 extern const struct device_type pci_dev_type;
237 extern const struct attribute_group *pci_bus_groups[];
239 extern unsigned long pci_hotplug_io_size;
240 extern unsigned long pci_hotplug_mmio_size;
241 extern unsigned long pci_hotplug_mmio_pref_size;
242 extern unsigned long pci_hotplug_bus_size;
245 * pci_match_one_device - Tell if a PCI device structure has a matching
246 * PCI device id structure
247 * @id: single PCI device id structure to match
248 * @dev: the PCI device structure to match against
250 * Returns the matching pci_device_id structure or %NULL if there is no match.
252 static inline const struct pci_device_id *
253 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
255 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
256 (id->device == PCI_ANY_ID || id->device == dev->device) &&
257 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
258 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
259 !((id->class ^ dev->class) & id->class_mask))
264 /* PCI slot sysfs helper code */
265 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
267 extern struct kset *pci_slots_kset;
269 struct pci_slot_attribute {
270 struct attribute attr;
271 ssize_t (*show)(struct pci_slot *, char *);
272 ssize_t (*store)(struct pci_slot *, const char *, size_t);
274 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
277 pci_bar_unknown, /* Standard PCI BAR probe */
278 pci_bar_io, /* An I/O port BAR */
279 pci_bar_mem32, /* A 32-bit memory BAR */
280 pci_bar_mem64, /* A 64-bit memory BAR */
283 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
284 void pci_put_host_bridge_device(struct device *dev);
286 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
287 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
289 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
291 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
293 int pci_setup_device(struct pci_dev *dev);
294 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
295 struct resource *res, unsigned int reg);
296 void pci_configure_ari(struct pci_dev *dev);
297 void __pci_bus_size_bridges(struct pci_bus *bus,
298 struct list_head *realloc_head);
299 void __pci_bus_assign_resources(const struct pci_bus *bus,
300 struct list_head *realloc_head,
301 struct list_head *fail_head);
302 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
304 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
305 void pci_disable_bridge_window(struct pci_dev *dev);
306 struct pci_bus *pci_bus_get(struct pci_bus *bus);
307 void pci_bus_put(struct pci_bus *bus);
309 /* PCIe link information from Link Capabilities 2 */
310 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
311 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
312 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
313 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
314 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
315 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
318 /* PCIe speed to Mb/s reduced by encoding overhead */
319 #define PCIE_SPEED2MBS_ENC(speed) \
320 ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
321 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
322 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
323 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
324 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
327 const char *pci_speed_string(enum pci_bus_speed speed);
328 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
329 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
330 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
331 enum pcie_link_width *width);
332 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
333 void pcie_report_downtraining(struct pci_dev *dev);
334 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
336 /* Single Root I/O Virtualization */
338 int pos; /* Capability position */
339 int nres; /* Number of resources */
340 u32 cap; /* SR-IOV Capabilities */
341 u16 ctrl; /* SR-IOV Control */
342 u16 total_VFs; /* Total VFs associated with the PF */
343 u16 initial_VFs; /* Initial VFs associated with the PF */
344 u16 num_VFs; /* Number of VFs available */
345 u16 offset; /* First VF Routing ID offset */
346 u16 stride; /* Following VF stride */
347 u16 vf_device; /* VF device ID */
348 u32 pgsz; /* Page size for BAR alignment */
349 u8 link; /* Function Dependency Link */
350 u8 max_VF_buses; /* Max buses consumed by VFs */
351 u16 driver_max_VFs; /* Max num VFs driver supports */
352 struct pci_dev *dev; /* Lowest numbered PF */
353 struct pci_dev *self; /* This PF */
354 u32 class; /* VF device */
355 u8 hdr_type; /* VF header type */
356 u16 subsystem_vendor; /* VF subsystem vendor */
357 u16 subsystem_device; /* VF subsystem device */
358 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
359 bool drivers_autoprobe; /* Auto probing of VFs by driver */
363 * pci_dev_set_io_state - Set the new error state if possible.
365 * @dev - pci device to set new error_state
366 * @new - the state we want dev to be in
368 * If the device is experiencing perm_failure, it has to remain in that state.
369 * Any other transition is allowed.
371 * Returns true if state has been changed to the requested state.
373 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
374 pci_channel_state_t new)
376 pci_channel_state_t old;
379 case pci_channel_io_perm_failure:
380 xchg(&dev->error_state, pci_channel_io_perm_failure);
382 case pci_channel_io_frozen:
383 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
384 pci_channel_io_frozen);
385 return old != pci_channel_io_perm_failure;
386 case pci_channel_io_normal:
387 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
388 pci_channel_io_normal);
389 return old != pci_channel_io_perm_failure;
395 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
397 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
402 /* pci_dev priv_flags */
403 #define PCI_DEV_ADDED 0
404 #define PCI_DPC_RECOVERED 1
405 #define PCI_DPC_RECOVERING 2
407 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
409 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
412 static inline bool pci_dev_is_added(const struct pci_dev *dev)
414 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
417 #ifdef CONFIG_PCIEAER
418 #include <linux/aer.h>
420 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
422 struct aer_err_info {
423 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
428 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
429 unsigned int __pad1:5;
430 unsigned int multi_error_valid:1;
432 unsigned int first_error:5;
433 unsigned int __pad2:2;
434 unsigned int tlp_header_valid:1;
436 unsigned int status; /* COR/UNCOR Error Status */
437 unsigned int mask; /* COR/UNCOR Error Mask */
438 struct aer_header_log_regs tlp; /* TLP Header */
441 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
442 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
443 #endif /* CONFIG_PCIEAER */
445 #ifdef CONFIG_PCIEPORTBUS
446 /* Cached RCEC Endpoint Association */
454 #ifdef CONFIG_PCIE_DPC
455 void pci_save_dpc_state(struct pci_dev *dev);
456 void pci_restore_dpc_state(struct pci_dev *dev);
457 void pci_dpc_init(struct pci_dev *pdev);
458 void dpc_process_error(struct pci_dev *pdev);
459 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
460 bool pci_dpc_recovered(struct pci_dev *pdev);
462 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
463 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
464 static inline void pci_dpc_init(struct pci_dev *pdev) {}
465 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
468 #ifdef CONFIG_PCIEPORTBUS
469 void pci_rcec_init(struct pci_dev *dev);
470 void pci_rcec_exit(struct pci_dev *dev);
472 static inline void pci_rcec_init(struct pci_dev *dev) {}
473 static inline void pci_rcec_exit(struct pci_dev *dev) {}
476 #ifdef CONFIG_PCI_ATS
477 /* Address Translation Service */
478 void pci_ats_init(struct pci_dev *dev);
479 void pci_restore_ats_state(struct pci_dev *dev);
481 static inline void pci_ats_init(struct pci_dev *d) { }
482 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
483 #endif /* CONFIG_PCI_ATS */
485 #ifdef CONFIG_PCI_PRI
486 void pci_pri_init(struct pci_dev *dev);
487 void pci_restore_pri_state(struct pci_dev *pdev);
489 static inline void pci_pri_init(struct pci_dev *dev) { }
490 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
493 #ifdef CONFIG_PCI_PASID
494 void pci_pasid_init(struct pci_dev *dev);
495 void pci_restore_pasid_state(struct pci_dev *pdev);
497 static inline void pci_pasid_init(struct pci_dev *dev) { }
498 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
501 #ifdef CONFIG_PCI_IOV
502 int pci_iov_init(struct pci_dev *dev);
503 void pci_iov_release(struct pci_dev *dev);
504 void pci_iov_remove(struct pci_dev *dev);
505 void pci_iov_update_resource(struct pci_dev *dev, int resno);
506 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
507 void pci_restore_iov_state(struct pci_dev *dev);
508 int pci_iov_bus_range(struct pci_bus *bus);
509 extern const struct attribute_group sriov_dev_attr_group;
511 static inline int pci_iov_init(struct pci_dev *dev)
515 static inline void pci_iov_release(struct pci_dev *dev)
519 static inline void pci_iov_remove(struct pci_dev *dev)
522 static inline void pci_restore_iov_state(struct pci_dev *dev)
525 static inline int pci_iov_bus_range(struct pci_bus *bus)
530 #endif /* CONFIG_PCI_IOV */
532 unsigned long pci_cardbus_resource_alignment(struct resource *);
534 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
535 struct resource *res)
537 #ifdef CONFIG_PCI_IOV
538 int resno = res - dev->resource;
540 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
541 return pci_sriov_resource_alignment(dev, resno);
543 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
544 return pci_cardbus_resource_alignment(res);
545 return resource_alignment(res);
548 void pci_acs_init(struct pci_dev *dev);
549 #ifdef CONFIG_PCI_QUIRKS
550 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
551 int pci_dev_specific_enable_acs(struct pci_dev *dev);
552 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
554 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
559 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
563 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
569 /* PCI error reporting and recovery */
570 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
571 pci_channel_state_t state,
572 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
574 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
575 #ifdef CONFIG_PCIEASPM
576 void pcie_aspm_init_link_state(struct pci_dev *pdev);
577 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
578 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
579 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
581 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
582 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
583 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
584 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
587 #ifdef CONFIG_PCIE_ECRC
588 void pcie_set_ecrc_checking(struct pci_dev *dev);
589 void pcie_ecrc_get_policy(char *str);
591 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
592 static inline void pcie_ecrc_get_policy(char *str) { }
595 #ifdef CONFIG_PCIE_PTM
596 void pci_ptm_init(struct pci_dev *dev);
598 static inline void pci_ptm_init(struct pci_dev *dev) { }
601 struct pci_dev_reset_methods {
604 int (*reset)(struct pci_dev *dev, int probe);
607 #ifdef CONFIG_PCI_QUIRKS
608 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
610 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
616 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
617 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
618 struct resource *res);
620 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
621 u16 segment, struct resource *res)
627 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
628 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
629 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
630 static inline u64 pci_rebar_size_to_bytes(int size)
632 return 1ULL << (size + 20);
638 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
639 int of_get_pci_domain_nr(struct device_node *node);
640 int of_pci_get_max_link_speed(struct device_node *node);
641 void pci_set_of_node(struct pci_dev *dev);
642 void pci_release_of_node(struct pci_dev *dev);
643 void pci_set_bus_of_node(struct pci_bus *bus);
644 void pci_release_bus_of_node(struct pci_bus *bus);
646 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
650 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
656 of_get_pci_domain_nr(struct device_node *node)
662 of_pci_get_max_link_speed(struct device_node *node)
667 static inline void pci_set_of_node(struct pci_dev *dev) { }
668 static inline void pci_release_of_node(struct pci_dev *dev) { }
669 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
670 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
672 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
677 #endif /* CONFIG_OF */
679 #ifdef CONFIG_PCIEAER
680 void pci_no_aer(void);
681 void pci_aer_init(struct pci_dev *dev);
682 void pci_aer_exit(struct pci_dev *dev);
683 extern const struct attribute_group aer_stats_attr_group;
684 void pci_aer_clear_fatal_status(struct pci_dev *dev);
685 int pci_aer_clear_status(struct pci_dev *dev);
686 int pci_aer_raw_clear_status(struct pci_dev *dev);
688 static inline void pci_no_aer(void) { }
689 static inline void pci_aer_init(struct pci_dev *d) { }
690 static inline void pci_aer_exit(struct pci_dev *d) { }
691 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
692 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
693 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
697 int pci_acpi_program_hp_params(struct pci_dev *dev);
699 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
705 #ifdef CONFIG_PCIEASPM
706 extern const struct attribute_group aspm_ctrl_attr_group;
709 #endif /* DRIVERS_PCI_H */