1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
10 #define PCI_FIND_CAP_TTL 48
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14 extern const unsigned char pcie_link_speed[];
15 extern bool pci_early_dump;
17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
20 /* Functions internal to the PCI core code */
22 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
24 void pci_cleanup_rom(struct pci_dev *dev);
26 extern const struct attribute_group pci_dev_smbios_attr_group;
30 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
31 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
33 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
34 enum pci_mmap_api mmap_api);
36 bool pci_reset_supported(struct pci_dev *dev);
37 void pci_init_reset_methods(struct pci_dev *dev);
38 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
39 int pci_bus_error_reset(struct pci_dev *dev);
41 struct pci_cap_saved_data {
48 struct pci_cap_saved_state {
49 struct hlist_node next;
50 struct pci_cap_saved_data cap;
53 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
54 void pci_free_cap_save_buffers(struct pci_dev *dev);
55 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
56 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
57 u16 cap, unsigned int size);
58 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
59 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
62 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
63 #define PCI_PM_D3HOT_WAIT 10 /* msec */
64 #define PCI_PM_D3COLD_WAIT 100 /* msec */
67 * Following exit from Conventional Reset, devices must be ready within 1 sec
68 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
69 * Reset (PCIe r6.0 sec 5.8).
71 #define PCI_RESET_WAIT 1000 /* msec */
73 * Devices may extend the 1 sec period through Request Retry Status completions
74 * (PCIe r6.0 sec 2.3.1). The spec does not provide an upper limit, but 60 sec
75 * ought to be enough for any device to become responsive.
77 #define PCIE_RESET_READY_POLL_MS 60000 /* msec */
79 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
80 void pci_refresh_power_state(struct pci_dev *dev);
81 int pci_power_up(struct pci_dev *dev);
82 void pci_disable_enabled_device(struct pci_dev *dev);
83 int pci_finish_runtime_suspend(struct pci_dev *dev);
84 void pcie_clear_device_status(struct pci_dev *dev);
85 void pcie_clear_root_pme_status(struct pci_dev *dev);
86 bool pci_check_pme_status(struct pci_dev *dev);
87 void pci_pme_wakeup_bus(struct pci_bus *bus);
88 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
89 void pci_pme_restore(struct pci_dev *dev);
90 bool pci_dev_need_resume(struct pci_dev *dev);
91 void pci_dev_adjust_pme(struct pci_dev *dev);
92 void pci_dev_complete_resume(struct pci_dev *pci_dev);
93 void pci_config_pm_runtime_get(struct pci_dev *dev);
94 void pci_config_pm_runtime_put(struct pci_dev *dev);
95 void pci_pm_init(struct pci_dev *dev);
96 void pci_ea_init(struct pci_dev *dev);
97 void pci_msi_init(struct pci_dev *dev);
98 void pci_msix_init(struct pci_dev *dev);
99 bool pci_bridge_d3_possible(struct pci_dev *dev);
100 void pci_bridge_d3_update(struct pci_dev *dev);
101 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
102 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
105 static inline void pci_wakeup_event(struct pci_dev *dev)
107 /* Wait 100 ms before the system can be put into a sleep state. */
108 pm_wakeup_event(&dev->dev, 100);
111 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
113 return !!(pci_dev->subordinate);
116 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
119 * Currently we allow normal PCI devices and PCI bridges transition
120 * into D3 if their bridge_d3 is set.
122 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
125 static inline bool pcie_downstream_port(const struct pci_dev *dev)
127 int type = pci_pcie_type(dev);
129 return type == PCI_EXP_TYPE_ROOT_PORT ||
130 type == PCI_EXP_TYPE_DOWNSTREAM ||
131 type == PCI_EXP_TYPE_PCIE_BRIDGE;
134 void pci_vpd_init(struct pci_dev *dev);
135 void pci_vpd_release(struct pci_dev *dev);
136 extern const struct attribute_group pci_dev_vpd_attr_group;
138 /* PCI Virtual Channel */
139 int pci_save_vc_state(struct pci_dev *dev);
140 void pci_restore_vc_state(struct pci_dev *dev);
141 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
143 /* PCI /proc functions */
144 #ifdef CONFIG_PROC_FS
145 int pci_proc_attach_device(struct pci_dev *dev);
146 int pci_proc_detach_device(struct pci_dev *dev);
147 int pci_proc_detach_bus(struct pci_bus *bus);
149 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
150 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
151 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
154 /* Functions for PCI Hotplug drivers to use */
155 int pci_hp_add_bridge(struct pci_dev *dev);
157 #ifdef HAVE_PCI_LEGACY
158 void pci_create_legacy_files(struct pci_bus *bus);
159 void pci_remove_legacy_files(struct pci_bus *bus);
161 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
162 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
165 /* Lock for read/write access to pci device and bus lists */
166 extern struct rw_semaphore pci_bus_sem;
167 extern struct mutex pci_slot_mutex;
169 extern raw_spinlock_t pci_lock;
171 extern unsigned int pci_pm_d3hot_delay;
173 #ifdef CONFIG_PCI_MSI
174 void pci_no_msi(void);
176 static inline void pci_no_msi(void) { }
179 void pci_realloc_get_opt(char *);
181 static inline int pci_no_d1d2(struct pci_dev *dev)
183 unsigned int parent_dstates = 0;
186 parent_dstates = dev->bus->self->no_d1d2;
187 return (dev->no_d1d2 || parent_dstates);
190 extern const struct attribute_group *pci_dev_groups[];
191 extern const struct attribute_group *pcibus_groups[];
192 extern const struct device_type pci_dev_type;
193 extern const struct attribute_group *pci_bus_groups[];
195 extern unsigned long pci_hotplug_io_size;
196 extern unsigned long pci_hotplug_mmio_size;
197 extern unsigned long pci_hotplug_mmio_pref_size;
198 extern unsigned long pci_hotplug_bus_size;
201 * pci_match_one_device - Tell if a PCI device structure has a matching
202 * PCI device id structure
203 * @id: single PCI device id structure to match
204 * @dev: the PCI device structure to match against
206 * Returns the matching pci_device_id structure or %NULL if there is no match.
208 static inline const struct pci_device_id *
209 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
211 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
212 (id->device == PCI_ANY_ID || id->device == dev->device) &&
213 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
214 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
215 !((id->class ^ dev->class) & id->class_mask))
220 /* PCI slot sysfs helper code */
221 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
223 extern struct kset *pci_slots_kset;
225 struct pci_slot_attribute {
226 struct attribute attr;
227 ssize_t (*show)(struct pci_slot *, char *);
228 ssize_t (*store)(struct pci_slot *, const char *, size_t);
230 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
233 pci_bar_unknown, /* Standard PCI BAR probe */
234 pci_bar_io, /* An I/O port BAR */
235 pci_bar_mem32, /* A 32-bit memory BAR */
236 pci_bar_mem64, /* A 64-bit memory BAR */
239 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
240 void pci_put_host_bridge_device(struct device *dev);
242 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
243 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
245 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
247 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
249 int pci_setup_device(struct pci_dev *dev);
250 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
251 struct resource *res, unsigned int reg);
252 void pci_configure_ari(struct pci_dev *dev);
253 void __pci_bus_size_bridges(struct pci_bus *bus,
254 struct list_head *realloc_head);
255 void __pci_bus_assign_resources(const struct pci_bus *bus,
256 struct list_head *realloc_head,
257 struct list_head *fail_head);
258 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
260 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
261 void pci_disable_bridge_window(struct pci_dev *dev);
262 struct pci_bus *pci_bus_get(struct pci_bus *bus);
263 void pci_bus_put(struct pci_bus *bus);
265 /* PCIe link information from Link Capabilities 2 */
266 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
267 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
268 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
269 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
270 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
271 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
272 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
275 /* PCIe speed to Mb/s reduced by encoding overhead */
276 #define PCIE_SPEED2MBS_ENC(speed) \
277 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
278 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
279 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
280 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
281 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
282 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
285 const char *pci_speed_string(enum pci_bus_speed speed);
286 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
287 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
288 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
289 enum pcie_link_width *width);
290 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
291 void pcie_report_downtraining(struct pci_dev *dev);
292 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
294 /* Single Root I/O Virtualization */
296 int pos; /* Capability position */
297 int nres; /* Number of resources */
298 u32 cap; /* SR-IOV Capabilities */
299 u16 ctrl; /* SR-IOV Control */
300 u16 total_VFs; /* Total VFs associated with the PF */
301 u16 initial_VFs; /* Initial VFs associated with the PF */
302 u16 num_VFs; /* Number of VFs available */
303 u16 offset; /* First VF Routing ID offset */
304 u16 stride; /* Following VF stride */
305 u16 vf_device; /* VF device ID */
306 u32 pgsz; /* Page size for BAR alignment */
307 u8 link; /* Function Dependency Link */
308 u8 max_VF_buses; /* Max buses consumed by VFs */
309 u16 driver_max_VFs; /* Max num VFs driver supports */
310 struct pci_dev *dev; /* Lowest numbered PF */
311 struct pci_dev *self; /* This PF */
312 u32 class; /* VF device */
313 u8 hdr_type; /* VF header type */
314 u16 subsystem_vendor; /* VF subsystem vendor */
315 u16 subsystem_device; /* VF subsystem device */
316 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
317 bool drivers_autoprobe; /* Auto probing of VFs by driver */
321 * pci_dev_set_io_state - Set the new error state if possible.
323 * @dev: PCI device to set new error_state
324 * @new: the state we want dev to be in
326 * If the device is experiencing perm_failure, it has to remain in that state.
327 * Any other transition is allowed.
329 * Returns true if state has been changed to the requested state.
331 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
332 pci_channel_state_t new)
334 pci_channel_state_t old;
337 case pci_channel_io_perm_failure:
338 xchg(&dev->error_state, pci_channel_io_perm_failure);
340 case pci_channel_io_frozen:
341 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
342 pci_channel_io_frozen);
343 return old != pci_channel_io_perm_failure;
344 case pci_channel_io_normal:
345 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
346 pci_channel_io_normal);
347 return old != pci_channel_io_perm_failure;
353 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
355 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
360 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
362 return dev->error_state == pci_channel_io_perm_failure;
365 /* pci_dev priv_flags */
366 #define PCI_DEV_ADDED 0
367 #define PCI_DPC_RECOVERED 1
368 #define PCI_DPC_RECOVERING 2
370 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
372 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
375 static inline bool pci_dev_is_added(const struct pci_dev *dev)
377 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
380 #ifdef CONFIG_PCIEAER
381 #include <linux/aer.h>
383 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
385 struct aer_err_info {
386 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
391 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
392 unsigned int __pad1:5;
393 unsigned int multi_error_valid:1;
395 unsigned int first_error:5;
396 unsigned int __pad2:2;
397 unsigned int tlp_header_valid:1;
399 unsigned int status; /* COR/UNCOR Error Status */
400 unsigned int mask; /* COR/UNCOR Error Mask */
401 struct aer_header_log_regs tlp; /* TLP Header */
404 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
405 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
406 #endif /* CONFIG_PCIEAER */
408 #ifdef CONFIG_PCIEPORTBUS
409 /* Cached RCEC Endpoint Association */
417 #ifdef CONFIG_PCIE_DPC
418 void pci_save_dpc_state(struct pci_dev *dev);
419 void pci_restore_dpc_state(struct pci_dev *dev);
420 void pci_dpc_init(struct pci_dev *pdev);
421 void dpc_process_error(struct pci_dev *pdev);
422 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
423 bool pci_dpc_recovered(struct pci_dev *pdev);
425 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
426 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
427 static inline void pci_dpc_init(struct pci_dev *pdev) {}
428 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
431 #ifdef CONFIG_PCIEPORTBUS
432 void pci_rcec_init(struct pci_dev *dev);
433 void pci_rcec_exit(struct pci_dev *dev);
434 void pcie_link_rcec(struct pci_dev *rcec);
435 void pcie_walk_rcec(struct pci_dev *rcec,
436 int (*cb)(struct pci_dev *, void *),
439 static inline void pci_rcec_init(struct pci_dev *dev) {}
440 static inline void pci_rcec_exit(struct pci_dev *dev) {}
441 static inline void pcie_link_rcec(struct pci_dev *rcec) {}
442 static inline void pcie_walk_rcec(struct pci_dev *rcec,
443 int (*cb)(struct pci_dev *, void *),
447 #ifdef CONFIG_PCI_ATS
448 /* Address Translation Service */
449 void pci_ats_init(struct pci_dev *dev);
450 void pci_restore_ats_state(struct pci_dev *dev);
452 static inline void pci_ats_init(struct pci_dev *d) { }
453 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
454 #endif /* CONFIG_PCI_ATS */
456 #ifdef CONFIG_PCI_PRI
457 void pci_pri_init(struct pci_dev *dev);
458 void pci_restore_pri_state(struct pci_dev *pdev);
460 static inline void pci_pri_init(struct pci_dev *dev) { }
461 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
464 #ifdef CONFIG_PCI_PASID
465 void pci_pasid_init(struct pci_dev *dev);
466 void pci_restore_pasid_state(struct pci_dev *pdev);
468 static inline void pci_pasid_init(struct pci_dev *dev) { }
469 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
472 #ifdef CONFIG_PCI_IOV
473 int pci_iov_init(struct pci_dev *dev);
474 void pci_iov_release(struct pci_dev *dev);
475 void pci_iov_remove(struct pci_dev *dev);
476 void pci_iov_update_resource(struct pci_dev *dev, int resno);
477 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
478 void pci_restore_iov_state(struct pci_dev *dev);
479 int pci_iov_bus_range(struct pci_bus *bus);
480 extern const struct attribute_group sriov_pf_dev_attr_group;
481 extern const struct attribute_group sriov_vf_dev_attr_group;
483 static inline int pci_iov_init(struct pci_dev *dev)
487 static inline void pci_iov_release(struct pci_dev *dev)
491 static inline void pci_iov_remove(struct pci_dev *dev)
494 static inline void pci_restore_iov_state(struct pci_dev *dev)
497 static inline int pci_iov_bus_range(struct pci_bus *bus)
502 #endif /* CONFIG_PCI_IOV */
504 #ifdef CONFIG_PCIE_PTM
505 void pci_ptm_init(struct pci_dev *dev);
506 void pci_save_ptm_state(struct pci_dev *dev);
507 void pci_restore_ptm_state(struct pci_dev *dev);
508 void pci_suspend_ptm(struct pci_dev *dev);
509 void pci_resume_ptm(struct pci_dev *dev);
511 static inline void pci_ptm_init(struct pci_dev *dev) { }
512 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
513 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
514 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
515 static inline void pci_resume_ptm(struct pci_dev *dev) { }
518 unsigned long pci_cardbus_resource_alignment(struct resource *);
520 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
521 struct resource *res)
523 #ifdef CONFIG_PCI_IOV
524 int resno = res - dev->resource;
526 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
527 return pci_sriov_resource_alignment(dev, resno);
529 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
530 return pci_cardbus_resource_alignment(res);
531 return resource_alignment(res);
534 void pci_acs_init(struct pci_dev *dev);
535 #ifdef CONFIG_PCI_QUIRKS
536 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
537 int pci_dev_specific_enable_acs(struct pci_dev *dev);
538 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
540 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
545 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
549 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
555 /* PCI error reporting and recovery */
556 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
557 pci_channel_state_t state,
558 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
560 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
561 #ifdef CONFIG_PCIEASPM
562 void pcie_aspm_init_link_state(struct pci_dev *pdev);
563 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
564 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
566 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
567 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
568 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
571 #ifdef CONFIG_PCIE_ECRC
572 void pcie_set_ecrc_checking(struct pci_dev *dev);
573 void pcie_ecrc_get_policy(char *str);
575 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
576 static inline void pcie_ecrc_get_policy(char *str) { }
579 struct pci_dev_reset_methods {
582 int (*reset)(struct pci_dev *dev, bool probe);
585 struct pci_reset_fn_method {
586 int (*reset_fn)(struct pci_dev *pdev, bool probe);
590 #ifdef CONFIG_PCI_QUIRKS
591 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
593 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
599 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
600 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
601 struct resource *res);
603 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
604 u16 segment, struct resource *res)
610 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
611 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
612 static inline u64 pci_rebar_size_to_bytes(int size)
614 return 1ULL << (size + 20);
620 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
621 int of_get_pci_domain_nr(struct device_node *node);
622 int of_pci_get_max_link_speed(struct device_node *node);
623 u32 of_pci_get_slot_power_limit(struct device_node *node,
624 u8 *slot_power_limit_value,
625 u8 *slot_power_limit_scale);
626 void pci_set_of_node(struct pci_dev *dev);
627 void pci_release_of_node(struct pci_dev *dev);
628 void pci_set_bus_of_node(struct pci_bus *bus);
629 void pci_release_bus_of_node(struct pci_bus *bus);
631 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
635 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
641 of_get_pci_domain_nr(struct device_node *node)
647 of_pci_get_max_link_speed(struct device_node *node)
653 of_pci_get_slot_power_limit(struct device_node *node,
654 u8 *slot_power_limit_value,
655 u8 *slot_power_limit_scale)
657 if (slot_power_limit_value)
658 *slot_power_limit_value = 0;
659 if (slot_power_limit_scale)
660 *slot_power_limit_scale = 0;
664 static inline void pci_set_of_node(struct pci_dev *dev) { }
665 static inline void pci_release_of_node(struct pci_dev *dev) { }
666 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
667 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
669 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
674 #endif /* CONFIG_OF */
676 #ifdef CONFIG_PCIEAER
677 void pci_no_aer(void);
678 void pci_aer_init(struct pci_dev *dev);
679 void pci_aer_exit(struct pci_dev *dev);
680 extern const struct attribute_group aer_stats_attr_group;
681 void pci_aer_clear_fatal_status(struct pci_dev *dev);
682 int pci_aer_clear_status(struct pci_dev *dev);
683 int pci_aer_raw_clear_status(struct pci_dev *dev);
685 static inline void pci_no_aer(void) { }
686 static inline void pci_aer_init(struct pci_dev *d) { }
687 static inline void pci_aer_exit(struct pci_dev *d) { }
688 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
689 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
690 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
694 int pci_acpi_program_hp_params(struct pci_dev *dev);
695 extern const struct attribute_group pci_dev_acpi_attr_group;
696 void pci_set_acpi_fwnode(struct pci_dev *dev);
697 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
698 bool acpi_pci_power_manageable(struct pci_dev *dev);
699 bool acpi_pci_bridge_d3(struct pci_dev *dev);
700 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
701 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
702 void acpi_pci_refresh_power_state(struct pci_dev *dev);
703 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
704 bool acpi_pci_need_resume(struct pci_dev *dev);
705 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
707 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
711 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
712 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
716 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
720 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
724 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
728 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
732 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
733 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
737 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
741 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
743 return PCI_POWER_ERROR;
747 #ifdef CONFIG_PCIEASPM
748 extern const struct attribute_group aspm_ctrl_attr_group;
751 extern const struct attribute_group pci_dev_reset_method_attr_group;
753 #ifdef CONFIG_X86_INTEL_MID
754 bool pci_use_mid_pm(void);
755 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
756 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
758 static inline bool pci_use_mid_pm(void)
762 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
766 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
773 * Config Address for PCI Configuration Mechanism #1
775 * See PCI Local Bus Specification, Revision 3.0,
776 * Section 3.2.2.3.2, Figure 3-2, p. 50.
779 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
780 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
781 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
783 #define PCI_CONF1_BUS_MASK 0xff
784 #define PCI_CONF1_DEV_MASK 0x1f
785 #define PCI_CONF1_FUNC_MASK 0x7
786 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
788 #define PCI_CONF1_ENABLE BIT(31)
789 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
790 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
791 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
792 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
794 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
795 (PCI_CONF1_ENABLE | \
796 PCI_CONF1_BUS(bus) | \
797 PCI_CONF1_DEV(dev) | \
798 PCI_CONF1_FUNC(func) | \
802 * Extension of PCI Config Address for accessing extended PCIe registers
804 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
805 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
806 * are used for specifying additional 4 high bits of PCI Express register.
809 #define PCI_CONF1_EXT_REG_SHIFT 16
810 #define PCI_CONF1_EXT_REG_MASK 0xf00
811 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
813 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
814 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
815 PCI_CONF1_EXT_REG(reg))
817 #endif /* DRIVERS_PCI_H */