1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
10 #define PCI_FIND_CAP_TTL 48
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14 extern const unsigned char pcie_link_speed[];
15 extern bool pci_early_dump;
17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
19 /* Functions internal to the PCI core code */
21 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
22 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
23 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
24 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
26 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
29 void pci_create_firmware_label_files(struct pci_dev *pdev);
30 void pci_remove_firmware_label_files(struct pci_dev *pdev);
32 void pci_cleanup_rom(struct pci_dev *dev);
35 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
36 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
38 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
39 enum pci_mmap_api mmap_api);
41 int pci_probe_reset_function(struct pci_dev *dev);
42 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
43 int pci_bus_error_reset(struct pci_dev *dev);
45 #define PCI_PM_D2_DELAY 200
46 #define PCI_PM_D3_WAIT 10
47 #define PCI_PM_D3COLD_WAIT 100
48 #define PCI_PM_BUS_WAIT 50
51 * Following exit from Conventional Reset, devices must be ready within 1 sec
52 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
53 * Reset (PCIe r6.0 sec 5.8).
55 #define PCI_RESET_WAIT 1000 /* msec */
58 * struct pci_platform_pm_ops - Firmware PM callbacks
60 * @bridge_d3: Does the bridge allow entering into D3
62 * @is_manageable: returns 'true' if given device is power manageable by the
65 * @set_state: invokes the platform firmware to set the device's power state
67 * @get_state: queries the platform firmware for a device's current power state
69 * @refresh_state: asks the platform to refresh the device's power state data
71 * @choose_state: returns PCI power state of given device preferred by the
72 * platform; to be used during system-wide transitions from a
73 * sleeping state to the working state and vice versa
75 * @set_wakeup: enables/disables wakeup capability for the device
77 * @need_resume: returns 'true' if the given device (which is currently
78 * suspended) needs to be resumed to be configured for system
81 * If given platform is generally capable of power managing PCI devices, all of
82 * these callbacks are mandatory.
84 struct pci_platform_pm_ops {
85 bool (*bridge_d3)(struct pci_dev *dev);
86 bool (*is_manageable)(struct pci_dev *dev);
87 int (*set_state)(struct pci_dev *dev, pci_power_t state);
88 pci_power_t (*get_state)(struct pci_dev *dev);
89 void (*refresh_state)(struct pci_dev *dev);
90 pci_power_t (*choose_state)(struct pci_dev *dev);
91 int (*set_wakeup)(struct pci_dev *dev, bool enable);
92 bool (*need_resume)(struct pci_dev *dev);
95 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
96 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
97 void pci_refresh_power_state(struct pci_dev *dev);
98 void pci_power_up(struct pci_dev *dev);
99 void pci_disable_enabled_device(struct pci_dev *dev);
100 int pci_finish_runtime_suspend(struct pci_dev *dev);
101 void pcie_clear_root_pme_status(struct pci_dev *dev);
102 bool pci_check_pme_status(struct pci_dev *dev);
103 void pci_pme_wakeup_bus(struct pci_bus *bus);
104 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
105 void pci_pme_restore(struct pci_dev *dev);
106 bool pci_dev_need_resume(struct pci_dev *dev);
107 void pci_dev_adjust_pme(struct pci_dev *dev);
108 void pci_dev_complete_resume(struct pci_dev *pci_dev);
109 void pci_config_pm_runtime_get(struct pci_dev *dev);
110 void pci_config_pm_runtime_put(struct pci_dev *dev);
111 void pci_pm_init(struct pci_dev *dev);
112 void pci_ea_init(struct pci_dev *dev);
113 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
114 void pci_free_cap_save_buffers(struct pci_dev *dev);
115 bool pci_bridge_d3_possible(struct pci_dev *dev);
116 void pci_bridge_d3_update(struct pci_dev *dev);
117 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
120 static inline void pci_wakeup_event(struct pci_dev *dev)
122 /* Wait 100 ms before the system can be put into a sleep state. */
123 pm_wakeup_event(&dev->dev, 100);
126 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
128 return !!(pci_dev->subordinate);
131 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
134 * Currently we allow normal PCI devices and PCI bridges transition
135 * into D3 if their bridge_d3 is set.
137 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
140 static inline bool pcie_downstream_port(const struct pci_dev *dev)
142 int type = pci_pcie_type(dev);
144 return type == PCI_EXP_TYPE_ROOT_PORT ||
145 type == PCI_EXP_TYPE_DOWNSTREAM ||
146 type == PCI_EXP_TYPE_PCIE_BRIDGE;
149 int pci_vpd_init(struct pci_dev *dev);
150 void pci_vpd_release(struct pci_dev *dev);
151 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
152 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
154 /* PCI Virtual Channel */
155 int pci_save_vc_state(struct pci_dev *dev);
156 void pci_restore_vc_state(struct pci_dev *dev);
157 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
159 /* PCI /proc functions */
160 #ifdef CONFIG_PROC_FS
161 int pci_proc_attach_device(struct pci_dev *dev);
162 int pci_proc_detach_device(struct pci_dev *dev);
163 int pci_proc_detach_bus(struct pci_bus *bus);
165 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
166 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
167 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
170 /* Functions for PCI Hotplug drivers to use */
171 int pci_hp_add_bridge(struct pci_dev *dev);
173 #ifdef HAVE_PCI_LEGACY
174 void pci_create_legacy_files(struct pci_bus *bus);
175 void pci_remove_legacy_files(struct pci_bus *bus);
177 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
178 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
181 /* Lock for read/write access to pci device and bus lists */
182 extern struct rw_semaphore pci_bus_sem;
183 extern struct mutex pci_slot_mutex;
185 extern raw_spinlock_t pci_lock;
187 extern unsigned int pci_pm_d3_delay;
189 #ifdef CONFIG_PCI_MSI
190 void pci_no_msi(void);
192 static inline void pci_no_msi(void) { }
195 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
199 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
200 control &= ~PCI_MSI_FLAGS_ENABLE;
202 control |= PCI_MSI_FLAGS_ENABLE;
203 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
206 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
210 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
213 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
216 void pci_realloc_get_opt(char *);
218 static inline int pci_no_d1d2(struct pci_dev *dev)
220 unsigned int parent_dstates = 0;
223 parent_dstates = dev->bus->self->no_d1d2;
224 return (dev->no_d1d2 || parent_dstates);
227 extern const struct attribute_group *pci_dev_groups[];
228 extern const struct attribute_group *pcibus_groups[];
229 extern const struct device_type pci_dev_type;
230 extern const struct attribute_group *pci_bus_groups[];
232 extern unsigned long pci_hotplug_io_size;
233 extern unsigned long pci_hotplug_mem_size;
234 extern unsigned long pci_hotplug_bus_size;
237 * pci_match_one_device - Tell if a PCI device structure has a matching
238 * PCI device id structure
239 * @id: single PCI device id structure to match
240 * @dev: the PCI device structure to match against
242 * Returns the matching pci_device_id structure or %NULL if there is no match.
244 static inline const struct pci_device_id *
245 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
247 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
248 (id->device == PCI_ANY_ID || id->device == dev->device) &&
249 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
250 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
251 !((id->class ^ dev->class) & id->class_mask))
256 /* PCI slot sysfs helper code */
257 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
259 extern struct kset *pci_slots_kset;
261 struct pci_slot_attribute {
262 struct attribute attr;
263 ssize_t (*show)(struct pci_slot *, char *);
264 ssize_t (*store)(struct pci_slot *, const char *, size_t);
266 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
269 pci_bar_unknown, /* Standard PCI BAR probe */
270 pci_bar_io, /* An I/O port BAR */
271 pci_bar_mem32, /* A 32-bit memory BAR */
272 pci_bar_mem64, /* A 64-bit memory BAR */
275 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
276 void pci_put_host_bridge_device(struct device *dev);
278 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
279 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
281 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
283 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
285 int pci_setup_device(struct pci_dev *dev);
286 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
287 struct resource *res, unsigned int reg);
288 void pci_configure_ari(struct pci_dev *dev);
289 void __pci_bus_size_bridges(struct pci_bus *bus,
290 struct list_head *realloc_head);
291 void __pci_bus_assign_resources(const struct pci_bus *bus,
292 struct list_head *realloc_head,
293 struct list_head *fail_head);
294 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
296 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
297 void pci_disable_bridge_window(struct pci_dev *dev);
298 struct pci_bus *pci_bus_get(struct pci_bus *bus);
299 void pci_bus_put(struct pci_bus *bus);
301 /* PCIe link information */
302 #define PCIE_SPEED2STR(speed) \
303 ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
304 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
305 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
306 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
309 /* PCIe speed to Mb/s reduced by encoding overhead */
310 #define PCIE_SPEED2MBS_ENC(speed) \
311 ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
312 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
313 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
314 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
317 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
318 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
319 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
320 enum pcie_link_width *width);
321 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
322 void pcie_report_downtraining(struct pci_dev *dev);
323 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
325 /* Single Root I/O Virtualization */
327 int pos; /* Capability position */
328 int nres; /* Number of resources */
329 u32 cap; /* SR-IOV Capabilities */
330 u16 ctrl; /* SR-IOV Control */
331 u16 total_VFs; /* Total VFs associated with the PF */
332 u16 initial_VFs; /* Initial VFs associated with the PF */
333 u16 num_VFs; /* Number of VFs available */
334 u16 offset; /* First VF Routing ID offset */
335 u16 stride; /* Following VF stride */
336 u16 vf_device; /* VF device ID */
337 u32 pgsz; /* Page size for BAR alignment */
338 u8 link; /* Function Dependency Link */
339 u8 max_VF_buses; /* Max buses consumed by VFs */
340 u16 driver_max_VFs; /* Max num VFs driver supports */
341 struct pci_dev *dev; /* Lowest numbered PF */
342 struct pci_dev *self; /* This PF */
343 u32 class; /* VF device */
344 u8 hdr_type; /* VF header type */
345 u16 subsystem_vendor; /* VF subsystem vendor */
346 u16 subsystem_device; /* VF subsystem device */
347 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
348 bool drivers_autoprobe; /* Auto probing of VFs by driver */
352 * pci_dev_set_io_state - Set the new error state if possible.
354 * @dev - pci device to set new error_state
355 * @new - the state we want dev to be in
357 * If the device is experiencing perm_failure, it has to remain in that state.
358 * Any other transition is allowed.
360 * Returns true if state has been changed to the requested state.
362 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
363 pci_channel_state_t new)
365 pci_channel_state_t old;
368 case pci_channel_io_perm_failure:
369 xchg(&dev->error_state, pci_channel_io_perm_failure);
371 case pci_channel_io_frozen:
372 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
373 pci_channel_io_frozen);
374 return old != pci_channel_io_perm_failure;
375 case pci_channel_io_normal:
376 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
377 pci_channel_io_normal);
378 return old != pci_channel_io_perm_failure;
384 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
386 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
391 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
393 return dev->error_state == pci_channel_io_perm_failure;
396 /* pci_dev priv_flags */
397 #define PCI_DEV_ADDED 0
399 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
401 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
404 static inline bool pci_dev_is_added(const struct pci_dev *dev)
406 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
409 #ifdef CONFIG_PCIEAER
410 #include <linux/aer.h>
412 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
414 struct aer_err_info {
415 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
420 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
421 unsigned int __pad1:5;
422 unsigned int multi_error_valid:1;
424 unsigned int first_error:5;
425 unsigned int __pad2:2;
426 unsigned int tlp_header_valid:1;
428 unsigned int status; /* COR/UNCOR Error Status */
429 unsigned int mask; /* COR/UNCOR Error Mask */
430 struct aer_header_log_regs tlp; /* TLP Header */
433 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
434 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
435 #endif /* CONFIG_PCIEAER */
437 #ifdef CONFIG_PCIE_DPC
438 void pci_save_dpc_state(struct pci_dev *dev);
439 void pci_restore_dpc_state(struct pci_dev *dev);
441 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
442 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
445 #ifdef CONFIG_PCI_ATS
446 /* Address Translation Service */
447 void pci_ats_init(struct pci_dev *dev);
448 void pci_restore_ats_state(struct pci_dev *dev);
450 static inline void pci_ats_init(struct pci_dev *d) { }
451 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
452 #endif /* CONFIG_PCI_ATS */
454 #ifdef CONFIG_PCI_IOV
455 int pci_iov_init(struct pci_dev *dev);
456 void pci_iov_release(struct pci_dev *dev);
457 void pci_iov_remove(struct pci_dev *dev);
458 void pci_iov_update_resource(struct pci_dev *dev, int resno);
459 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
460 void pci_restore_iov_state(struct pci_dev *dev);
461 int pci_iov_bus_range(struct pci_bus *bus);
462 extern const struct attribute_group sriov_dev_attr_group;
464 static inline int pci_iov_init(struct pci_dev *dev)
468 static inline void pci_iov_release(struct pci_dev *dev)
472 static inline void pci_iov_remove(struct pci_dev *dev)
475 static inline void pci_restore_iov_state(struct pci_dev *dev)
478 static inline int pci_iov_bus_range(struct pci_bus *bus)
483 #endif /* CONFIG_PCI_IOV */
485 unsigned long pci_cardbus_resource_alignment(struct resource *);
487 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
488 struct resource *res)
490 #ifdef CONFIG_PCI_IOV
491 int resno = res - dev->resource;
493 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
494 return pci_sriov_resource_alignment(dev, resno);
496 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
497 return pci_cardbus_resource_alignment(res);
498 return resource_alignment(res);
501 void pci_enable_acs(struct pci_dev *dev);
502 #ifdef CONFIG_PCI_QUIRKS
503 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
504 int pci_dev_specific_enable_acs(struct pci_dev *dev);
505 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
507 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
512 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
516 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
522 /* PCI error reporting and recovery */
523 void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,
526 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
527 #ifdef CONFIG_PCIEASPM
528 void pcie_aspm_init_link_state(struct pci_dev *pdev);
529 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
530 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
531 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
533 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
534 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
535 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
536 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
539 #ifdef CONFIG_PCIEASPM_DEBUG
540 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
541 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
543 static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
544 static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
547 #ifdef CONFIG_PCIE_ECRC
548 void pcie_set_ecrc_checking(struct pci_dev *dev);
549 void pcie_ecrc_get_policy(char *str);
551 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
552 static inline void pcie_ecrc_get_policy(char *str) { }
555 #ifdef CONFIG_PCIE_PTM
556 void pci_ptm_init(struct pci_dev *dev);
557 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
559 static inline void pci_ptm_init(struct pci_dev *dev) { }
560 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
564 struct pci_dev_reset_methods {
567 int (*reset)(struct pci_dev *dev, int probe);
570 #ifdef CONFIG_PCI_QUIRKS
571 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
573 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
579 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
580 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
581 struct resource *res);
583 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
584 u16 segment, struct resource *res)
590 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
591 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
592 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
593 static inline u64 pci_rebar_size_to_bytes(int size)
595 return 1ULL << (size + 20);
601 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
602 int of_get_pci_domain_nr(struct device_node *node);
603 int of_pci_get_max_link_speed(struct device_node *node);
604 void pci_set_of_node(struct pci_dev *dev);
605 void pci_release_of_node(struct pci_dev *dev);
606 void pci_set_bus_of_node(struct pci_bus *bus);
607 void pci_release_bus_of_node(struct pci_bus *bus);
611 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
617 of_get_pci_domain_nr(struct device_node *node)
623 of_pci_get_max_link_speed(struct device_node *node)
628 static inline void pci_set_of_node(struct pci_dev *dev) { }
629 static inline void pci_release_of_node(struct pci_dev *dev) { }
630 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
631 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
632 #endif /* CONFIG_OF */
634 #if defined(CONFIG_OF_ADDRESS)
635 int devm_of_pci_get_host_bridge_resources(struct device *dev,
636 unsigned char busno, unsigned char bus_max,
637 struct list_head *resources, resource_size_t *io_base);
639 static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
640 unsigned char busno, unsigned char bus_max,
641 struct list_head *resources, resource_size_t *io_base)
647 #ifdef CONFIG_PCIEAER
648 void pci_no_aer(void);
649 void pci_aer_init(struct pci_dev *dev);
650 void pci_aer_exit(struct pci_dev *dev);
651 extern const struct attribute_group aer_stats_attr_group;
652 void pci_aer_clear_fatal_status(struct pci_dev *dev);
653 void pci_aer_clear_device_status(struct pci_dev *dev);
655 static inline void pci_no_aer(void) { }
656 static inline void pci_aer_init(struct pci_dev *d) { }
657 static inline void pci_aer_exit(struct pci_dev *d) { }
658 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
659 static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
663 int pci_acpi_program_hp_params(struct pci_dev *dev);
665 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
671 #endif /* DRIVERS_PCI_H */