2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/interrupt.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pci_hotplug.h>
30 #include <linux/vmalloc.h>
31 #include <asm/setup.h>
33 #include <linux/aer.h>
36 const char *pci_power_names[] = {
37 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
39 EXPORT_SYMBOL_GPL(pci_power_names);
41 int isa_dma_bridge_buggy;
42 EXPORT_SYMBOL(isa_dma_bridge_buggy);
45 EXPORT_SYMBOL(pci_pci_problems);
47 unsigned int pci_pm_d3_delay;
49 static void pci_pme_list_scan(struct work_struct *work);
51 static LIST_HEAD(pci_pme_list);
52 static DEFINE_MUTEX(pci_pme_list_mutex);
53 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
55 struct pci_pme_device {
56 struct list_head list;
60 #define PME_TIMEOUT 1000 /* How long between PME checks */
62 static void pci_dev_d3_sleep(struct pci_dev *dev)
64 unsigned int delay = dev->d3_delay;
66 if (delay < pci_pm_d3_delay)
67 delay = pci_pm_d3_delay;
72 #ifdef CONFIG_PCI_DOMAINS
73 int pci_domains_supported = 1;
76 #define DEFAULT_CARDBUS_IO_SIZE (256)
77 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
78 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
79 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
80 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
82 #define DEFAULT_HOTPLUG_IO_SIZE (256)
83 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
84 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
85 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
86 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
88 #define DEFAULT_HOTPLUG_BUS_SIZE 1
89 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
91 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
94 * The default CLS is used if arch didn't set CLS explicitly and not
95 * all pci devices agree on the same value. Arch can override either
96 * the dfl or actual value as it sees fit. Don't forget this is
97 * measured in 32-bit words, not bytes.
99 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
100 u8 pci_cache_line_size;
103 * If we set up a device for bus mastering, we need to check the latency
104 * timer as certain BIOSes forget to set it properly.
106 unsigned int pcibios_max_latency = 255;
108 /* If set, the PCIe ARI capability will not be used. */
109 static bool pcie_ari_disabled;
111 /* Disable bridge_d3 for all PCIe ports */
112 static bool pci_bridge_d3_disable;
113 /* Force bridge_d3 for all PCIe ports */
114 static bool pci_bridge_d3_force;
116 static int __init pcie_port_pm_setup(char *str)
118 if (!strcmp(str, "off"))
119 pci_bridge_d3_disable = true;
120 else if (!strcmp(str, "force"))
121 pci_bridge_d3_force = true;
124 __setup("pcie_port_pm=", pcie_port_pm_setup);
127 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
128 * @bus: pointer to PCI bus structure to search
130 * Given a PCI bus, returns the highest PCI bus number present in the set
131 * including the given PCI bus and its list of child PCI buses.
133 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
136 unsigned char max, n;
138 max = bus->busn_res.end;
139 list_for_each_entry(tmp, &bus->children, node) {
140 n = pci_bus_max_busnr(tmp);
146 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
148 #ifdef CONFIG_HAS_IOMEM
149 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
151 struct resource *res = &pdev->resource[bar];
154 * Make sure the BAR is actually a memory resource, not an IO resource
156 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
157 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
160 return ioremap_nocache(res->start, resource_size(res));
162 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
164 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
167 * Make sure the BAR is actually a memory resource, not an IO resource
169 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
173 return ioremap_wc(pci_resource_start(pdev, bar),
174 pci_resource_len(pdev, bar));
176 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
180 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
181 u8 pos, int cap, int *ttl)
186 pci_bus_read_config_byte(bus, devfn, pos, &pos);
192 pci_bus_read_config_word(bus, devfn, pos, &ent);
204 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
207 int ttl = PCI_FIND_CAP_TTL;
209 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
212 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
214 return __pci_find_next_cap(dev->bus, dev->devfn,
215 pos + PCI_CAP_LIST_NEXT, cap);
217 EXPORT_SYMBOL_GPL(pci_find_next_capability);
219 static int __pci_bus_find_cap_start(struct pci_bus *bus,
220 unsigned int devfn, u8 hdr_type)
224 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
225 if (!(status & PCI_STATUS_CAP_LIST))
229 case PCI_HEADER_TYPE_NORMAL:
230 case PCI_HEADER_TYPE_BRIDGE:
231 return PCI_CAPABILITY_LIST;
232 case PCI_HEADER_TYPE_CARDBUS:
233 return PCI_CB_CAPABILITY_LIST;
240 * pci_find_capability - query for devices' capabilities
241 * @dev: PCI device to query
242 * @cap: capability code
244 * Tell if a device supports a given PCI capability.
245 * Returns the address of the requested capability structure within the
246 * device's PCI configuration space or 0 in case the device does not
247 * support it. Possible values for @cap:
249 * %PCI_CAP_ID_PM Power Management
250 * %PCI_CAP_ID_AGP Accelerated Graphics Port
251 * %PCI_CAP_ID_VPD Vital Product Data
252 * %PCI_CAP_ID_SLOTID Slot Identification
253 * %PCI_CAP_ID_MSI Message Signalled Interrupts
254 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
255 * %PCI_CAP_ID_PCIX PCI-X
256 * %PCI_CAP_ID_EXP PCI Express
258 int pci_find_capability(struct pci_dev *dev, int cap)
262 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
264 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
268 EXPORT_SYMBOL(pci_find_capability);
271 * pci_bus_find_capability - query for devices' capabilities
272 * @bus: the PCI bus to query
273 * @devfn: PCI device to query
274 * @cap: capability code
276 * Like pci_find_capability() but works for pci devices that do not have a
277 * pci_dev structure set up yet.
279 * Returns the address of the requested capability structure within the
280 * device's PCI configuration space or 0 in case the device does not
283 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
288 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
290 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
292 pos = __pci_find_next_cap(bus, devfn, pos, cap);
296 EXPORT_SYMBOL(pci_bus_find_capability);
299 * pci_find_next_ext_capability - Find an extended capability
300 * @dev: PCI device to query
301 * @start: address at which to start looking (0 to start at beginning of list)
302 * @cap: capability code
304 * Returns the address of the next matching extended capability structure
305 * within the device's PCI configuration space or 0 if the device does
306 * not support it. Some capabilities can occur several times, e.g., the
307 * vendor-specific capability, and this provides a way to find them all.
309 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
313 int pos = PCI_CFG_SPACE_SIZE;
315 /* minimum 8 bytes per capability */
316 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
318 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
324 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
328 * If we have no capabilities, this is indicated by cap ID,
329 * cap version and next pointer all being 0.
335 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
338 pos = PCI_EXT_CAP_NEXT(header);
339 if (pos < PCI_CFG_SPACE_SIZE)
342 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
348 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
351 * pci_find_ext_capability - Find an extended capability
352 * @dev: PCI device to query
353 * @cap: capability code
355 * Returns the address of the requested extended capability structure
356 * within the device's PCI configuration space or 0 if the device does
357 * not support it. Possible values for @cap:
359 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
360 * %PCI_EXT_CAP_ID_VC Virtual Channel
361 * %PCI_EXT_CAP_ID_DSN Device Serial Number
362 * %PCI_EXT_CAP_ID_PWR Power Budgeting
364 int pci_find_ext_capability(struct pci_dev *dev, int cap)
366 return pci_find_next_ext_capability(dev, 0, cap);
368 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
370 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
372 int rc, ttl = PCI_FIND_CAP_TTL;
375 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
376 mask = HT_3BIT_CAP_MASK;
378 mask = HT_5BIT_CAP_MASK;
380 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
381 PCI_CAP_ID_HT, &ttl);
383 rc = pci_read_config_byte(dev, pos + 3, &cap);
384 if (rc != PCIBIOS_SUCCESSFUL)
387 if ((cap & mask) == ht_cap)
390 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
391 pos + PCI_CAP_LIST_NEXT,
392 PCI_CAP_ID_HT, &ttl);
398 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
399 * @dev: PCI device to query
400 * @pos: Position from which to continue searching
401 * @ht_cap: Hypertransport capability code
403 * To be used in conjunction with pci_find_ht_capability() to search for
404 * all capabilities matching @ht_cap. @pos should always be a value returned
405 * from pci_find_ht_capability().
407 * NB. To be 100% safe against broken PCI devices, the caller should take
408 * steps to avoid an infinite loop.
410 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
412 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
414 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
417 * pci_find_ht_capability - query a device's Hypertransport capabilities
418 * @dev: PCI device to query
419 * @ht_cap: Hypertransport capability code
421 * Tell if a device supports a given Hypertransport capability.
422 * Returns an address within the device's PCI configuration space
423 * or 0 in case the device does not support the request capability.
424 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
425 * which has a Hypertransport capability matching @ht_cap.
427 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
431 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
433 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
437 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
440 * pci_find_parent_resource - return resource region of parent bus of given region
441 * @dev: PCI device structure contains resources to be searched
442 * @res: child resource record for which parent is sought
444 * For given resource region of given device, return the resource
445 * region of parent bus the given region is contained in.
447 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
448 struct resource *res)
450 const struct pci_bus *bus = dev->bus;
454 pci_bus_for_each_resource(bus, r, i) {
457 if (res->start && resource_contains(r, res)) {
460 * If the window is prefetchable but the BAR is
461 * not, the allocator made a mistake.
463 if (r->flags & IORESOURCE_PREFETCH &&
464 !(res->flags & IORESOURCE_PREFETCH))
468 * If we're below a transparent bridge, there may
469 * be both a positively-decoded aperture and a
470 * subtractively-decoded region that contain the BAR.
471 * We want the positively-decoded one, so this depends
472 * on pci_bus_for_each_resource() giving us those
480 EXPORT_SYMBOL(pci_find_parent_resource);
483 * pci_find_resource - Return matching PCI device resource
484 * @dev: PCI device to query
485 * @res: Resource to look for
487 * Goes over standard PCI resources (BARs) and checks if the given resource
488 * is partially or fully contained in any of them. In that case the
489 * matching resource is returned, %NULL otherwise.
491 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
495 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
496 struct resource *r = &dev->resource[i];
498 if (r->start && resource_contains(r, res))
504 EXPORT_SYMBOL(pci_find_resource);
507 * pci_find_pcie_root_port - return PCIe Root Port
508 * @dev: PCI device to query
510 * Traverse up the parent chain and return the PCIe Root Port PCI Device
511 * for a given PCI Device.
513 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
515 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
517 bridge = pci_upstream_bridge(dev);
518 while (bridge && pci_is_pcie(bridge)) {
519 highest_pcie_bridge = bridge;
520 bridge = pci_upstream_bridge(bridge);
523 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
526 return highest_pcie_bridge;
528 EXPORT_SYMBOL(pci_find_pcie_root_port);
531 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
532 * @dev: the PCI device to operate on
533 * @pos: config space offset of status word
534 * @mask: mask of bit(s) to care about in status word
536 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
538 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
542 /* Wait for Transaction Pending bit clean */
543 for (i = 0; i < 4; i++) {
546 msleep((1 << (i - 1)) * 100);
548 pci_read_config_word(dev, pos, &status);
549 if (!(status & mask))
557 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
558 * @dev: PCI device to have its BARs restored
560 * Restore the BAR values for a given device, so as to make it
561 * accessible by its driver.
563 static void pci_restore_bars(struct pci_dev *dev)
567 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
568 pci_update_resource(dev, i);
571 static const struct pci_platform_pm_ops *pci_platform_pm;
573 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
575 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
576 !ops->choose_state || !ops->sleep_wake || !ops->run_wake ||
579 pci_platform_pm = ops;
583 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
585 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
588 static inline int platform_pci_set_power_state(struct pci_dev *dev,
591 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
594 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
596 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
599 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
601 return pci_platform_pm ?
602 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
605 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
607 return pci_platform_pm ?
608 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
611 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
613 return pci_platform_pm ?
614 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
617 static inline bool platform_pci_need_resume(struct pci_dev *dev)
619 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
623 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
625 * @dev: PCI device to handle.
626 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
629 * -EINVAL if the requested state is invalid.
630 * -EIO if device does not support PCI PM or its PM capabilities register has a
631 * wrong version, or device doesn't support the requested state.
632 * 0 if device already is in the requested state.
633 * 0 if device's power state has been successfully changed.
635 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
638 bool need_restore = false;
640 /* Check if we're already there */
641 if (dev->current_state == state)
647 if (state < PCI_D0 || state > PCI_D3hot)
650 /* Validate current state:
651 * Can enter D0 from any state, but if we can only go deeper
652 * to sleep if we're already in a low power state
654 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
655 && dev->current_state > state) {
656 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
657 dev->current_state, state);
661 /* check if this device supports the desired state */
662 if ((state == PCI_D1 && !dev->d1_support)
663 || (state == PCI_D2 && !dev->d2_support))
666 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
668 /* If we're (effectively) in D3, force entire word to 0.
669 * This doesn't affect PME_Status, disables PME_En, and
670 * sets PowerState to 0.
672 switch (dev->current_state) {
676 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
681 case PCI_UNKNOWN: /* Boot-up */
682 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
683 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
685 /* Fall-through: force to D0 */
691 /* enter specified state */
692 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
694 /* Mandatory power management transition delays */
695 /* see PCI PM 1.1 5.6.1 table 18 */
696 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
697 pci_dev_d3_sleep(dev);
698 else if (state == PCI_D2 || dev->current_state == PCI_D2)
699 udelay(PCI_PM_D2_DELAY);
701 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
702 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
703 if (dev->current_state != state && printk_ratelimit())
704 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
708 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
709 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
710 * from D3hot to D0 _may_ perform an internal reset, thereby
711 * going to "D0 Uninitialized" rather than "D0 Initialized".
712 * For example, at least some versions of the 3c905B and the
713 * 3c556B exhibit this behaviour.
715 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
716 * devices in a D3hot state at boot. Consequently, we need to
717 * restore at least the BARs so that the device will be
718 * accessible to its driver.
721 pci_restore_bars(dev);
724 pcie_aspm_pm_state_change(dev->bus->self);
730 * pci_update_current_state - Read power state of given device and cache it
731 * @dev: PCI device to handle.
732 * @state: State to cache in case the device doesn't have the PM capability
734 * The power state is read from the PMCSR register, which however is
735 * inaccessible in D3cold. The platform firmware is therefore queried first
736 * to detect accessibility of the register. In case the platform firmware
737 * reports an incorrect state or the device isn't power manageable by the
738 * platform at all, we try to detect D3cold by testing accessibility of the
739 * vendor ID in config space.
741 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
743 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
744 !pci_device_is_present(dev)) {
745 dev->current_state = PCI_D3cold;
746 } else if (dev->pm_cap) {
749 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
750 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
752 dev->current_state = state;
757 * pci_platform_power_transition - Use platform to change device power state
758 * @dev: PCI device to handle.
759 * @state: State to put the device into.
761 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
765 if (platform_pci_power_manageable(dev)) {
766 error = platform_pci_set_power_state(dev, state);
768 pci_update_current_state(dev, state);
772 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
773 dev->current_state = PCI_D0;
779 * pci_wakeup - Wake up a PCI device
780 * @pci_dev: Device to handle.
781 * @ign: ignored parameter
783 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
785 pci_wakeup_event(pci_dev);
786 pm_request_resume(&pci_dev->dev);
791 * pci_wakeup_bus - Walk given bus and wake up devices on it
792 * @bus: Top bus of the subtree to walk.
794 static void pci_wakeup_bus(struct pci_bus *bus)
797 pci_walk_bus(bus, pci_wakeup, NULL);
801 * __pci_start_power_transition - Start power transition of a PCI device
802 * @dev: PCI device to handle.
803 * @state: State to put the device into.
805 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
807 if (state == PCI_D0) {
808 pci_platform_power_transition(dev, PCI_D0);
810 * Mandatory power management transition delays, see
811 * PCI Express Base Specification Revision 2.0 Section
812 * 6.6.1: Conventional Reset. Do not delay for
813 * devices powered on/off by corresponding bridge,
814 * because have already delayed for the bridge.
816 if (dev->runtime_d3cold) {
817 msleep(dev->d3cold_delay);
819 * When powering on a bridge from D3cold, the
820 * whole hierarchy may be powered on into
821 * D0uninitialized state, resume them to give
822 * them a chance to suspend again
824 pci_wakeup_bus(dev->subordinate);
830 * __pci_dev_set_current_state - Set current state of a PCI device
831 * @dev: Device to handle
832 * @data: pointer to state to be set
834 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
836 pci_power_t state = *(pci_power_t *)data;
838 dev->current_state = state;
843 * __pci_bus_set_current_state - Walk given bus and set current state of devices
844 * @bus: Top bus of the subtree to walk.
845 * @state: state to be set
847 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
850 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
854 * __pci_complete_power_transition - Complete power transition of a PCI device
855 * @dev: PCI device to handle.
856 * @state: State to put the device into.
858 * This function should not be called directly by device drivers.
860 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
866 ret = pci_platform_power_transition(dev, state);
867 /* Power off the bridge may power off the whole hierarchy */
868 if (!ret && state == PCI_D3cold)
869 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
872 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
875 * pci_set_power_state - Set the power state of a PCI device
876 * @dev: PCI device to handle.
877 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
879 * Transition a device to a new power state, using the platform firmware and/or
880 * the device's PCI PM registers.
883 * -EINVAL if the requested state is invalid.
884 * -EIO if device does not support PCI PM or its PM capabilities register has a
885 * wrong version, or device doesn't support the requested state.
886 * 0 if device already is in the requested state.
887 * 0 if device's power state has been successfully changed.
889 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
893 /* bound the state we're entering */
894 if (state > PCI_D3cold)
896 else if (state < PCI_D0)
898 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
900 * If the device or the parent bridge do not support PCI PM,
901 * ignore the request if we're doing anything other than putting
902 * it into D0 (which would only happen on boot).
906 /* Check if we're already there */
907 if (dev->current_state == state)
910 __pci_start_power_transition(dev, state);
912 /* This device is quirked not to be put into D3, so
913 don't put it in D3 */
914 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
918 * To put device in D3cold, we put device into D3hot in native
919 * way, then put device into D3cold with platform ops
921 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
924 if (!__pci_complete_power_transition(dev, state))
929 EXPORT_SYMBOL(pci_set_power_state);
932 * pci_power_up - Put the given device into D0 forcibly
933 * @dev: PCI device to power up
935 void pci_power_up(struct pci_dev *dev)
937 __pci_start_power_transition(dev, PCI_D0);
938 pci_raw_set_power_state(dev, PCI_D0);
939 pci_update_current_state(dev, PCI_D0);
943 * pci_choose_state - Choose the power state of a PCI device
944 * @dev: PCI device to be suspended
945 * @state: target sleep state for the whole system. This is the value
946 * that is passed to suspend() function.
948 * Returns PCI power state suitable for given device and given system
952 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
959 ret = platform_pci_choose_state(dev);
960 if (ret != PCI_POWER_ERROR)
963 switch (state.event) {
966 case PM_EVENT_FREEZE:
967 case PM_EVENT_PRETHAW:
968 /* REVISIT both freeze and pre-thaw "should" use D0 */
969 case PM_EVENT_SUSPEND:
970 case PM_EVENT_HIBERNATE:
973 dev_info(&dev->dev, "unrecognized suspend event %d\n",
979 EXPORT_SYMBOL(pci_choose_state);
981 #define PCI_EXP_SAVE_REGS 7
983 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
984 u16 cap, bool extended)
986 struct pci_cap_saved_state *tmp;
988 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
989 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
995 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
997 return _pci_find_saved_cap(dev, cap, false);
1000 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1002 return _pci_find_saved_cap(dev, cap, true);
1005 static int pci_save_pcie_state(struct pci_dev *dev)
1008 struct pci_cap_saved_state *save_state;
1011 if (!pci_is_pcie(dev))
1014 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1016 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1020 cap = (u16 *)&save_state->cap.data[0];
1021 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1022 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1023 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1024 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1025 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1026 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1027 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1032 static void pci_restore_pcie_state(struct pci_dev *dev)
1035 struct pci_cap_saved_state *save_state;
1038 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1042 cap = (u16 *)&save_state->cap.data[0];
1043 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1044 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1045 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1046 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1047 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1048 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1049 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1053 static int pci_save_pcix_state(struct pci_dev *dev)
1056 struct pci_cap_saved_state *save_state;
1058 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1062 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1064 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1068 pci_read_config_word(dev, pos + PCI_X_CMD,
1069 (u16 *)save_state->cap.data);
1074 static void pci_restore_pcix_state(struct pci_dev *dev)
1077 struct pci_cap_saved_state *save_state;
1080 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1081 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1082 if (!save_state || !pos)
1084 cap = (u16 *)&save_state->cap.data[0];
1086 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1091 * pci_save_state - save the PCI configuration space of a device before suspending
1092 * @dev: - PCI device that we're dealing with
1094 int pci_save_state(struct pci_dev *dev)
1097 /* XXX: 100% dword access ok here? */
1098 for (i = 0; i < 16; i++)
1099 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1100 dev->state_saved = true;
1102 i = pci_save_pcie_state(dev);
1106 i = pci_save_pcix_state(dev);
1110 return pci_save_vc_state(dev);
1112 EXPORT_SYMBOL(pci_save_state);
1114 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1115 u32 saved_val, int retry, bool force)
1119 pci_read_config_dword(pdev, offset, &val);
1120 if (!force && val == saved_val)
1124 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1125 offset, val, saved_val);
1126 pci_write_config_dword(pdev, offset, saved_val);
1130 pci_read_config_dword(pdev, offset, &val);
1131 if (val == saved_val)
1138 static void pci_restore_config_space_range(struct pci_dev *pdev,
1139 int start, int end, int retry,
1144 for (index = end; index >= start; index--)
1145 pci_restore_config_dword(pdev, 4 * index,
1146 pdev->saved_config_space[index],
1150 static void pci_restore_config_space(struct pci_dev *pdev)
1152 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1153 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1154 /* Restore BARs before the command register. */
1155 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1156 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1157 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1158 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1161 * Force rewriting of prefetch registers to avoid S3 resume
1162 * issues on Intel PCI bridges that occur when these
1163 * registers are not explicitly written.
1165 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1166 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1168 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1173 * pci_restore_state - Restore the saved state of a PCI device
1174 * @dev: - PCI device that we're dealing with
1176 void pci_restore_state(struct pci_dev *dev)
1178 if (!dev->state_saved)
1181 /* PCI Express register must be restored first */
1182 pci_restore_pcie_state(dev);
1183 pci_restore_ats_state(dev);
1184 pci_restore_vc_state(dev);
1186 pci_cleanup_aer_error_status_regs(dev);
1188 pci_restore_config_space(dev);
1190 pci_restore_pcix_state(dev);
1191 pci_restore_msi_state(dev);
1193 /* Restore ACS and IOV configuration state */
1194 pci_enable_acs(dev);
1195 pci_restore_iov_state(dev);
1197 dev->state_saved = false;
1199 EXPORT_SYMBOL(pci_restore_state);
1201 struct pci_saved_state {
1202 u32 config_space[16];
1203 struct pci_cap_saved_data cap[0];
1207 * pci_store_saved_state - Allocate and return an opaque struct containing
1208 * the device saved state.
1209 * @dev: PCI device that we're dealing with
1211 * Return NULL if no state or error.
1213 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1215 struct pci_saved_state *state;
1216 struct pci_cap_saved_state *tmp;
1217 struct pci_cap_saved_data *cap;
1220 if (!dev->state_saved)
1223 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1225 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1226 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1228 state = kzalloc(size, GFP_KERNEL);
1232 memcpy(state->config_space, dev->saved_config_space,
1233 sizeof(state->config_space));
1236 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1237 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1238 memcpy(cap, &tmp->cap, len);
1239 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1241 /* Empty cap_save terminates list */
1245 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1248 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1249 * @dev: PCI device that we're dealing with
1250 * @state: Saved state returned from pci_store_saved_state()
1252 int pci_load_saved_state(struct pci_dev *dev,
1253 struct pci_saved_state *state)
1255 struct pci_cap_saved_data *cap;
1257 dev->state_saved = false;
1262 memcpy(dev->saved_config_space, state->config_space,
1263 sizeof(state->config_space));
1267 struct pci_cap_saved_state *tmp;
1269 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1270 if (!tmp || tmp->cap.size != cap->size)
1273 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1274 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1275 sizeof(struct pci_cap_saved_data) + cap->size);
1278 dev->state_saved = true;
1281 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1284 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1285 * and free the memory allocated for it.
1286 * @dev: PCI device that we're dealing with
1287 * @state: Pointer to saved state returned from pci_store_saved_state()
1289 int pci_load_and_free_saved_state(struct pci_dev *dev,
1290 struct pci_saved_state **state)
1292 int ret = pci_load_saved_state(dev, *state);
1297 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1299 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1301 return pci_enable_resources(dev, bars);
1304 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1307 struct pci_dev *bridge;
1311 err = pci_set_power_state(dev, PCI_D0);
1312 if (err < 0 && err != -EIO)
1315 bridge = pci_upstream_bridge(dev);
1317 pcie_aspm_powersave_config_link(bridge);
1319 err = pcibios_enable_device(dev, bars);
1322 pci_fixup_device(pci_fixup_enable, dev);
1324 if (dev->msi_enabled || dev->msix_enabled)
1327 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1329 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1330 if (cmd & PCI_COMMAND_INTX_DISABLE)
1331 pci_write_config_word(dev, PCI_COMMAND,
1332 cmd & ~PCI_COMMAND_INTX_DISABLE);
1339 * pci_reenable_device - Resume abandoned device
1340 * @dev: PCI device to be resumed
1342 * Note this function is a backend of pci_default_resume and is not supposed
1343 * to be called by normal code, write proper resume handler and use it instead.
1345 int pci_reenable_device(struct pci_dev *dev)
1347 if (pci_is_enabled(dev))
1348 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1351 EXPORT_SYMBOL(pci_reenable_device);
1353 static void pci_enable_bridge(struct pci_dev *dev)
1355 struct pci_dev *bridge;
1358 bridge = pci_upstream_bridge(dev);
1360 pci_enable_bridge(bridge);
1362 if (pci_is_enabled(dev)) {
1363 if (!dev->is_busmaster)
1364 pci_set_master(dev);
1368 retval = pci_enable_device(dev);
1370 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1372 pci_set_master(dev);
1375 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1377 struct pci_dev *bridge;
1382 * Power state could be unknown at this point, either due to a fresh
1383 * boot or a device removal call. So get the current power state
1384 * so that things like MSI message writing will behave as expected
1385 * (e.g. if the device really is in D0 at enable time).
1387 pci_update_current_state(dev, dev->current_state);
1389 if (atomic_inc_return(&dev->enable_cnt) > 1)
1390 return 0; /* already enabled */
1392 bridge = pci_upstream_bridge(dev);
1394 pci_enable_bridge(bridge);
1396 /* only skip sriov related */
1397 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1398 if (dev->resource[i].flags & flags)
1400 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1401 if (dev->resource[i].flags & flags)
1404 err = do_pci_enable_device(dev, bars);
1406 atomic_dec(&dev->enable_cnt);
1411 * pci_enable_device_io - Initialize a device for use with IO space
1412 * @dev: PCI device to be initialized
1414 * Initialize device before it's used by a driver. Ask low-level code
1415 * to enable I/O resources. Wake up the device if it was suspended.
1416 * Beware, this function can fail.
1418 int pci_enable_device_io(struct pci_dev *dev)
1420 return pci_enable_device_flags(dev, IORESOURCE_IO);
1422 EXPORT_SYMBOL(pci_enable_device_io);
1425 * pci_enable_device_mem - Initialize a device for use with Memory space
1426 * @dev: PCI device to be initialized
1428 * Initialize device before it's used by a driver. Ask low-level code
1429 * to enable Memory resources. Wake up the device if it was suspended.
1430 * Beware, this function can fail.
1432 int pci_enable_device_mem(struct pci_dev *dev)
1434 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1436 EXPORT_SYMBOL(pci_enable_device_mem);
1439 * pci_enable_device - Initialize device before it's used by a driver.
1440 * @dev: PCI device to be initialized
1442 * Initialize device before it's used by a driver. Ask low-level code
1443 * to enable I/O and memory. Wake up the device if it was suspended.
1444 * Beware, this function can fail.
1446 * Note we don't actually enable the device many times if we call
1447 * this function repeatedly (we just increment the count).
1449 int pci_enable_device(struct pci_dev *dev)
1451 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1453 EXPORT_SYMBOL(pci_enable_device);
1456 * Managed PCI resources. This manages device on/off, intx/msi/msix
1457 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1458 * there's no need to track it separately. pci_devres is initialized
1459 * when a device is enabled using managed PCI device enable interface.
1462 unsigned int enabled:1;
1463 unsigned int pinned:1;
1464 unsigned int orig_intx:1;
1465 unsigned int restore_intx:1;
1469 static void pcim_release(struct device *gendev, void *res)
1471 struct pci_dev *dev = to_pci_dev(gendev);
1472 struct pci_devres *this = res;
1475 if (dev->msi_enabled)
1476 pci_disable_msi(dev);
1477 if (dev->msix_enabled)
1478 pci_disable_msix(dev);
1480 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1481 if (this->region_mask & (1 << i))
1482 pci_release_region(dev, i);
1484 if (this->restore_intx)
1485 pci_intx(dev, this->orig_intx);
1487 if (this->enabled && !this->pinned)
1488 pci_disable_device(dev);
1491 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1493 struct pci_devres *dr, *new_dr;
1495 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1499 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1502 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1505 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1507 if (pci_is_managed(pdev))
1508 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1513 * pcim_enable_device - Managed pci_enable_device()
1514 * @pdev: PCI device to be initialized
1516 * Managed pci_enable_device().
1518 int pcim_enable_device(struct pci_dev *pdev)
1520 struct pci_devres *dr;
1523 dr = get_pci_dr(pdev);
1529 rc = pci_enable_device(pdev);
1531 pdev->is_managed = 1;
1536 EXPORT_SYMBOL(pcim_enable_device);
1539 * pcim_pin_device - Pin managed PCI device
1540 * @pdev: PCI device to pin
1542 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1543 * driver detach. @pdev must have been enabled with
1544 * pcim_enable_device().
1546 void pcim_pin_device(struct pci_dev *pdev)
1548 struct pci_devres *dr;
1550 dr = find_pci_dr(pdev);
1551 WARN_ON(!dr || !dr->enabled);
1555 EXPORT_SYMBOL(pcim_pin_device);
1558 * pcibios_add_device - provide arch specific hooks when adding device dev
1559 * @dev: the PCI device being added
1561 * Permits the platform to provide architecture specific functionality when
1562 * devices are added. This is the default implementation. Architecture
1563 * implementations can override this.
1565 int __weak pcibios_add_device(struct pci_dev *dev)
1571 * pcibios_release_device - provide arch specific hooks when releasing device dev
1572 * @dev: the PCI device being released
1574 * Permits the platform to provide architecture specific functionality when
1575 * devices are released. This is the default implementation. Architecture
1576 * implementations can override this.
1578 void __weak pcibios_release_device(struct pci_dev *dev) {}
1581 * pcibios_disable_device - disable arch specific PCI resources for device dev
1582 * @dev: the PCI device to disable
1584 * Disables architecture specific PCI resources for the device. This
1585 * is the default implementation. Architecture implementations can
1588 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1591 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1592 * @irq: ISA IRQ to penalize
1593 * @active: IRQ active or not
1595 * Permits the platform to provide architecture-specific functionality when
1596 * penalizing ISA IRQs. This is the default implementation. Architecture
1597 * implementations can override this.
1599 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1601 static void do_pci_disable_device(struct pci_dev *dev)
1605 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1606 if (pci_command & PCI_COMMAND_MASTER) {
1607 pci_command &= ~PCI_COMMAND_MASTER;
1608 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1611 pcibios_disable_device(dev);
1615 * pci_disable_enabled_device - Disable device without updating enable_cnt
1616 * @dev: PCI device to disable
1618 * NOTE: This function is a backend of PCI power management routines and is
1619 * not supposed to be called drivers.
1621 void pci_disable_enabled_device(struct pci_dev *dev)
1623 if (pci_is_enabled(dev))
1624 do_pci_disable_device(dev);
1628 * pci_disable_device - Disable PCI device after use
1629 * @dev: PCI device to be disabled
1631 * Signal to the system that the PCI device is not in use by the system
1632 * anymore. This only involves disabling PCI bus-mastering, if active.
1634 * Note we don't actually disable the device until all callers of
1635 * pci_enable_device() have called pci_disable_device().
1637 void pci_disable_device(struct pci_dev *dev)
1639 struct pci_devres *dr;
1641 dr = find_pci_dr(dev);
1645 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1646 "disabling already-disabled device");
1648 if (atomic_dec_return(&dev->enable_cnt) != 0)
1651 do_pci_disable_device(dev);
1653 dev->is_busmaster = 0;
1655 EXPORT_SYMBOL(pci_disable_device);
1658 * pcibios_set_pcie_reset_state - set reset state for device dev
1659 * @dev: the PCIe device reset
1660 * @state: Reset state to enter into
1663 * Sets the PCIe reset state for the device. This is the default
1664 * implementation. Architecture implementations can override this.
1666 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1667 enum pcie_reset_state state)
1673 * pci_set_pcie_reset_state - set reset state for device dev
1674 * @dev: the PCIe device reset
1675 * @state: Reset state to enter into
1678 * Sets the PCI reset state for the device.
1680 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1682 return pcibios_set_pcie_reset_state(dev, state);
1684 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1687 * pci_check_pme_status - Check if given device has generated PME.
1688 * @dev: Device to check.
1690 * Check the PME status of the device and if set, clear it and clear PME enable
1691 * (if set). Return 'true' if PME status and PME enable were both set or
1692 * 'false' otherwise.
1694 bool pci_check_pme_status(struct pci_dev *dev)
1703 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1704 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1705 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1708 /* Clear PME status. */
1709 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1710 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1711 /* Disable PME to avoid interrupt flood. */
1712 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1716 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1722 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1723 * @dev: Device to handle.
1724 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1726 * Check if @dev has generated PME and queue a resume request for it in that
1729 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1731 if (pme_poll_reset && dev->pme_poll)
1732 dev->pme_poll = false;
1734 if (pci_check_pme_status(dev)) {
1735 pci_wakeup_event(dev);
1736 pm_request_resume(&dev->dev);
1742 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1743 * @bus: Top bus of the subtree to walk.
1745 void pci_pme_wakeup_bus(struct pci_bus *bus)
1748 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1753 * pci_pme_capable - check the capability of PCI device to generate PME#
1754 * @dev: PCI device to handle.
1755 * @state: PCI state from which device will issue PME#.
1757 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1762 return !!(dev->pme_support & (1 << state));
1764 EXPORT_SYMBOL(pci_pme_capable);
1766 static void pci_pme_list_scan(struct work_struct *work)
1768 struct pci_pme_device *pme_dev, *n;
1770 mutex_lock(&pci_pme_list_mutex);
1771 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1772 if (pme_dev->dev->pme_poll) {
1773 struct pci_dev *bridge;
1775 bridge = pme_dev->dev->bus->self;
1777 * If bridge is in low power state, the
1778 * configuration space of subordinate devices
1779 * may be not accessible
1781 if (bridge && bridge->current_state != PCI_D0)
1784 * If the device is in D3cold it should not be
1787 if (pme_dev->dev->current_state == PCI_D3cold)
1790 pci_pme_wakeup(pme_dev->dev, NULL);
1792 list_del(&pme_dev->list);
1796 if (!list_empty(&pci_pme_list))
1797 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1798 msecs_to_jiffies(PME_TIMEOUT));
1799 mutex_unlock(&pci_pme_list_mutex);
1802 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1806 if (!dev->pme_support)
1809 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1810 /* Clear PME_Status by writing 1 to it and enable PME# */
1811 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1813 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1815 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1819 * pci_pme_active - enable or disable PCI device's PME# function
1820 * @dev: PCI device to handle.
1821 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1823 * The caller must verify that the device is capable of generating PME# before
1824 * calling this function with @enable equal to 'true'.
1826 void pci_pme_active(struct pci_dev *dev, bool enable)
1828 __pci_pme_active(dev, enable);
1831 * PCI (as opposed to PCIe) PME requires that the device have
1832 * its PME# line hooked up correctly. Not all hardware vendors
1833 * do this, so the PME never gets delivered and the device
1834 * remains asleep. The easiest way around this is to
1835 * periodically walk the list of suspended devices and check
1836 * whether any have their PME flag set. The assumption is that
1837 * we'll wake up often enough anyway that this won't be a huge
1838 * hit, and the power savings from the devices will still be a
1841 * Although PCIe uses in-band PME message instead of PME# line
1842 * to report PME, PME does not work for some PCIe devices in
1843 * reality. For example, there are devices that set their PME
1844 * status bits, but don't really bother to send a PME message;
1845 * there are PCI Express Root Ports that don't bother to
1846 * trigger interrupts when they receive PME messages from the
1847 * devices below. So PME poll is used for PCIe devices too.
1850 if (dev->pme_poll) {
1851 struct pci_pme_device *pme_dev;
1853 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1856 dev_warn(&dev->dev, "can't enable PME#\n");
1860 mutex_lock(&pci_pme_list_mutex);
1861 list_add(&pme_dev->list, &pci_pme_list);
1862 if (list_is_singular(&pci_pme_list))
1863 queue_delayed_work(system_freezable_wq,
1865 msecs_to_jiffies(PME_TIMEOUT));
1866 mutex_unlock(&pci_pme_list_mutex);
1868 mutex_lock(&pci_pme_list_mutex);
1869 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1870 if (pme_dev->dev == dev) {
1871 list_del(&pme_dev->list);
1876 mutex_unlock(&pci_pme_list_mutex);
1880 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1882 EXPORT_SYMBOL(pci_pme_active);
1885 * __pci_enable_wake - enable PCI device as wakeup event source
1886 * @dev: PCI device affected
1887 * @state: PCI state from which device will issue wakeup events
1888 * @runtime: True if the events are to be generated at run time
1889 * @enable: True to enable event generation; false to disable
1891 * This enables the device as a wakeup event source, or disables it.
1892 * When such events involves platform-specific hooks, those hooks are
1893 * called automatically by this routine.
1895 * Devices with legacy power management (no standard PCI PM capabilities)
1896 * always require such platform hooks.
1899 * 0 is returned on success
1900 * -EINVAL is returned if device is not supposed to wake up the system
1901 * Error code depending on the platform is returned if both the platform and
1902 * the native mechanism fail to enable the generation of wake-up events
1904 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1905 bool runtime, bool enable)
1909 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1912 /* Don't do the same thing twice in a row for one device. */
1913 if (!!enable == !!dev->wakeup_prepared)
1917 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1918 * Anderson we should be doing PME# wake enable followed by ACPI wake
1919 * enable. To disable wake-up we call the platform first, for symmetry.
1926 * Enable PME signaling if the device can signal PME from
1927 * D3cold regardless of whether or not it can signal PME from
1928 * the current target state, because that will allow it to
1929 * signal PME when the hierarchy above it goes into D3cold and
1930 * the device itself ends up in D3cold as a result of that.
1932 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
1933 pci_pme_active(dev, true);
1936 error = runtime ? platform_pci_run_wake(dev, true) :
1937 platform_pci_sleep_wake(dev, true);
1941 dev->wakeup_prepared = true;
1944 platform_pci_run_wake(dev, false);
1946 platform_pci_sleep_wake(dev, false);
1947 pci_pme_active(dev, false);
1948 dev->wakeup_prepared = false;
1953 EXPORT_SYMBOL(__pci_enable_wake);
1956 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1957 * @dev: PCI device to prepare
1958 * @enable: True to enable wake-up event generation; false to disable
1960 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1961 * and this function allows them to set that up cleanly - pci_enable_wake()
1962 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1963 * ordering constraints.
1965 * This function only returns error code if the device is not capable of
1966 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1967 * enable wake-up power for it.
1969 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1971 return pci_pme_capable(dev, PCI_D3cold) ?
1972 pci_enable_wake(dev, PCI_D3cold, enable) :
1973 pci_enable_wake(dev, PCI_D3hot, enable);
1975 EXPORT_SYMBOL(pci_wake_from_d3);
1978 * pci_target_state - find an appropriate low power state for a given PCI dev
1981 * Use underlying platform code to find a supported low power state for @dev.
1982 * If the platform can't manage @dev, return the deepest state from which it
1983 * can generate wake events, based on any available PME info.
1985 static pci_power_t pci_target_state(struct pci_dev *dev)
1987 pci_power_t target_state = PCI_D3hot;
1989 if (platform_pci_power_manageable(dev)) {
1991 * Call the platform to choose the target state of the device
1992 * and enable wake-up from this state if supported.
1994 pci_power_t state = platform_pci_choose_state(dev);
1997 case PCI_POWER_ERROR:
2002 if (pci_no_d1d2(dev))
2005 target_state = state;
2008 return target_state;
2012 target_state = PCI_D0;
2015 * If the device is in D3cold even though it's not power-manageable by
2016 * the platform, it may have been powered down by non-standard means.
2017 * Best to let it slumber.
2019 if (dev->current_state == PCI_D3cold)
2020 target_state = PCI_D3cold;
2022 if (device_may_wakeup(&dev->dev)) {
2024 * Find the deepest state from which the device can generate
2025 * wake-up events, make it the target state and enable device
2028 if (dev->pme_support) {
2030 && !(dev->pme_support & (1 << target_state)))
2035 return target_state;
2039 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2040 * @dev: Device to handle.
2042 * Choose the power state appropriate for the device depending on whether
2043 * it can wake up the system and/or is power manageable by the platform
2044 * (PCI_D3hot is the default) and put the device into that state.
2046 int pci_prepare_to_sleep(struct pci_dev *dev)
2048 pci_power_t target_state = pci_target_state(dev);
2051 if (target_state == PCI_POWER_ERROR)
2054 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
2056 error = pci_set_power_state(dev, target_state);
2059 pci_enable_wake(dev, target_state, false);
2063 EXPORT_SYMBOL(pci_prepare_to_sleep);
2066 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2067 * @dev: Device to handle.
2069 * Disable device's system wake-up capability and put it into D0.
2071 int pci_back_from_sleep(struct pci_dev *dev)
2073 pci_enable_wake(dev, PCI_D0, false);
2074 return pci_set_power_state(dev, PCI_D0);
2076 EXPORT_SYMBOL(pci_back_from_sleep);
2079 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2080 * @dev: PCI device being suspended.
2082 * Prepare @dev to generate wake-up events at run time and put it into a low
2085 int pci_finish_runtime_suspend(struct pci_dev *dev)
2087 pci_power_t target_state = pci_target_state(dev);
2090 if (target_state == PCI_POWER_ERROR)
2093 dev->runtime_d3cold = target_state == PCI_D3cold;
2095 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2097 error = pci_set_power_state(dev, target_state);
2100 __pci_enable_wake(dev, target_state, true, false);
2101 dev->runtime_d3cold = false;
2108 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2109 * @dev: Device to check.
2111 * Return true if the device itself is capable of generating wake-up events
2112 * (through the platform or using the native PCIe PME) or if the device supports
2113 * PME and one of its upstream bridges can generate wake-up events.
2115 bool pci_dev_run_wake(struct pci_dev *dev)
2117 struct pci_bus *bus = dev->bus;
2119 if (device_run_wake(&dev->dev))
2122 if (!dev->pme_support)
2125 /* PME-capable in principle, but not from the intended sleep state */
2126 if (!pci_pme_capable(dev, pci_target_state(dev)))
2129 while (bus->parent) {
2130 struct pci_dev *bridge = bus->self;
2132 if (device_run_wake(&bridge->dev))
2138 /* We have reached the root bus. */
2140 return device_run_wake(bus->bridge);
2144 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2147 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2148 * @pci_dev: Device to check.
2150 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2151 * reconfigured due to wakeup settings difference between system and runtime
2152 * suspend and the current power state of it is suitable for the upcoming
2153 * (system) transition.
2155 * If the device is not configured for system wakeup, disable PME for it before
2156 * returning 'true' to prevent it from waking up the system unnecessarily.
2158 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2160 struct device *dev = &pci_dev->dev;
2162 if (!pm_runtime_suspended(dev)
2163 || pci_target_state(pci_dev) != pci_dev->current_state
2164 || platform_pci_need_resume(pci_dev)
2165 || (pci_dev->dev_flags & PCI_DEV_FLAGS_NEEDS_RESUME))
2169 * At this point the device is good to go unless it's been configured
2170 * to generate PME at the runtime suspend time, but it is not supposed
2171 * to wake up the system. In that case, simply disable PME for it
2172 * (it will have to be re-enabled on exit from system resume).
2174 * If the device's power state is D3cold and the platform check above
2175 * hasn't triggered, the device's configuration is suitable and we don't
2176 * need to manipulate it at all.
2178 spin_lock_irq(&dev->power.lock);
2180 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2181 !device_may_wakeup(dev))
2182 __pci_pme_active(pci_dev, false);
2184 spin_unlock_irq(&dev->power.lock);
2189 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2190 * @pci_dev: Device to handle.
2192 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2193 * it might have been disabled during the prepare phase of system suspend if
2194 * the device was not configured for system wakeup.
2196 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2198 struct device *dev = &pci_dev->dev;
2200 if (!pci_dev_run_wake(pci_dev))
2203 spin_lock_irq(&dev->power.lock);
2205 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2206 __pci_pme_active(pci_dev, true);
2208 spin_unlock_irq(&dev->power.lock);
2211 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2213 struct device *dev = &pdev->dev;
2214 struct device *parent = dev->parent;
2217 pm_runtime_get_sync(parent);
2218 pm_runtime_get_noresume(dev);
2220 * pdev->current_state is set to PCI_D3cold during suspending,
2221 * so wait until suspending completes
2223 pm_runtime_barrier(dev);
2225 * Only need to resume devices in D3cold, because config
2226 * registers are still accessible for devices suspended but
2229 if (pdev->current_state == PCI_D3cold)
2230 pm_runtime_resume(dev);
2233 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2235 struct device *dev = &pdev->dev;
2236 struct device *parent = dev->parent;
2238 pm_runtime_put(dev);
2240 pm_runtime_put_sync(parent);
2244 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2245 * @bridge: Bridge to check
2247 * This function checks if it is possible to move the bridge to D3.
2248 * Currently we only allow D3 for recent enough PCIe ports.
2250 static bool pci_bridge_d3_possible(struct pci_dev *bridge)
2254 if (!pci_is_pcie(bridge))
2257 switch (pci_pcie_type(bridge)) {
2258 case PCI_EXP_TYPE_ROOT_PORT:
2259 case PCI_EXP_TYPE_UPSTREAM:
2260 case PCI_EXP_TYPE_DOWNSTREAM:
2261 if (pci_bridge_d3_disable)
2263 if (pci_bridge_d3_force)
2267 * It should be safe to put PCIe ports from 2015 or newer
2270 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2280 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2282 bool *d3cold_ok = data;
2286 * The device needs to be allowed to go D3cold and if it is wake
2287 * capable to do so from D3cold.
2289 no_d3cold = dev->no_d3cold || !dev->d3cold_allowed ||
2290 (device_may_wakeup(&dev->dev) && !pci_pme_capable(dev, PCI_D3cold)) ||
2291 !pci_power_manageable(dev);
2293 *d3cold_ok = !no_d3cold;
2299 * pci_bridge_d3_update - Update bridge D3 capabilities
2300 * @dev: PCI device which is changed
2301 * @remove: Is the device being removed
2303 * Update upstream bridge PM capabilities accordingly depending on if the
2304 * device PM configuration was changed or the device is being removed. The
2305 * change is also propagated upstream.
2307 static void pci_bridge_d3_update(struct pci_dev *dev, bool remove)
2309 struct pci_dev *bridge;
2310 bool d3cold_ok = true;
2312 bridge = pci_upstream_bridge(dev);
2313 if (!bridge || !pci_bridge_d3_possible(bridge))
2316 pci_dev_get(bridge);
2318 * If the device is removed we do not care about its D3cold
2322 pci_dev_check_d3cold(dev, &d3cold_ok);
2326 * We need to go through all children to find out if all of
2327 * them can still go to D3cold.
2329 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2333 if (bridge->bridge_d3 != d3cold_ok) {
2334 bridge->bridge_d3 = d3cold_ok;
2335 /* Propagate change to upstream bridges */
2336 pci_bridge_d3_update(bridge, false);
2339 pci_dev_put(bridge);
2343 * pci_bridge_d3_device_changed - Update bridge D3 capabilities on change
2344 * @dev: PCI device that was changed
2346 * If a device is added or its PM configuration, such as is it allowed to
2347 * enter D3cold, is changed this function updates upstream bridge PM
2348 * capabilities accordingly.
2350 void pci_bridge_d3_device_changed(struct pci_dev *dev)
2352 pci_bridge_d3_update(dev, false);
2356 * pci_bridge_d3_device_removed - Update bridge D3 capabilities on remove
2357 * @dev: PCI device being removed
2359 * Function updates upstream bridge PM capabilities based on other devices
2360 * still left on the bus.
2362 void pci_bridge_d3_device_removed(struct pci_dev *dev)
2364 pci_bridge_d3_update(dev, true);
2368 * pci_d3cold_enable - Enable D3cold for device
2369 * @dev: PCI device to handle
2371 * This function can be used in drivers to enable D3cold from the device
2372 * they handle. It also updates upstream PCI bridge PM capabilities
2375 void pci_d3cold_enable(struct pci_dev *dev)
2377 if (dev->no_d3cold) {
2378 dev->no_d3cold = false;
2379 pci_bridge_d3_device_changed(dev);
2382 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2385 * pci_d3cold_disable - Disable D3cold for device
2386 * @dev: PCI device to handle
2388 * This function can be used in drivers to disable D3cold from the device
2389 * they handle. It also updates upstream PCI bridge PM capabilities
2392 void pci_d3cold_disable(struct pci_dev *dev)
2394 if (!dev->no_d3cold) {
2395 dev->no_d3cold = true;
2396 pci_bridge_d3_device_changed(dev);
2399 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2402 * pci_pm_init - Initialize PM functions of given PCI device
2403 * @dev: PCI device to handle.
2405 void pci_pm_init(struct pci_dev *dev)
2410 pm_runtime_forbid(&dev->dev);
2411 pm_runtime_set_active(&dev->dev);
2412 pm_runtime_enable(&dev->dev);
2413 device_enable_async_suspend(&dev->dev);
2414 dev->wakeup_prepared = false;
2417 dev->pme_support = 0;
2419 /* find PCI PM capability in list */
2420 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2423 /* Check device's ability to generate PME# */
2424 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2426 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2427 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2428 pmc & PCI_PM_CAP_VER_MASK);
2433 dev->d3_delay = PCI_PM_D3_WAIT;
2434 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2435 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2436 dev->d3cold_allowed = true;
2438 dev->d1_support = false;
2439 dev->d2_support = false;
2440 if (!pci_no_d1d2(dev)) {
2441 if (pmc & PCI_PM_CAP_D1)
2442 dev->d1_support = true;
2443 if (pmc & PCI_PM_CAP_D2)
2444 dev->d2_support = true;
2446 if (dev->d1_support || dev->d2_support)
2447 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2448 dev->d1_support ? " D1" : "",
2449 dev->d2_support ? " D2" : "");
2452 pmc &= PCI_PM_CAP_PME_MASK;
2454 dev_printk(KERN_DEBUG, &dev->dev,
2455 "PME# supported from%s%s%s%s%s\n",
2456 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2457 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2458 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2459 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2460 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2461 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2462 dev->pme_poll = true;
2464 * Make device's PM flags reflect the wake-up capability, but
2465 * let the user space enable it to wake up the system as needed.
2467 device_set_wakeup_capable(&dev->dev, true);
2468 /* Disable the PME# generation functionality */
2469 pci_pme_active(dev, false);
2473 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2475 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2479 case PCI_EA_P_VF_MEM:
2480 flags |= IORESOURCE_MEM;
2482 case PCI_EA_P_MEM_PREFETCH:
2483 case PCI_EA_P_VF_MEM_PREFETCH:
2484 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2487 flags |= IORESOURCE_IO;
2496 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2499 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2500 return &dev->resource[bei];
2501 #ifdef CONFIG_PCI_IOV
2502 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2503 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2504 return &dev->resource[PCI_IOV_RESOURCES +
2505 bei - PCI_EA_BEI_VF_BAR0];
2507 else if (bei == PCI_EA_BEI_ROM)
2508 return &dev->resource[PCI_ROM_RESOURCE];
2513 /* Read an Enhanced Allocation (EA) entry */
2514 static int pci_ea_read(struct pci_dev *dev, int offset)
2516 struct resource *res;
2517 int ent_size, ent_offset = offset;
2518 resource_size_t start, end;
2519 unsigned long flags;
2520 u32 dw0, bei, base, max_offset;
2522 bool support_64 = (sizeof(resource_size_t) >= 8);
2524 pci_read_config_dword(dev, ent_offset, &dw0);
2527 /* Entry size field indicates DWORDs after 1st */
2528 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2530 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2533 bei = (dw0 & PCI_EA_BEI) >> 4;
2534 prop = (dw0 & PCI_EA_PP) >> 8;
2537 * If the Property is in the reserved range, try the Secondary
2540 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2541 prop = (dw0 & PCI_EA_SP) >> 16;
2542 if (prop > PCI_EA_P_BRIDGE_IO)
2545 res = pci_ea_get_resource(dev, bei, prop);
2547 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2551 flags = pci_ea_flags(dev, prop);
2553 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2558 pci_read_config_dword(dev, ent_offset, &base);
2559 start = (base & PCI_EA_FIELD_MASK);
2562 /* Read MaxOffset */
2563 pci_read_config_dword(dev, ent_offset, &max_offset);
2566 /* Read Base MSBs (if 64-bit entry) */
2567 if (base & PCI_EA_IS_64) {
2570 pci_read_config_dword(dev, ent_offset, &base_upper);
2573 flags |= IORESOURCE_MEM_64;
2575 /* entry starts above 32-bit boundary, can't use */
2576 if (!support_64 && base_upper)
2580 start |= ((u64)base_upper << 32);
2583 end = start + (max_offset | 0x03);
2585 /* Read MaxOffset MSBs (if 64-bit entry) */
2586 if (max_offset & PCI_EA_IS_64) {
2587 u32 max_offset_upper;
2589 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2592 flags |= IORESOURCE_MEM_64;
2594 /* entry too big, can't use */
2595 if (!support_64 && max_offset_upper)
2599 end += ((u64)max_offset_upper << 32);
2603 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2607 if (ent_size != ent_offset - offset) {
2609 "EA Entry Size (%d) does not match length read (%d)\n",
2610 ent_size, ent_offset - offset);
2614 res->name = pci_name(dev);
2619 if (bei <= PCI_EA_BEI_BAR5)
2620 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2622 else if (bei == PCI_EA_BEI_ROM)
2623 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2625 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2626 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2627 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2629 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2633 return offset + ent_size;
2636 /* Enhanced Allocation Initialization */
2637 void pci_ea_init(struct pci_dev *dev)
2644 /* find PCI EA capability in list */
2645 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2649 /* determine the number of entries */
2650 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2652 num_ent &= PCI_EA_NUM_ENT_MASK;
2654 offset = ea + PCI_EA_FIRST_ENT;
2656 /* Skip DWORD 2 for type 1 functions */
2657 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2660 /* parse each EA entry */
2661 for (i = 0; i < num_ent; ++i)
2662 offset = pci_ea_read(dev, offset);
2665 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2666 struct pci_cap_saved_state *new_cap)
2668 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2672 * _pci_add_cap_save_buffer - allocate buffer for saving given
2673 * capability registers
2674 * @dev: the PCI device
2675 * @cap: the capability to allocate the buffer for
2676 * @extended: Standard or Extended capability ID
2677 * @size: requested size of the buffer
2679 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2680 bool extended, unsigned int size)
2683 struct pci_cap_saved_state *save_state;
2686 pos = pci_find_ext_capability(dev, cap);
2688 pos = pci_find_capability(dev, cap);
2693 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2697 save_state->cap.cap_nr = cap;
2698 save_state->cap.cap_extended = extended;
2699 save_state->cap.size = size;
2700 pci_add_saved_cap(dev, save_state);
2705 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2707 return _pci_add_cap_save_buffer(dev, cap, false, size);
2710 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2712 return _pci_add_cap_save_buffer(dev, cap, true, size);
2716 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2717 * @dev: the PCI device
2719 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2723 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2724 PCI_EXP_SAVE_REGS * sizeof(u16));
2727 "unable to preallocate PCI Express save buffer\n");
2729 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2732 "unable to preallocate PCI-X save buffer\n");
2734 pci_allocate_vc_save_buffers(dev);
2737 void pci_free_cap_save_buffers(struct pci_dev *dev)
2739 struct pci_cap_saved_state *tmp;
2740 struct hlist_node *n;
2742 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2747 * pci_configure_ari - enable or disable ARI forwarding
2748 * @dev: the PCI device
2750 * If @dev and its upstream bridge both support ARI, enable ARI in the
2751 * bridge. Otherwise, disable ARI in the bridge.
2753 void pci_configure_ari(struct pci_dev *dev)
2756 struct pci_dev *bridge;
2758 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2761 bridge = dev->bus->self;
2765 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2766 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2769 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2770 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2771 PCI_EXP_DEVCTL2_ARI);
2772 bridge->ari_enabled = 1;
2774 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2775 PCI_EXP_DEVCTL2_ARI);
2776 bridge->ari_enabled = 0;
2780 static int pci_acs_enable;
2783 * pci_request_acs - ask for ACS to be enabled if supported
2785 void pci_request_acs(void)
2791 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2792 * @dev: the PCI device
2794 static void pci_std_enable_acs(struct pci_dev *dev)
2800 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2804 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2805 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2807 /* Source Validation */
2808 ctrl |= (cap & PCI_ACS_SV);
2810 /* P2P Request Redirect */
2811 ctrl |= (cap & PCI_ACS_RR);
2813 /* P2P Completion Redirect */
2814 ctrl |= (cap & PCI_ACS_CR);
2816 /* Upstream Forwarding */
2817 ctrl |= (cap & PCI_ACS_UF);
2819 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2823 * pci_enable_acs - enable ACS if hardware support it
2824 * @dev: the PCI device
2826 void pci_enable_acs(struct pci_dev *dev)
2828 if (!pci_acs_enable)
2831 if (!pci_dev_specific_enable_acs(dev))
2834 pci_std_enable_acs(dev);
2837 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2842 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2847 * Except for egress control, capabilities are either required
2848 * or only required if controllable. Features missing from the
2849 * capability field can therefore be assumed as hard-wired enabled.
2851 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2852 acs_flags &= (cap | PCI_ACS_EC);
2854 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2855 return (ctrl & acs_flags) == acs_flags;
2859 * pci_acs_enabled - test ACS against required flags for a given device
2860 * @pdev: device to test
2861 * @acs_flags: required PCI ACS flags
2863 * Return true if the device supports the provided flags. Automatically
2864 * filters out flags that are not implemented on multifunction devices.
2866 * Note that this interface checks the effective ACS capabilities of the
2867 * device rather than the actual capabilities. For instance, most single
2868 * function endpoints are not required to support ACS because they have no
2869 * opportunity for peer-to-peer access. We therefore return 'true'
2870 * regardless of whether the device exposes an ACS capability. This makes
2871 * it much easier for callers of this function to ignore the actual type
2872 * or topology of the device when testing ACS support.
2874 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2878 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2883 * Conventional PCI and PCI-X devices never support ACS, either
2884 * effectively or actually. The shared bus topology implies that
2885 * any device on the bus can receive or snoop DMA.
2887 if (!pci_is_pcie(pdev))
2890 switch (pci_pcie_type(pdev)) {
2892 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2893 * but since their primary interface is PCI/X, we conservatively
2894 * handle them as we would a non-PCIe device.
2896 case PCI_EXP_TYPE_PCIE_BRIDGE:
2898 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2899 * applicable... must never implement an ACS Extended Capability...".
2900 * This seems arbitrary, but we take a conservative interpretation
2901 * of this statement.
2903 case PCI_EXP_TYPE_PCI_BRIDGE:
2904 case PCI_EXP_TYPE_RC_EC:
2907 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2908 * implement ACS in order to indicate their peer-to-peer capabilities,
2909 * regardless of whether they are single- or multi-function devices.
2911 case PCI_EXP_TYPE_DOWNSTREAM:
2912 case PCI_EXP_TYPE_ROOT_PORT:
2913 return pci_acs_flags_enabled(pdev, acs_flags);
2915 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2916 * implemented by the remaining PCIe types to indicate peer-to-peer
2917 * capabilities, but only when they are part of a multifunction
2918 * device. The footnote for section 6.12 indicates the specific
2919 * PCIe types included here.
2921 case PCI_EXP_TYPE_ENDPOINT:
2922 case PCI_EXP_TYPE_UPSTREAM:
2923 case PCI_EXP_TYPE_LEG_END:
2924 case PCI_EXP_TYPE_RC_END:
2925 if (!pdev->multifunction)
2928 return pci_acs_flags_enabled(pdev, acs_flags);
2932 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2933 * to single function devices with the exception of downstream ports.
2939 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2940 * @start: starting downstream device
2941 * @end: ending upstream device or NULL to search to the root bus
2942 * @acs_flags: required flags
2944 * Walk up a device tree from start to end testing PCI ACS support. If
2945 * any step along the way does not support the required flags, return false.
2947 bool pci_acs_path_enabled(struct pci_dev *start,
2948 struct pci_dev *end, u16 acs_flags)
2950 struct pci_dev *pdev, *parent = start;
2955 if (!pci_acs_enabled(pdev, acs_flags))
2958 if (pci_is_root_bus(pdev->bus))
2959 return (end == NULL);
2961 parent = pdev->bus->self;
2962 } while (pdev != end);
2968 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2969 * @dev: the PCI device
2970 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2972 * Perform INTx swizzling for a device behind one level of bridge. This is
2973 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2974 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2975 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2976 * the PCI Express Base Specification, Revision 2.1)
2978 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2982 if (pci_ari_enabled(dev->bus))
2985 slot = PCI_SLOT(dev->devfn);
2987 return (((pin - 1) + slot) % 4) + 1;
2990 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2998 while (!pci_is_root_bus(dev->bus)) {
2999 pin = pci_swizzle_interrupt_pin(dev, pin);
3000 dev = dev->bus->self;
3007 * pci_common_swizzle - swizzle INTx all the way to root bridge
3008 * @dev: the PCI device
3009 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3011 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3012 * bridges all the way up to a PCI root bus.
3014 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3018 while (!pci_is_root_bus(dev->bus)) {
3019 pin = pci_swizzle_interrupt_pin(dev, pin);
3020 dev = dev->bus->self;
3023 return PCI_SLOT(dev->devfn);
3025 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3028 * pci_release_region - Release a PCI bar
3029 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3030 * @bar: BAR to release
3032 * Releases the PCI I/O and memory resources previously reserved by a
3033 * successful call to pci_request_region. Call this function only
3034 * after all use of the PCI regions has ceased.
3036 void pci_release_region(struct pci_dev *pdev, int bar)
3038 struct pci_devres *dr;
3040 if (pci_resource_len(pdev, bar) == 0)
3042 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3043 release_region(pci_resource_start(pdev, bar),
3044 pci_resource_len(pdev, bar));
3045 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3046 release_mem_region(pci_resource_start(pdev, bar),
3047 pci_resource_len(pdev, bar));
3049 dr = find_pci_dr(pdev);
3051 dr->region_mask &= ~(1 << bar);
3053 EXPORT_SYMBOL(pci_release_region);
3056 * __pci_request_region - Reserved PCI I/O and memory resource
3057 * @pdev: PCI device whose resources are to be reserved
3058 * @bar: BAR to be reserved
3059 * @res_name: Name to be associated with resource.
3060 * @exclusive: whether the region access is exclusive or not
3062 * Mark the PCI region associated with PCI device @pdev BR @bar as
3063 * being reserved by owner @res_name. Do not access any
3064 * address inside the PCI regions unless this call returns
3067 * If @exclusive is set, then the region is marked so that userspace
3068 * is explicitly not allowed to map the resource via /dev/mem or
3069 * sysfs MMIO access.
3071 * Returns 0 on success, or %EBUSY on error. A warning
3072 * message is also printed on failure.
3074 static int __pci_request_region(struct pci_dev *pdev, int bar,
3075 const char *res_name, int exclusive)
3077 struct pci_devres *dr;
3079 if (pci_resource_len(pdev, bar) == 0)
3082 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3083 if (!request_region(pci_resource_start(pdev, bar),
3084 pci_resource_len(pdev, bar), res_name))
3086 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3087 if (!__request_mem_region(pci_resource_start(pdev, bar),
3088 pci_resource_len(pdev, bar), res_name,
3093 dr = find_pci_dr(pdev);
3095 dr->region_mask |= 1 << bar;
3100 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
3101 &pdev->resource[bar]);
3106 * pci_request_region - Reserve PCI I/O and memory resource
3107 * @pdev: PCI device whose resources are to be reserved
3108 * @bar: BAR to be reserved
3109 * @res_name: Name to be associated with resource
3111 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3112 * being reserved by owner @res_name. Do not access any
3113 * address inside the PCI regions unless this call returns
3116 * Returns 0 on success, or %EBUSY on error. A warning
3117 * message is also printed on failure.
3119 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3121 return __pci_request_region(pdev, bar, res_name, 0);
3123 EXPORT_SYMBOL(pci_request_region);
3126 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3127 * @pdev: PCI device whose resources are to be reserved
3128 * @bar: BAR to be reserved
3129 * @res_name: Name to be associated with resource.
3131 * Mark the PCI region associated with PCI device @pdev BR @bar as
3132 * being reserved by owner @res_name. Do not access any
3133 * address inside the PCI regions unless this call returns
3136 * Returns 0 on success, or %EBUSY on error. A warning
3137 * message is also printed on failure.
3139 * The key difference that _exclusive makes it that userspace is
3140 * explicitly not allowed to map the resource via /dev/mem or
3143 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3144 const char *res_name)
3146 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3148 EXPORT_SYMBOL(pci_request_region_exclusive);
3151 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3152 * @pdev: PCI device whose resources were previously reserved
3153 * @bars: Bitmask of BARs to be released
3155 * Release selected PCI I/O and memory resources previously reserved.
3156 * Call this function only after all use of the PCI regions has ceased.
3158 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3162 for (i = 0; i < 6; i++)
3163 if (bars & (1 << i))
3164 pci_release_region(pdev, i);
3166 EXPORT_SYMBOL(pci_release_selected_regions);
3168 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3169 const char *res_name, int excl)
3173 for (i = 0; i < 6; i++)
3174 if (bars & (1 << i))
3175 if (__pci_request_region(pdev, i, res_name, excl))
3181 if (bars & (1 << i))
3182 pci_release_region(pdev, i);
3189 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3190 * @pdev: PCI device whose resources are to be reserved
3191 * @bars: Bitmask of BARs to be requested
3192 * @res_name: Name to be associated with resource
3194 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3195 const char *res_name)
3197 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3199 EXPORT_SYMBOL(pci_request_selected_regions);
3201 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3202 const char *res_name)
3204 return __pci_request_selected_regions(pdev, bars, res_name,
3205 IORESOURCE_EXCLUSIVE);
3207 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3210 * pci_release_regions - Release reserved PCI I/O and memory resources
3211 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3213 * Releases all PCI I/O and memory resources previously reserved by a
3214 * successful call to pci_request_regions. Call this function only
3215 * after all use of the PCI regions has ceased.
3218 void pci_release_regions(struct pci_dev *pdev)
3220 pci_release_selected_regions(pdev, (1 << 6) - 1);
3222 EXPORT_SYMBOL(pci_release_regions);
3225 * pci_request_regions - Reserved PCI I/O and memory resources
3226 * @pdev: PCI device whose resources are to be reserved
3227 * @res_name: Name to be associated with resource.
3229 * Mark all PCI regions associated with PCI device @pdev as
3230 * being reserved by owner @res_name. Do not access any
3231 * address inside the PCI regions unless this call returns
3234 * Returns 0 on success, or %EBUSY on error. A warning
3235 * message is also printed on failure.
3237 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3239 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3241 EXPORT_SYMBOL(pci_request_regions);
3244 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3245 * @pdev: PCI device whose resources are to be reserved
3246 * @res_name: Name to be associated with resource.
3248 * Mark all PCI regions associated with PCI device @pdev as
3249 * being reserved by owner @res_name. Do not access any
3250 * address inside the PCI regions unless this call returns
3253 * pci_request_regions_exclusive() will mark the region so that
3254 * /dev/mem and the sysfs MMIO access will not be allowed.
3256 * Returns 0 on success, or %EBUSY on error. A warning
3257 * message is also printed on failure.
3259 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3261 return pci_request_selected_regions_exclusive(pdev,
3262 ((1 << 6) - 1), res_name);
3264 EXPORT_SYMBOL(pci_request_regions_exclusive);
3268 struct list_head list;
3270 resource_size_t size;
3273 static LIST_HEAD(io_range_list);
3274 static DEFINE_SPINLOCK(io_range_lock);
3278 * Record the PCI IO range (expressed as CPU physical address + size).
3279 * Return a negative value if an error has occured, zero otherwise
3281 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3286 struct io_range *range;
3287 resource_size_t allocated_size = 0;
3289 /* check if the range hasn't been previously recorded */
3290 spin_lock(&io_range_lock);
3291 list_for_each_entry(range, &io_range_list, list) {
3292 if (addr >= range->start && addr + size <= range->start + size) {
3293 /* range already registered, bail out */
3296 allocated_size += range->size;
3299 /* range not registed yet, check for available space */
3300 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3301 /* if it's too big check if 64K space can be reserved */
3302 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3308 pr_warn("Requested IO range too big, new size set to 64K\n");
3311 /* add the range to the list */
3312 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3318 range->start = addr;
3321 list_add_tail(&range->list, &io_range_list);
3324 spin_unlock(&io_range_lock);
3330 phys_addr_t pci_pio_to_address(unsigned long pio)
3332 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3335 struct io_range *range;
3336 resource_size_t allocated_size = 0;
3338 if (pio > IO_SPACE_LIMIT)
3341 spin_lock(&io_range_lock);
3342 list_for_each_entry(range, &io_range_list, list) {
3343 if (pio >= allocated_size && pio < allocated_size + range->size) {
3344 address = range->start + pio - allocated_size;
3347 allocated_size += range->size;
3349 spin_unlock(&io_range_lock);
3355 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3358 struct io_range *res;
3359 resource_size_t offset = 0;
3360 unsigned long addr = -1;
3362 spin_lock(&io_range_lock);
3363 list_for_each_entry(res, &io_range_list, list) {
3364 if (address >= res->start && address < res->start + res->size) {
3365 addr = address - res->start + offset;
3368 offset += res->size;
3370 spin_unlock(&io_range_lock);
3374 if (address > IO_SPACE_LIMIT)
3375 return (unsigned long)-1;
3377 return (unsigned long) address;
3382 * pci_remap_iospace - Remap the memory mapped I/O space
3383 * @res: Resource describing the I/O space
3384 * @phys_addr: physical address of range to be mapped
3386 * Remap the memory mapped I/O space described by the @res
3387 * and the CPU physical address @phys_addr into virtual address space.
3388 * Only architectures that have memory mapped IO functions defined
3389 * (and the PCI_IOBASE value defined) should call this function.
3391 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3393 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3394 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3396 if (!(res->flags & IORESOURCE_IO))
3399 if (res->end > IO_SPACE_LIMIT)
3402 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3403 pgprot_device(PAGE_KERNEL));
3405 /* this architecture does not have memory mapped I/O space,
3406 so this function should never be called */
3407 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3413 * pci_unmap_iospace - Unmap the memory mapped I/O space
3414 * @res: resource to be unmapped
3416 * Unmap the CPU virtual address @res from virtual address space.
3417 * Only architectures that have memory mapped IO functions defined
3418 * (and the PCI_IOBASE value defined) should call this function.
3420 void pci_unmap_iospace(struct resource *res)
3422 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3423 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3425 unmap_kernel_range(vaddr, resource_size(res));
3429 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
3431 struct resource **res = ptr;
3433 pci_unmap_iospace(*res);
3437 * devm_pci_remap_iospace - Managed pci_remap_iospace()
3438 * @dev: Generic device to remap IO address for
3439 * @res: Resource describing the I/O space
3440 * @phys_addr: physical address of range to be mapped
3442 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
3445 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
3446 phys_addr_t phys_addr)
3448 const struct resource **ptr;
3451 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
3455 error = pci_remap_iospace(res, phys_addr);
3460 devres_add(dev, ptr);
3465 EXPORT_SYMBOL(devm_pci_remap_iospace);
3467 static void __pci_set_master(struct pci_dev *dev, bool enable)
3471 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3473 cmd = old_cmd | PCI_COMMAND_MASTER;
3475 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3476 if (cmd != old_cmd) {
3477 dev_dbg(&dev->dev, "%s bus mastering\n",
3478 enable ? "enabling" : "disabling");
3479 pci_write_config_word(dev, PCI_COMMAND, cmd);
3481 dev->is_busmaster = enable;
3485 * pcibios_setup - process "pci=" kernel boot arguments
3486 * @str: string used to pass in "pci=" kernel boot arguments
3488 * Process kernel boot arguments. This is the default implementation.
3489 * Architecture specific implementations can override this as necessary.
3491 char * __weak __init pcibios_setup(char *str)
3497 * pcibios_set_master - enable PCI bus-mastering for device dev
3498 * @dev: the PCI device to enable
3500 * Enables PCI bus-mastering for the device. This is the default
3501 * implementation. Architecture specific implementations can override
3502 * this if necessary.
3504 void __weak pcibios_set_master(struct pci_dev *dev)
3508 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3509 if (pci_is_pcie(dev))
3512 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3514 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3515 else if (lat > pcibios_max_latency)
3516 lat = pcibios_max_latency;
3520 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3524 * pci_set_master - enables bus-mastering for device dev
3525 * @dev: the PCI device to enable
3527 * Enables bus-mastering on the device and calls pcibios_set_master()
3528 * to do the needed arch specific settings.
3530 void pci_set_master(struct pci_dev *dev)
3532 __pci_set_master(dev, true);
3533 pcibios_set_master(dev);
3535 EXPORT_SYMBOL(pci_set_master);
3538 * pci_clear_master - disables bus-mastering for device dev
3539 * @dev: the PCI device to disable
3541 void pci_clear_master(struct pci_dev *dev)
3543 __pci_set_master(dev, false);
3545 EXPORT_SYMBOL(pci_clear_master);
3548 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3549 * @dev: the PCI device for which MWI is to be enabled
3551 * Helper function for pci_set_mwi.
3552 * Originally copied from drivers/net/acenic.c.
3553 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3555 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3557 int pci_set_cacheline_size(struct pci_dev *dev)
3561 if (!pci_cache_line_size)
3564 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3565 equal to or multiple of the right value. */
3566 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3567 if (cacheline_size >= pci_cache_line_size &&
3568 (cacheline_size % pci_cache_line_size) == 0)
3571 /* Write the correct value. */
3572 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3574 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3575 if (cacheline_size == pci_cache_line_size)
3578 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3579 pci_cache_line_size << 2);
3583 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3586 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3587 * @dev: the PCI device for which MWI is enabled
3589 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3591 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3593 int pci_set_mwi(struct pci_dev *dev)
3595 #ifdef PCI_DISABLE_MWI
3601 rc = pci_set_cacheline_size(dev);
3605 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3606 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3607 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3608 cmd |= PCI_COMMAND_INVALIDATE;
3609 pci_write_config_word(dev, PCI_COMMAND, cmd);
3614 EXPORT_SYMBOL(pci_set_mwi);
3617 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3618 * @dev: the PCI device for which MWI is enabled
3620 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3621 * Callers are not required to check the return value.
3623 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3625 int pci_try_set_mwi(struct pci_dev *dev)
3627 #ifdef PCI_DISABLE_MWI
3630 return pci_set_mwi(dev);
3633 EXPORT_SYMBOL(pci_try_set_mwi);
3636 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3637 * @dev: the PCI device to disable
3639 * Disables PCI Memory-Write-Invalidate transaction on the device
3641 void pci_clear_mwi(struct pci_dev *dev)
3643 #ifndef PCI_DISABLE_MWI
3646 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3647 if (cmd & PCI_COMMAND_INVALIDATE) {
3648 cmd &= ~PCI_COMMAND_INVALIDATE;
3649 pci_write_config_word(dev, PCI_COMMAND, cmd);
3653 EXPORT_SYMBOL(pci_clear_mwi);
3656 * pci_intx - enables/disables PCI INTx for device dev
3657 * @pdev: the PCI device to operate on
3658 * @enable: boolean: whether to enable or disable PCI INTx
3660 * Enables/disables PCI INTx for device dev
3662 void pci_intx(struct pci_dev *pdev, int enable)
3664 u16 pci_command, new;
3666 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3669 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3671 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3673 if (new != pci_command) {
3674 struct pci_devres *dr;
3676 pci_write_config_word(pdev, PCI_COMMAND, new);
3678 dr = find_pci_dr(pdev);
3679 if (dr && !dr->restore_intx) {
3680 dr->restore_intx = 1;
3681 dr->orig_intx = !enable;
3685 EXPORT_SYMBOL_GPL(pci_intx);
3688 * pci_intx_mask_supported - probe for INTx masking support
3689 * @dev: the PCI device to operate on
3691 * Check if the device dev support INTx masking via the config space
3694 bool pci_intx_mask_supported(struct pci_dev *dev)
3696 bool mask_supported = false;
3699 if (dev->broken_intx_masking)
3702 pci_cfg_access_lock(dev);
3704 pci_read_config_word(dev, PCI_COMMAND, &orig);
3705 pci_write_config_word(dev, PCI_COMMAND,
3706 orig ^ PCI_COMMAND_INTX_DISABLE);
3707 pci_read_config_word(dev, PCI_COMMAND, &new);
3710 * There's no way to protect against hardware bugs or detect them
3711 * reliably, but as long as we know what the value should be, let's
3712 * go ahead and check it.
3714 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3715 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3717 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3718 mask_supported = true;
3719 pci_write_config_word(dev, PCI_COMMAND, orig);
3722 pci_cfg_access_unlock(dev);
3723 return mask_supported;
3725 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3727 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3729 struct pci_bus *bus = dev->bus;
3730 bool mask_updated = true;
3731 u32 cmd_status_dword;
3732 u16 origcmd, newcmd;
3733 unsigned long flags;
3737 * We do a single dword read to retrieve both command and status.
3738 * Document assumptions that make this possible.
3740 BUILD_BUG_ON(PCI_COMMAND % 4);
3741 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3743 raw_spin_lock_irqsave(&pci_lock, flags);
3745 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3747 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3750 * Check interrupt status register to see whether our device
3751 * triggered the interrupt (when masking) or the next IRQ is
3752 * already pending (when unmasking).
3754 if (mask != irq_pending) {
3755 mask_updated = false;
3759 origcmd = cmd_status_dword;
3760 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3762 newcmd |= PCI_COMMAND_INTX_DISABLE;
3763 if (newcmd != origcmd)
3764 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3767 raw_spin_unlock_irqrestore(&pci_lock, flags);
3769 return mask_updated;
3773 * pci_check_and_mask_intx - mask INTx on pending interrupt
3774 * @dev: the PCI device to operate on
3776 * Check if the device dev has its INTx line asserted, mask it and
3777 * return true in that case. False is returned if not interrupt was
3780 bool pci_check_and_mask_intx(struct pci_dev *dev)
3782 return pci_check_and_set_intx_mask(dev, true);
3784 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3787 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3788 * @dev: the PCI device to operate on
3790 * Check if the device dev has its INTx line asserted, unmask it if not
3791 * and return true. False is returned and the mask remains active if
3792 * there was still an interrupt pending.
3794 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3796 return pci_check_and_set_intx_mask(dev, false);
3798 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3801 * pci_wait_for_pending_transaction - waits for pending transaction
3802 * @dev: the PCI device to operate on
3804 * Return 0 if transaction is pending 1 otherwise.
3806 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3808 if (!pci_is_pcie(dev))
3811 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3812 PCI_EXP_DEVSTA_TRPND);
3814 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3816 static void pci_flr_wait(struct pci_dev *dev)
3818 int delay = 1, timeout = 60000;
3822 * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
3823 * 100ms, but may silently discard requests while the FLR is in
3824 * progress. Wait 100ms before trying to access the device.
3829 * After 100ms, the device should not silently discard config
3830 * requests, but it may still indicate that it needs more time by
3831 * responding to them with CRS completions. The Root Port will
3832 * generally synthesize ~0 data to complete the read (except when
3833 * CRS SV is enabled and the read was for the Vendor ID; in that
3834 * case it synthesizes 0x0001 data).
3836 * Wait for the device to return a non-CRS completion. Read the
3837 * Command register instead of Vendor ID so we don't have to
3838 * contend with the CRS SV value.
3840 pci_read_config_dword(dev, PCI_COMMAND, &id);
3842 if (delay > timeout) {
3843 dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n",
3849 dev_info(&dev->dev, "not ready %dms after FLR; waiting\n",
3854 pci_read_config_dword(dev, PCI_COMMAND, &id);
3858 dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1);
3861 static int pcie_flr(struct pci_dev *dev, int probe)
3865 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3866 if (!(cap & PCI_EXP_DEVCAP_FLR))
3872 if (!pci_wait_for_pending_transaction(dev))
3873 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3875 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3880 static int pci_af_flr(struct pci_dev *dev, int probe)
3885 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3889 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3890 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3897 * Wait for Transaction Pending bit to clear. A word-aligned test
3898 * is used, so we use the conrol offset rather than status and shift
3899 * the test bit to match.
3901 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3902 PCI_AF_STATUS_TP << 8))
3903 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3905 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3911 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3912 * @dev: Device to reset.
3913 * @probe: If set, only check if the device can be reset this way.
3915 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3916 * unset, it will be reinitialized internally when going from PCI_D3hot to
3917 * PCI_D0. If that's the case and the device is not in a low-power state
3918 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3920 * NOTE: This causes the caller to sleep for twice the device power transition
3921 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3922 * by default (i.e. unless the @dev's d3_delay field has a different value).
3923 * Moreover, only devices in D0 can be reset by this function.
3925 static int pci_pm_reset(struct pci_dev *dev, int probe)
3929 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3932 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3933 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3939 if (dev->current_state != PCI_D0)
3942 csr &= ~PCI_PM_CTRL_STATE_MASK;
3944 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3945 pci_dev_d3_sleep(dev);
3947 csr &= ~PCI_PM_CTRL_STATE_MASK;
3949 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3950 pci_dev_d3_sleep(dev);
3955 void pci_reset_secondary_bus(struct pci_dev *dev)
3959 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3960 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3961 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3963 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3964 * this to 2ms to ensure that we meet the minimum requirement.
3968 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3969 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3972 * Trhfa for conventional PCI is 2^25 clock cycles.
3973 * Assuming a minimum 33MHz clock this results in a 1s
3974 * delay before we can consider subordinate devices to
3975 * be re-initialized. PCIe has some ways to shorten this,
3976 * but we don't make use of them yet.
3981 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3983 pci_reset_secondary_bus(dev);
3987 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3988 * @dev: Bridge device
3990 * Use the bridge control register to assert reset on the secondary bus.
3991 * Devices on the secondary bus are left in power-on state.
3993 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3995 pcibios_reset_secondary_bus(dev);
3997 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3999 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4001 struct pci_dev *pdev;
4003 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4004 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4007 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4014 pci_reset_bridge_secondary_bus(dev->bus->self);
4019 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4023 if (!hotplug || !try_module_get(hotplug->ops->owner))
4026 if (hotplug->ops->reset_slot)
4027 rc = hotplug->ops->reset_slot(hotplug, probe);
4029 module_put(hotplug->ops->owner);
4034 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4036 struct pci_dev *pdev;
4038 if (dev->subordinate || !dev->slot ||
4039 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4042 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4043 if (pdev != dev && pdev->slot == dev->slot)
4046 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4049 static int __pci_dev_reset(struct pci_dev *dev, int probe)
4055 rc = pci_dev_specific_reset(dev, probe);
4059 rc = pcie_flr(dev, probe);
4063 rc = pci_af_flr(dev, probe);
4067 rc = pci_pm_reset(dev, probe);
4071 rc = pci_dev_reset_slot_function(dev, probe);
4075 rc = pci_parent_bus_reset(dev, probe);
4080 static void pci_dev_lock(struct pci_dev *dev)
4082 /* block PM suspend, driver probe, etc. */
4083 device_lock(&dev->dev);
4084 pci_cfg_access_lock(dev);
4087 /* Return 1 on successful lock, 0 on contention */
4088 static int pci_dev_trylock(struct pci_dev *dev)
4090 if (device_trylock(&dev->dev)) {
4091 if (pci_cfg_access_trylock(dev))
4093 device_unlock(&dev->dev);
4099 static void pci_dev_unlock(struct pci_dev *dev)
4101 pci_cfg_access_unlock(dev);
4102 device_unlock(&dev->dev);
4106 * pci_reset_notify - notify device driver of reset
4107 * @dev: device to be notified of reset
4108 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
4111 * Must be called prior to device access being disabled and after device
4112 * access is restored.
4114 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
4116 const struct pci_error_handlers *err_handler =
4117 dev->driver ? dev->driver->err_handler : NULL;
4118 if (err_handler && err_handler->reset_notify)
4119 err_handler->reset_notify(dev, prepare);
4122 static void pci_dev_save_and_disable(struct pci_dev *dev)
4124 pci_reset_notify(dev, true);
4127 * Wake-up device prior to save. PM registers default to D0 after
4128 * reset and a simple register restore doesn't reliably return
4129 * to a non-D0 state anyway.
4131 pci_set_power_state(dev, PCI_D0);
4133 pci_save_state(dev);
4135 * Disable the device by clearing the Command register, except for
4136 * INTx-disable which is set. This not only disables MMIO and I/O port
4137 * BARs, but also prevents the device from being Bus Master, preventing
4138 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4139 * compliant devices, INTx-disable prevents legacy interrupts.
4141 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4144 static void pci_dev_restore(struct pci_dev *dev)
4146 pci_restore_state(dev);
4147 pci_reset_notify(dev, false);
4150 static int pci_dev_reset(struct pci_dev *dev, int probe)
4157 rc = __pci_dev_reset(dev, probe);
4160 pci_dev_unlock(dev);
4166 * __pci_reset_function - reset a PCI device function
4167 * @dev: PCI device to reset
4169 * Some devices allow an individual function to be reset without affecting
4170 * other functions in the same device. The PCI device must be responsive
4171 * to PCI config space in order to use this function.
4173 * The device function is presumed to be unused when this function is called.
4174 * Resetting the device will make the contents of PCI configuration space
4175 * random, so any caller of this must be prepared to reinitialise the
4176 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4179 * Returns 0 if the device function was successfully reset or negative if the
4180 * device doesn't support resetting a single function.
4182 int __pci_reset_function(struct pci_dev *dev)
4184 return pci_dev_reset(dev, 0);
4186 EXPORT_SYMBOL_GPL(__pci_reset_function);
4189 * __pci_reset_function_locked - reset a PCI device function while holding
4190 * the @dev mutex lock.
4191 * @dev: PCI device to reset
4193 * Some devices allow an individual function to be reset without affecting
4194 * other functions in the same device. The PCI device must be responsive
4195 * to PCI config space in order to use this function.
4197 * The device function is presumed to be unused and the caller is holding
4198 * the device mutex lock when this function is called.
4199 * Resetting the device will make the contents of PCI configuration space
4200 * random, so any caller of this must be prepared to reinitialise the
4201 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4204 * Returns 0 if the device function was successfully reset or negative if the
4205 * device doesn't support resetting a single function.
4207 int __pci_reset_function_locked(struct pci_dev *dev)
4209 return __pci_dev_reset(dev, 0);
4211 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4214 * pci_probe_reset_function - check whether the device can be safely reset
4215 * @dev: PCI device to reset
4217 * Some devices allow an individual function to be reset without affecting
4218 * other functions in the same device. The PCI device must be responsive
4219 * to PCI config space in order to use this function.
4221 * Returns 0 if the device function can be reset or negative if the
4222 * device doesn't support resetting a single function.
4224 int pci_probe_reset_function(struct pci_dev *dev)
4226 return pci_dev_reset(dev, 1);
4230 * pci_reset_function - quiesce and reset a PCI device function
4231 * @dev: PCI device to reset
4233 * Some devices allow an individual function to be reset without affecting
4234 * other functions in the same device. The PCI device must be responsive
4235 * to PCI config space in order to use this function.
4237 * This function does not just reset the PCI portion of a device, but
4238 * clears all the state associated with the device. This function differs
4239 * from __pci_reset_function in that it saves and restores device state
4242 * Returns 0 if the device function was successfully reset or negative if the
4243 * device doesn't support resetting a single function.
4245 int pci_reset_function(struct pci_dev *dev)
4249 rc = pci_dev_reset(dev, 1);
4253 pci_dev_save_and_disable(dev);
4255 rc = pci_dev_reset(dev, 0);
4257 pci_dev_restore(dev);
4261 EXPORT_SYMBOL_GPL(pci_reset_function);
4264 * pci_try_reset_function - quiesce and reset a PCI device function
4265 * @dev: PCI device to reset
4267 * Same as above, except return -EAGAIN if unable to lock device.
4269 int pci_try_reset_function(struct pci_dev *dev)
4273 rc = pci_dev_reset(dev, 1);
4277 pci_dev_save_and_disable(dev);
4279 if (pci_dev_trylock(dev)) {
4280 rc = __pci_dev_reset(dev, 0);
4281 pci_dev_unlock(dev);
4285 pci_dev_restore(dev);
4289 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4291 /* Do any devices on or below this bus prevent a bus reset? */
4292 static bool pci_bus_resetable(struct pci_bus *bus)
4294 struct pci_dev *dev;
4297 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4300 list_for_each_entry(dev, &bus->devices, bus_list) {
4301 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4302 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4309 /* Lock devices from the top of the tree down */
4310 static void pci_bus_lock(struct pci_bus *bus)
4312 struct pci_dev *dev;
4314 list_for_each_entry(dev, &bus->devices, bus_list) {
4316 if (dev->subordinate)
4317 pci_bus_lock(dev->subordinate);
4321 /* Unlock devices from the bottom of the tree up */
4322 static void pci_bus_unlock(struct pci_bus *bus)
4324 struct pci_dev *dev;
4326 list_for_each_entry(dev, &bus->devices, bus_list) {
4327 if (dev->subordinate)
4328 pci_bus_unlock(dev->subordinate);
4329 pci_dev_unlock(dev);
4333 /* Return 1 on successful lock, 0 on contention */
4334 static int pci_bus_trylock(struct pci_bus *bus)
4336 struct pci_dev *dev;
4338 list_for_each_entry(dev, &bus->devices, bus_list) {
4339 if (!pci_dev_trylock(dev))
4341 if (dev->subordinate) {
4342 if (!pci_bus_trylock(dev->subordinate)) {
4343 pci_dev_unlock(dev);
4351 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4352 if (dev->subordinate)
4353 pci_bus_unlock(dev->subordinate);
4354 pci_dev_unlock(dev);
4359 /* Do any devices on or below this slot prevent a bus reset? */
4360 static bool pci_slot_resetable(struct pci_slot *slot)
4362 struct pci_dev *dev;
4364 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4365 if (!dev->slot || dev->slot != slot)
4367 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4368 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4375 /* Lock devices from the top of the tree down */
4376 static void pci_slot_lock(struct pci_slot *slot)
4378 struct pci_dev *dev;
4380 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4381 if (!dev->slot || dev->slot != slot)
4384 if (dev->subordinate)
4385 pci_bus_lock(dev->subordinate);
4389 /* Unlock devices from the bottom of the tree up */
4390 static void pci_slot_unlock(struct pci_slot *slot)
4392 struct pci_dev *dev;
4394 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4395 if (!dev->slot || dev->slot != slot)
4397 if (dev->subordinate)
4398 pci_bus_unlock(dev->subordinate);
4399 pci_dev_unlock(dev);
4403 /* Return 1 on successful lock, 0 on contention */
4404 static int pci_slot_trylock(struct pci_slot *slot)
4406 struct pci_dev *dev;
4408 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4409 if (!dev->slot || dev->slot != slot)
4411 if (!pci_dev_trylock(dev))
4413 if (dev->subordinate) {
4414 if (!pci_bus_trylock(dev->subordinate)) {
4415 pci_dev_unlock(dev);
4423 list_for_each_entry_continue_reverse(dev,
4424 &slot->bus->devices, bus_list) {
4425 if (!dev->slot || dev->slot != slot)
4427 if (dev->subordinate)
4428 pci_bus_unlock(dev->subordinate);
4429 pci_dev_unlock(dev);
4434 /* Save and disable devices from the top of the tree down */
4435 static void pci_bus_save_and_disable(struct pci_bus *bus)
4437 struct pci_dev *dev;
4439 list_for_each_entry(dev, &bus->devices, bus_list) {
4440 pci_dev_save_and_disable(dev);
4441 if (dev->subordinate)
4442 pci_bus_save_and_disable(dev->subordinate);
4447 * Restore devices from top of the tree down - parent bridges need to be
4448 * restored before we can get to subordinate devices.
4450 static void pci_bus_restore(struct pci_bus *bus)
4452 struct pci_dev *dev;
4454 list_for_each_entry(dev, &bus->devices, bus_list) {
4455 pci_dev_restore(dev);
4456 if (dev->subordinate)
4457 pci_bus_restore(dev->subordinate);
4461 /* Save and disable devices from the top of the tree down */
4462 static void pci_slot_save_and_disable(struct pci_slot *slot)
4464 struct pci_dev *dev;
4466 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4467 if (!dev->slot || dev->slot != slot)
4469 pci_dev_save_and_disable(dev);
4470 if (dev->subordinate)
4471 pci_bus_save_and_disable(dev->subordinate);
4476 * Restore devices from top of the tree down - parent bridges need to be
4477 * restored before we can get to subordinate devices.
4479 static void pci_slot_restore(struct pci_slot *slot)
4481 struct pci_dev *dev;
4483 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4484 if (!dev->slot || dev->slot != slot)
4486 pci_dev_restore(dev);
4487 if (dev->subordinate)
4488 pci_bus_restore(dev->subordinate);
4492 static int pci_slot_reset(struct pci_slot *slot, int probe)
4496 if (!slot || !pci_slot_resetable(slot))
4500 pci_slot_lock(slot);
4504 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4507 pci_slot_unlock(slot);
4513 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4514 * @slot: PCI slot to probe
4516 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4518 int pci_probe_reset_slot(struct pci_slot *slot)
4520 return pci_slot_reset(slot, 1);
4522 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4525 * pci_reset_slot - reset a PCI slot
4526 * @slot: PCI slot to reset
4528 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4529 * independent of other slots. For instance, some slots may support slot power
4530 * control. In the case of a 1:1 bus to slot architecture, this function may
4531 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4532 * Generally a slot reset should be attempted before a bus reset. All of the
4533 * function of the slot and any subordinate buses behind the slot are reset
4534 * through this function. PCI config space of all devices in the slot and
4535 * behind the slot is saved before and restored after reset.
4537 * Return 0 on success, non-zero on error.
4539 int pci_reset_slot(struct pci_slot *slot)
4543 rc = pci_slot_reset(slot, 1);
4547 pci_slot_save_and_disable(slot);
4549 rc = pci_slot_reset(slot, 0);
4551 pci_slot_restore(slot);
4555 EXPORT_SYMBOL_GPL(pci_reset_slot);
4558 * pci_try_reset_slot - Try to reset a PCI slot
4559 * @slot: PCI slot to reset
4561 * Same as above except return -EAGAIN if the slot cannot be locked
4563 int pci_try_reset_slot(struct pci_slot *slot)
4567 rc = pci_slot_reset(slot, 1);
4571 pci_slot_save_and_disable(slot);
4573 if (pci_slot_trylock(slot)) {
4575 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4576 pci_slot_unlock(slot);
4580 pci_slot_restore(slot);
4584 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4586 static int pci_bus_reset(struct pci_bus *bus, int probe)
4588 if (!bus->self || !pci_bus_resetable(bus))
4598 pci_reset_bridge_secondary_bus(bus->self);
4600 pci_bus_unlock(bus);
4606 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4607 * @bus: PCI bus to probe
4609 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4611 int pci_probe_reset_bus(struct pci_bus *bus)
4613 return pci_bus_reset(bus, 1);
4615 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4618 * pci_reset_bus - reset a PCI bus
4619 * @bus: top level PCI bus to reset
4621 * Do a bus reset on the given bus and any subordinate buses, saving
4622 * and restoring state of all devices.
4624 * Return 0 on success, non-zero on error.
4626 int pci_reset_bus(struct pci_bus *bus)
4630 rc = pci_bus_reset(bus, 1);
4634 pci_bus_save_and_disable(bus);
4636 rc = pci_bus_reset(bus, 0);
4638 pci_bus_restore(bus);
4642 EXPORT_SYMBOL_GPL(pci_reset_bus);
4645 * pci_try_reset_bus - Try to reset a PCI bus
4646 * @bus: top level PCI bus to reset
4648 * Same as above except return -EAGAIN if the bus cannot be locked
4650 int pci_try_reset_bus(struct pci_bus *bus)
4654 rc = pci_bus_reset(bus, 1);
4658 pci_bus_save_and_disable(bus);
4660 if (pci_bus_trylock(bus)) {
4662 pci_reset_bridge_secondary_bus(bus->self);
4663 pci_bus_unlock(bus);
4667 pci_bus_restore(bus);
4671 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4674 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4675 * @dev: PCI device to query
4677 * Returns mmrbc: maximum designed memory read count in bytes
4678 * or appropriate error value.
4680 int pcix_get_max_mmrbc(struct pci_dev *dev)
4685 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4689 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4692 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4694 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4697 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4698 * @dev: PCI device to query
4700 * Returns mmrbc: maximum memory read count in bytes
4701 * or appropriate error value.
4703 int pcix_get_mmrbc(struct pci_dev *dev)
4708 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4712 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4715 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4717 EXPORT_SYMBOL(pcix_get_mmrbc);
4720 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4721 * @dev: PCI device to query
4722 * @mmrbc: maximum memory read count in bytes
4723 * valid values are 512, 1024, 2048, 4096
4725 * If possible sets maximum memory read byte count, some bridges have erratas
4726 * that prevent this.
4728 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4734 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4737 v = ffs(mmrbc) - 10;
4739 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4743 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4746 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4749 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4752 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4754 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4757 cmd &= ~PCI_X_CMD_MAX_READ;
4759 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4764 EXPORT_SYMBOL(pcix_set_mmrbc);
4767 * pcie_get_readrq - get PCI Express read request size
4768 * @dev: PCI device to query
4770 * Returns maximum memory read request in bytes
4771 * or appropriate error value.
4773 int pcie_get_readrq(struct pci_dev *dev)
4777 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4779 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4781 EXPORT_SYMBOL(pcie_get_readrq);
4784 * pcie_set_readrq - set PCI Express maximum memory read request
4785 * @dev: PCI device to query
4786 * @rq: maximum memory read count in bytes
4787 * valid values are 128, 256, 512, 1024, 2048, 4096
4789 * If possible sets maximum memory read request in bytes
4791 int pcie_set_readrq(struct pci_dev *dev, int rq)
4795 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4799 * If using the "performance" PCIe config, we clamp the
4800 * read rq size to the max packet size to prevent the
4801 * host bridge generating requests larger than we can
4804 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4805 int mps = pcie_get_mps(dev);
4811 v = (ffs(rq) - 8) << 12;
4813 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4814 PCI_EXP_DEVCTL_READRQ, v);
4816 EXPORT_SYMBOL(pcie_set_readrq);
4819 * pcie_get_mps - get PCI Express maximum payload size
4820 * @dev: PCI device to query
4822 * Returns maximum payload size in bytes
4824 int pcie_get_mps(struct pci_dev *dev)
4828 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4830 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4832 EXPORT_SYMBOL(pcie_get_mps);
4835 * pcie_set_mps - set PCI Express maximum payload size
4836 * @dev: PCI device to query
4837 * @mps: maximum payload size in bytes
4838 * valid values are 128, 256, 512, 1024, 2048, 4096
4840 * If possible sets maximum payload size
4842 int pcie_set_mps(struct pci_dev *dev, int mps)
4846 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4850 if (v > dev->pcie_mpss)
4854 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4855 PCI_EXP_DEVCTL_PAYLOAD, v);
4857 EXPORT_SYMBOL(pcie_set_mps);
4860 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4861 * @dev: PCI device to query
4862 * @speed: storage for minimum speed
4863 * @width: storage for minimum width
4865 * This function will walk up the PCI device chain and determine the minimum
4866 * link width and speed of the device.
4868 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4869 enum pcie_link_width *width)
4873 *speed = PCI_SPEED_UNKNOWN;
4874 *width = PCIE_LNK_WIDTH_UNKNOWN;
4878 enum pci_bus_speed next_speed;
4879 enum pcie_link_width next_width;
4881 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4885 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4886 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4887 PCI_EXP_LNKSTA_NLW_SHIFT;
4889 if (next_speed < *speed)
4890 *speed = next_speed;
4892 if (next_width < *width)
4893 *width = next_width;
4895 dev = dev->bus->self;
4900 EXPORT_SYMBOL(pcie_get_minimum_link);
4903 * pci_select_bars - Make BAR mask from the type of resource
4904 * @dev: the PCI device for which BAR mask is made
4905 * @flags: resource type mask to be selected
4907 * This helper routine makes bar mask from the type of resource.
4909 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4912 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4913 if (pci_resource_flags(dev, i) & flags)
4917 EXPORT_SYMBOL(pci_select_bars);
4919 /* Some architectures require additional programming to enable VGA */
4920 static arch_set_vga_state_t arch_set_vga_state;
4922 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4924 arch_set_vga_state = func; /* NULL disables */
4927 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4928 unsigned int command_bits, u32 flags)
4930 if (arch_set_vga_state)
4931 return arch_set_vga_state(dev, decode, command_bits,
4937 * pci_set_vga_state - set VGA decode state on device and parents if requested
4938 * @dev: the PCI device
4939 * @decode: true = enable decoding, false = disable decoding
4940 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4941 * @flags: traverse ancestors and change bridges
4942 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4944 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4945 unsigned int command_bits, u32 flags)
4947 struct pci_bus *bus;
4948 struct pci_dev *bridge;
4952 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4954 /* ARCH specific VGA enables */
4955 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4959 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4960 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4962 cmd |= command_bits;
4964 cmd &= ~command_bits;
4965 pci_write_config_word(dev, PCI_COMMAND, cmd);
4968 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4975 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4978 cmd |= PCI_BRIDGE_CTL_VGA;
4980 cmd &= ~PCI_BRIDGE_CTL_VGA;
4981 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4990 * pci_add_dma_alias - Add a DMA devfn alias for a device
4991 * @dev: the PCI device for which alias is added
4992 * @devfn: alias slot and function
4994 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
4995 * It should be called early, preferably as PCI fixup header quirk.
4997 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
4999 if (!dev->dma_alias_mask)
5000 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5001 sizeof(long), GFP_KERNEL);
5002 if (!dev->dma_alias_mask) {
5003 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
5007 set_bit(devfn, dev->dma_alias_mask);
5008 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
5009 PCI_SLOT(devfn), PCI_FUNC(devfn));
5012 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5014 return (dev1->dma_alias_mask &&
5015 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5016 (dev2->dma_alias_mask &&
5017 test_bit(dev1->devfn, dev2->dma_alias_mask));
5020 bool pci_device_is_present(struct pci_dev *pdev)
5024 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5026 EXPORT_SYMBOL_GPL(pci_device_is_present);
5028 void pci_ignore_hotplug(struct pci_dev *dev)
5030 struct pci_dev *bridge = dev->bus->self;
5032 dev->ignore_hotplug = 1;
5033 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5035 bridge->ignore_hotplug = 1;
5037 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5039 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5040 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5041 static DEFINE_SPINLOCK(resource_alignment_lock);
5044 * pci_specified_resource_alignment - get resource alignment specified by user.
5045 * @dev: the PCI device to get
5047 * RETURNS: Resource alignment if it is specified.
5048 * Zero if it is not specified.
5050 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
5052 int seg, bus, slot, func, align_order, count;
5053 unsigned short vendor, device, subsystem_vendor, subsystem_device;
5054 resource_size_t align = 0;
5057 spin_lock(&resource_alignment_lock);
5058 p = resource_alignment_param;
5061 if (pci_has_flag(PCI_PROBE_ONLY)) {
5062 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5068 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5074 if (strncmp(p, "pci:", 4) == 0) {
5075 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5077 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
5078 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
5079 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5080 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5084 subsystem_vendor = subsystem_device = 0;
5087 if ((!vendor || (vendor == dev->vendor)) &&
5088 (!device || (device == dev->device)) &&
5089 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5090 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5091 if (align_order == -1)
5094 align = 1 << align_order;
5100 if (sscanf(p, "%x:%x:%x.%x%n",
5101 &seg, &bus, &slot, &func, &count) != 4) {
5103 if (sscanf(p, "%x:%x.%x%n",
5104 &bus, &slot, &func, &count) != 3) {
5105 /* Invalid format */
5106 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5112 if (seg == pci_domain_nr(dev->bus) &&
5113 bus == dev->bus->number &&
5114 slot == PCI_SLOT(dev->devfn) &&
5115 func == PCI_FUNC(dev->devfn)) {
5116 if (align_order == -1)
5119 align = 1 << align_order;
5124 if (*p != ';' && *p != ',') {
5125 /* End of param or invalid format */
5131 spin_unlock(&resource_alignment_lock);
5136 * This function disables memory decoding and releases memory resources
5137 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5138 * It also rounds up size to specified alignment.
5139 * Later on, the kernel will assign page-aligned memory resource back
5142 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5146 resource_size_t align, size;
5150 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5151 * 3.4.1.11. Their resources are allocated from the space
5152 * described by the VF BARx register in the PF's SR-IOV capability.
5153 * We can't influence their alignment here.
5158 /* check if specified PCI is target device to reassign */
5159 align = pci_specified_resource_alignment(dev);
5163 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5164 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5166 "Can't reassign resources to host bridge.\n");
5171 "Disabling memory decoding and releasing memory resources.\n");
5172 pci_read_config_word(dev, PCI_COMMAND, &command);
5173 command &= ~PCI_COMMAND_MEMORY;
5174 pci_write_config_word(dev, PCI_COMMAND, command);
5176 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
5177 r = &dev->resource[i];
5178 if (!(r->flags & IORESOURCE_MEM))
5180 if (r->flags & IORESOURCE_PCI_FIXED) {
5181 dev_info(&dev->dev, "Ignoring requested alignment for BAR%d: %pR\n",
5186 size = resource_size(r);
5190 "Rounding up size of resource #%d to %#llx.\n",
5191 i, (unsigned long long)size);
5193 r->flags |= IORESOURCE_UNSET;
5197 /* Need to disable bridge's resource window,
5198 * to enable the kernel to reassign new resource
5201 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5202 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5203 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5204 r = &dev->resource[i];
5205 if (!(r->flags & IORESOURCE_MEM))
5207 r->flags |= IORESOURCE_UNSET;
5208 r->end = resource_size(r) - 1;
5211 pci_disable_bridge_window(dev);
5215 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5217 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5218 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5219 spin_lock(&resource_alignment_lock);
5220 strncpy(resource_alignment_param, buf, count);
5221 resource_alignment_param[count] = '\0';
5222 spin_unlock(&resource_alignment_lock);
5226 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5229 spin_lock(&resource_alignment_lock);
5230 count = snprintf(buf, size, "%s", resource_alignment_param);
5231 spin_unlock(&resource_alignment_lock);
5235 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5237 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5240 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5241 const char *buf, size_t count)
5243 return pci_set_resource_alignment_param(buf, count);
5246 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5247 pci_resource_alignment_store);
5249 static int __init pci_resource_alignment_sysfs_init(void)
5251 return bus_create_file(&pci_bus_type,
5252 &bus_attr_resource_alignment);
5254 late_initcall(pci_resource_alignment_sysfs_init);
5256 static void pci_no_domains(void)
5258 #ifdef CONFIG_PCI_DOMAINS
5259 pci_domains_supported = 0;
5263 #ifdef CONFIG_PCI_DOMAINS
5264 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5266 int pci_get_new_domain_nr(void)
5268 return atomic_inc_return(&__domain_nr);
5271 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5272 static int of_pci_bus_find_domain_nr(struct device *parent)
5274 static int use_dt_domains = -1;
5278 domain = of_get_pci_domain_nr(parent->of_node);
5280 * Check DT domain and use_dt_domains values.
5282 * If DT domain property is valid (domain >= 0) and
5283 * use_dt_domains != 0, the DT assignment is valid since this means
5284 * we have not previously allocated a domain number by using
5285 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5286 * 1, to indicate that we have just assigned a domain number from
5289 * If DT domain property value is not valid (ie domain < 0), and we
5290 * have not previously assigned a domain number from DT
5291 * (use_dt_domains != 1) we should assign a domain number by
5294 * pci_get_new_domain_nr()
5296 * API and update the use_dt_domains value to keep track of method we
5297 * are using to assign domain numbers (use_dt_domains = 0).
5299 * All other combinations imply we have a platform that is trying
5300 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5301 * which is a recipe for domain mishandling and it is prevented by
5302 * invalidating the domain value (domain = -1) and printing a
5303 * corresponding error.
5305 if (domain >= 0 && use_dt_domains) {
5307 } else if (domain < 0 && use_dt_domains != 1) {
5309 domain = pci_get_new_domain_nr();
5311 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
5312 parent->of_node->full_name);
5319 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5321 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5322 acpi_pci_bus_find_domain_nr(bus);
5328 * pci_ext_cfg_avail - can we access extended PCI config space?
5330 * Returns 1 if we can access PCI extended config space (offsets
5331 * greater than 0xff). This is the default implementation. Architecture
5332 * implementations can override this.
5334 int __weak pci_ext_cfg_avail(void)
5339 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5342 EXPORT_SYMBOL(pci_fixup_cardbus);
5344 static int __init pci_setup(char *str)
5347 char *k = strchr(str, ',');
5350 if (*str && (str = pcibios_setup(str)) && *str) {
5351 if (!strcmp(str, "nomsi")) {
5353 } else if (!strcmp(str, "noaer")) {
5355 } else if (!strncmp(str, "realloc=", 8)) {
5356 pci_realloc_get_opt(str + 8);
5357 } else if (!strncmp(str, "realloc", 7)) {
5358 pci_realloc_get_opt("on");
5359 } else if (!strcmp(str, "nodomains")) {
5361 } else if (!strncmp(str, "noari", 5)) {
5362 pcie_ari_disabled = true;
5363 } else if (!strncmp(str, "cbiosize=", 9)) {
5364 pci_cardbus_io_size = memparse(str + 9, &str);
5365 } else if (!strncmp(str, "cbmemsize=", 10)) {
5366 pci_cardbus_mem_size = memparse(str + 10, &str);
5367 } else if (!strncmp(str, "resource_alignment=", 19)) {
5368 pci_set_resource_alignment_param(str + 19,
5370 } else if (!strncmp(str, "ecrc=", 5)) {
5371 pcie_ecrc_get_policy(str + 5);
5372 } else if (!strncmp(str, "hpiosize=", 9)) {
5373 pci_hotplug_io_size = memparse(str + 9, &str);
5374 } else if (!strncmp(str, "hpmemsize=", 10)) {
5375 pci_hotplug_mem_size = memparse(str + 10, &str);
5376 } else if (!strncmp(str, "hpbussize=", 10)) {
5377 pci_hotplug_bus_size =
5378 simple_strtoul(str + 10, &str, 0);
5379 if (pci_hotplug_bus_size > 0xff)
5380 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5381 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5382 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5383 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5384 pcie_bus_config = PCIE_BUS_SAFE;
5385 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5386 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5387 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5388 pcie_bus_config = PCIE_BUS_PEER2PEER;
5389 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5390 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5392 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5400 early_param("pci", pci_setup);