1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex);
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
48 EXPORT_SYMBOL(pci_pci_problems);
50 unsigned int pci_pm_d3hot_delay;
52 static void pci_pme_list_scan(struct work_struct *work);
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
58 struct pci_pme_device {
59 struct list_head list;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
67 unsigned int delay = dev->d3hot_delay;
69 if (delay < pci_pm_d3hot_delay)
70 delay = pci_pm_d3hot_delay;
76 #ifdef CONFIG_PCI_DOMAINS
77 int pci_domains_supported = 1;
80 #define DEFAULT_CARDBUS_IO_SIZE (256)
81 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
82 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
83 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
84 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
86 #define DEFAULT_HOTPLUG_IO_SIZE (256)
87 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
88 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
89 /* hpiosize=nn can override this */
90 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
92 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
93 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
94 * pci=hpmemsize=nnM overrides both
96 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
97 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
99 #define DEFAULT_HOTPLUG_BUS_SIZE 1
100 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
103 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
104 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
105 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
106 #elif defined CONFIG_PCIE_BUS_SAFE
107 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
108 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
109 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
110 #elif defined CONFIG_PCIE_BUS_PEER2PEER
111 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
113 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
117 * The default CLS is used if arch didn't set CLS explicitly and not
118 * all pci devices agree on the same value. Arch can override either
119 * the dfl or actual value as it sees fit. Don't forget this is
120 * measured in 32-bit words, not bytes.
122 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
123 u8 pci_cache_line_size;
126 * If we set up a device for bus mastering, we need to check the latency
127 * timer as certain BIOSes forget to set it properly.
129 unsigned int pcibios_max_latency = 255;
131 /* If set, the PCIe ARI capability will not be used. */
132 static bool pcie_ari_disabled;
134 /* If set, the PCIe ATS capability will not be used. */
135 static bool pcie_ats_disabled;
137 /* If set, the PCI config space of each device is printed during boot. */
140 bool pci_ats_disabled(void)
142 return pcie_ats_disabled;
144 EXPORT_SYMBOL_GPL(pci_ats_disabled);
146 /* Disable bridge_d3 for all PCIe ports */
147 static bool pci_bridge_d3_disable;
148 /* Force bridge_d3 for all PCIe ports */
149 static bool pci_bridge_d3_force;
151 static int __init pcie_port_pm_setup(char *str)
153 if (!strcmp(str, "off"))
154 pci_bridge_d3_disable = true;
155 else if (!strcmp(str, "force"))
156 pci_bridge_d3_force = true;
159 __setup("pcie_port_pm=", pcie_port_pm_setup);
162 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
163 * @bus: pointer to PCI bus structure to search
165 * Given a PCI bus, returns the highest PCI bus number present in the set
166 * including the given PCI bus and its list of child PCI buses.
168 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
171 unsigned char max, n;
173 max = bus->busn_res.end;
174 list_for_each_entry(tmp, &bus->children, node) {
175 n = pci_bus_max_busnr(tmp);
181 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
184 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
185 * @pdev: the PCI device
187 * Returns error bits set in PCI_STATUS and clears them.
189 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
194 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
195 if (ret != PCIBIOS_SUCCESSFUL)
198 status &= PCI_STATUS_ERROR_BITS;
200 pci_write_config_word(pdev, PCI_STATUS, status);
204 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
206 #ifdef CONFIG_HAS_IOMEM
207 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
209 struct resource *res = &pdev->resource[bar];
212 * Make sure the BAR is actually a memory resource, not an IO resource
214 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
215 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
218 return ioremap(res->start, resource_size(res));
220 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
222 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
225 * Make sure the BAR is actually a memory resource, not an IO resource
227 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
231 return ioremap_wc(pci_resource_start(pdev, bar),
232 pci_resource_len(pdev, bar));
234 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
238 * pci_dev_str_match_path - test if a path string matches a device
239 * @dev: the PCI device to test
240 * @path: string to match the device against
241 * @endptr: pointer to the string after the match
243 * Test if a string (typically from a kernel parameter) formatted as a
244 * path of device/function addresses matches a PCI device. The string must
247 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
249 * A path for a device can be obtained using 'lspci -t'. Using a path
250 * is more robust against bus renumbering than using only a single bus,
251 * device and function address.
253 * Returns 1 if the string matches the device, 0 if it does not and
254 * a negative error code if it fails to parse the string.
256 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
260 int seg, bus, slot, func;
264 *endptr = strchrnul(path, ';');
266 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
271 p = strrchr(wpath, '/');
274 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
280 if (dev->devfn != PCI_DEVFN(slot, func)) {
286 * Note: we don't need to get a reference to the upstream
287 * bridge because we hold a reference to the top level
288 * device which should hold a reference to the bridge,
291 dev = pci_upstream_bridge(dev);
300 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
304 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
311 ret = (seg == pci_domain_nr(dev->bus) &&
312 bus == dev->bus->number &&
313 dev->devfn == PCI_DEVFN(slot, func));
321 * pci_dev_str_match - test if a string matches a device
322 * @dev: the PCI device to test
323 * @p: string to match the device against
324 * @endptr: pointer to the string after the match
326 * Test if a string (typically from a kernel parameter) matches a specified
327 * PCI device. The string may be of one of the following formats:
329 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
330 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
332 * The first format specifies a PCI bus/device/function address which
333 * may change if new hardware is inserted, if motherboard firmware changes,
334 * or due to changes caused in kernel parameters. If the domain is
335 * left unspecified, it is taken to be 0. In order to be robust against
336 * bus renumbering issues, a path of PCI device/function numbers may be used
337 * to address the specific device. The path for a device can be determined
338 * through the use of 'lspci -t'.
340 * The second format matches devices using IDs in the configuration
341 * space which may match multiple devices in the system. A value of 0
342 * for any field will match all devices. (Note: this differs from
343 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
344 * legacy reasons and convenience so users don't have to specify
345 * FFFFFFFFs on the command line.)
347 * Returns 1 if the string matches the device, 0 if it does not and
348 * a negative error code if the string cannot be parsed.
350 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
355 unsigned short vendor, device, subsystem_vendor, subsystem_device;
357 if (strncmp(p, "pci:", 4) == 0) {
358 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
360 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
361 &subsystem_vendor, &subsystem_device, &count);
363 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
367 subsystem_vendor = 0;
368 subsystem_device = 0;
373 if ((!vendor || vendor == dev->vendor) &&
374 (!device || device == dev->device) &&
375 (!subsystem_vendor ||
376 subsystem_vendor == dev->subsystem_vendor) &&
377 (!subsystem_device ||
378 subsystem_device == dev->subsystem_device))
382 * PCI Bus, Device, Function IDs are specified
383 * (optionally, may include a path of devfns following it)
385 ret = pci_dev_str_match_path(dev, p, &p);
400 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
401 u8 pos, int cap, int *ttl)
406 pci_bus_read_config_byte(bus, devfn, pos, &pos);
412 pci_bus_read_config_word(bus, devfn, pos, &ent);
424 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
427 int ttl = PCI_FIND_CAP_TTL;
429 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
432 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
434 return __pci_find_next_cap(dev->bus, dev->devfn,
435 pos + PCI_CAP_LIST_NEXT, cap);
437 EXPORT_SYMBOL_GPL(pci_find_next_capability);
439 static int __pci_bus_find_cap_start(struct pci_bus *bus,
440 unsigned int devfn, u8 hdr_type)
444 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
445 if (!(status & PCI_STATUS_CAP_LIST))
449 case PCI_HEADER_TYPE_NORMAL:
450 case PCI_HEADER_TYPE_BRIDGE:
451 return PCI_CAPABILITY_LIST;
452 case PCI_HEADER_TYPE_CARDBUS:
453 return PCI_CB_CAPABILITY_LIST;
460 * pci_find_capability - query for devices' capabilities
461 * @dev: PCI device to query
462 * @cap: capability code
464 * Tell if a device supports a given PCI capability.
465 * Returns the address of the requested capability structure within the
466 * device's PCI configuration space or 0 in case the device does not
467 * support it. Possible values for @cap include:
469 * %PCI_CAP_ID_PM Power Management
470 * %PCI_CAP_ID_AGP Accelerated Graphics Port
471 * %PCI_CAP_ID_VPD Vital Product Data
472 * %PCI_CAP_ID_SLOTID Slot Identification
473 * %PCI_CAP_ID_MSI Message Signalled Interrupts
474 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
475 * %PCI_CAP_ID_PCIX PCI-X
476 * %PCI_CAP_ID_EXP PCI Express
478 int pci_find_capability(struct pci_dev *dev, int cap)
482 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
484 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
488 EXPORT_SYMBOL(pci_find_capability);
491 * pci_bus_find_capability - query for devices' capabilities
492 * @bus: the PCI bus to query
493 * @devfn: PCI device to query
494 * @cap: capability code
496 * Like pci_find_capability() but works for PCI devices that do not have a
497 * pci_dev structure set up yet.
499 * Returns the address of the requested capability structure within the
500 * device's PCI configuration space or 0 in case the device does not
503 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
508 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
510 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
512 pos = __pci_find_next_cap(bus, devfn, pos, cap);
516 EXPORT_SYMBOL(pci_bus_find_capability);
519 * pci_find_next_ext_capability - Find an extended capability
520 * @dev: PCI device to query
521 * @start: address at which to start looking (0 to start at beginning of list)
522 * @cap: capability code
524 * Returns the address of the next matching extended capability structure
525 * within the device's PCI configuration space or 0 if the device does
526 * not support it. Some capabilities can occur several times, e.g., the
527 * vendor-specific capability, and this provides a way to find them all.
529 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
533 int pos = PCI_CFG_SPACE_SIZE;
535 /* minimum 8 bytes per capability */
536 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
538 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
544 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
548 * If we have no capabilities, this is indicated by cap ID,
549 * cap version and next pointer all being 0.
555 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
558 pos = PCI_EXT_CAP_NEXT(header);
559 if (pos < PCI_CFG_SPACE_SIZE)
562 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
568 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
571 * pci_find_ext_capability - Find an extended capability
572 * @dev: PCI device to query
573 * @cap: capability code
575 * Returns the address of the requested extended capability structure
576 * within the device's PCI configuration space or 0 if the device does
577 * not support it. Possible values for @cap include:
579 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
580 * %PCI_EXT_CAP_ID_VC Virtual Channel
581 * %PCI_EXT_CAP_ID_DSN Device Serial Number
582 * %PCI_EXT_CAP_ID_PWR Power Budgeting
584 int pci_find_ext_capability(struct pci_dev *dev, int cap)
586 return pci_find_next_ext_capability(dev, 0, cap);
588 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
591 * pci_get_dsn - Read and return the 8-byte Device Serial Number
592 * @dev: PCI device to query
594 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
597 * Returns the DSN, or zero if the capability does not exist.
599 u64 pci_get_dsn(struct pci_dev *dev)
605 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
610 * The Device Serial Number is two dwords offset 4 bytes from the
611 * capability position. The specification says that the first dword is
612 * the lower half, and the second dword is the upper half.
615 pci_read_config_dword(dev, pos, &dword);
617 pci_read_config_dword(dev, pos + 4, &dword);
618 dsn |= ((u64)dword) << 32;
622 EXPORT_SYMBOL_GPL(pci_get_dsn);
624 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
626 int rc, ttl = PCI_FIND_CAP_TTL;
629 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
630 mask = HT_3BIT_CAP_MASK;
632 mask = HT_5BIT_CAP_MASK;
634 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
635 PCI_CAP_ID_HT, &ttl);
637 rc = pci_read_config_byte(dev, pos + 3, &cap);
638 if (rc != PCIBIOS_SUCCESSFUL)
641 if ((cap & mask) == ht_cap)
644 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
645 pos + PCI_CAP_LIST_NEXT,
646 PCI_CAP_ID_HT, &ttl);
652 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
653 * @dev: PCI device to query
654 * @pos: Position from which to continue searching
655 * @ht_cap: Hypertransport capability code
657 * To be used in conjunction with pci_find_ht_capability() to search for
658 * all capabilities matching @ht_cap. @pos should always be a value returned
659 * from pci_find_ht_capability().
661 * NB. To be 100% safe against broken PCI devices, the caller should take
662 * steps to avoid an infinite loop.
664 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
666 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
668 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
671 * pci_find_ht_capability - query a device's Hypertransport capabilities
672 * @dev: PCI device to query
673 * @ht_cap: Hypertransport capability code
675 * Tell if a device supports a given Hypertransport capability.
676 * Returns an address within the device's PCI configuration space
677 * or 0 in case the device does not support the request capability.
678 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
679 * which has a Hypertransport capability matching @ht_cap.
681 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
685 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
687 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
691 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
694 * pci_find_parent_resource - return resource region of parent bus of given
696 * @dev: PCI device structure contains resources to be searched
697 * @res: child resource record for which parent is sought
699 * For given resource region of given device, return the resource region of
700 * parent bus the given region is contained in.
702 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
703 struct resource *res)
705 const struct pci_bus *bus = dev->bus;
709 pci_bus_for_each_resource(bus, r, i) {
712 if (resource_contains(r, res)) {
715 * If the window is prefetchable but the BAR is
716 * not, the allocator made a mistake.
718 if (r->flags & IORESOURCE_PREFETCH &&
719 !(res->flags & IORESOURCE_PREFETCH))
723 * If we're below a transparent bridge, there may
724 * be both a positively-decoded aperture and a
725 * subtractively-decoded region that contain the BAR.
726 * We want the positively-decoded one, so this depends
727 * on pci_bus_for_each_resource() giving us those
735 EXPORT_SYMBOL(pci_find_parent_resource);
738 * pci_find_resource - Return matching PCI device resource
739 * @dev: PCI device to query
740 * @res: Resource to look for
742 * Goes over standard PCI resources (BARs) and checks if the given resource
743 * is partially or fully contained in any of them. In that case the
744 * matching resource is returned, %NULL otherwise.
746 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
750 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
751 struct resource *r = &dev->resource[i];
753 if (r->start && resource_contains(r, res))
759 EXPORT_SYMBOL(pci_find_resource);
762 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
763 * @dev: the PCI device to operate on
764 * @pos: config space offset of status word
765 * @mask: mask of bit(s) to care about in status word
767 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
769 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
773 /* Wait for Transaction Pending bit clean */
774 for (i = 0; i < 4; i++) {
777 msleep((1 << (i - 1)) * 100);
779 pci_read_config_word(dev, pos, &status);
780 if (!(status & mask))
787 static int pci_acs_enable;
790 * pci_request_acs - ask for ACS to be enabled if supported
792 void pci_request_acs(void)
797 static const char *disable_acs_redir_param;
800 * pci_disable_acs_redir - disable ACS redirect capabilities
801 * @dev: the PCI device
803 * For only devices specified in the disable_acs_redir parameter.
805 static void pci_disable_acs_redir(struct pci_dev *dev)
812 if (!disable_acs_redir_param)
815 p = disable_acs_redir_param;
817 ret = pci_dev_str_match(dev, p, &p);
819 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
820 disable_acs_redir_param);
823 } else if (ret == 1) {
828 if (*p != ';' && *p != ',') {
829 /* End of param or invalid format */
838 if (!pci_dev_specific_disable_acs_redir(dev))
843 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
847 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
849 /* P2P Request & Completion Redirect */
850 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
852 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
854 pci_info(dev, "disabled ACS redirect\n");
858 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
859 * @dev: the PCI device
861 static void pci_std_enable_acs(struct pci_dev *dev)
871 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
872 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
874 /* Source Validation */
875 ctrl |= (cap & PCI_ACS_SV);
877 /* P2P Request Redirect */
878 ctrl |= (cap & PCI_ACS_RR);
880 /* P2P Completion Redirect */
881 ctrl |= (cap & PCI_ACS_CR);
883 /* Upstream Forwarding */
884 ctrl |= (cap & PCI_ACS_UF);
886 /* Enable Translation Blocking for external devices */
887 if (dev->external_facing || dev->untrusted)
888 ctrl |= (cap & PCI_ACS_TB);
890 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
894 * pci_enable_acs - enable ACS if hardware support it
895 * @dev: the PCI device
897 static void pci_enable_acs(struct pci_dev *dev)
900 goto disable_acs_redir;
902 if (!pci_dev_specific_enable_acs(dev))
903 goto disable_acs_redir;
905 pci_std_enable_acs(dev);
909 * Note: pci_disable_acs_redir() must be called even if ACS was not
910 * enabled by the kernel because it may have been enabled by
911 * platform firmware. So if we are told to disable it, we should
912 * always disable it after setting the kernel's default
915 pci_disable_acs_redir(dev);
919 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
920 * @dev: PCI device to have its BARs restored
922 * Restore the BAR values for a given device, so as to make it
923 * accessible by its driver.
925 static void pci_restore_bars(struct pci_dev *dev)
929 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
930 pci_update_resource(dev, i);
933 static const struct pci_platform_pm_ops *pci_platform_pm;
935 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
937 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
938 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
940 pci_platform_pm = ops;
944 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
946 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
949 static inline int platform_pci_set_power_state(struct pci_dev *dev,
952 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
955 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
957 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
960 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
962 if (pci_platform_pm && pci_platform_pm->refresh_state)
963 pci_platform_pm->refresh_state(dev);
966 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
968 return pci_platform_pm ?
969 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
972 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
974 return pci_platform_pm ?
975 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
978 static inline bool platform_pci_need_resume(struct pci_dev *dev)
980 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
983 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
985 if (pci_platform_pm && pci_platform_pm->bridge_d3)
986 return pci_platform_pm->bridge_d3(dev);
991 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
993 * @dev: PCI device to handle.
994 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
997 * -EINVAL if the requested state is invalid.
998 * -EIO if device does not support PCI PM or its PM capabilities register has a
999 * wrong version, or device doesn't support the requested state.
1000 * 0 if device already is in the requested state.
1001 * 0 if device's power state has been successfully changed.
1003 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1006 bool need_restore = false;
1008 /* Check if we're already there */
1009 if (dev->current_state == state)
1015 if (state < PCI_D0 || state > PCI_D3hot)
1019 * Validate transition: We can enter D0 from any state, but if
1020 * we're already in a low-power state, we can only go deeper. E.g.,
1021 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1022 * we'd have to go from D3 to D0, then to D1.
1024 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1025 && dev->current_state > state) {
1026 pci_err(dev, "invalid power transition (from %s to %s)\n",
1027 pci_power_name(dev->current_state),
1028 pci_power_name(state));
1032 /* Check if this device supports the desired state */
1033 if ((state == PCI_D1 && !dev->d1_support)
1034 || (state == PCI_D2 && !dev->d2_support))
1037 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1038 if (pmcsr == (u16) ~0) {
1039 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1040 pci_power_name(dev->current_state),
1041 pci_power_name(state));
1046 * If we're (effectively) in D3, force entire word to 0.
1047 * This doesn't affect PME_Status, disables PME_En, and
1048 * sets PowerState to 0.
1050 switch (dev->current_state) {
1054 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1059 case PCI_UNKNOWN: /* Boot-up */
1060 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1061 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1062 need_restore = true;
1063 fallthrough; /* force to D0 */
1069 /* Enter specified state */
1070 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1073 * Mandatory power management transition delays; see PCI PM 1.1
1076 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1077 pci_dev_d3_sleep(dev);
1078 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1079 udelay(PCI_PM_D2_DELAY);
1081 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1082 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1083 if (dev->current_state != state)
1084 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1085 pci_power_name(dev->current_state),
1086 pci_power_name(state));
1089 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1090 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1091 * from D3hot to D0 _may_ perform an internal reset, thereby
1092 * going to "D0 Uninitialized" rather than "D0 Initialized".
1093 * For example, at least some versions of the 3c905B and the
1094 * 3c556B exhibit this behaviour.
1096 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1097 * devices in a D3hot state at boot. Consequently, we need to
1098 * restore at least the BARs so that the device will be
1099 * accessible to its driver.
1102 pci_restore_bars(dev);
1105 pcie_aspm_pm_state_change(dev->bus->self);
1111 * pci_update_current_state - Read power state of given device and cache it
1112 * @dev: PCI device to handle.
1113 * @state: State to cache in case the device doesn't have the PM capability
1115 * The power state is read from the PMCSR register, which however is
1116 * inaccessible in D3cold. The platform firmware is therefore queried first
1117 * to detect accessibility of the register. In case the platform firmware
1118 * reports an incorrect state or the device isn't power manageable by the
1119 * platform at all, we try to detect D3cold by testing accessibility of the
1120 * vendor ID in config space.
1122 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1124 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1125 !pci_device_is_present(dev)) {
1126 dev->current_state = PCI_D3cold;
1127 } else if (dev->pm_cap) {
1130 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1131 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1133 dev->current_state = state;
1138 * pci_refresh_power_state - Refresh the given device's power state data
1139 * @dev: Target PCI device.
1141 * Ask the platform to refresh the devices power state information and invoke
1142 * pci_update_current_state() to update its current PCI power state.
1144 void pci_refresh_power_state(struct pci_dev *dev)
1146 if (platform_pci_power_manageable(dev))
1147 platform_pci_refresh_power_state(dev);
1149 pci_update_current_state(dev, dev->current_state);
1153 * pci_platform_power_transition - Use platform to change device power state
1154 * @dev: PCI device to handle.
1155 * @state: State to put the device into.
1157 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1161 if (platform_pci_power_manageable(dev)) {
1162 error = platform_pci_set_power_state(dev, state);
1164 pci_update_current_state(dev, state);
1168 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
1169 dev->current_state = PCI_D0;
1173 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1176 * pci_wakeup - Wake up a PCI device
1177 * @pci_dev: Device to handle.
1178 * @ign: ignored parameter
1180 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1182 pci_wakeup_event(pci_dev);
1183 pm_request_resume(&pci_dev->dev);
1188 * pci_wakeup_bus - Walk given bus and wake up devices on it
1189 * @bus: Top bus of the subtree to walk.
1191 void pci_wakeup_bus(struct pci_bus *bus)
1194 pci_walk_bus(bus, pci_wakeup, NULL);
1197 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1203 * After reset, the device should not silently discard config
1204 * requests, but it may still indicate that it needs more time by
1205 * responding to them with CRS completions. The Root Port will
1206 * generally synthesize ~0 data to complete the read (except when
1207 * CRS SV is enabled and the read was for the Vendor ID; in that
1208 * case it synthesizes 0x0001 data).
1210 * Wait for the device to return a non-CRS completion. Read the
1211 * Command register instead of Vendor ID so we don't have to
1212 * contend with the CRS SV value.
1214 pci_read_config_dword(dev, PCI_COMMAND, &id);
1216 if (delay > timeout) {
1217 pci_warn(dev, "not ready %dms after %s; giving up\n",
1218 delay - 1, reset_type);
1222 if (delay > PCI_RESET_WAIT)
1223 pci_info(dev, "not ready %dms after %s; waiting\n",
1224 delay - 1, reset_type);
1228 pci_read_config_dword(dev, PCI_COMMAND, &id);
1231 if (delay > PCI_RESET_WAIT)
1232 pci_info(dev, "ready %dms after %s\n", delay - 1,
1239 * pci_power_up - Put the given device into D0
1240 * @dev: PCI device to power up
1242 int pci_power_up(struct pci_dev *dev)
1244 pci_platform_power_transition(dev, PCI_D0);
1247 * Mandatory power management transition delays are handled in
1248 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1249 * corresponding bridge.
1251 if (dev->runtime_d3cold) {
1253 * When powering on a bridge from D3cold, the whole hierarchy
1254 * may be powered on into D0uninitialized state, resume them to
1255 * give them a chance to suspend again
1257 pci_wakeup_bus(dev->subordinate);
1260 return pci_raw_set_power_state(dev, PCI_D0);
1264 * __pci_dev_set_current_state - Set current state of a PCI device
1265 * @dev: Device to handle
1266 * @data: pointer to state to be set
1268 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1270 pci_power_t state = *(pci_power_t *)data;
1272 dev->current_state = state;
1277 * pci_bus_set_current_state - Walk given bus and set current state of devices
1278 * @bus: Top bus of the subtree to walk.
1279 * @state: state to be set
1281 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1284 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1288 * pci_set_power_state - Set the power state of a PCI device
1289 * @dev: PCI device to handle.
1290 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1292 * Transition a device to a new power state, using the platform firmware and/or
1293 * the device's PCI PM registers.
1296 * -EINVAL if the requested state is invalid.
1297 * -EIO if device does not support PCI PM or its PM capabilities register has a
1298 * wrong version, or device doesn't support the requested state.
1299 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1300 * 0 if device already is in the requested state.
1301 * 0 if the transition is to D3 but D3 is not supported.
1302 * 0 if device's power state has been successfully changed.
1304 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1308 /* Bound the state we're entering */
1309 if (state > PCI_D3cold)
1311 else if (state < PCI_D0)
1313 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1316 * If the device or the parent bridge do not support PCI
1317 * PM, ignore the request if we're doing anything other
1318 * than putting it into D0 (which would only happen on
1323 /* Check if we're already there */
1324 if (dev->current_state == state)
1327 if (state == PCI_D0)
1328 return pci_power_up(dev);
1331 * This device is quirked not to be put into D3, so don't put it in
1334 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1338 * To put device in D3cold, we put device into D3hot in native
1339 * way, then put device into D3cold with platform ops
1341 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1344 if (pci_platform_power_transition(dev, state))
1347 /* Powering off a bridge may power off the whole hierarchy */
1348 if (state == PCI_D3cold)
1349 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1353 EXPORT_SYMBOL(pci_set_power_state);
1356 * pci_choose_state - Choose the power state of a PCI device
1357 * @dev: PCI device to be suspended
1358 * @state: target sleep state for the whole system. This is the value
1359 * that is passed to suspend() function.
1361 * Returns PCI power state suitable for given device and given system
1364 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1371 ret = platform_pci_choose_state(dev);
1372 if (ret != PCI_POWER_ERROR)
1375 switch (state.event) {
1378 case PM_EVENT_FREEZE:
1379 case PM_EVENT_PRETHAW:
1380 /* REVISIT both freeze and pre-thaw "should" use D0 */
1381 case PM_EVENT_SUSPEND:
1382 case PM_EVENT_HIBERNATE:
1385 pci_info(dev, "unrecognized suspend event %d\n",
1391 EXPORT_SYMBOL(pci_choose_state);
1393 #define PCI_EXP_SAVE_REGS 7
1395 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1396 u16 cap, bool extended)
1398 struct pci_cap_saved_state *tmp;
1400 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1401 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1407 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1409 return _pci_find_saved_cap(dev, cap, false);
1412 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1414 return _pci_find_saved_cap(dev, cap, true);
1417 static int pci_save_pcie_state(struct pci_dev *dev)
1420 struct pci_cap_saved_state *save_state;
1423 if (!pci_is_pcie(dev))
1426 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1428 pci_err(dev, "buffer not found in %s\n", __func__);
1432 cap = (u16 *)&save_state->cap.data[0];
1433 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1434 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1435 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1436 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1437 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1438 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1439 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1444 static void pci_restore_pcie_state(struct pci_dev *dev)
1447 struct pci_cap_saved_state *save_state;
1450 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1454 cap = (u16 *)&save_state->cap.data[0];
1455 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1456 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1457 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1458 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1459 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1460 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1461 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1464 static int pci_save_pcix_state(struct pci_dev *dev)
1467 struct pci_cap_saved_state *save_state;
1469 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1473 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1475 pci_err(dev, "buffer not found in %s\n", __func__);
1479 pci_read_config_word(dev, pos + PCI_X_CMD,
1480 (u16 *)save_state->cap.data);
1485 static void pci_restore_pcix_state(struct pci_dev *dev)
1488 struct pci_cap_saved_state *save_state;
1491 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1492 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1493 if (!save_state || !pos)
1495 cap = (u16 *)&save_state->cap.data[0];
1497 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1500 static void pci_save_ltr_state(struct pci_dev *dev)
1503 struct pci_cap_saved_state *save_state;
1506 if (!pci_is_pcie(dev))
1509 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1513 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1515 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1519 cap = (u16 *)&save_state->cap.data[0];
1520 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1521 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1524 static void pci_restore_ltr_state(struct pci_dev *dev)
1526 struct pci_cap_saved_state *save_state;
1530 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1531 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1532 if (!save_state || !ltr)
1535 cap = (u16 *)&save_state->cap.data[0];
1536 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1537 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1541 * pci_save_state - save the PCI configuration space of a device before
1543 * @dev: PCI device that we're dealing with
1545 int pci_save_state(struct pci_dev *dev)
1548 /* XXX: 100% dword access ok here? */
1549 for (i = 0; i < 16; i++) {
1550 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1551 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1552 i * 4, dev->saved_config_space[i]);
1554 dev->state_saved = true;
1556 i = pci_save_pcie_state(dev);
1560 i = pci_save_pcix_state(dev);
1564 pci_save_ltr_state(dev);
1565 pci_save_dpc_state(dev);
1566 pci_save_aer_state(dev);
1567 return pci_save_vc_state(dev);
1569 EXPORT_SYMBOL(pci_save_state);
1571 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1572 u32 saved_val, int retry, bool force)
1576 pci_read_config_dword(pdev, offset, &val);
1577 if (!force && val == saved_val)
1581 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1582 offset, val, saved_val);
1583 pci_write_config_dword(pdev, offset, saved_val);
1587 pci_read_config_dword(pdev, offset, &val);
1588 if (val == saved_val)
1595 static void pci_restore_config_space_range(struct pci_dev *pdev,
1596 int start, int end, int retry,
1601 for (index = end; index >= start; index--)
1602 pci_restore_config_dword(pdev, 4 * index,
1603 pdev->saved_config_space[index],
1607 static void pci_restore_config_space(struct pci_dev *pdev)
1609 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1610 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1611 /* Restore BARs before the command register. */
1612 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1613 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1614 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1615 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1618 * Force rewriting of prefetch registers to avoid S3 resume
1619 * issues on Intel PCI bridges that occur when these
1620 * registers are not explicitly written.
1622 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1623 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1625 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1629 static void pci_restore_rebar_state(struct pci_dev *pdev)
1631 unsigned int pos, nbars, i;
1634 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1638 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1639 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1640 PCI_REBAR_CTRL_NBAR_SHIFT;
1642 for (i = 0; i < nbars; i++, pos += 8) {
1643 struct resource *res;
1646 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1647 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1648 res = pdev->resource + bar_idx;
1649 size = ilog2(resource_size(res)) - 20;
1650 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1651 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1652 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1657 * pci_restore_state - Restore the saved state of a PCI device
1658 * @dev: PCI device that we're dealing with
1660 void pci_restore_state(struct pci_dev *dev)
1662 if (!dev->state_saved)
1666 * Restore max latencies (in the LTR capability) before enabling
1667 * LTR itself (in the PCIe capability).
1669 pci_restore_ltr_state(dev);
1671 pci_restore_pcie_state(dev);
1672 pci_restore_pasid_state(dev);
1673 pci_restore_pri_state(dev);
1674 pci_restore_ats_state(dev);
1675 pci_restore_vc_state(dev);
1676 pci_restore_rebar_state(dev);
1677 pci_restore_dpc_state(dev);
1679 pci_aer_clear_status(dev);
1680 pci_restore_aer_state(dev);
1682 pci_restore_config_space(dev);
1684 pci_restore_pcix_state(dev);
1685 pci_restore_msi_state(dev);
1687 /* Restore ACS and IOV configuration state */
1688 pci_enable_acs(dev);
1689 pci_restore_iov_state(dev);
1691 dev->state_saved = false;
1693 EXPORT_SYMBOL(pci_restore_state);
1695 struct pci_saved_state {
1696 u32 config_space[16];
1697 struct pci_cap_saved_data cap[];
1701 * pci_store_saved_state - Allocate and return an opaque struct containing
1702 * the device saved state.
1703 * @dev: PCI device that we're dealing with
1705 * Return NULL if no state or error.
1707 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1709 struct pci_saved_state *state;
1710 struct pci_cap_saved_state *tmp;
1711 struct pci_cap_saved_data *cap;
1714 if (!dev->state_saved)
1717 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1719 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1720 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1722 state = kzalloc(size, GFP_KERNEL);
1726 memcpy(state->config_space, dev->saved_config_space,
1727 sizeof(state->config_space));
1730 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1731 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1732 memcpy(cap, &tmp->cap, len);
1733 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1735 /* Empty cap_save terminates list */
1739 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1742 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1743 * @dev: PCI device that we're dealing with
1744 * @state: Saved state returned from pci_store_saved_state()
1746 int pci_load_saved_state(struct pci_dev *dev,
1747 struct pci_saved_state *state)
1749 struct pci_cap_saved_data *cap;
1751 dev->state_saved = false;
1756 memcpy(dev->saved_config_space, state->config_space,
1757 sizeof(state->config_space));
1761 struct pci_cap_saved_state *tmp;
1763 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1764 if (!tmp || tmp->cap.size != cap->size)
1767 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1768 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1769 sizeof(struct pci_cap_saved_data) + cap->size);
1772 dev->state_saved = true;
1775 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1778 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1779 * and free the memory allocated for it.
1780 * @dev: PCI device that we're dealing with
1781 * @state: Pointer to saved state returned from pci_store_saved_state()
1783 int pci_load_and_free_saved_state(struct pci_dev *dev,
1784 struct pci_saved_state **state)
1786 int ret = pci_load_saved_state(dev, *state);
1791 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1793 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1795 return pci_enable_resources(dev, bars);
1798 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1801 struct pci_dev *bridge;
1805 err = pci_set_power_state(dev, PCI_D0);
1806 if (err < 0 && err != -EIO)
1809 bridge = pci_upstream_bridge(dev);
1811 pcie_aspm_powersave_config_link(bridge);
1813 err = pcibios_enable_device(dev, bars);
1816 pci_fixup_device(pci_fixup_enable, dev);
1818 if (dev->msi_enabled || dev->msix_enabled)
1821 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1823 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1824 if (cmd & PCI_COMMAND_INTX_DISABLE)
1825 pci_write_config_word(dev, PCI_COMMAND,
1826 cmd & ~PCI_COMMAND_INTX_DISABLE);
1833 * pci_reenable_device - Resume abandoned device
1834 * @dev: PCI device to be resumed
1836 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1837 * to be called by normal code, write proper resume handler and use it instead.
1839 int pci_reenable_device(struct pci_dev *dev)
1841 if (pci_is_enabled(dev))
1842 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1845 EXPORT_SYMBOL(pci_reenable_device);
1847 static void pci_enable_bridge(struct pci_dev *dev)
1849 struct pci_dev *bridge;
1852 bridge = pci_upstream_bridge(dev);
1854 pci_enable_bridge(bridge);
1856 if (pci_is_enabled(dev)) {
1857 if (!dev->is_busmaster)
1858 pci_set_master(dev);
1862 retval = pci_enable_device(dev);
1864 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1866 pci_set_master(dev);
1869 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1871 struct pci_dev *bridge;
1876 * Power state could be unknown at this point, either due to a fresh
1877 * boot or a device removal call. So get the current power state
1878 * so that things like MSI message writing will behave as expected
1879 * (e.g. if the device really is in D0 at enable time).
1881 pci_update_current_state(dev, dev->current_state);
1883 if (atomic_inc_return(&dev->enable_cnt) > 1)
1884 return 0; /* already enabled */
1886 bridge = pci_upstream_bridge(dev);
1888 pci_enable_bridge(bridge);
1890 /* only skip sriov related */
1891 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1892 if (dev->resource[i].flags & flags)
1894 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1895 if (dev->resource[i].flags & flags)
1898 err = do_pci_enable_device(dev, bars);
1900 atomic_dec(&dev->enable_cnt);
1905 * pci_enable_device_io - Initialize a device for use with IO space
1906 * @dev: PCI device to be initialized
1908 * Initialize device before it's used by a driver. Ask low-level code
1909 * to enable I/O resources. Wake up the device if it was suspended.
1910 * Beware, this function can fail.
1912 int pci_enable_device_io(struct pci_dev *dev)
1914 return pci_enable_device_flags(dev, IORESOURCE_IO);
1916 EXPORT_SYMBOL(pci_enable_device_io);
1919 * pci_enable_device_mem - Initialize a device for use with Memory space
1920 * @dev: PCI device to be initialized
1922 * Initialize device before it's used by a driver. Ask low-level code
1923 * to enable Memory resources. Wake up the device if it was suspended.
1924 * Beware, this function can fail.
1926 int pci_enable_device_mem(struct pci_dev *dev)
1928 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1930 EXPORT_SYMBOL(pci_enable_device_mem);
1933 * pci_enable_device - Initialize device before it's used by a driver.
1934 * @dev: PCI device to be initialized
1936 * Initialize device before it's used by a driver. Ask low-level code
1937 * to enable I/O and memory. Wake up the device if it was suspended.
1938 * Beware, this function can fail.
1940 * Note we don't actually enable the device many times if we call
1941 * this function repeatedly (we just increment the count).
1943 int pci_enable_device(struct pci_dev *dev)
1945 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1947 EXPORT_SYMBOL(pci_enable_device);
1950 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1951 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1952 * there's no need to track it separately. pci_devres is initialized
1953 * when a device is enabled using managed PCI device enable interface.
1956 unsigned int enabled:1;
1957 unsigned int pinned:1;
1958 unsigned int orig_intx:1;
1959 unsigned int restore_intx:1;
1964 static void pcim_release(struct device *gendev, void *res)
1966 struct pci_dev *dev = to_pci_dev(gendev);
1967 struct pci_devres *this = res;
1970 if (dev->msi_enabled)
1971 pci_disable_msi(dev);
1972 if (dev->msix_enabled)
1973 pci_disable_msix(dev);
1975 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1976 if (this->region_mask & (1 << i))
1977 pci_release_region(dev, i);
1982 if (this->restore_intx)
1983 pci_intx(dev, this->orig_intx);
1985 if (this->enabled && !this->pinned)
1986 pci_disable_device(dev);
1989 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1991 struct pci_devres *dr, *new_dr;
1993 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1997 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2000 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2003 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2005 if (pci_is_managed(pdev))
2006 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2011 * pcim_enable_device - Managed pci_enable_device()
2012 * @pdev: PCI device to be initialized
2014 * Managed pci_enable_device().
2016 int pcim_enable_device(struct pci_dev *pdev)
2018 struct pci_devres *dr;
2021 dr = get_pci_dr(pdev);
2027 rc = pci_enable_device(pdev);
2029 pdev->is_managed = 1;
2034 EXPORT_SYMBOL(pcim_enable_device);
2037 * pcim_pin_device - Pin managed PCI device
2038 * @pdev: PCI device to pin
2040 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2041 * driver detach. @pdev must have been enabled with
2042 * pcim_enable_device().
2044 void pcim_pin_device(struct pci_dev *pdev)
2046 struct pci_devres *dr;
2048 dr = find_pci_dr(pdev);
2049 WARN_ON(!dr || !dr->enabled);
2053 EXPORT_SYMBOL(pcim_pin_device);
2056 * pcibios_add_device - provide arch specific hooks when adding device dev
2057 * @dev: the PCI device being added
2059 * Permits the platform to provide architecture specific functionality when
2060 * devices are added. This is the default implementation. Architecture
2061 * implementations can override this.
2063 int __weak pcibios_add_device(struct pci_dev *dev)
2069 * pcibios_release_device - provide arch specific hooks when releasing
2071 * @dev: the PCI device being released
2073 * Permits the platform to provide architecture specific functionality when
2074 * devices are released. This is the default implementation. Architecture
2075 * implementations can override this.
2077 void __weak pcibios_release_device(struct pci_dev *dev) {}
2080 * pcibios_disable_device - disable arch specific PCI resources for device dev
2081 * @dev: the PCI device to disable
2083 * Disables architecture specific PCI resources for the device. This
2084 * is the default implementation. Architecture implementations can
2087 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2090 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2091 * @irq: ISA IRQ to penalize
2092 * @active: IRQ active or not
2094 * Permits the platform to provide architecture-specific functionality when
2095 * penalizing ISA IRQs. This is the default implementation. Architecture
2096 * implementations can override this.
2098 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2100 static void do_pci_disable_device(struct pci_dev *dev)
2104 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2105 if (pci_command & PCI_COMMAND_MASTER) {
2106 pci_command &= ~PCI_COMMAND_MASTER;
2107 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2110 pcibios_disable_device(dev);
2114 * pci_disable_enabled_device - Disable device without updating enable_cnt
2115 * @dev: PCI device to disable
2117 * NOTE: This function is a backend of PCI power management routines and is
2118 * not supposed to be called drivers.
2120 void pci_disable_enabled_device(struct pci_dev *dev)
2122 if (pci_is_enabled(dev))
2123 do_pci_disable_device(dev);
2127 * pci_disable_device - Disable PCI device after use
2128 * @dev: PCI device to be disabled
2130 * Signal to the system that the PCI device is not in use by the system
2131 * anymore. This only involves disabling PCI bus-mastering, if active.
2133 * Note we don't actually disable the device until all callers of
2134 * pci_enable_device() have called pci_disable_device().
2136 void pci_disable_device(struct pci_dev *dev)
2138 struct pci_devres *dr;
2140 dr = find_pci_dr(dev);
2144 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2145 "disabling already-disabled device");
2147 if (atomic_dec_return(&dev->enable_cnt) != 0)
2150 do_pci_disable_device(dev);
2152 dev->is_busmaster = 0;
2154 EXPORT_SYMBOL(pci_disable_device);
2157 * pcibios_set_pcie_reset_state - set reset state for device dev
2158 * @dev: the PCIe device reset
2159 * @state: Reset state to enter into
2161 * Set the PCIe reset state for the device. This is the default
2162 * implementation. Architecture implementations can override this.
2164 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2165 enum pcie_reset_state state)
2171 * pci_set_pcie_reset_state - set reset state for device dev
2172 * @dev: the PCIe device reset
2173 * @state: Reset state to enter into
2175 * Sets the PCI reset state for the device.
2177 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2179 return pcibios_set_pcie_reset_state(dev, state);
2181 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2183 void pcie_clear_device_status(struct pci_dev *dev)
2187 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2188 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2192 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2193 * @dev: PCIe root port or event collector.
2195 void pcie_clear_root_pme_status(struct pci_dev *dev)
2197 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2201 * pci_check_pme_status - Check if given device has generated PME.
2202 * @dev: Device to check.
2204 * Check the PME status of the device and if set, clear it and clear PME enable
2205 * (if set). Return 'true' if PME status and PME enable were both set or
2206 * 'false' otherwise.
2208 bool pci_check_pme_status(struct pci_dev *dev)
2217 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2218 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2219 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2222 /* Clear PME status. */
2223 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2224 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2225 /* Disable PME to avoid interrupt flood. */
2226 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2230 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2236 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2237 * @dev: Device to handle.
2238 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2240 * Check if @dev has generated PME and queue a resume request for it in that
2243 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2245 if (pme_poll_reset && dev->pme_poll)
2246 dev->pme_poll = false;
2248 if (pci_check_pme_status(dev)) {
2249 pci_wakeup_event(dev);
2250 pm_request_resume(&dev->dev);
2256 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2257 * @bus: Top bus of the subtree to walk.
2259 void pci_pme_wakeup_bus(struct pci_bus *bus)
2262 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2267 * pci_pme_capable - check the capability of PCI device to generate PME#
2268 * @dev: PCI device to handle.
2269 * @state: PCI state from which device will issue PME#.
2271 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2276 return !!(dev->pme_support & (1 << state));
2278 EXPORT_SYMBOL(pci_pme_capable);
2280 static void pci_pme_list_scan(struct work_struct *work)
2282 struct pci_pme_device *pme_dev, *n;
2284 mutex_lock(&pci_pme_list_mutex);
2285 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2286 if (pme_dev->dev->pme_poll) {
2287 struct pci_dev *bridge;
2289 bridge = pme_dev->dev->bus->self;
2291 * If bridge is in low power state, the
2292 * configuration space of subordinate devices
2293 * may be not accessible
2295 if (bridge && bridge->current_state != PCI_D0)
2298 * If the device is in D3cold it should not be
2301 if (pme_dev->dev->current_state == PCI_D3cold)
2304 pci_pme_wakeup(pme_dev->dev, NULL);
2306 list_del(&pme_dev->list);
2310 if (!list_empty(&pci_pme_list))
2311 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2312 msecs_to_jiffies(PME_TIMEOUT));
2313 mutex_unlock(&pci_pme_list_mutex);
2316 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2320 if (!dev->pme_support)
2323 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2324 /* Clear PME_Status by writing 1 to it and enable PME# */
2325 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2327 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2329 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2333 * pci_pme_restore - Restore PME configuration after config space restore.
2334 * @dev: PCI device to update.
2336 void pci_pme_restore(struct pci_dev *dev)
2340 if (!dev->pme_support)
2343 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2344 if (dev->wakeup_prepared) {
2345 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2346 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2348 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2349 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2351 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2355 * pci_pme_active - enable or disable PCI device's PME# function
2356 * @dev: PCI device to handle.
2357 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2359 * The caller must verify that the device is capable of generating PME# before
2360 * calling this function with @enable equal to 'true'.
2362 void pci_pme_active(struct pci_dev *dev, bool enable)
2364 __pci_pme_active(dev, enable);
2367 * PCI (as opposed to PCIe) PME requires that the device have
2368 * its PME# line hooked up correctly. Not all hardware vendors
2369 * do this, so the PME never gets delivered and the device
2370 * remains asleep. The easiest way around this is to
2371 * periodically walk the list of suspended devices and check
2372 * whether any have their PME flag set. The assumption is that
2373 * we'll wake up often enough anyway that this won't be a huge
2374 * hit, and the power savings from the devices will still be a
2377 * Although PCIe uses in-band PME message instead of PME# line
2378 * to report PME, PME does not work for some PCIe devices in
2379 * reality. For example, there are devices that set their PME
2380 * status bits, but don't really bother to send a PME message;
2381 * there are PCI Express Root Ports that don't bother to
2382 * trigger interrupts when they receive PME messages from the
2383 * devices below. So PME poll is used for PCIe devices too.
2386 if (dev->pme_poll) {
2387 struct pci_pme_device *pme_dev;
2389 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2392 pci_warn(dev, "can't enable PME#\n");
2396 mutex_lock(&pci_pme_list_mutex);
2397 list_add(&pme_dev->list, &pci_pme_list);
2398 if (list_is_singular(&pci_pme_list))
2399 queue_delayed_work(system_freezable_wq,
2401 msecs_to_jiffies(PME_TIMEOUT));
2402 mutex_unlock(&pci_pme_list_mutex);
2404 mutex_lock(&pci_pme_list_mutex);
2405 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2406 if (pme_dev->dev == dev) {
2407 list_del(&pme_dev->list);
2412 mutex_unlock(&pci_pme_list_mutex);
2416 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2418 EXPORT_SYMBOL(pci_pme_active);
2421 * __pci_enable_wake - enable PCI device as wakeup event source
2422 * @dev: PCI device affected
2423 * @state: PCI state from which device will issue wakeup events
2424 * @enable: True to enable event generation; false to disable
2426 * This enables the device as a wakeup event source, or disables it.
2427 * When such events involves platform-specific hooks, those hooks are
2428 * called automatically by this routine.
2430 * Devices with legacy power management (no standard PCI PM capabilities)
2431 * always require such platform hooks.
2434 * 0 is returned on success
2435 * -EINVAL is returned if device is not supposed to wake up the system
2436 * Error code depending on the platform is returned if both the platform and
2437 * the native mechanism fail to enable the generation of wake-up events
2439 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2444 * Bridges that are not power-manageable directly only signal
2445 * wakeup on behalf of subordinate devices which is set up
2446 * elsewhere, so skip them. However, bridges that are
2447 * power-manageable may signal wakeup for themselves (for example,
2448 * on a hotplug event) and they need to be covered here.
2450 if (!pci_power_manageable(dev))
2453 /* Don't do the same thing twice in a row for one device. */
2454 if (!!enable == !!dev->wakeup_prepared)
2458 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2459 * Anderson we should be doing PME# wake enable followed by ACPI wake
2460 * enable. To disable wake-up we call the platform first, for symmetry.
2467 * Enable PME signaling if the device can signal PME from
2468 * D3cold regardless of whether or not it can signal PME from
2469 * the current target state, because that will allow it to
2470 * signal PME when the hierarchy above it goes into D3cold and
2471 * the device itself ends up in D3cold as a result of that.
2473 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2474 pci_pme_active(dev, true);
2477 error = platform_pci_set_wakeup(dev, true);
2481 dev->wakeup_prepared = true;
2483 platform_pci_set_wakeup(dev, false);
2484 pci_pme_active(dev, false);
2485 dev->wakeup_prepared = false;
2492 * pci_enable_wake - change wakeup settings for a PCI device
2493 * @pci_dev: Target device
2494 * @state: PCI state from which device will issue wakeup events
2495 * @enable: Whether or not to enable event generation
2497 * If @enable is set, check device_may_wakeup() for the device before calling
2498 * __pci_enable_wake() for it.
2500 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2502 if (enable && !device_may_wakeup(&pci_dev->dev))
2505 return __pci_enable_wake(pci_dev, state, enable);
2507 EXPORT_SYMBOL(pci_enable_wake);
2510 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2511 * @dev: PCI device to prepare
2512 * @enable: True to enable wake-up event generation; false to disable
2514 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2515 * and this function allows them to set that up cleanly - pci_enable_wake()
2516 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2517 * ordering constraints.
2519 * This function only returns error code if the device is not allowed to wake
2520 * up the system from sleep or it is not capable of generating PME# from both
2521 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2523 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2525 return pci_pme_capable(dev, PCI_D3cold) ?
2526 pci_enable_wake(dev, PCI_D3cold, enable) :
2527 pci_enable_wake(dev, PCI_D3hot, enable);
2529 EXPORT_SYMBOL(pci_wake_from_d3);
2532 * pci_target_state - find an appropriate low power state for a given PCI dev
2534 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2536 * Use underlying platform code to find a supported low power state for @dev.
2537 * If the platform can't manage @dev, return the deepest state from which it
2538 * can generate wake events, based on any available PME info.
2540 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2542 pci_power_t target_state = PCI_D3hot;
2544 if (platform_pci_power_manageable(dev)) {
2546 * Call the platform to find the target state for the device.
2548 pci_power_t state = platform_pci_choose_state(dev);
2551 case PCI_POWER_ERROR:
2556 if (pci_no_d1d2(dev))
2560 target_state = state;
2563 return target_state;
2567 target_state = PCI_D0;
2570 * If the device is in D3cold even though it's not power-manageable by
2571 * the platform, it may have been powered down by non-standard means.
2572 * Best to let it slumber.
2574 if (dev->current_state == PCI_D3cold)
2575 target_state = PCI_D3cold;
2577 if (wakeup && dev->pme_support) {
2578 pci_power_t state = target_state;
2581 * Find the deepest state from which the device can generate
2584 while (state && !(dev->pme_support & (1 << state)))
2589 else if (dev->pme_support & 1)
2593 return target_state;
2597 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2598 * into a sleep state
2599 * @dev: Device to handle.
2601 * Choose the power state appropriate for the device depending on whether
2602 * it can wake up the system and/or is power manageable by the platform
2603 * (PCI_D3hot is the default) and put the device into that state.
2605 int pci_prepare_to_sleep(struct pci_dev *dev)
2607 bool wakeup = device_may_wakeup(&dev->dev);
2608 pci_power_t target_state = pci_target_state(dev, wakeup);
2611 if (target_state == PCI_POWER_ERROR)
2614 pci_enable_wake(dev, target_state, wakeup);
2616 error = pci_set_power_state(dev, target_state);
2619 pci_enable_wake(dev, target_state, false);
2623 EXPORT_SYMBOL(pci_prepare_to_sleep);
2626 * pci_back_from_sleep - turn PCI device on during system-wide transition
2627 * into working state
2628 * @dev: Device to handle.
2630 * Disable device's system wake-up capability and put it into D0.
2632 int pci_back_from_sleep(struct pci_dev *dev)
2634 pci_enable_wake(dev, PCI_D0, false);
2635 return pci_set_power_state(dev, PCI_D0);
2637 EXPORT_SYMBOL(pci_back_from_sleep);
2640 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2641 * @dev: PCI device being suspended.
2643 * Prepare @dev to generate wake-up events at run time and put it into a low
2646 int pci_finish_runtime_suspend(struct pci_dev *dev)
2648 pci_power_t target_state;
2651 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2652 if (target_state == PCI_POWER_ERROR)
2655 dev->runtime_d3cold = target_state == PCI_D3cold;
2657 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2659 error = pci_set_power_state(dev, target_state);
2662 pci_enable_wake(dev, target_state, false);
2663 dev->runtime_d3cold = false;
2670 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2671 * @dev: Device to check.
2673 * Return true if the device itself is capable of generating wake-up events
2674 * (through the platform or using the native PCIe PME) or if the device supports
2675 * PME and one of its upstream bridges can generate wake-up events.
2677 bool pci_dev_run_wake(struct pci_dev *dev)
2679 struct pci_bus *bus = dev->bus;
2681 if (!dev->pme_support)
2684 /* PME-capable in principle, but not from the target power state */
2685 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2688 if (device_can_wakeup(&dev->dev))
2691 while (bus->parent) {
2692 struct pci_dev *bridge = bus->self;
2694 if (device_can_wakeup(&bridge->dev))
2700 /* We have reached the root bus. */
2702 return device_can_wakeup(bus->bridge);
2706 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2709 * pci_dev_need_resume - Check if it is necessary to resume the device.
2710 * @pci_dev: Device to check.
2712 * Return 'true' if the device is not runtime-suspended or it has to be
2713 * reconfigured due to wakeup settings difference between system and runtime
2714 * suspend, or the current power state of it is not suitable for the upcoming
2715 * (system-wide) transition.
2717 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2719 struct device *dev = &pci_dev->dev;
2720 pci_power_t target_state;
2722 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2725 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2728 * If the earlier platform check has not triggered, D3cold is just power
2729 * removal on top of D3hot, so no need to resume the device in that
2732 return target_state != pci_dev->current_state &&
2733 target_state != PCI_D3cold &&
2734 pci_dev->current_state != PCI_D3hot;
2738 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2739 * @pci_dev: Device to check.
2741 * If the device is suspended and it is not configured for system wakeup,
2742 * disable PME for it to prevent it from waking up the system unnecessarily.
2744 * Note that if the device's power state is D3cold and the platform check in
2745 * pci_dev_need_resume() has not triggered, the device's configuration need not
2748 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2750 struct device *dev = &pci_dev->dev;
2752 spin_lock_irq(&dev->power.lock);
2754 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2755 pci_dev->current_state < PCI_D3cold)
2756 __pci_pme_active(pci_dev, false);
2758 spin_unlock_irq(&dev->power.lock);
2762 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2763 * @pci_dev: Device to handle.
2765 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2766 * it might have been disabled during the prepare phase of system suspend if
2767 * the device was not configured for system wakeup.
2769 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2771 struct device *dev = &pci_dev->dev;
2773 if (!pci_dev_run_wake(pci_dev))
2776 spin_lock_irq(&dev->power.lock);
2778 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2779 __pci_pme_active(pci_dev, true);
2781 spin_unlock_irq(&dev->power.lock);
2784 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2786 struct device *dev = &pdev->dev;
2787 struct device *parent = dev->parent;
2790 pm_runtime_get_sync(parent);
2791 pm_runtime_get_noresume(dev);
2793 * pdev->current_state is set to PCI_D3cold during suspending,
2794 * so wait until suspending completes
2796 pm_runtime_barrier(dev);
2798 * Only need to resume devices in D3cold, because config
2799 * registers are still accessible for devices suspended but
2802 if (pdev->current_state == PCI_D3cold)
2803 pm_runtime_resume(dev);
2806 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2808 struct device *dev = &pdev->dev;
2809 struct device *parent = dev->parent;
2811 pm_runtime_put(dev);
2813 pm_runtime_put_sync(parent);
2816 static const struct dmi_system_id bridge_d3_blacklist[] = {
2820 * Gigabyte X299 root port is not marked as hotplug capable
2821 * which allows Linux to power manage it. However, this
2822 * confuses the BIOS SMI handler so don't power manage root
2823 * ports on that system.
2825 .ident = "X299 DESIGNARE EX-CF",
2827 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2828 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2833 * Downstream device is not accessible after putting a root port
2834 * into D3cold and back into D0 on Elo Continental Z2 board
2836 .ident = "Elo Continental Z2",
2838 DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"),
2839 DMI_MATCH(DMI_BOARD_NAME, "Geminilake"),
2840 DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"),
2848 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2849 * @bridge: Bridge to check
2851 * This function checks if it is possible to move the bridge to D3.
2852 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2854 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2856 if (!pci_is_pcie(bridge))
2859 switch (pci_pcie_type(bridge)) {
2860 case PCI_EXP_TYPE_ROOT_PORT:
2861 case PCI_EXP_TYPE_UPSTREAM:
2862 case PCI_EXP_TYPE_DOWNSTREAM:
2863 if (pci_bridge_d3_disable)
2867 * Hotplug ports handled by firmware in System Management Mode
2868 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2870 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2873 if (pci_bridge_d3_force)
2876 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2877 if (bridge->is_thunderbolt)
2880 /* Platform might know better if the bridge supports D3 */
2881 if (platform_pci_bridge_d3(bridge))
2885 * Hotplug ports handled natively by the OS were not validated
2886 * by vendors for runtime D3 at least until 2018 because there
2887 * was no OS support.
2889 if (bridge->is_hotplug_bridge)
2892 if (dmi_check_system(bridge_d3_blacklist))
2896 * It should be safe to put PCIe ports from 2015 or newer
2899 if (dmi_get_bios_year() >= 2015)
2907 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2909 bool *d3cold_ok = data;
2911 if (/* The device needs to be allowed to go D3cold ... */
2912 dev->no_d3cold || !dev->d3cold_allowed ||
2914 /* ... and if it is wakeup capable to do so from D3cold. */
2915 (device_may_wakeup(&dev->dev) &&
2916 !pci_pme_capable(dev, PCI_D3cold)) ||
2918 /* If it is a bridge it must be allowed to go to D3. */
2919 !pci_power_manageable(dev))
2927 * pci_bridge_d3_update - Update bridge D3 capabilities
2928 * @dev: PCI device which is changed
2930 * Update upstream bridge PM capabilities accordingly depending on if the
2931 * device PM configuration was changed or the device is being removed. The
2932 * change is also propagated upstream.
2934 void pci_bridge_d3_update(struct pci_dev *dev)
2936 bool remove = !device_is_registered(&dev->dev);
2937 struct pci_dev *bridge;
2938 bool d3cold_ok = true;
2940 bridge = pci_upstream_bridge(dev);
2941 if (!bridge || !pci_bridge_d3_possible(bridge))
2945 * If D3 is currently allowed for the bridge, removing one of its
2946 * children won't change that.
2948 if (remove && bridge->bridge_d3)
2952 * If D3 is currently allowed for the bridge and a child is added or
2953 * changed, disallowance of D3 can only be caused by that child, so
2954 * we only need to check that single device, not any of its siblings.
2956 * If D3 is currently not allowed for the bridge, checking the device
2957 * first may allow us to skip checking its siblings.
2960 pci_dev_check_d3cold(dev, &d3cold_ok);
2963 * If D3 is currently not allowed for the bridge, this may be caused
2964 * either by the device being changed/removed or any of its siblings,
2965 * so we need to go through all children to find out if one of them
2966 * continues to block D3.
2968 if (d3cold_ok && !bridge->bridge_d3)
2969 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2972 if (bridge->bridge_d3 != d3cold_ok) {
2973 bridge->bridge_d3 = d3cold_ok;
2974 /* Propagate change to upstream bridges */
2975 pci_bridge_d3_update(bridge);
2980 * pci_d3cold_enable - Enable D3cold for device
2981 * @dev: PCI device to handle
2983 * This function can be used in drivers to enable D3cold from the device
2984 * they handle. It also updates upstream PCI bridge PM capabilities
2987 void pci_d3cold_enable(struct pci_dev *dev)
2989 if (dev->no_d3cold) {
2990 dev->no_d3cold = false;
2991 pci_bridge_d3_update(dev);
2994 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2997 * pci_d3cold_disable - Disable D3cold for device
2998 * @dev: PCI device to handle
3000 * This function can be used in drivers to disable D3cold from the device
3001 * they handle. It also updates upstream PCI bridge PM capabilities
3004 void pci_d3cold_disable(struct pci_dev *dev)
3006 if (!dev->no_d3cold) {
3007 dev->no_d3cold = true;
3008 pci_bridge_d3_update(dev);
3011 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3014 * pci_pm_init - Initialize PM functions of given PCI device
3015 * @dev: PCI device to handle.
3017 void pci_pm_init(struct pci_dev *dev)
3023 pm_runtime_forbid(&dev->dev);
3024 pm_runtime_set_active(&dev->dev);
3025 pm_runtime_enable(&dev->dev);
3026 device_enable_async_suspend(&dev->dev);
3027 dev->wakeup_prepared = false;
3030 dev->pme_support = 0;
3032 /* find PCI PM capability in list */
3033 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3036 /* Check device's ability to generate PME# */
3037 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3039 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3040 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3041 pmc & PCI_PM_CAP_VER_MASK);
3046 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3047 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3048 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3049 dev->d3cold_allowed = true;
3051 dev->d1_support = false;
3052 dev->d2_support = false;
3053 if (!pci_no_d1d2(dev)) {
3054 if (pmc & PCI_PM_CAP_D1)
3055 dev->d1_support = true;
3056 if (pmc & PCI_PM_CAP_D2)
3057 dev->d2_support = true;
3059 if (dev->d1_support || dev->d2_support)
3060 pci_info(dev, "supports%s%s\n",
3061 dev->d1_support ? " D1" : "",
3062 dev->d2_support ? " D2" : "");
3065 pmc &= PCI_PM_CAP_PME_MASK;
3067 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3068 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3069 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3070 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3071 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3072 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3073 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3074 dev->pme_poll = true;
3076 * Make device's PM flags reflect the wake-up capability, but
3077 * let the user space enable it to wake up the system as needed.
3079 device_set_wakeup_capable(&dev->dev, true);
3080 /* Disable the PME# generation functionality */
3081 pci_pme_active(dev, false);
3084 pci_read_config_word(dev, PCI_STATUS, &status);
3085 if (status & PCI_STATUS_IMM_READY)
3089 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3091 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3095 case PCI_EA_P_VF_MEM:
3096 flags |= IORESOURCE_MEM;
3098 case PCI_EA_P_MEM_PREFETCH:
3099 case PCI_EA_P_VF_MEM_PREFETCH:
3100 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3103 flags |= IORESOURCE_IO;
3112 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3115 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3116 return &dev->resource[bei];
3117 #ifdef CONFIG_PCI_IOV
3118 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3119 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3120 return &dev->resource[PCI_IOV_RESOURCES +
3121 bei - PCI_EA_BEI_VF_BAR0];
3123 else if (bei == PCI_EA_BEI_ROM)
3124 return &dev->resource[PCI_ROM_RESOURCE];
3129 /* Read an Enhanced Allocation (EA) entry */
3130 static int pci_ea_read(struct pci_dev *dev, int offset)
3132 struct resource *res;
3133 int ent_size, ent_offset = offset;
3134 resource_size_t start, end;
3135 unsigned long flags;
3136 u32 dw0, bei, base, max_offset;
3138 bool support_64 = (sizeof(resource_size_t) >= 8);
3140 pci_read_config_dword(dev, ent_offset, &dw0);
3143 /* Entry size field indicates DWORDs after 1st */
3144 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3146 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3149 bei = (dw0 & PCI_EA_BEI) >> 4;
3150 prop = (dw0 & PCI_EA_PP) >> 8;
3153 * If the Property is in the reserved range, try the Secondary
3156 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3157 prop = (dw0 & PCI_EA_SP) >> 16;
3158 if (prop > PCI_EA_P_BRIDGE_IO)
3161 res = pci_ea_get_resource(dev, bei, prop);
3163 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3167 flags = pci_ea_flags(dev, prop);
3169 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3174 pci_read_config_dword(dev, ent_offset, &base);
3175 start = (base & PCI_EA_FIELD_MASK);
3178 /* Read MaxOffset */
3179 pci_read_config_dword(dev, ent_offset, &max_offset);
3182 /* Read Base MSBs (if 64-bit entry) */
3183 if (base & PCI_EA_IS_64) {
3186 pci_read_config_dword(dev, ent_offset, &base_upper);
3189 flags |= IORESOURCE_MEM_64;
3191 /* entry starts above 32-bit boundary, can't use */
3192 if (!support_64 && base_upper)
3196 start |= ((u64)base_upper << 32);
3199 end = start + (max_offset | 0x03);
3201 /* Read MaxOffset MSBs (if 64-bit entry) */
3202 if (max_offset & PCI_EA_IS_64) {
3203 u32 max_offset_upper;
3205 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3208 flags |= IORESOURCE_MEM_64;
3210 /* entry too big, can't use */
3211 if (!support_64 && max_offset_upper)
3215 end += ((u64)max_offset_upper << 32);
3219 pci_err(dev, "EA Entry crosses address boundary\n");
3223 if (ent_size != ent_offset - offset) {
3224 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3225 ent_size, ent_offset - offset);
3229 res->name = pci_name(dev);
3234 if (bei <= PCI_EA_BEI_BAR5)
3235 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3237 else if (bei == PCI_EA_BEI_ROM)
3238 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3240 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3241 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3242 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3244 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3248 return offset + ent_size;
3251 /* Enhanced Allocation Initialization */
3252 void pci_ea_init(struct pci_dev *dev)
3259 /* find PCI EA capability in list */
3260 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3264 /* determine the number of entries */
3265 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3267 num_ent &= PCI_EA_NUM_ENT_MASK;
3269 offset = ea + PCI_EA_FIRST_ENT;
3271 /* Skip DWORD 2 for type 1 functions */
3272 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3275 /* parse each EA entry */
3276 for (i = 0; i < num_ent; ++i)
3277 offset = pci_ea_read(dev, offset);
3280 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3281 struct pci_cap_saved_state *new_cap)
3283 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3287 * _pci_add_cap_save_buffer - allocate buffer for saving given
3288 * capability registers
3289 * @dev: the PCI device
3290 * @cap: the capability to allocate the buffer for
3291 * @extended: Standard or Extended capability ID
3292 * @size: requested size of the buffer
3294 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3295 bool extended, unsigned int size)
3298 struct pci_cap_saved_state *save_state;
3301 pos = pci_find_ext_capability(dev, cap);
3303 pos = pci_find_capability(dev, cap);
3308 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3312 save_state->cap.cap_nr = cap;
3313 save_state->cap.cap_extended = extended;
3314 save_state->cap.size = size;
3315 pci_add_saved_cap(dev, save_state);
3320 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3322 return _pci_add_cap_save_buffer(dev, cap, false, size);
3325 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3327 return _pci_add_cap_save_buffer(dev, cap, true, size);
3331 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3332 * @dev: the PCI device
3334 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3338 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3339 PCI_EXP_SAVE_REGS * sizeof(u16));
3341 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3343 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3345 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3347 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3350 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3352 pci_allocate_vc_save_buffers(dev);
3355 void pci_free_cap_save_buffers(struct pci_dev *dev)
3357 struct pci_cap_saved_state *tmp;
3358 struct hlist_node *n;
3360 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3365 * pci_configure_ari - enable or disable ARI forwarding
3366 * @dev: the PCI device
3368 * If @dev and its upstream bridge both support ARI, enable ARI in the
3369 * bridge. Otherwise, disable ARI in the bridge.
3371 void pci_configure_ari(struct pci_dev *dev)
3374 struct pci_dev *bridge;
3376 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3379 bridge = dev->bus->self;
3383 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3384 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3387 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3388 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3389 PCI_EXP_DEVCTL2_ARI);
3390 bridge->ari_enabled = 1;
3392 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3393 PCI_EXP_DEVCTL2_ARI);
3394 bridge->ari_enabled = 0;
3398 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3403 pos = pdev->acs_cap;
3408 * Except for egress control, capabilities are either required
3409 * or only required if controllable. Features missing from the
3410 * capability field can therefore be assumed as hard-wired enabled.
3412 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3413 acs_flags &= (cap | PCI_ACS_EC);
3415 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3416 return (ctrl & acs_flags) == acs_flags;
3420 * pci_acs_enabled - test ACS against required flags for a given device
3421 * @pdev: device to test
3422 * @acs_flags: required PCI ACS flags
3424 * Return true if the device supports the provided flags. Automatically
3425 * filters out flags that are not implemented on multifunction devices.
3427 * Note that this interface checks the effective ACS capabilities of the
3428 * device rather than the actual capabilities. For instance, most single
3429 * function endpoints are not required to support ACS because they have no
3430 * opportunity for peer-to-peer access. We therefore return 'true'
3431 * regardless of whether the device exposes an ACS capability. This makes
3432 * it much easier for callers of this function to ignore the actual type
3433 * or topology of the device when testing ACS support.
3435 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3439 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3444 * Conventional PCI and PCI-X devices never support ACS, either
3445 * effectively or actually. The shared bus topology implies that
3446 * any device on the bus can receive or snoop DMA.
3448 if (!pci_is_pcie(pdev))
3451 switch (pci_pcie_type(pdev)) {
3453 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3454 * but since their primary interface is PCI/X, we conservatively
3455 * handle them as we would a non-PCIe device.
3457 case PCI_EXP_TYPE_PCIE_BRIDGE:
3459 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3460 * applicable... must never implement an ACS Extended Capability...".
3461 * This seems arbitrary, but we take a conservative interpretation
3462 * of this statement.
3464 case PCI_EXP_TYPE_PCI_BRIDGE:
3465 case PCI_EXP_TYPE_RC_EC:
3468 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3469 * implement ACS in order to indicate their peer-to-peer capabilities,
3470 * regardless of whether they are single- or multi-function devices.
3472 case PCI_EXP_TYPE_DOWNSTREAM:
3473 case PCI_EXP_TYPE_ROOT_PORT:
3474 return pci_acs_flags_enabled(pdev, acs_flags);
3476 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3477 * implemented by the remaining PCIe types to indicate peer-to-peer
3478 * capabilities, but only when they are part of a multifunction
3479 * device. The footnote for section 6.12 indicates the specific
3480 * PCIe types included here.
3482 case PCI_EXP_TYPE_ENDPOINT:
3483 case PCI_EXP_TYPE_UPSTREAM:
3484 case PCI_EXP_TYPE_LEG_END:
3485 case PCI_EXP_TYPE_RC_END:
3486 if (!pdev->multifunction)
3489 return pci_acs_flags_enabled(pdev, acs_flags);
3493 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3494 * to single function devices with the exception of downstream ports.
3500 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3501 * @start: starting downstream device
3502 * @end: ending upstream device or NULL to search to the root bus
3503 * @acs_flags: required flags
3505 * Walk up a device tree from start to end testing PCI ACS support. If
3506 * any step along the way does not support the required flags, return false.
3508 bool pci_acs_path_enabled(struct pci_dev *start,
3509 struct pci_dev *end, u16 acs_flags)
3511 struct pci_dev *pdev, *parent = start;
3516 if (!pci_acs_enabled(pdev, acs_flags))
3519 if (pci_is_root_bus(pdev->bus))
3520 return (end == NULL);
3522 parent = pdev->bus->self;
3523 } while (pdev != end);
3529 * pci_acs_init - Initialize ACS if hardware supports it
3530 * @dev: the PCI device
3532 void pci_acs_init(struct pci_dev *dev)
3534 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3537 * Attempt to enable ACS regardless of capability because some Root
3538 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3539 * the standard ACS capability but still support ACS via those
3542 pci_enable_acs(dev);
3546 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3550 * Helper to find the position of the ctrl register for a BAR.
3551 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3552 * Returns -ENOENT if no ctrl register for the BAR could be found.
3554 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3556 unsigned int pos, nbars, i;
3559 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3563 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3564 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3565 PCI_REBAR_CTRL_NBAR_SHIFT;
3567 for (i = 0; i < nbars; i++, pos += 8) {
3570 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3571 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3580 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3582 * @bar: BAR to query
3584 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3585 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3587 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3592 pos = pci_rebar_find_pos(pdev, bar);
3596 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3597 cap &= PCI_REBAR_CAP_SIZES;
3599 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3600 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3601 bar == 0 && cap == 0x7000)
3608 * pci_rebar_get_current_size - get the current size of a BAR
3610 * @bar: BAR to set size to
3612 * Read the size of a BAR from the resizable BAR config.
3613 * Returns size if found or negative error code.
3615 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3620 pos = pci_rebar_find_pos(pdev, bar);
3624 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3625 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3629 * pci_rebar_set_size - set a new size for a BAR
3631 * @bar: BAR to set size to
3632 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3634 * Set the new size of a BAR as defined in the spec.
3635 * Returns zero if resizing was successful, error code otherwise.
3637 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3642 pos = pci_rebar_find_pos(pdev, bar);
3646 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3647 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3648 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3649 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3654 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3655 * @dev: the PCI device
3656 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3657 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3658 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3659 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3661 * Return 0 if all upstream bridges support AtomicOp routing, egress
3662 * blocking is disabled on all upstream ports, and the root port supports
3663 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3664 * AtomicOp completion), or negative otherwise.
3666 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3668 struct pci_bus *bus = dev->bus;
3669 struct pci_dev *bridge;
3672 if (!pci_is_pcie(dev))
3676 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3677 * AtomicOp requesters. For now, we only support endpoints as
3678 * requesters and root ports as completers. No endpoints as
3679 * completers, and no peer-to-peer.
3682 switch (pci_pcie_type(dev)) {
3683 case PCI_EXP_TYPE_ENDPOINT:
3684 case PCI_EXP_TYPE_LEG_END:
3685 case PCI_EXP_TYPE_RC_END:
3691 while (bus->parent) {
3694 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3696 switch (pci_pcie_type(bridge)) {
3697 /* Ensure switch ports support AtomicOp routing */
3698 case PCI_EXP_TYPE_UPSTREAM:
3699 case PCI_EXP_TYPE_DOWNSTREAM:
3700 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3704 /* Ensure root port supports all the sizes we care about */
3705 case PCI_EXP_TYPE_ROOT_PORT:
3706 if ((cap & cap_mask) != cap_mask)
3711 /* Ensure upstream ports don't block AtomicOps on egress */
3712 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3713 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3715 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3722 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3723 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3726 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3729 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3730 * @dev: the PCI device
3731 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3733 * Perform INTx swizzling for a device behind one level of bridge. This is
3734 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3735 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3736 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3737 * the PCI Express Base Specification, Revision 2.1)
3739 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3743 if (pci_ari_enabled(dev->bus))
3746 slot = PCI_SLOT(dev->devfn);
3748 return (((pin - 1) + slot) % 4) + 1;
3751 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3759 while (!pci_is_root_bus(dev->bus)) {
3760 pin = pci_swizzle_interrupt_pin(dev, pin);
3761 dev = dev->bus->self;
3768 * pci_common_swizzle - swizzle INTx all the way to root bridge
3769 * @dev: the PCI device
3770 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3772 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3773 * bridges all the way up to a PCI root bus.
3775 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3779 while (!pci_is_root_bus(dev->bus)) {
3780 pin = pci_swizzle_interrupt_pin(dev, pin);
3781 dev = dev->bus->self;
3784 return PCI_SLOT(dev->devfn);
3786 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3789 * pci_release_region - Release a PCI bar
3790 * @pdev: PCI device whose resources were previously reserved by
3791 * pci_request_region()
3792 * @bar: BAR to release
3794 * Releases the PCI I/O and memory resources previously reserved by a
3795 * successful call to pci_request_region(). Call this function only
3796 * after all use of the PCI regions has ceased.
3798 void pci_release_region(struct pci_dev *pdev, int bar)
3800 struct pci_devres *dr;
3802 if (pci_resource_len(pdev, bar) == 0)
3804 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3805 release_region(pci_resource_start(pdev, bar),
3806 pci_resource_len(pdev, bar));
3807 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3808 release_mem_region(pci_resource_start(pdev, bar),
3809 pci_resource_len(pdev, bar));
3811 dr = find_pci_dr(pdev);
3813 dr->region_mask &= ~(1 << bar);
3815 EXPORT_SYMBOL(pci_release_region);
3818 * __pci_request_region - Reserved PCI I/O and memory resource
3819 * @pdev: PCI device whose resources are to be reserved
3820 * @bar: BAR to be reserved
3821 * @res_name: Name to be associated with resource.
3822 * @exclusive: whether the region access is exclusive or not
3824 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3825 * being reserved by owner @res_name. Do not access any
3826 * address inside the PCI regions unless this call returns
3829 * If @exclusive is set, then the region is marked so that userspace
3830 * is explicitly not allowed to map the resource via /dev/mem or
3831 * sysfs MMIO access.
3833 * Returns 0 on success, or %EBUSY on error. A warning
3834 * message is also printed on failure.
3836 static int __pci_request_region(struct pci_dev *pdev, int bar,
3837 const char *res_name, int exclusive)
3839 struct pci_devres *dr;
3841 if (pci_resource_len(pdev, bar) == 0)
3844 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3845 if (!request_region(pci_resource_start(pdev, bar),
3846 pci_resource_len(pdev, bar), res_name))
3848 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3849 if (!__request_mem_region(pci_resource_start(pdev, bar),
3850 pci_resource_len(pdev, bar), res_name,
3855 dr = find_pci_dr(pdev);
3857 dr->region_mask |= 1 << bar;
3862 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3863 &pdev->resource[bar]);
3868 * pci_request_region - Reserve PCI I/O and memory resource
3869 * @pdev: PCI device whose resources are to be reserved
3870 * @bar: BAR to be reserved
3871 * @res_name: Name to be associated with resource
3873 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3874 * being reserved by owner @res_name. Do not access any
3875 * address inside the PCI regions unless this call returns
3878 * Returns 0 on success, or %EBUSY on error. A warning
3879 * message is also printed on failure.
3881 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3883 return __pci_request_region(pdev, bar, res_name, 0);
3885 EXPORT_SYMBOL(pci_request_region);
3888 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3889 * @pdev: PCI device whose resources were previously reserved
3890 * @bars: Bitmask of BARs to be released
3892 * Release selected PCI I/O and memory resources previously reserved.
3893 * Call this function only after all use of the PCI regions has ceased.
3895 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3899 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3900 if (bars & (1 << i))
3901 pci_release_region(pdev, i);
3903 EXPORT_SYMBOL(pci_release_selected_regions);
3905 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3906 const char *res_name, int excl)
3910 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3911 if (bars & (1 << i))
3912 if (__pci_request_region(pdev, i, res_name, excl))
3918 if (bars & (1 << i))
3919 pci_release_region(pdev, i);
3926 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3927 * @pdev: PCI device whose resources are to be reserved
3928 * @bars: Bitmask of BARs to be requested
3929 * @res_name: Name to be associated with resource
3931 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3932 const char *res_name)
3934 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3936 EXPORT_SYMBOL(pci_request_selected_regions);
3938 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3939 const char *res_name)
3941 return __pci_request_selected_regions(pdev, bars, res_name,
3942 IORESOURCE_EXCLUSIVE);
3944 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3947 * pci_release_regions - Release reserved PCI I/O and memory resources
3948 * @pdev: PCI device whose resources were previously reserved by
3949 * pci_request_regions()
3951 * Releases all PCI I/O and memory resources previously reserved by a
3952 * successful call to pci_request_regions(). Call this function only
3953 * after all use of the PCI regions has ceased.
3956 void pci_release_regions(struct pci_dev *pdev)
3958 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
3960 EXPORT_SYMBOL(pci_release_regions);
3963 * pci_request_regions - Reserve PCI I/O and memory resources
3964 * @pdev: PCI device whose resources are to be reserved
3965 * @res_name: Name to be associated with resource.
3967 * Mark all PCI regions associated with PCI device @pdev as
3968 * being reserved by owner @res_name. Do not access any
3969 * address inside the PCI regions unless this call returns
3972 * Returns 0 on success, or %EBUSY on error. A warning
3973 * message is also printed on failure.
3975 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3977 return pci_request_selected_regions(pdev,
3978 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
3980 EXPORT_SYMBOL(pci_request_regions);
3983 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
3984 * @pdev: PCI device whose resources are to be reserved
3985 * @res_name: Name to be associated with resource.
3987 * Mark all PCI regions associated with PCI device @pdev as being reserved
3988 * by owner @res_name. Do not access any address inside the PCI regions
3989 * unless this call returns successfully.
3991 * pci_request_regions_exclusive() will mark the region so that /dev/mem
3992 * and the sysfs MMIO access will not be allowed.
3994 * Returns 0 on success, or %EBUSY on error. A warning message is also
3995 * printed on failure.
3997 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3999 return pci_request_selected_regions_exclusive(pdev,
4000 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4002 EXPORT_SYMBOL(pci_request_regions_exclusive);
4005 * Record the PCI IO range (expressed as CPU physical address + size).
4006 * Return a negative value if an error has occurred, zero otherwise
4008 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4009 resource_size_t size)
4013 struct logic_pio_hwaddr *range;
4015 if (!size || addr + size < addr)
4018 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4022 range->fwnode = fwnode;
4024 range->hw_start = addr;
4025 range->flags = LOGIC_PIO_CPU_MMIO;
4027 ret = logic_pio_register_range(range);
4031 /* Ignore duplicates due to deferred probing */
4039 phys_addr_t pci_pio_to_address(unsigned long pio)
4041 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4044 if (pio >= MMIO_UPPER_LIMIT)
4047 address = logic_pio_to_hwaddr(pio);
4052 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4054 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4057 return logic_pio_trans_cpuaddr(address);
4059 if (address > IO_SPACE_LIMIT)
4060 return (unsigned long)-1;
4062 return (unsigned long) address;
4067 * pci_remap_iospace - Remap the memory mapped I/O space
4068 * @res: Resource describing the I/O space
4069 * @phys_addr: physical address of range to be mapped
4071 * Remap the memory mapped I/O space described by the @res and the CPU
4072 * physical address @phys_addr into virtual address space. Only
4073 * architectures that have memory mapped IO functions defined (and the
4074 * PCI_IOBASE value defined) should call this function.
4076 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4078 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4079 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4081 if (!(res->flags & IORESOURCE_IO))
4084 if (res->end > IO_SPACE_LIMIT)
4087 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4088 pgprot_device(PAGE_KERNEL));
4091 * This architecture does not have memory mapped I/O space,
4092 * so this function should never be called
4094 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4098 EXPORT_SYMBOL(pci_remap_iospace);
4101 * pci_unmap_iospace - Unmap the memory mapped I/O space
4102 * @res: resource to be unmapped
4104 * Unmap the CPU virtual address @res from virtual address space. Only
4105 * architectures that have memory mapped IO functions defined (and the
4106 * PCI_IOBASE value defined) should call this function.
4108 void pci_unmap_iospace(struct resource *res)
4110 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4111 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4113 unmap_kernel_range(vaddr, resource_size(res));
4116 EXPORT_SYMBOL(pci_unmap_iospace);
4118 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4120 struct resource **res = ptr;
4122 pci_unmap_iospace(*res);
4126 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4127 * @dev: Generic device to remap IO address for
4128 * @res: Resource describing the I/O space
4129 * @phys_addr: physical address of range to be mapped
4131 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4134 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4135 phys_addr_t phys_addr)
4137 const struct resource **ptr;
4140 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4144 error = pci_remap_iospace(res, phys_addr);
4149 devres_add(dev, ptr);
4154 EXPORT_SYMBOL(devm_pci_remap_iospace);
4157 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4158 * @dev: Generic device to remap IO address for
4159 * @offset: Resource address to map
4160 * @size: Size of map
4162 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4165 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4166 resource_size_t offset,
4167 resource_size_t size)
4169 void __iomem **ptr, *addr;
4171 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4175 addr = pci_remap_cfgspace(offset, size);
4178 devres_add(dev, ptr);
4184 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4187 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4188 * @dev: generic device to handle the resource for
4189 * @res: configuration space resource to be handled
4191 * Checks that a resource is a valid memory region, requests the memory
4192 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4193 * proper PCI configuration space memory attributes are guaranteed.
4195 * All operations are managed and will be undone on driver detach.
4197 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4198 * on failure. Usage example::
4200 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4201 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4203 * return PTR_ERR(base);
4205 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4206 struct resource *res)
4208 resource_size_t size;
4210 void __iomem *dest_ptr;
4214 if (!res || resource_type(res) != IORESOURCE_MEM) {
4215 dev_err(dev, "invalid resource\n");
4216 return IOMEM_ERR_PTR(-EINVAL);
4219 size = resource_size(res);
4220 name = res->name ?: dev_name(dev);
4222 if (!devm_request_mem_region(dev, res->start, size, name)) {
4223 dev_err(dev, "can't request region for resource %pR\n", res);
4224 return IOMEM_ERR_PTR(-EBUSY);
4227 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4229 dev_err(dev, "ioremap failed for resource %pR\n", res);
4230 devm_release_mem_region(dev, res->start, size);
4231 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4236 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4238 static void __pci_set_master(struct pci_dev *dev, bool enable)
4242 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4244 cmd = old_cmd | PCI_COMMAND_MASTER;
4246 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4247 if (cmd != old_cmd) {
4248 pci_dbg(dev, "%s bus mastering\n",
4249 enable ? "enabling" : "disabling");
4250 pci_write_config_word(dev, PCI_COMMAND, cmd);
4252 dev->is_busmaster = enable;
4256 * pcibios_setup - process "pci=" kernel boot arguments
4257 * @str: string used to pass in "pci=" kernel boot arguments
4259 * Process kernel boot arguments. This is the default implementation.
4260 * Architecture specific implementations can override this as necessary.
4262 char * __weak __init pcibios_setup(char *str)
4268 * pcibios_set_master - enable PCI bus-mastering for device dev
4269 * @dev: the PCI device to enable
4271 * Enables PCI bus-mastering for the device. This is the default
4272 * implementation. Architecture specific implementations can override
4273 * this if necessary.
4275 void __weak pcibios_set_master(struct pci_dev *dev)
4279 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4280 if (pci_is_pcie(dev))
4283 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4285 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4286 else if (lat > pcibios_max_latency)
4287 lat = pcibios_max_latency;
4291 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4295 * pci_set_master - enables bus-mastering for device dev
4296 * @dev: the PCI device to enable
4298 * Enables bus-mastering on the device and calls pcibios_set_master()
4299 * to do the needed arch specific settings.
4301 void pci_set_master(struct pci_dev *dev)
4303 __pci_set_master(dev, true);
4304 pcibios_set_master(dev);
4306 EXPORT_SYMBOL(pci_set_master);
4309 * pci_clear_master - disables bus-mastering for device dev
4310 * @dev: the PCI device to disable
4312 void pci_clear_master(struct pci_dev *dev)
4314 __pci_set_master(dev, false);
4316 EXPORT_SYMBOL(pci_clear_master);
4319 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4320 * @dev: the PCI device for which MWI is to be enabled
4322 * Helper function for pci_set_mwi.
4323 * Originally copied from drivers/net/acenic.c.
4324 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4326 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4328 int pci_set_cacheline_size(struct pci_dev *dev)
4332 if (!pci_cache_line_size)
4335 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4336 equal to or multiple of the right value. */
4337 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4338 if (cacheline_size >= pci_cache_line_size &&
4339 (cacheline_size % pci_cache_line_size) == 0)
4342 /* Write the correct value. */
4343 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4345 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4346 if (cacheline_size == pci_cache_line_size)
4349 pci_info(dev, "cache line size of %d is not supported\n",
4350 pci_cache_line_size << 2);
4354 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4357 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4358 * @dev: the PCI device for which MWI is enabled
4360 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4362 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4364 int pci_set_mwi(struct pci_dev *dev)
4366 #ifdef PCI_DISABLE_MWI
4372 rc = pci_set_cacheline_size(dev);
4376 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4377 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4378 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4379 cmd |= PCI_COMMAND_INVALIDATE;
4380 pci_write_config_word(dev, PCI_COMMAND, cmd);
4385 EXPORT_SYMBOL(pci_set_mwi);
4388 * pcim_set_mwi - a device-managed pci_set_mwi()
4389 * @dev: the PCI device for which MWI is enabled
4391 * Managed pci_set_mwi().
4393 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4395 int pcim_set_mwi(struct pci_dev *dev)
4397 struct pci_devres *dr;
4399 dr = find_pci_dr(dev);
4404 return pci_set_mwi(dev);
4406 EXPORT_SYMBOL(pcim_set_mwi);
4409 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4410 * @dev: the PCI device for which MWI is enabled
4412 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4413 * Callers are not required to check the return value.
4415 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4417 int pci_try_set_mwi(struct pci_dev *dev)
4419 #ifdef PCI_DISABLE_MWI
4422 return pci_set_mwi(dev);
4425 EXPORT_SYMBOL(pci_try_set_mwi);
4428 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4429 * @dev: the PCI device to disable
4431 * Disables PCI Memory-Write-Invalidate transaction on the device
4433 void pci_clear_mwi(struct pci_dev *dev)
4435 #ifndef PCI_DISABLE_MWI
4438 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4439 if (cmd & PCI_COMMAND_INVALIDATE) {
4440 cmd &= ~PCI_COMMAND_INVALIDATE;
4441 pci_write_config_word(dev, PCI_COMMAND, cmd);
4445 EXPORT_SYMBOL(pci_clear_mwi);
4448 * pci_intx - enables/disables PCI INTx for device dev
4449 * @pdev: the PCI device to operate on
4450 * @enable: boolean: whether to enable or disable PCI INTx
4452 * Enables/disables PCI INTx for device @pdev
4454 void pci_intx(struct pci_dev *pdev, int enable)
4456 u16 pci_command, new;
4458 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4461 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4463 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4465 if (new != pci_command) {
4466 struct pci_devres *dr;
4468 pci_write_config_word(pdev, PCI_COMMAND, new);
4470 dr = find_pci_dr(pdev);
4471 if (dr && !dr->restore_intx) {
4472 dr->restore_intx = 1;
4473 dr->orig_intx = !enable;
4477 EXPORT_SYMBOL_GPL(pci_intx);
4479 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4481 struct pci_bus *bus = dev->bus;
4482 bool mask_updated = true;
4483 u32 cmd_status_dword;
4484 u16 origcmd, newcmd;
4485 unsigned long flags;
4489 * We do a single dword read to retrieve both command and status.
4490 * Document assumptions that make this possible.
4492 BUILD_BUG_ON(PCI_COMMAND % 4);
4493 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4495 raw_spin_lock_irqsave(&pci_lock, flags);
4497 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4499 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4502 * Check interrupt status register to see whether our device
4503 * triggered the interrupt (when masking) or the next IRQ is
4504 * already pending (when unmasking).
4506 if (mask != irq_pending) {
4507 mask_updated = false;
4511 origcmd = cmd_status_dword;
4512 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4514 newcmd |= PCI_COMMAND_INTX_DISABLE;
4515 if (newcmd != origcmd)
4516 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4519 raw_spin_unlock_irqrestore(&pci_lock, flags);
4521 return mask_updated;
4525 * pci_check_and_mask_intx - mask INTx on pending interrupt
4526 * @dev: the PCI device to operate on
4528 * Check if the device dev has its INTx line asserted, mask it and return
4529 * true in that case. False is returned if no interrupt was pending.
4531 bool pci_check_and_mask_intx(struct pci_dev *dev)
4533 return pci_check_and_set_intx_mask(dev, true);
4535 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4538 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4539 * @dev: the PCI device to operate on
4541 * Check if the device dev has its INTx line asserted, unmask it if not and
4542 * return true. False is returned and the mask remains active if there was
4543 * still an interrupt pending.
4545 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4547 return pci_check_and_set_intx_mask(dev, false);
4549 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4552 * pci_wait_for_pending_transaction - wait for pending transaction
4553 * @dev: the PCI device to operate on
4555 * Return 0 if transaction is pending 1 otherwise.
4557 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4559 if (!pci_is_pcie(dev))
4562 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4563 PCI_EXP_DEVSTA_TRPND);
4565 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4568 * pcie_has_flr - check if a device supports function level resets
4569 * @dev: device to check
4571 * Returns true if the device advertises support for PCIe function level
4574 bool pcie_has_flr(struct pci_dev *dev)
4576 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4579 return FIELD_GET(PCI_EXP_DEVCAP_FLR, dev->devcap) == 1;
4581 EXPORT_SYMBOL_GPL(pcie_has_flr);
4584 * pcie_flr - initiate a PCIe function level reset
4585 * @dev: device to reset
4587 * Initiate a function level reset on @dev. The caller should ensure the
4588 * device supports FLR before calling this function, e.g. by using the
4589 * pcie_has_flr() helper.
4591 int pcie_flr(struct pci_dev *dev)
4593 if (!pci_wait_for_pending_transaction(dev))
4594 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4596 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4602 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4603 * 100ms, but may silently discard requests while the FLR is in
4604 * progress. Wait 100ms before trying to access the device.
4608 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4610 EXPORT_SYMBOL_GPL(pcie_flr);
4612 static int pci_af_flr(struct pci_dev *dev, int probe)
4617 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4621 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4624 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4625 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4632 * Wait for Transaction Pending bit to clear. A word-aligned test
4633 * is used, so we use the control offset rather than status and shift
4634 * the test bit to match.
4636 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4637 PCI_AF_STATUS_TP << 8))
4638 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4640 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4646 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4647 * updated 27 July 2006; a device must complete an FLR within
4648 * 100ms, but may silently discard requests while the FLR is in
4649 * progress. Wait 100ms before trying to access the device.
4653 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4657 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4658 * @dev: Device to reset.
4659 * @probe: If set, only check if the device can be reset this way.
4661 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4662 * unset, it will be reinitialized internally when going from PCI_D3hot to
4663 * PCI_D0. If that's the case and the device is not in a low-power state
4664 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4666 * NOTE: This causes the caller to sleep for twice the device power transition
4667 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4668 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4669 * Moreover, only devices in D0 can be reset by this function.
4671 static int pci_pm_reset(struct pci_dev *dev, int probe)
4675 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4678 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4679 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4685 if (dev->current_state != PCI_D0)
4688 csr &= ~PCI_PM_CTRL_STATE_MASK;
4690 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4691 pci_dev_d3_sleep(dev);
4693 csr &= ~PCI_PM_CTRL_STATE_MASK;
4695 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4696 pci_dev_d3_sleep(dev);
4698 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4702 * pcie_wait_for_link_delay - Wait until link is active or inactive
4703 * @pdev: Bridge device
4704 * @active: waiting for active or inactive?
4705 * @delay: Delay to wait after link has become active (in ms)
4707 * Use this to wait till link becomes active or inactive.
4709 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4717 * Some controllers might not implement link active reporting. In this
4718 * case, we wait for 1000 ms + any delay requested by the caller.
4720 if (!pdev->link_active_reporting) {
4721 msleep(timeout + delay);
4726 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4727 * after which we should expect an link active if the reset was
4728 * successful. If so, software must wait a minimum 100ms before sending
4729 * configuration requests to devices downstream this port.
4731 * If the link fails to activate, either the device was physically
4732 * removed or the link is permanently failed.
4737 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4738 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4749 return ret == active;
4753 * pcie_wait_for_link - Wait until link is active or inactive
4754 * @pdev: Bridge device
4755 * @active: waiting for active or inactive?
4757 * Use this to wait till link becomes active or inactive.
4759 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4761 return pcie_wait_for_link_delay(pdev, active, 100);
4765 * Find maximum D3cold delay required by all the devices on the bus. The
4766 * spec says 100 ms, but firmware can lower it and we allow drivers to
4767 * increase it as well.
4769 * Called with @pci_bus_sem locked for reading.
4771 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4773 const struct pci_dev *pdev;
4774 int min_delay = 100;
4777 list_for_each_entry(pdev, &bus->devices, bus_list) {
4778 if (pdev->d3cold_delay < min_delay)
4779 min_delay = pdev->d3cold_delay;
4780 if (pdev->d3cold_delay > max_delay)
4781 max_delay = pdev->d3cold_delay;
4784 return max(min_delay, max_delay);
4788 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4790 * @reset_type: reset type in human-readable form
4791 * @timeout: maximum time to wait for devices on secondary bus (milliseconds)
4793 * Handle necessary delays before access to the devices on the secondary
4794 * side of the bridge are permitted after D3cold to D0 transition
4795 * or Conventional Reset.
4797 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4798 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4801 * Return 0 on success or -ENOTTY if the first device on the secondary bus
4802 * failed to become accessible.
4804 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
4807 struct pci_dev *child;
4810 if (pci_dev_is_disconnected(dev))
4813 if (!pci_is_bridge(dev))
4816 down_read(&pci_bus_sem);
4819 * We only deal with devices that are present currently on the bus.
4820 * For any hot-added devices the access delay is handled in pciehp
4821 * board_added(). In case of ACPI hotplug the firmware is expected
4822 * to configure the devices before OS is notified.
4824 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4825 up_read(&pci_bus_sem);
4829 /* Take d3cold_delay requirements into account */
4830 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4832 up_read(&pci_bus_sem);
4836 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4838 up_read(&pci_bus_sem);
4841 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4842 * accessing the device after reset (that is 1000 ms + 100 ms).
4844 if (!pci_is_pcie(dev)) {
4845 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4846 msleep(1000 + delay);
4851 * For PCIe downstream and root ports that do not support speeds
4852 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4853 * speeds (gen3) we need to wait first for the data link layer to
4856 * However, 100 ms is the minimum and the PCIe spec says the
4857 * software must allow at least 1s before it can determine that the
4858 * device that did not respond is a broken device. There is
4859 * evidence that 100 ms is not always enough, for example certain
4860 * Titan Ridge xHCI controller does not always respond to
4861 * configuration requests if we only wait for 100 ms (see
4862 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4864 * Therefore we wait for 100 ms and check for the device presence
4865 * until the timeout expires.
4867 if (!pcie_downstream_port(dev))
4870 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4871 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4874 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4876 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4877 /* Did not train, no need to wait any further */
4878 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4883 return pci_dev_wait(child, reset_type, timeout - delay);
4886 void pci_reset_secondary_bus(struct pci_dev *dev)
4890 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4891 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4892 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4895 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4896 * this to 2ms to ensure that we meet the minimum requirement.
4900 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4901 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4904 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4906 pci_reset_secondary_bus(dev);
4910 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4911 * @dev: Bridge device
4913 * Use the bridge control register to assert reset on the secondary bus.
4914 * Devices on the secondary bus are left in power-on state.
4916 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4918 pcibios_reset_secondary_bus(dev);
4920 return pci_bridge_wait_for_secondary_bus(dev, "bus reset",
4921 PCIE_RESET_READY_POLL_MS);
4923 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4925 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4927 struct pci_dev *pdev;
4929 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4930 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4933 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4940 return pci_bridge_secondary_bus_reset(dev->bus->self);
4943 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4947 if (!hotplug || !try_module_get(hotplug->owner))
4950 if (hotplug->ops->reset_slot)
4951 rc = hotplug->ops->reset_slot(hotplug, probe);
4953 module_put(hotplug->owner);
4958 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4960 if (dev->multifunction || dev->subordinate || !dev->slot ||
4961 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4964 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4967 static void pci_dev_lock(struct pci_dev *dev)
4969 /* block PM suspend, driver probe, etc. */
4970 device_lock(&dev->dev);
4971 pci_cfg_access_lock(dev);
4974 /* Return 1 on successful lock, 0 on contention */
4975 static int pci_dev_trylock(struct pci_dev *dev)
4977 if (device_trylock(&dev->dev)) {
4978 if (pci_cfg_access_trylock(dev))
4980 device_unlock(&dev->dev);
4986 static void pci_dev_unlock(struct pci_dev *dev)
4988 pci_cfg_access_unlock(dev);
4989 device_unlock(&dev->dev);
4992 static void pci_dev_save_and_disable(struct pci_dev *dev)
4994 const struct pci_error_handlers *err_handler =
4995 dev->driver ? dev->driver->err_handler : NULL;
4998 * dev->driver->err_handler->reset_prepare() is protected against
4999 * races with ->remove() by the device lock, which must be held by
5002 if (err_handler && err_handler->reset_prepare)
5003 err_handler->reset_prepare(dev);
5006 * Wake-up device prior to save. PM registers default to D0 after
5007 * reset and a simple register restore doesn't reliably return
5008 * to a non-D0 state anyway.
5010 pci_set_power_state(dev, PCI_D0);
5012 pci_save_state(dev);
5014 * Disable the device by clearing the Command register, except for
5015 * INTx-disable which is set. This not only disables MMIO and I/O port
5016 * BARs, but also prevents the device from being Bus Master, preventing
5017 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5018 * compliant devices, INTx-disable prevents legacy interrupts.
5020 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5023 static void pci_dev_restore(struct pci_dev *dev)
5025 const struct pci_error_handlers *err_handler =
5026 dev->driver ? dev->driver->err_handler : NULL;
5028 pci_restore_state(dev);
5031 * dev->driver->err_handler->reset_done() is protected against
5032 * races with ->remove() by the device lock, which must be held by
5035 if (err_handler && err_handler->reset_done)
5036 err_handler->reset_done(dev);
5040 * __pci_reset_function_locked - reset a PCI device function while holding
5041 * the @dev mutex lock.
5042 * @dev: PCI device to reset
5044 * Some devices allow an individual function to be reset without affecting
5045 * other functions in the same device. The PCI device must be responsive
5046 * to PCI config space in order to use this function.
5048 * The device function is presumed to be unused and the caller is holding
5049 * the device mutex lock when this function is called.
5051 * Resetting the device will make the contents of PCI configuration space
5052 * random, so any caller of this must be prepared to reinitialise the
5053 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5056 * Returns 0 if the device function was successfully reset or negative if the
5057 * device doesn't support resetting a single function.
5059 int __pci_reset_function_locked(struct pci_dev *dev)
5066 * A reset method returns -ENOTTY if it doesn't support this device
5067 * and we should try the next method.
5069 * If it returns 0 (success), we're finished. If it returns any
5070 * other error, we're also finished: this indicates that further
5071 * reset mechanisms might be broken on the device.
5073 rc = pci_dev_specific_reset(dev, 0);
5076 if (pcie_has_flr(dev)) {
5081 rc = pci_af_flr(dev, 0);
5084 rc = pci_pm_reset(dev, 0);
5087 rc = pci_dev_reset_slot_function(dev, 0);
5090 return pci_parent_bus_reset(dev, 0);
5092 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5095 * pci_probe_reset_function - check whether the device can be safely reset
5096 * @dev: PCI device to reset
5098 * Some devices allow an individual function to be reset without affecting
5099 * other functions in the same device. The PCI device must be responsive
5100 * to PCI config space in order to use this function.
5102 * Returns 0 if the device function can be reset or negative if the
5103 * device doesn't support resetting a single function.
5105 int pci_probe_reset_function(struct pci_dev *dev)
5111 rc = pci_dev_specific_reset(dev, 1);
5114 if (pcie_has_flr(dev))
5116 rc = pci_af_flr(dev, 1);
5119 rc = pci_pm_reset(dev, 1);
5122 rc = pci_dev_reset_slot_function(dev, 1);
5126 return pci_parent_bus_reset(dev, 1);
5130 * pci_reset_function - quiesce and reset a PCI device function
5131 * @dev: PCI device to reset
5133 * Some devices allow an individual function to be reset without affecting
5134 * other functions in the same device. The PCI device must be responsive
5135 * to PCI config space in order to use this function.
5137 * This function does not just reset the PCI portion of a device, but
5138 * clears all the state associated with the device. This function differs
5139 * from __pci_reset_function_locked() in that it saves and restores device state
5140 * over the reset and takes the PCI device lock.
5142 * Returns 0 if the device function was successfully reset or negative if the
5143 * device doesn't support resetting a single function.
5145 int pci_reset_function(struct pci_dev *dev)
5153 pci_dev_save_and_disable(dev);
5155 rc = __pci_reset_function_locked(dev);
5157 pci_dev_restore(dev);
5158 pci_dev_unlock(dev);
5162 EXPORT_SYMBOL_GPL(pci_reset_function);
5165 * pci_reset_function_locked - quiesce and reset a PCI device function
5166 * @dev: PCI device to reset
5168 * Some devices allow an individual function to be reset without affecting
5169 * other functions in the same device. The PCI device must be responsive
5170 * to PCI config space in order to use this function.
5172 * This function does not just reset the PCI portion of a device, but
5173 * clears all the state associated with the device. This function differs
5174 * from __pci_reset_function_locked() in that it saves and restores device state
5175 * over the reset. It also differs from pci_reset_function() in that it
5176 * requires the PCI device lock to be held.
5178 * Returns 0 if the device function was successfully reset or negative if the
5179 * device doesn't support resetting a single function.
5181 int pci_reset_function_locked(struct pci_dev *dev)
5188 pci_dev_save_and_disable(dev);
5190 rc = __pci_reset_function_locked(dev);
5192 pci_dev_restore(dev);
5196 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5199 * pci_try_reset_function - quiesce and reset a PCI device function
5200 * @dev: PCI device to reset
5202 * Same as above, except return -EAGAIN if unable to lock device.
5204 int pci_try_reset_function(struct pci_dev *dev)
5211 if (!pci_dev_trylock(dev))
5214 pci_dev_save_and_disable(dev);
5215 rc = __pci_reset_function_locked(dev);
5216 pci_dev_restore(dev);
5217 pci_dev_unlock(dev);
5221 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5223 /* Do any devices on or below this bus prevent a bus reset? */
5224 static bool pci_bus_resetable(struct pci_bus *bus)
5226 struct pci_dev *dev;
5229 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5232 list_for_each_entry(dev, &bus->devices, bus_list) {
5233 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5234 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5241 /* Lock devices from the top of the tree down */
5242 static void pci_bus_lock(struct pci_bus *bus)
5244 struct pci_dev *dev;
5246 list_for_each_entry(dev, &bus->devices, bus_list) {
5248 if (dev->subordinate)
5249 pci_bus_lock(dev->subordinate);
5253 /* Unlock devices from the bottom of the tree up */
5254 static void pci_bus_unlock(struct pci_bus *bus)
5256 struct pci_dev *dev;
5258 list_for_each_entry(dev, &bus->devices, bus_list) {
5259 if (dev->subordinate)
5260 pci_bus_unlock(dev->subordinate);
5261 pci_dev_unlock(dev);
5265 /* Return 1 on successful lock, 0 on contention */
5266 static int pci_bus_trylock(struct pci_bus *bus)
5268 struct pci_dev *dev;
5270 list_for_each_entry(dev, &bus->devices, bus_list) {
5271 if (!pci_dev_trylock(dev))
5273 if (dev->subordinate) {
5274 if (!pci_bus_trylock(dev->subordinate)) {
5275 pci_dev_unlock(dev);
5283 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5284 if (dev->subordinate)
5285 pci_bus_unlock(dev->subordinate);
5286 pci_dev_unlock(dev);
5291 /* Do any devices on or below this slot prevent a bus reset? */
5292 static bool pci_slot_resetable(struct pci_slot *slot)
5294 struct pci_dev *dev;
5296 if (slot->bus->self &&
5297 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5300 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5301 if (!dev->slot || dev->slot != slot)
5303 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5304 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5311 /* Lock devices from the top of the tree down */
5312 static void pci_slot_lock(struct pci_slot *slot)
5314 struct pci_dev *dev;
5316 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5317 if (!dev->slot || dev->slot != slot)
5320 if (dev->subordinate)
5321 pci_bus_lock(dev->subordinate);
5325 /* Unlock devices from the bottom of the tree up */
5326 static void pci_slot_unlock(struct pci_slot *slot)
5328 struct pci_dev *dev;
5330 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5331 if (!dev->slot || dev->slot != slot)
5333 if (dev->subordinate)
5334 pci_bus_unlock(dev->subordinate);
5335 pci_dev_unlock(dev);
5339 /* Return 1 on successful lock, 0 on contention */
5340 static int pci_slot_trylock(struct pci_slot *slot)
5342 struct pci_dev *dev;
5344 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5345 if (!dev->slot || dev->slot != slot)
5347 if (!pci_dev_trylock(dev))
5349 if (dev->subordinate) {
5350 if (!pci_bus_trylock(dev->subordinate)) {
5351 pci_dev_unlock(dev);
5359 list_for_each_entry_continue_reverse(dev,
5360 &slot->bus->devices, bus_list) {
5361 if (!dev->slot || dev->slot != slot)
5363 if (dev->subordinate)
5364 pci_bus_unlock(dev->subordinate);
5365 pci_dev_unlock(dev);
5371 * Save and disable devices from the top of the tree down while holding
5372 * the @dev mutex lock for the entire tree.
5374 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5376 struct pci_dev *dev;
5378 list_for_each_entry(dev, &bus->devices, bus_list) {
5379 pci_dev_save_and_disable(dev);
5380 if (dev->subordinate)
5381 pci_bus_save_and_disable_locked(dev->subordinate);
5386 * Restore devices from top of the tree down while holding @dev mutex lock
5387 * for the entire tree. Parent bridges need to be restored before we can
5388 * get to subordinate devices.
5390 static void pci_bus_restore_locked(struct pci_bus *bus)
5392 struct pci_dev *dev;
5394 list_for_each_entry(dev, &bus->devices, bus_list) {
5395 pci_dev_restore(dev);
5396 if (dev->subordinate)
5397 pci_bus_restore_locked(dev->subordinate);
5402 * Save and disable devices from the top of the tree down while holding
5403 * the @dev mutex lock for the entire tree.
5405 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5407 struct pci_dev *dev;
5409 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5410 if (!dev->slot || dev->slot != slot)
5412 pci_dev_save_and_disable(dev);
5413 if (dev->subordinate)
5414 pci_bus_save_and_disable_locked(dev->subordinate);
5419 * Restore devices from top of the tree down while holding @dev mutex lock
5420 * for the entire tree. Parent bridges need to be restored before we can
5421 * get to subordinate devices.
5423 static void pci_slot_restore_locked(struct pci_slot *slot)
5425 struct pci_dev *dev;
5427 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5428 if (!dev->slot || dev->slot != slot)
5430 pci_dev_restore(dev);
5431 if (dev->subordinate)
5432 pci_bus_restore_locked(dev->subordinate);
5436 static int pci_slot_reset(struct pci_slot *slot, int probe)
5440 if (!slot || !pci_slot_resetable(slot))
5444 pci_slot_lock(slot);
5448 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5451 pci_slot_unlock(slot);
5457 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5458 * @slot: PCI slot to probe
5460 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5462 int pci_probe_reset_slot(struct pci_slot *slot)
5464 return pci_slot_reset(slot, 1);
5466 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5469 * __pci_reset_slot - Try to reset a PCI slot
5470 * @slot: PCI slot to reset
5472 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5473 * independent of other slots. For instance, some slots may support slot power
5474 * control. In the case of a 1:1 bus to slot architecture, this function may
5475 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5476 * Generally a slot reset should be attempted before a bus reset. All of the
5477 * function of the slot and any subordinate buses behind the slot are reset
5478 * through this function. PCI config space of all devices in the slot and
5479 * behind the slot is saved before and restored after reset.
5481 * Same as above except return -EAGAIN if the slot cannot be locked
5483 static int __pci_reset_slot(struct pci_slot *slot)
5487 rc = pci_slot_reset(slot, 1);
5491 if (pci_slot_trylock(slot)) {
5492 pci_slot_save_and_disable_locked(slot);
5494 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5495 pci_slot_restore_locked(slot);
5496 pci_slot_unlock(slot);
5503 static int pci_bus_reset(struct pci_bus *bus, int probe)
5507 if (!bus->self || !pci_bus_resetable(bus))
5517 ret = pci_bridge_secondary_bus_reset(bus->self);
5519 pci_bus_unlock(bus);
5525 * pci_bus_error_reset - reset the bridge's subordinate bus
5526 * @bridge: The parent device that connects to the bus to reset
5528 * This function will first try to reset the slots on this bus if the method is
5529 * available. If slot reset fails or is not available, this will fall back to a
5530 * secondary bus reset.
5532 int pci_bus_error_reset(struct pci_dev *bridge)
5534 struct pci_bus *bus = bridge->subordinate;
5535 struct pci_slot *slot;
5540 mutex_lock(&pci_slot_mutex);
5541 if (list_empty(&bus->slots))
5544 list_for_each_entry(slot, &bus->slots, list)
5545 if (pci_probe_reset_slot(slot))
5548 list_for_each_entry(slot, &bus->slots, list)
5549 if (pci_slot_reset(slot, 0))
5552 mutex_unlock(&pci_slot_mutex);
5555 mutex_unlock(&pci_slot_mutex);
5556 return pci_bus_reset(bridge->subordinate, 0);
5560 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5561 * @bus: PCI bus to probe
5563 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5565 int pci_probe_reset_bus(struct pci_bus *bus)
5567 return pci_bus_reset(bus, 1);
5569 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5572 * __pci_reset_bus - Try to reset a PCI bus
5573 * @bus: top level PCI bus to reset
5575 * Same as above except return -EAGAIN if the bus cannot be locked
5577 static int __pci_reset_bus(struct pci_bus *bus)
5581 rc = pci_bus_reset(bus, 1);
5585 if (pci_bus_trylock(bus)) {
5586 pci_bus_save_and_disable_locked(bus);
5588 rc = pci_bridge_secondary_bus_reset(bus->self);
5589 pci_bus_restore_locked(bus);
5590 pci_bus_unlock(bus);
5598 * pci_reset_bus - Try to reset a PCI bus
5599 * @pdev: top level PCI device to reset via slot/bus
5601 * Same as above except return -EAGAIN if the bus cannot be locked
5603 int pci_reset_bus(struct pci_dev *pdev)
5605 return (!pci_probe_reset_slot(pdev->slot)) ?
5606 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5608 EXPORT_SYMBOL_GPL(pci_reset_bus);
5611 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5612 * @dev: PCI device to query
5614 * Returns mmrbc: maximum designed memory read count in bytes or
5615 * appropriate error value.
5617 int pcix_get_max_mmrbc(struct pci_dev *dev)
5622 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5626 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5629 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5631 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5634 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5635 * @dev: PCI device to query
5637 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5640 int pcix_get_mmrbc(struct pci_dev *dev)
5645 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5649 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5652 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5654 EXPORT_SYMBOL(pcix_get_mmrbc);
5657 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5658 * @dev: PCI device to query
5659 * @mmrbc: maximum memory read count in bytes
5660 * valid values are 512, 1024, 2048, 4096
5662 * If possible sets maximum memory read byte count, some bridges have errata
5663 * that prevent this.
5665 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5671 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5674 v = ffs(mmrbc) - 10;
5676 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5680 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5683 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5686 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5689 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5691 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5694 cmd &= ~PCI_X_CMD_MAX_READ;
5696 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5701 EXPORT_SYMBOL(pcix_set_mmrbc);
5704 * pcie_get_readrq - get PCI Express read request size
5705 * @dev: PCI device to query
5707 * Returns maximum memory read request in bytes or appropriate error value.
5709 int pcie_get_readrq(struct pci_dev *dev)
5713 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5715 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5717 EXPORT_SYMBOL(pcie_get_readrq);
5720 * pcie_set_readrq - set PCI Express maximum memory read request
5721 * @dev: PCI device to query
5722 * @rq: maximum memory read count in bytes
5723 * valid values are 128, 256, 512, 1024, 2048, 4096
5725 * If possible sets maximum memory read request in bytes
5727 int pcie_set_readrq(struct pci_dev *dev, int rq)
5731 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
5733 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5737 * If using the "performance" PCIe config, we clamp the read rq
5738 * size to the max packet size to keep the host bridge from
5739 * generating requests larger than we can cope with.
5741 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5742 int mps = pcie_get_mps(dev);
5748 v = (ffs(rq) - 8) << 12;
5750 if (bridge->no_inc_mrrs) {
5751 int max_mrrs = pcie_get_readrq(dev);
5753 if (rq > max_mrrs) {
5754 pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
5759 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5760 PCI_EXP_DEVCTL_READRQ, v);
5762 return pcibios_err_to_errno(ret);
5764 EXPORT_SYMBOL(pcie_set_readrq);
5767 * pcie_get_mps - get PCI Express maximum payload size
5768 * @dev: PCI device to query
5770 * Returns maximum payload size in bytes
5772 int pcie_get_mps(struct pci_dev *dev)
5776 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5778 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5780 EXPORT_SYMBOL(pcie_get_mps);
5783 * pcie_set_mps - set PCI Express maximum payload size
5784 * @dev: PCI device to query
5785 * @mps: maximum payload size in bytes
5786 * valid values are 128, 256, 512, 1024, 2048, 4096
5788 * If possible sets maximum payload size
5790 int pcie_set_mps(struct pci_dev *dev, int mps)
5795 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5799 if (v > dev->pcie_mpss)
5803 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5804 PCI_EXP_DEVCTL_PAYLOAD, v);
5806 return pcibios_err_to_errno(ret);
5808 EXPORT_SYMBOL(pcie_set_mps);
5811 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5812 * device and its bandwidth limitation
5813 * @dev: PCI device to query
5814 * @limiting_dev: storage for device causing the bandwidth limitation
5815 * @speed: storage for speed of limiting device
5816 * @width: storage for width of limiting device
5818 * Walk up the PCI device chain and find the point where the minimum
5819 * bandwidth is available. Return the bandwidth available there and (if
5820 * limiting_dev, speed, and width pointers are supplied) information about
5821 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5824 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5825 enum pci_bus_speed *speed,
5826 enum pcie_link_width *width)
5829 enum pci_bus_speed next_speed;
5830 enum pcie_link_width next_width;
5834 *speed = PCI_SPEED_UNKNOWN;
5836 *width = PCIE_LNK_WIDTH_UNKNOWN;
5841 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5843 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5844 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5845 PCI_EXP_LNKSTA_NLW_SHIFT;
5847 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5849 /* Check if current device limits the total bandwidth */
5850 if (!bw || next_bw <= bw) {
5854 *limiting_dev = dev;
5856 *speed = next_speed;
5858 *width = next_width;
5861 dev = pci_upstream_bridge(dev);
5866 EXPORT_SYMBOL(pcie_bandwidth_available);
5869 * pcie_get_speed_cap - query for the PCI device's link speed capability
5870 * @dev: PCI device to query
5872 * Query the PCI device speed capability. Return the maximum link speed
5873 * supported by the device.
5875 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5877 u32 lnkcap2, lnkcap;
5880 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
5881 * implementation note there recommends using the Supported Link
5882 * Speeds Vector in Link Capabilities 2 when supported.
5884 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
5885 * should use the Supported Link Speeds field in Link Capabilities,
5886 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
5888 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5890 /* PCIe r3.0-compliant */
5892 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
5894 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5895 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
5896 return PCIE_SPEED_5_0GT;
5897 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
5898 return PCIE_SPEED_2_5GT;
5900 return PCI_SPEED_UNKNOWN;
5902 EXPORT_SYMBOL(pcie_get_speed_cap);
5905 * pcie_get_width_cap - query for the PCI device's link width capability
5906 * @dev: PCI device to query
5908 * Query the PCI device width capability. Return the maximum link width
5909 * supported by the device.
5911 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5915 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5917 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5919 return PCIE_LNK_WIDTH_UNKNOWN;
5921 EXPORT_SYMBOL(pcie_get_width_cap);
5924 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5926 * @speed: storage for link speed
5927 * @width: storage for link width
5929 * Calculate a PCI device's link bandwidth by querying for its link speed
5930 * and width, multiplying them, and applying encoding overhead. The result
5931 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5933 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5934 enum pcie_link_width *width)
5936 *speed = pcie_get_speed_cap(dev);
5937 *width = pcie_get_width_cap(dev);
5939 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5942 return *width * PCIE_SPEED2MBS_ENC(*speed);
5946 * __pcie_print_link_status - Report the PCI device's link speed and width
5947 * @dev: PCI device to query
5948 * @verbose: Print info even when enough bandwidth is available
5950 * If the available bandwidth at the device is less than the device is
5951 * capable of, report the device's maximum possible bandwidth and the
5952 * upstream link that limits its performance. If @verbose, always print
5953 * the available bandwidth, even if the device isn't constrained.
5955 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
5957 enum pcie_link_width width, width_cap;
5958 enum pci_bus_speed speed, speed_cap;
5959 struct pci_dev *limiting_dev = NULL;
5960 u32 bw_avail, bw_cap;
5962 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5963 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5965 if (bw_avail >= bw_cap && verbose)
5966 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5967 bw_cap / 1000, bw_cap % 1000,
5968 pci_speed_string(speed_cap), width_cap);
5969 else if (bw_avail < bw_cap)
5970 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5971 bw_avail / 1000, bw_avail % 1000,
5972 pci_speed_string(speed), width,
5973 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5974 bw_cap / 1000, bw_cap % 1000,
5975 pci_speed_string(speed_cap), width_cap);
5979 * pcie_print_link_status - Report the PCI device's link speed and width
5980 * @dev: PCI device to query
5982 * Report the available bandwidth at the device.
5984 void pcie_print_link_status(struct pci_dev *dev)
5986 __pcie_print_link_status(dev, true);
5988 EXPORT_SYMBOL(pcie_print_link_status);
5991 * pci_select_bars - Make BAR mask from the type of resource
5992 * @dev: the PCI device for which BAR mask is made
5993 * @flags: resource type mask to be selected
5995 * This helper routine makes bar mask from the type of resource.
5997 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6000 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6001 if (pci_resource_flags(dev, i) & flags)
6005 EXPORT_SYMBOL(pci_select_bars);
6007 /* Some architectures require additional programming to enable VGA */
6008 static arch_set_vga_state_t arch_set_vga_state;
6010 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6012 arch_set_vga_state = func; /* NULL disables */
6015 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6016 unsigned int command_bits, u32 flags)
6018 if (arch_set_vga_state)
6019 return arch_set_vga_state(dev, decode, command_bits,
6025 * pci_set_vga_state - set VGA decode state on device and parents if requested
6026 * @dev: the PCI device
6027 * @decode: true = enable decoding, false = disable decoding
6028 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6029 * @flags: traverse ancestors and change bridges
6030 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6032 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6033 unsigned int command_bits, u32 flags)
6035 struct pci_bus *bus;
6036 struct pci_dev *bridge;
6040 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6042 /* ARCH specific VGA enables */
6043 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6047 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6048 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6050 cmd |= command_bits;
6052 cmd &= ~command_bits;
6053 pci_write_config_word(dev, PCI_COMMAND, cmd);
6056 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6063 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6066 cmd |= PCI_BRIDGE_CTL_VGA;
6068 cmd &= ~PCI_BRIDGE_CTL_VGA;
6069 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6078 bool pci_pr3_present(struct pci_dev *pdev)
6080 struct acpi_device *adev;
6085 adev = ACPI_COMPANION(&pdev->dev);
6089 return adev->power.flags.power_resources &&
6090 acpi_has_method(adev->handle, "_PR3");
6092 EXPORT_SYMBOL_GPL(pci_pr3_present);
6096 * pci_add_dma_alias - Add a DMA devfn alias for a device
6097 * @dev: the PCI device for which alias is added
6098 * @devfn_from: alias slot and function
6099 * @nr_devfns: number of subsequent devfns to alias
6101 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6102 * which is used to program permissible bus-devfn source addresses for DMA
6103 * requests in an IOMMU. These aliases factor into IOMMU group creation
6104 * and are useful for devices generating DMA requests beyond or different
6105 * from their logical bus-devfn. Examples include device quirks where the
6106 * device simply uses the wrong devfn, as well as non-transparent bridges
6107 * where the alias may be a proxy for devices in another domain.
6109 * IOMMU group creation is performed during device discovery or addition,
6110 * prior to any potential DMA mapping and therefore prior to driver probing
6111 * (especially for userspace assigned devices where IOMMU group definition
6112 * cannot be left as a userspace activity). DMA aliases should therefore
6113 * be configured via quirks, such as the PCI fixup header quirk.
6115 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6119 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
6120 devfn_to = devfn_from + nr_devfns - 1;
6122 if (!dev->dma_alias_mask)
6123 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6124 if (!dev->dma_alias_mask) {
6125 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6129 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6132 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6133 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6134 else if (nr_devfns > 1)
6135 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6136 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6137 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6140 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6142 return (dev1->dma_alias_mask &&
6143 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6144 (dev2->dma_alias_mask &&
6145 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6146 pci_real_dma_dev(dev1) == dev2 ||
6147 pci_real_dma_dev(dev2) == dev1;
6150 bool pci_device_is_present(struct pci_dev *pdev)
6154 /* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6155 pdev = pci_physfn(pdev);
6156 if (pci_dev_is_disconnected(pdev))
6158 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6160 EXPORT_SYMBOL_GPL(pci_device_is_present);
6162 void pci_ignore_hotplug(struct pci_dev *dev)
6164 struct pci_dev *bridge = dev->bus->self;
6166 dev->ignore_hotplug = 1;
6167 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6169 bridge->ignore_hotplug = 1;
6171 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6174 * pci_real_dma_dev - Get PCI DMA device for PCI device
6175 * @dev: the PCI device that may have a PCI DMA alias
6177 * Permits the platform to provide architecture-specific functionality to
6178 * devices needing to alias DMA to another PCI device on another PCI bus. If
6179 * the PCI device is on the same bus, it is recommended to use
6180 * pci_add_dma_alias(). This is the default implementation. Architecture
6181 * implementations can override this.
6183 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6188 resource_size_t __weak pcibios_default_alignment(void)
6194 * Arches that don't want to expose struct resource to userland as-is in
6195 * sysfs and /proc can implement their own pci_resource_to_user().
6197 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6198 const struct resource *rsrc,
6199 resource_size_t *start, resource_size_t *end)
6201 *start = rsrc->start;
6205 static char *resource_alignment_param;
6206 static DEFINE_SPINLOCK(resource_alignment_lock);
6209 * pci_specified_resource_alignment - get resource alignment specified by user.
6210 * @dev: the PCI device to get
6211 * @resize: whether or not to change resources' size when reassigning alignment
6213 * RETURNS: Resource alignment if it is specified.
6214 * Zero if it is not specified.
6216 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6219 int align_order, count;
6220 resource_size_t align = pcibios_default_alignment();
6224 spin_lock(&resource_alignment_lock);
6225 p = resource_alignment_param;
6228 if (pci_has_flag(PCI_PROBE_ONLY)) {
6230 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6236 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6239 if (align_order > 63) {
6240 pr_err("PCI: Invalid requested alignment (order %d)\n",
6242 align_order = PAGE_SHIFT;
6245 align_order = PAGE_SHIFT;
6248 ret = pci_dev_str_match(dev, p, &p);
6251 align = 1ULL << align_order;
6253 } else if (ret < 0) {
6254 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6259 if (*p != ';' && *p != ',') {
6260 /* End of param or invalid format */
6266 spin_unlock(&resource_alignment_lock);
6270 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6271 resource_size_t align, bool resize)
6273 struct resource *r = &dev->resource[bar];
6274 resource_size_t size;
6276 if (!(r->flags & IORESOURCE_MEM))
6279 if (r->flags & IORESOURCE_PCI_FIXED) {
6280 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6281 bar, r, (unsigned long long)align);
6285 size = resource_size(r);
6290 * Increase the alignment of the resource. There are two ways we
6293 * 1) Increase the size of the resource. BARs are aligned on their
6294 * size, so when we reallocate space for this resource, we'll
6295 * allocate it with the larger alignment. This also prevents
6296 * assignment of any other BARs inside the alignment region, so
6297 * if we're requesting page alignment, this means no other BARs
6298 * will share the page.
6300 * The disadvantage is that this makes the resource larger than
6301 * the hardware BAR, which may break drivers that compute things
6302 * based on the resource size, e.g., to find registers at a
6303 * fixed offset before the end of the BAR.
6305 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6306 * set r->start to the desired alignment. By itself this
6307 * doesn't prevent other BARs being put inside the alignment
6308 * region, but if we realign *every* resource of every device in
6309 * the system, none of them will share an alignment region.
6311 * When the user has requested alignment for only some devices via
6312 * the "pci=resource_alignment" argument, "resize" is true and we
6313 * use the first method. Otherwise we assume we're aligning all
6314 * devices and we use the second.
6317 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6318 bar, r, (unsigned long long)align);
6324 r->flags &= ~IORESOURCE_SIZEALIGN;
6325 r->flags |= IORESOURCE_STARTALIGN;
6327 r->end = r->start + size - 1;
6329 r->flags |= IORESOURCE_UNSET;
6333 * This function disables memory decoding and releases memory resources
6334 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6335 * It also rounds up size to specified alignment.
6336 * Later on, the kernel will assign page-aligned memory resource back
6339 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6343 resource_size_t align;
6345 bool resize = false;
6348 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6349 * 3.4.1.11. Their resources are allocated from the space
6350 * described by the VF BARx register in the PF's SR-IOV capability.
6351 * We can't influence their alignment here.
6356 /* check if specified PCI is target device to reassign */
6357 align = pci_specified_resource_alignment(dev, &resize);
6361 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6362 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6363 pci_warn(dev, "Can't reassign resources to host bridge\n");
6367 pci_read_config_word(dev, PCI_COMMAND, &command);
6368 command &= ~PCI_COMMAND_MEMORY;
6369 pci_write_config_word(dev, PCI_COMMAND, command);
6371 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6372 pci_request_resource_alignment(dev, i, align, resize);
6375 * Need to disable bridge's resource window,
6376 * to enable the kernel to reassign new resource
6379 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6380 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6381 r = &dev->resource[i];
6382 if (!(r->flags & IORESOURCE_MEM))
6384 r->flags |= IORESOURCE_UNSET;
6385 r->end = resource_size(r) - 1;
6388 pci_disable_bridge_window(dev);
6392 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6396 spin_lock(&resource_alignment_lock);
6397 if (resource_alignment_param)
6398 count = scnprintf(buf, PAGE_SIZE, "%s", resource_alignment_param);
6399 spin_unlock(&resource_alignment_lock);
6402 * When set by the command line, resource_alignment_param will not
6403 * have a trailing line feed, which is ugly. So conditionally add
6406 if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) {
6407 buf[count - 1] = '\n';
6414 static ssize_t resource_alignment_store(struct bus_type *bus,
6415 const char *buf, size_t count)
6417 char *param = kstrndup(buf, count, GFP_KERNEL);
6422 spin_lock(&resource_alignment_lock);
6423 kfree(resource_alignment_param);
6424 resource_alignment_param = param;
6425 spin_unlock(&resource_alignment_lock);
6429 static BUS_ATTR_RW(resource_alignment);
6431 static int __init pci_resource_alignment_sysfs_init(void)
6433 return bus_create_file(&pci_bus_type,
6434 &bus_attr_resource_alignment);
6436 late_initcall(pci_resource_alignment_sysfs_init);
6438 static void pci_no_domains(void)
6440 #ifdef CONFIG_PCI_DOMAINS
6441 pci_domains_supported = 0;
6445 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6446 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6448 static int pci_get_new_domain_nr(void)
6450 return atomic_inc_return(&__domain_nr);
6453 static int of_pci_bus_find_domain_nr(struct device *parent)
6455 static int use_dt_domains = -1;
6459 domain = of_get_pci_domain_nr(parent->of_node);
6462 * Check DT domain and use_dt_domains values.
6464 * If DT domain property is valid (domain >= 0) and
6465 * use_dt_domains != 0, the DT assignment is valid since this means
6466 * we have not previously allocated a domain number by using
6467 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6468 * 1, to indicate that we have just assigned a domain number from
6471 * If DT domain property value is not valid (ie domain < 0), and we
6472 * have not previously assigned a domain number from DT
6473 * (use_dt_domains != 1) we should assign a domain number by
6476 * pci_get_new_domain_nr()
6478 * API and update the use_dt_domains value to keep track of method we
6479 * are using to assign domain numbers (use_dt_domains = 0).
6481 * All other combinations imply we have a platform that is trying
6482 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6483 * which is a recipe for domain mishandling and it is prevented by
6484 * invalidating the domain value (domain = -1) and printing a
6485 * corresponding error.
6487 if (domain >= 0 && use_dt_domains) {
6489 } else if (domain < 0 && use_dt_domains != 1) {
6491 domain = pci_get_new_domain_nr();
6494 pr_err("Node %pOF has ", parent->of_node);
6495 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6502 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6504 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6505 acpi_pci_bus_find_domain_nr(bus);
6510 * pci_ext_cfg_avail - can we access extended PCI config space?
6512 * Returns 1 if we can access PCI extended config space (offsets
6513 * greater than 0xff). This is the default implementation. Architecture
6514 * implementations can override this.
6516 int __weak pci_ext_cfg_avail(void)
6521 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6524 EXPORT_SYMBOL(pci_fixup_cardbus);
6526 static int __init pci_setup(char *str)
6529 char *k = strchr(str, ',');
6532 if (*str && (str = pcibios_setup(str)) && *str) {
6533 if (!strcmp(str, "nomsi")) {
6535 } else if (!strncmp(str, "noats", 5)) {
6536 pr_info("PCIe: ATS is disabled\n");
6537 pcie_ats_disabled = true;
6538 } else if (!strcmp(str, "noaer")) {
6540 } else if (!strcmp(str, "earlydump")) {
6541 pci_early_dump = true;
6542 } else if (!strncmp(str, "realloc=", 8)) {
6543 pci_realloc_get_opt(str + 8);
6544 } else if (!strncmp(str, "realloc", 7)) {
6545 pci_realloc_get_opt("on");
6546 } else if (!strcmp(str, "nodomains")) {
6548 } else if (!strncmp(str, "noari", 5)) {
6549 pcie_ari_disabled = true;
6550 } else if (!strncmp(str, "cbiosize=", 9)) {
6551 pci_cardbus_io_size = memparse(str + 9, &str);
6552 } else if (!strncmp(str, "cbmemsize=", 10)) {
6553 pci_cardbus_mem_size = memparse(str + 10, &str);
6554 } else if (!strncmp(str, "resource_alignment=", 19)) {
6555 resource_alignment_param = str + 19;
6556 } else if (!strncmp(str, "ecrc=", 5)) {
6557 pcie_ecrc_get_policy(str + 5);
6558 } else if (!strncmp(str, "hpiosize=", 9)) {
6559 pci_hotplug_io_size = memparse(str + 9, &str);
6560 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6561 pci_hotplug_mmio_size = memparse(str + 11, &str);
6562 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6563 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6564 } else if (!strncmp(str, "hpmemsize=", 10)) {
6565 pci_hotplug_mmio_size = memparse(str + 10, &str);
6566 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6567 } else if (!strncmp(str, "hpbussize=", 10)) {
6568 pci_hotplug_bus_size =
6569 simple_strtoul(str + 10, &str, 0);
6570 if (pci_hotplug_bus_size > 0xff)
6571 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6572 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6573 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6574 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6575 pcie_bus_config = PCIE_BUS_SAFE;
6576 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6577 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6578 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6579 pcie_bus_config = PCIE_BUS_PEER2PEER;
6580 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6581 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6582 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6583 disable_acs_redir_param = str + 18;
6585 pr_err("PCI: Unknown option `%s'\n", str);
6592 early_param("pci", pci_setup);
6595 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6596 * in pci_setup(), above, to point to data in the __initdata section which
6597 * will be freed after the init sequence is complete. We can't allocate memory
6598 * in pci_setup() because some architectures do not have any memory allocation
6599 * service available during an early_param() call. So we allocate memory and
6600 * copy the variable here before the init section is freed.
6603 static int __init pci_realloc_setup_params(void)
6605 resource_alignment_param = kstrdup(resource_alignment_param,
6607 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6611 pure_initcall(pci_realloc_setup_params);