1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex);
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
45 int isa_dma_bridge_buggy;
46 EXPORT_SYMBOL(isa_dma_bridge_buggy);
50 EXPORT_SYMBOL(pci_pci_problems);
52 unsigned int pci_pm_d3hot_delay;
54 static void pci_pme_list_scan(struct work_struct *work);
56 static LIST_HEAD(pci_pme_list);
57 static DEFINE_MUTEX(pci_pme_list_mutex);
58 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
60 struct pci_pme_device {
61 struct list_head list;
65 #define PME_TIMEOUT 1000 /* How long between PME checks */
68 * Following exit from Conventional Reset, devices must be ready within 1 sec
69 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
70 * Reset (PCIe r6.0 sec 5.8).
72 #define PCI_RESET_WAIT 1000 /* msec */
75 * Devices may extend the 1 sec period through Request Retry Status
76 * completions (PCIe r6.0 sec 2.3.1). The spec does not provide an upper
77 * limit, but 60 sec ought to be enough for any device to become
80 #define PCIE_RESET_READY_POLL_MS 60000 /* msec */
82 static void pci_dev_d3_sleep(struct pci_dev *dev)
84 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
88 /* Use a 20% upper bound, 1ms minimum */
89 upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
90 usleep_range(delay_ms * USEC_PER_MSEC,
91 (delay_ms + upper) * USEC_PER_MSEC);
95 bool pci_reset_supported(struct pci_dev *dev)
97 return dev->reset_methods[0] != 0;
100 #ifdef CONFIG_PCI_DOMAINS
101 int pci_domains_supported = 1;
104 #define DEFAULT_CARDBUS_IO_SIZE (256)
105 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
106 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
107 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
108 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
110 #define DEFAULT_HOTPLUG_IO_SIZE (256)
111 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
112 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
113 /* hpiosize=nn can override this */
114 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
116 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
117 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
118 * pci=hpmemsize=nnM overrides both
120 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
121 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
123 #define DEFAULT_HOTPLUG_BUS_SIZE 1
124 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
127 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
128 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
129 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
130 #elif defined CONFIG_PCIE_BUS_SAFE
131 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
132 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
133 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
134 #elif defined CONFIG_PCIE_BUS_PEER2PEER
135 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
137 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
141 * The default CLS is used if arch didn't set CLS explicitly and not
142 * all pci devices agree on the same value. Arch can override either
143 * the dfl or actual value as it sees fit. Don't forget this is
144 * measured in 32-bit words, not bytes.
146 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
147 u8 pci_cache_line_size;
150 * If we set up a device for bus mastering, we need to check the latency
151 * timer as certain BIOSes forget to set it properly.
153 unsigned int pcibios_max_latency = 255;
155 /* If set, the PCIe ARI capability will not be used. */
156 static bool pcie_ari_disabled;
158 /* If set, the PCIe ATS capability will not be used. */
159 static bool pcie_ats_disabled;
161 /* If set, the PCI config space of each device is printed during boot. */
164 bool pci_ats_disabled(void)
166 return pcie_ats_disabled;
168 EXPORT_SYMBOL_GPL(pci_ats_disabled);
170 /* Disable bridge_d3 for all PCIe ports */
171 static bool pci_bridge_d3_disable;
172 /* Force bridge_d3 for all PCIe ports */
173 static bool pci_bridge_d3_force;
175 static int __init pcie_port_pm_setup(char *str)
177 if (!strcmp(str, "off"))
178 pci_bridge_d3_disable = true;
179 else if (!strcmp(str, "force"))
180 pci_bridge_d3_force = true;
183 __setup("pcie_port_pm=", pcie_port_pm_setup);
186 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
187 * @bus: pointer to PCI bus structure to search
189 * Given a PCI bus, returns the highest PCI bus number present in the set
190 * including the given PCI bus and its list of child PCI buses.
192 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
195 unsigned char max, n;
197 max = bus->busn_res.end;
198 list_for_each_entry(tmp, &bus->children, node) {
199 n = pci_bus_max_busnr(tmp);
205 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
208 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
209 * @pdev: the PCI device
211 * Returns error bits set in PCI_STATUS and clears them.
213 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
218 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
219 if (ret != PCIBIOS_SUCCESSFUL)
222 status &= PCI_STATUS_ERROR_BITS;
224 pci_write_config_word(pdev, PCI_STATUS, status);
228 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
230 #ifdef CONFIG_HAS_IOMEM
231 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
234 struct resource *res = &pdev->resource[bar];
235 resource_size_t start = res->start;
236 resource_size_t size = resource_size(res);
239 * Make sure the BAR is actually a memory resource, not an IO resource
241 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
242 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
247 return ioremap_wc(start, size);
249 return ioremap(start, size);
252 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
254 return __pci_ioremap_resource(pdev, bar, false);
256 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
258 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
260 return __pci_ioremap_resource(pdev, bar, true);
262 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
266 * pci_dev_str_match_path - test if a path string matches a device
267 * @dev: the PCI device to test
268 * @path: string to match the device against
269 * @endptr: pointer to the string after the match
271 * Test if a string (typically from a kernel parameter) formatted as a
272 * path of device/function addresses matches a PCI device. The string must
275 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
277 * A path for a device can be obtained using 'lspci -t'. Using a path
278 * is more robust against bus renumbering than using only a single bus,
279 * device and function address.
281 * Returns 1 if the string matches the device, 0 if it does not and
282 * a negative error code if it fails to parse the string.
284 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
288 unsigned int seg, bus, slot, func;
292 *endptr = strchrnul(path, ';');
294 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
299 p = strrchr(wpath, '/');
302 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
308 if (dev->devfn != PCI_DEVFN(slot, func)) {
314 * Note: we don't need to get a reference to the upstream
315 * bridge because we hold a reference to the top level
316 * device which should hold a reference to the bridge,
319 dev = pci_upstream_bridge(dev);
328 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
332 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
339 ret = (seg == pci_domain_nr(dev->bus) &&
340 bus == dev->bus->number &&
341 dev->devfn == PCI_DEVFN(slot, func));
349 * pci_dev_str_match - test if a string matches a device
350 * @dev: the PCI device to test
351 * @p: string to match the device against
352 * @endptr: pointer to the string after the match
354 * Test if a string (typically from a kernel parameter) matches a specified
355 * PCI device. The string may be of one of the following formats:
357 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
358 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
360 * The first format specifies a PCI bus/device/function address which
361 * may change if new hardware is inserted, if motherboard firmware changes,
362 * or due to changes caused in kernel parameters. If the domain is
363 * left unspecified, it is taken to be 0. In order to be robust against
364 * bus renumbering issues, a path of PCI device/function numbers may be used
365 * to address the specific device. The path for a device can be determined
366 * through the use of 'lspci -t'.
368 * The second format matches devices using IDs in the configuration
369 * space which may match multiple devices in the system. A value of 0
370 * for any field will match all devices. (Note: this differs from
371 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
372 * legacy reasons and convenience so users don't have to specify
373 * FFFFFFFFs on the command line.)
375 * Returns 1 if the string matches the device, 0 if it does not and
376 * a negative error code if the string cannot be parsed.
378 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
383 unsigned short vendor, device, subsystem_vendor, subsystem_device;
385 if (strncmp(p, "pci:", 4) == 0) {
386 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
388 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
389 &subsystem_vendor, &subsystem_device, &count);
391 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
395 subsystem_vendor = 0;
396 subsystem_device = 0;
401 if ((!vendor || vendor == dev->vendor) &&
402 (!device || device == dev->device) &&
403 (!subsystem_vendor ||
404 subsystem_vendor == dev->subsystem_vendor) &&
405 (!subsystem_device ||
406 subsystem_device == dev->subsystem_device))
410 * PCI Bus, Device, Function IDs are specified
411 * (optionally, may include a path of devfns following it)
413 ret = pci_dev_str_match_path(dev, p, &p);
428 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
429 u8 pos, int cap, int *ttl)
434 pci_bus_read_config_byte(bus, devfn, pos, &pos);
440 pci_bus_read_config_word(bus, devfn, pos, &ent);
452 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
455 int ttl = PCI_FIND_CAP_TTL;
457 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
460 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
462 return __pci_find_next_cap(dev->bus, dev->devfn,
463 pos + PCI_CAP_LIST_NEXT, cap);
465 EXPORT_SYMBOL_GPL(pci_find_next_capability);
467 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
468 unsigned int devfn, u8 hdr_type)
472 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
473 if (!(status & PCI_STATUS_CAP_LIST))
477 case PCI_HEADER_TYPE_NORMAL:
478 case PCI_HEADER_TYPE_BRIDGE:
479 return PCI_CAPABILITY_LIST;
480 case PCI_HEADER_TYPE_CARDBUS:
481 return PCI_CB_CAPABILITY_LIST;
488 * pci_find_capability - query for devices' capabilities
489 * @dev: PCI device to query
490 * @cap: capability code
492 * Tell if a device supports a given PCI capability.
493 * Returns the address of the requested capability structure within the
494 * device's PCI configuration space or 0 in case the device does not
495 * support it. Possible values for @cap include:
497 * %PCI_CAP_ID_PM Power Management
498 * %PCI_CAP_ID_AGP Accelerated Graphics Port
499 * %PCI_CAP_ID_VPD Vital Product Data
500 * %PCI_CAP_ID_SLOTID Slot Identification
501 * %PCI_CAP_ID_MSI Message Signalled Interrupts
502 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
503 * %PCI_CAP_ID_PCIX PCI-X
504 * %PCI_CAP_ID_EXP PCI Express
506 u8 pci_find_capability(struct pci_dev *dev, int cap)
510 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
512 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
516 EXPORT_SYMBOL(pci_find_capability);
519 * pci_bus_find_capability - query for devices' capabilities
520 * @bus: the PCI bus to query
521 * @devfn: PCI device to query
522 * @cap: capability code
524 * Like pci_find_capability() but works for PCI devices that do not have a
525 * pci_dev structure set up yet.
527 * Returns the address of the requested capability structure within the
528 * device's PCI configuration space or 0 in case the device does not
531 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
535 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
537 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & PCI_HEADER_TYPE_MASK);
539 pos = __pci_find_next_cap(bus, devfn, pos, cap);
543 EXPORT_SYMBOL(pci_bus_find_capability);
546 * pci_find_next_ext_capability - Find an extended capability
547 * @dev: PCI device to query
548 * @start: address at which to start looking (0 to start at beginning of list)
549 * @cap: capability code
551 * Returns the address of the next matching extended capability structure
552 * within the device's PCI configuration space or 0 if the device does
553 * not support it. Some capabilities can occur several times, e.g., the
554 * vendor-specific capability, and this provides a way to find them all.
556 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
560 u16 pos = PCI_CFG_SPACE_SIZE;
562 /* minimum 8 bytes per capability */
563 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
565 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
571 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
575 * If we have no capabilities, this is indicated by cap ID,
576 * cap version and next pointer all being 0.
582 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
585 pos = PCI_EXT_CAP_NEXT(header);
586 if (pos < PCI_CFG_SPACE_SIZE)
589 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
595 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
598 * pci_find_ext_capability - Find an extended capability
599 * @dev: PCI device to query
600 * @cap: capability code
602 * Returns the address of the requested extended capability structure
603 * within the device's PCI configuration space or 0 if the device does
604 * not support it. Possible values for @cap include:
606 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
607 * %PCI_EXT_CAP_ID_VC Virtual Channel
608 * %PCI_EXT_CAP_ID_DSN Device Serial Number
609 * %PCI_EXT_CAP_ID_PWR Power Budgeting
611 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
613 return pci_find_next_ext_capability(dev, 0, cap);
615 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
618 * pci_get_dsn - Read and return the 8-byte Device Serial Number
619 * @dev: PCI device to query
621 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
624 * Returns the DSN, or zero if the capability does not exist.
626 u64 pci_get_dsn(struct pci_dev *dev)
632 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
637 * The Device Serial Number is two dwords offset 4 bytes from the
638 * capability position. The specification says that the first dword is
639 * the lower half, and the second dword is the upper half.
642 pci_read_config_dword(dev, pos, &dword);
644 pci_read_config_dword(dev, pos + 4, &dword);
645 dsn |= ((u64)dword) << 32;
649 EXPORT_SYMBOL_GPL(pci_get_dsn);
651 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
653 int rc, ttl = PCI_FIND_CAP_TTL;
656 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
657 mask = HT_3BIT_CAP_MASK;
659 mask = HT_5BIT_CAP_MASK;
661 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
662 PCI_CAP_ID_HT, &ttl);
664 rc = pci_read_config_byte(dev, pos + 3, &cap);
665 if (rc != PCIBIOS_SUCCESSFUL)
668 if ((cap & mask) == ht_cap)
671 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
672 pos + PCI_CAP_LIST_NEXT,
673 PCI_CAP_ID_HT, &ttl);
680 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
681 * @dev: PCI device to query
682 * @pos: Position from which to continue searching
683 * @ht_cap: HyperTransport capability code
685 * To be used in conjunction with pci_find_ht_capability() to search for
686 * all capabilities matching @ht_cap. @pos should always be a value returned
687 * from pci_find_ht_capability().
689 * NB. To be 100% safe against broken PCI devices, the caller should take
690 * steps to avoid an infinite loop.
692 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
694 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
696 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
699 * pci_find_ht_capability - query a device's HyperTransport capabilities
700 * @dev: PCI device to query
701 * @ht_cap: HyperTransport capability code
703 * Tell if a device supports a given HyperTransport capability.
704 * Returns an address within the device's PCI configuration space
705 * or 0 in case the device does not support the request capability.
706 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
707 * which has a HyperTransport capability matching @ht_cap.
709 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
713 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
715 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
719 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
722 * pci_find_vsec_capability - Find a vendor-specific extended capability
723 * @dev: PCI device to query
724 * @vendor: Vendor ID for which capability is defined
725 * @cap: Vendor-specific capability ID
727 * If @dev has Vendor ID @vendor, search for a VSEC capability with
728 * VSEC ID @cap. If found, return the capability offset in
729 * config space; otherwise return 0.
731 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
737 if (vendor != dev->vendor)
740 while ((vsec = pci_find_next_ext_capability(dev, vsec,
741 PCI_EXT_CAP_ID_VNDR))) {
742 ret = pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
743 if (ret != PCIBIOS_SUCCESSFUL)
746 if (PCI_VNDR_HEADER_ID(header) == cap)
752 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
755 * pci_find_dvsec_capability - Find DVSEC for vendor
756 * @dev: PCI device to query
757 * @vendor: Vendor ID to match for the DVSEC
758 * @dvsec: Designated Vendor-specific capability ID
760 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
761 * offset in config space; otherwise return 0.
763 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
767 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
774 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
775 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
776 if (vendor == v && dvsec == id)
779 pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
784 EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
787 * pci_find_parent_resource - return resource region of parent bus of given
789 * @dev: PCI device structure contains resources to be searched
790 * @res: child resource record for which parent is sought
792 * For given resource region of given device, return the resource region of
793 * parent bus the given region is contained in.
795 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
796 struct resource *res)
798 const struct pci_bus *bus = dev->bus;
801 pci_bus_for_each_resource(bus, r) {
804 if (resource_contains(r, res)) {
807 * If the window is prefetchable but the BAR is
808 * not, the allocator made a mistake.
810 if (r->flags & IORESOURCE_PREFETCH &&
811 !(res->flags & IORESOURCE_PREFETCH))
815 * If we're below a transparent bridge, there may
816 * be both a positively-decoded aperture and a
817 * subtractively-decoded region that contain the BAR.
818 * We want the positively-decoded one, so this depends
819 * on pci_bus_for_each_resource() giving us those
827 EXPORT_SYMBOL(pci_find_parent_resource);
830 * pci_find_resource - Return matching PCI device resource
831 * @dev: PCI device to query
832 * @res: Resource to look for
834 * Goes over standard PCI resources (BARs) and checks if the given resource
835 * is partially or fully contained in any of them. In that case the
836 * matching resource is returned, %NULL otherwise.
838 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
842 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
843 struct resource *r = &dev->resource[i];
845 if (r->start && resource_contains(r, res))
851 EXPORT_SYMBOL(pci_find_resource);
854 * pci_resource_name - Return the name of the PCI resource
855 * @dev: PCI device to query
856 * @i: index of the resource
858 * Return the standard PCI resource (BAR) name according to their index.
860 const char *pci_resource_name(struct pci_dev *dev, unsigned int i)
862 static const char * const bar_name[] = {
870 #ifdef CONFIG_PCI_IOV
878 "bridge window", /* "io" included in %pR */
879 "bridge window", /* "mem" included in %pR */
880 "bridge window", /* "mem pref" included in %pR */
882 static const char * const cardbus_name[] = {
889 #ifdef CONFIG_PCI_IOV
897 "CardBus bridge window 0", /* I/O */
898 "CardBus bridge window 1", /* I/O */
899 "CardBus bridge window 0", /* mem */
900 "CardBus bridge window 1", /* mem */
903 if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS &&
904 i < ARRAY_SIZE(cardbus_name))
905 return cardbus_name[i];
907 if (i < ARRAY_SIZE(bar_name))
914 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
915 * @dev: the PCI device to operate on
916 * @pos: config space offset of status word
917 * @mask: mask of bit(s) to care about in status word
919 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
921 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
925 /* Wait for Transaction Pending bit clean */
926 for (i = 0; i < 4; i++) {
929 msleep((1 << (i - 1)) * 100);
931 pci_read_config_word(dev, pos, &status);
932 if (!(status & mask))
939 static int pci_acs_enable;
942 * pci_request_acs - ask for ACS to be enabled if supported
944 void pci_request_acs(void)
949 static const char *disable_acs_redir_param;
952 * pci_disable_acs_redir - disable ACS redirect capabilities
953 * @dev: the PCI device
955 * For only devices specified in the disable_acs_redir parameter.
957 static void pci_disable_acs_redir(struct pci_dev *dev)
964 if (!disable_acs_redir_param)
967 p = disable_acs_redir_param;
969 ret = pci_dev_str_match(dev, p, &p);
971 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
972 disable_acs_redir_param);
975 } else if (ret == 1) {
980 if (*p != ';' && *p != ',') {
981 /* End of param or invalid format */
990 if (!pci_dev_specific_disable_acs_redir(dev))
995 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
999 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1001 /* P2P Request & Completion Redirect */
1002 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
1004 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1006 pci_info(dev, "disabled ACS redirect\n");
1010 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
1011 * @dev: the PCI device
1013 static void pci_std_enable_acs(struct pci_dev *dev)
1023 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1024 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1026 /* Source Validation */
1027 ctrl |= (cap & PCI_ACS_SV);
1029 /* P2P Request Redirect */
1030 ctrl |= (cap & PCI_ACS_RR);
1032 /* P2P Completion Redirect */
1033 ctrl |= (cap & PCI_ACS_CR);
1035 /* Upstream Forwarding */
1036 ctrl |= (cap & PCI_ACS_UF);
1038 /* Enable Translation Blocking for external devices and noats */
1039 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
1040 ctrl |= (cap & PCI_ACS_TB);
1042 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1046 * pci_enable_acs - enable ACS if hardware support it
1047 * @dev: the PCI device
1049 static void pci_enable_acs(struct pci_dev *dev)
1051 if (!pci_acs_enable)
1052 goto disable_acs_redir;
1054 if (!pci_dev_specific_enable_acs(dev))
1055 goto disable_acs_redir;
1057 pci_std_enable_acs(dev);
1061 * Note: pci_disable_acs_redir() must be called even if ACS was not
1062 * enabled by the kernel because it may have been enabled by
1063 * platform firmware. So if we are told to disable it, we should
1064 * always disable it after setting the kernel's default
1067 pci_disable_acs_redir(dev);
1071 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1072 * @dev: PCI device to have its BARs restored
1074 * Restore the BAR values for a given device, so as to make it
1075 * accessible by its driver.
1077 static void pci_restore_bars(struct pci_dev *dev)
1081 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
1082 pci_update_resource(dev, i);
1085 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1087 if (pci_use_mid_pm())
1090 return acpi_pci_power_manageable(dev);
1093 static inline int platform_pci_set_power_state(struct pci_dev *dev,
1096 if (pci_use_mid_pm())
1097 return mid_pci_set_power_state(dev, t);
1099 return acpi_pci_set_power_state(dev, t);
1102 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1104 if (pci_use_mid_pm())
1105 return mid_pci_get_power_state(dev);
1107 return acpi_pci_get_power_state(dev);
1110 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1112 if (!pci_use_mid_pm())
1113 acpi_pci_refresh_power_state(dev);
1116 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1118 if (pci_use_mid_pm())
1119 return PCI_POWER_ERROR;
1121 return acpi_pci_choose_state(dev);
1124 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1126 if (pci_use_mid_pm())
1127 return PCI_POWER_ERROR;
1129 return acpi_pci_wakeup(dev, enable);
1132 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1134 if (pci_use_mid_pm())
1137 return acpi_pci_need_resume(dev);
1140 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1142 if (pci_use_mid_pm())
1145 return acpi_pci_bridge_d3(dev);
1149 * pci_update_current_state - Read power state of given device and cache it
1150 * @dev: PCI device to handle.
1151 * @state: State to cache in case the device doesn't have the PM capability
1153 * The power state is read from the PMCSR register, which however is
1154 * inaccessible in D3cold. The platform firmware is therefore queried first
1155 * to detect accessibility of the register. In case the platform firmware
1156 * reports an incorrect state or the device isn't power manageable by the
1157 * platform at all, we try to detect D3cold by testing accessibility of the
1158 * vendor ID in config space.
1160 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1162 if (platform_pci_get_power_state(dev) == PCI_D3cold) {
1163 dev->current_state = PCI_D3cold;
1164 } else if (dev->pm_cap) {
1167 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1168 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1169 dev->current_state = PCI_D3cold;
1172 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1174 dev->current_state = state;
1179 * pci_refresh_power_state - Refresh the given device's power state data
1180 * @dev: Target PCI device.
1182 * Ask the platform to refresh the devices power state information and invoke
1183 * pci_update_current_state() to update its current PCI power state.
1185 void pci_refresh_power_state(struct pci_dev *dev)
1187 platform_pci_refresh_power_state(dev);
1188 pci_update_current_state(dev, dev->current_state);
1192 * pci_platform_power_transition - Use platform to change device power state
1193 * @dev: PCI device to handle.
1194 * @state: State to put the device into.
1196 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1200 error = platform_pci_set_power_state(dev, state);
1202 pci_update_current_state(dev, state);
1203 else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1204 dev->current_state = PCI_D0;
1208 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1210 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1212 pm_request_resume(&pci_dev->dev);
1217 * pci_resume_bus - Walk given bus and runtime resume devices on it
1218 * @bus: Top bus of the subtree to walk.
1220 void pci_resume_bus(struct pci_bus *bus)
1223 pci_walk_bus(bus, pci_resume_one, NULL);
1226 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1229 bool retrain = false;
1230 struct pci_dev *bridge;
1232 if (pci_is_pcie(dev)) {
1233 bridge = pci_upstream_bridge(dev);
1239 * After reset, the device should not silently discard config
1240 * requests, but it may still indicate that it needs more time by
1241 * responding to them with CRS completions. The Root Port will
1242 * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
1243 * the read (except when CRS SV is enabled and the read was for the
1244 * Vendor ID; in that case it synthesizes 0x0001 data).
1246 * Wait for the device to return a non-CRS completion. Read the
1247 * Command register instead of Vendor ID so we don't have to
1248 * contend with the CRS SV value.
1253 pci_read_config_dword(dev, PCI_COMMAND, &id);
1254 if (!PCI_POSSIBLE_ERROR(id))
1257 if (delay > timeout) {
1258 pci_warn(dev, "not ready %dms after %s; giving up\n",
1259 delay - 1, reset_type);
1263 if (delay > PCI_RESET_WAIT) {
1266 if (pcie_failed_link_retrain(bridge)) {
1271 pci_info(dev, "not ready %dms after %s; waiting\n",
1272 delay - 1, reset_type);
1279 if (delay > PCI_RESET_WAIT)
1280 pci_info(dev, "ready %dms after %s\n", delay - 1,
1283 pci_dbg(dev, "ready %dms after %s\n", delay - 1,
1290 * pci_power_up - Put the given device into D0
1291 * @dev: PCI device to power up
1293 * On success, return 0 or 1, depending on whether or not it is necessary to
1294 * restore the device's BARs subsequently (1 is returned in that case).
1296 * On failure, return a negative error code. Always return failure if @dev
1297 * lacks a Power Management Capability, even if the platform was able to
1298 * put the device in D0 via non-PCI means.
1300 int pci_power_up(struct pci_dev *dev)
1306 platform_pci_set_power_state(dev, PCI_D0);
1309 state = platform_pci_get_power_state(dev);
1310 if (state == PCI_UNKNOWN)
1311 dev->current_state = PCI_D0;
1313 dev->current_state = state;
1318 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1319 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1320 pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",
1321 pci_power_name(dev->current_state));
1322 dev->current_state = PCI_D3cold;
1326 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1328 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
1329 !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET);
1331 if (state == PCI_D0)
1335 * Force the entire word to 0. This doesn't affect PME_Status, disables
1336 * PME_En, and sets PowerState to 0.
1338 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
1340 /* Mandatory transition delays; see PCI PM 1.2. */
1341 if (state == PCI_D3hot)
1342 pci_dev_d3_sleep(dev);
1343 else if (state == PCI_D2)
1344 udelay(PCI_PM_D2_DELAY);
1347 dev->current_state = PCI_D0;
1355 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1356 * @dev: PCI device to power up
1357 * @locked: whether pci_bus_sem is held
1359 * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1360 * to confirm the state change, restore its BARs if they might be lost and
1361 * reconfigure ASPM in accordance with the new power state.
1363 * If pci_restore_state() is going to be called right after a power state change
1364 * to D0, it is more efficient to use pci_power_up() directly instead of this
1367 static int pci_set_full_power_state(struct pci_dev *dev, bool locked)
1372 ret = pci_power_up(dev);
1374 if (dev->current_state == PCI_D0)
1380 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1381 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1382 if (dev->current_state != PCI_D0) {
1383 pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",
1384 pci_power_name(dev->current_state));
1385 } else if (ret > 0) {
1387 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1388 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1389 * from D3hot to D0 _may_ perform an internal reset, thereby
1390 * going to "D0 Uninitialized" rather than "D0 Initialized".
1391 * For example, at least some versions of the 3c905B and the
1392 * 3c556B exhibit this behaviour.
1394 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1395 * devices in a D3hot state at boot. Consequently, we need to
1396 * restore at least the BARs so that the device will be
1397 * accessible to its driver.
1399 pci_restore_bars(dev);
1403 pcie_aspm_pm_state_change(dev->bus->self, locked);
1409 * __pci_dev_set_current_state - Set current state of a PCI device
1410 * @dev: Device to handle
1411 * @data: pointer to state to be set
1413 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1415 pci_power_t state = *(pci_power_t *)data;
1417 dev->current_state = state;
1422 * pci_bus_set_current_state - Walk given bus and set current state of devices
1423 * @bus: Top bus of the subtree to walk.
1424 * @state: state to be set
1426 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1429 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1432 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state, bool locked)
1438 pci_walk_bus_locked(bus, __pci_dev_set_current_state, &state);
1440 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1444 * pci_set_low_power_state - Put a PCI device into a low-power state.
1445 * @dev: PCI device to handle.
1446 * @state: PCI power state (D1, D2, D3hot) to put the device into.
1447 * @locked: whether pci_bus_sem is held
1449 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1452 * -EINVAL if the requested state is invalid.
1453 * -EIO if device does not support PCI PM or its PM capabilities register has a
1454 * wrong version, or device doesn't support the requested state.
1455 * 0 if device already is in the requested state.
1456 * 0 if device's power state has been successfully changed.
1458 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state, bool locked)
1466 * Validate transition: We can enter D0 from any state, but if
1467 * we're already in a low-power state, we can only go deeper. E.g.,
1468 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1469 * we'd have to go from D3 to D0, then to D1.
1471 if (dev->current_state <= PCI_D3cold && dev->current_state > state) {
1472 pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1473 pci_power_name(dev->current_state),
1474 pci_power_name(state));
1478 /* Check if this device supports the desired state */
1479 if ((state == PCI_D1 && !dev->d1_support)
1480 || (state == PCI_D2 && !dev->d2_support))
1483 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1484 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1485 pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",
1486 pci_power_name(dev->current_state),
1487 pci_power_name(state));
1488 dev->current_state = PCI_D3cold;
1492 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1495 /* Enter specified state */
1496 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1498 /* Mandatory power management transition delays; see PCI PM 1.2. */
1499 if (state == PCI_D3hot)
1500 pci_dev_d3_sleep(dev);
1501 else if (state == PCI_D2)
1502 udelay(PCI_PM_D2_DELAY);
1504 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1505 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1506 if (dev->current_state != state)
1507 pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",
1508 pci_power_name(dev->current_state),
1509 pci_power_name(state));
1512 pcie_aspm_pm_state_change(dev->bus->self, locked);
1517 static int __pci_set_power_state(struct pci_dev *dev, pci_power_t state, bool locked)
1521 /* Bound the state we're entering */
1522 if (state > PCI_D3cold)
1524 else if (state < PCI_D0)
1526 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1529 * If the device or the parent bridge do not support PCI
1530 * PM, ignore the request if we're doing anything other
1531 * than putting it into D0 (which would only happen on
1536 /* Check if we're already there */
1537 if (dev->current_state == state)
1540 if (state == PCI_D0)
1541 return pci_set_full_power_state(dev, locked);
1544 * This device is quirked not to be put into D3, so don't put it in
1547 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1550 if (state == PCI_D3cold) {
1552 * To put the device in D3cold, put it into D3hot in the native
1553 * way, then put it into D3cold using platform ops.
1555 error = pci_set_low_power_state(dev, PCI_D3hot, locked);
1557 if (pci_platform_power_transition(dev, PCI_D3cold))
1560 /* Powering off a bridge may power off the whole hierarchy */
1561 if (dev->current_state == PCI_D3cold)
1562 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold, locked);
1564 error = pci_set_low_power_state(dev, state, locked);
1566 if (pci_platform_power_transition(dev, state))
1574 * pci_set_power_state - Set the power state of a PCI device
1575 * @dev: PCI device to handle.
1576 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1578 * Transition a device to a new power state, using the platform firmware and/or
1579 * the device's PCI PM registers.
1582 * -EINVAL if the requested state is invalid.
1583 * -EIO if device does not support PCI PM or its PM capabilities register has a
1584 * wrong version, or device doesn't support the requested state.
1585 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1586 * 0 if device already is in the requested state.
1587 * 0 if the transition is to D3 but D3 is not supported.
1588 * 0 if device's power state has been successfully changed.
1590 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1592 return __pci_set_power_state(dev, state, false);
1594 EXPORT_SYMBOL(pci_set_power_state);
1596 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state)
1598 lockdep_assert_held(&pci_bus_sem);
1600 return __pci_set_power_state(dev, state, true);
1602 EXPORT_SYMBOL(pci_set_power_state_locked);
1604 #define PCI_EXP_SAVE_REGS 7
1606 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1607 u16 cap, bool extended)
1609 struct pci_cap_saved_state *tmp;
1611 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1612 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1618 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1620 return _pci_find_saved_cap(dev, cap, false);
1623 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1625 return _pci_find_saved_cap(dev, cap, true);
1628 static int pci_save_pcie_state(struct pci_dev *dev)
1631 struct pci_cap_saved_state *save_state;
1634 if (!pci_is_pcie(dev))
1637 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1639 pci_err(dev, "buffer not found in %s\n", __func__);
1643 cap = (u16 *)&save_state->cap.data[0];
1644 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1645 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1646 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1647 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1648 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1649 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1650 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1655 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1657 #ifdef CONFIG_PCIEASPM
1658 struct pci_dev *bridge;
1661 bridge = pci_upstream_bridge(dev);
1662 if (bridge && bridge->ltr_path) {
1663 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1664 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1665 pci_dbg(bridge, "re-enabling LTR\n");
1666 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1667 PCI_EXP_DEVCTL2_LTR_EN);
1673 static void pci_restore_pcie_state(struct pci_dev *dev)
1676 struct pci_cap_saved_state *save_state;
1679 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1684 * Downstream ports reset the LTR enable bit when link goes down.
1685 * Check and re-configure the bit here before restoring device.
1686 * PCIe r5.0, sec 7.5.3.16.
1688 pci_bridge_reconfigure_ltr(dev);
1690 cap = (u16 *)&save_state->cap.data[0];
1691 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1692 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1693 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1694 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1695 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1696 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1697 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1700 static int pci_save_pcix_state(struct pci_dev *dev)
1703 struct pci_cap_saved_state *save_state;
1705 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1709 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1711 pci_err(dev, "buffer not found in %s\n", __func__);
1715 pci_read_config_word(dev, pos + PCI_X_CMD,
1716 (u16 *)save_state->cap.data);
1721 static void pci_restore_pcix_state(struct pci_dev *dev)
1724 struct pci_cap_saved_state *save_state;
1727 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1728 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1729 if (!save_state || !pos)
1731 cap = (u16 *)&save_state->cap.data[0];
1733 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1736 static void pci_save_ltr_state(struct pci_dev *dev)
1739 struct pci_cap_saved_state *save_state;
1742 if (!pci_is_pcie(dev))
1745 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1749 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1751 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1755 /* Some broken devices only support dword access to LTR */
1756 cap = &save_state->cap.data[0];
1757 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1760 static void pci_restore_ltr_state(struct pci_dev *dev)
1762 struct pci_cap_saved_state *save_state;
1766 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1767 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1768 if (!save_state || !ltr)
1771 /* Some broken devices only support dword access to LTR */
1772 cap = &save_state->cap.data[0];
1773 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1777 * pci_save_state - save the PCI configuration space of a device before
1779 * @dev: PCI device that we're dealing with
1781 int pci_save_state(struct pci_dev *dev)
1784 /* XXX: 100% dword access ok here? */
1785 for (i = 0; i < 16; i++) {
1786 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1787 pci_dbg(dev, "save config %#04x: %#010x\n",
1788 i * 4, dev->saved_config_space[i]);
1790 dev->state_saved = true;
1792 i = pci_save_pcie_state(dev);
1796 i = pci_save_pcix_state(dev);
1800 pci_save_ltr_state(dev);
1801 pci_save_dpc_state(dev);
1802 pci_save_aer_state(dev);
1803 pci_save_ptm_state(dev);
1804 return pci_save_vc_state(dev);
1806 EXPORT_SYMBOL(pci_save_state);
1808 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1809 u32 saved_val, int retry, bool force)
1813 pci_read_config_dword(pdev, offset, &val);
1814 if (!force && val == saved_val)
1818 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n",
1819 offset, val, saved_val);
1820 pci_write_config_dword(pdev, offset, saved_val);
1824 pci_read_config_dword(pdev, offset, &val);
1825 if (val == saved_val)
1832 static void pci_restore_config_space_range(struct pci_dev *pdev,
1833 int start, int end, int retry,
1838 for (index = end; index >= start; index--)
1839 pci_restore_config_dword(pdev, 4 * index,
1840 pdev->saved_config_space[index],
1844 static void pci_restore_config_space(struct pci_dev *pdev)
1846 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1847 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1848 /* Restore BARs before the command register. */
1849 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1850 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1851 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1852 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1855 * Force rewriting of prefetch registers to avoid S3 resume
1856 * issues on Intel PCI bridges that occur when these
1857 * registers are not explicitly written.
1859 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1860 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1862 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1866 static void pci_restore_rebar_state(struct pci_dev *pdev)
1868 unsigned int pos, nbars, i;
1871 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1875 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1876 nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
1878 for (i = 0; i < nbars; i++, pos += 8) {
1879 struct resource *res;
1882 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1883 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1884 res = pdev->resource + bar_idx;
1885 size = pci_rebar_bytes_to_size(resource_size(res));
1886 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1887 ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
1888 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1893 * pci_restore_state - Restore the saved state of a PCI device
1894 * @dev: PCI device that we're dealing with
1896 void pci_restore_state(struct pci_dev *dev)
1898 if (!dev->state_saved)
1902 * Restore max latencies (in the LTR capability) before enabling
1903 * LTR itself (in the PCIe capability).
1905 pci_restore_ltr_state(dev);
1907 pci_restore_pcie_state(dev);
1908 pci_restore_pasid_state(dev);
1909 pci_restore_pri_state(dev);
1910 pci_restore_ats_state(dev);
1911 pci_restore_vc_state(dev);
1912 pci_restore_rebar_state(dev);
1913 pci_restore_dpc_state(dev);
1914 pci_restore_ptm_state(dev);
1916 pci_aer_clear_status(dev);
1917 pci_restore_aer_state(dev);
1919 pci_restore_config_space(dev);
1921 pci_restore_pcix_state(dev);
1922 pci_restore_msi_state(dev);
1924 /* Restore ACS and IOV configuration state */
1925 pci_enable_acs(dev);
1926 pci_restore_iov_state(dev);
1928 dev->state_saved = false;
1930 EXPORT_SYMBOL(pci_restore_state);
1932 struct pci_saved_state {
1933 u32 config_space[16];
1934 struct pci_cap_saved_data cap[];
1938 * pci_store_saved_state - Allocate and return an opaque struct containing
1939 * the device saved state.
1940 * @dev: PCI device that we're dealing with
1942 * Return NULL if no state or error.
1944 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1946 struct pci_saved_state *state;
1947 struct pci_cap_saved_state *tmp;
1948 struct pci_cap_saved_data *cap;
1951 if (!dev->state_saved)
1954 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1956 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1957 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1959 state = kzalloc(size, GFP_KERNEL);
1963 memcpy(state->config_space, dev->saved_config_space,
1964 sizeof(state->config_space));
1967 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1968 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1969 memcpy(cap, &tmp->cap, len);
1970 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1972 /* Empty cap_save terminates list */
1976 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1979 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1980 * @dev: PCI device that we're dealing with
1981 * @state: Saved state returned from pci_store_saved_state()
1983 int pci_load_saved_state(struct pci_dev *dev,
1984 struct pci_saved_state *state)
1986 struct pci_cap_saved_data *cap;
1988 dev->state_saved = false;
1993 memcpy(dev->saved_config_space, state->config_space,
1994 sizeof(state->config_space));
1998 struct pci_cap_saved_state *tmp;
2000 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
2001 if (!tmp || tmp->cap.size != cap->size)
2004 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
2005 cap = (struct pci_cap_saved_data *)((u8 *)cap +
2006 sizeof(struct pci_cap_saved_data) + cap->size);
2009 dev->state_saved = true;
2012 EXPORT_SYMBOL_GPL(pci_load_saved_state);
2015 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
2016 * and free the memory allocated for it.
2017 * @dev: PCI device that we're dealing with
2018 * @state: Pointer to saved state returned from pci_store_saved_state()
2020 int pci_load_and_free_saved_state(struct pci_dev *dev,
2021 struct pci_saved_state **state)
2023 int ret = pci_load_saved_state(dev, *state);
2028 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
2030 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
2032 return pci_enable_resources(dev, bars);
2035 static int do_pci_enable_device(struct pci_dev *dev, int bars)
2038 struct pci_dev *bridge;
2042 err = pci_set_power_state(dev, PCI_D0);
2043 if (err < 0 && err != -EIO)
2046 bridge = pci_upstream_bridge(dev);
2048 pcie_aspm_powersave_config_link(bridge);
2050 err = pcibios_enable_device(dev, bars);
2053 pci_fixup_device(pci_fixup_enable, dev);
2055 if (dev->msi_enabled || dev->msix_enabled)
2058 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
2060 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2061 if (cmd & PCI_COMMAND_INTX_DISABLE)
2062 pci_write_config_word(dev, PCI_COMMAND,
2063 cmd & ~PCI_COMMAND_INTX_DISABLE);
2070 * pci_reenable_device - Resume abandoned device
2071 * @dev: PCI device to be resumed
2073 * NOTE: This function is a backend of pci_default_resume() and is not supposed
2074 * to be called by normal code, write proper resume handler and use it instead.
2076 int pci_reenable_device(struct pci_dev *dev)
2078 if (pci_is_enabled(dev))
2079 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
2082 EXPORT_SYMBOL(pci_reenable_device);
2084 static void pci_enable_bridge(struct pci_dev *dev)
2086 struct pci_dev *bridge;
2089 bridge = pci_upstream_bridge(dev);
2091 pci_enable_bridge(bridge);
2093 if (pci_is_enabled(dev)) {
2094 if (!dev->is_busmaster)
2095 pci_set_master(dev);
2099 retval = pci_enable_device(dev);
2101 pci_err(dev, "Error enabling bridge (%d), continuing\n",
2103 pci_set_master(dev);
2106 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
2108 struct pci_dev *bridge;
2113 * Power state could be unknown at this point, either due to a fresh
2114 * boot or a device removal call. So get the current power state
2115 * so that things like MSI message writing will behave as expected
2116 * (e.g. if the device really is in D0 at enable time).
2118 pci_update_current_state(dev, dev->current_state);
2120 if (atomic_inc_return(&dev->enable_cnt) > 1)
2121 return 0; /* already enabled */
2123 bridge = pci_upstream_bridge(dev);
2125 pci_enable_bridge(bridge);
2127 /* only skip sriov related */
2128 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
2129 if (dev->resource[i].flags & flags)
2131 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
2132 if (dev->resource[i].flags & flags)
2135 err = do_pci_enable_device(dev, bars);
2137 atomic_dec(&dev->enable_cnt);
2142 * pci_enable_device_io - Initialize a device for use with IO space
2143 * @dev: PCI device to be initialized
2145 * Initialize device before it's used by a driver. Ask low-level code
2146 * to enable I/O resources. Wake up the device if it was suspended.
2147 * Beware, this function can fail.
2149 int pci_enable_device_io(struct pci_dev *dev)
2151 return pci_enable_device_flags(dev, IORESOURCE_IO);
2153 EXPORT_SYMBOL(pci_enable_device_io);
2156 * pci_enable_device_mem - Initialize a device for use with Memory space
2157 * @dev: PCI device to be initialized
2159 * Initialize device before it's used by a driver. Ask low-level code
2160 * to enable Memory resources. Wake up the device if it was suspended.
2161 * Beware, this function can fail.
2163 int pci_enable_device_mem(struct pci_dev *dev)
2165 return pci_enable_device_flags(dev, IORESOURCE_MEM);
2167 EXPORT_SYMBOL(pci_enable_device_mem);
2170 * pci_enable_device - Initialize device before it's used by a driver.
2171 * @dev: PCI device to be initialized
2173 * Initialize device before it's used by a driver. Ask low-level code
2174 * to enable I/O and memory. Wake up the device if it was suspended.
2175 * Beware, this function can fail.
2177 * Note we don't actually enable the device many times if we call
2178 * this function repeatedly (we just increment the count).
2180 int pci_enable_device(struct pci_dev *dev)
2182 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2184 EXPORT_SYMBOL(pci_enable_device);
2187 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2188 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2189 * there's no need to track it separately. pci_devres is initialized
2190 * when a device is enabled using managed PCI device enable interface.
2193 unsigned int enabled:1;
2194 unsigned int pinned:1;
2195 unsigned int orig_intx:1;
2196 unsigned int restore_intx:1;
2201 static void pcim_release(struct device *gendev, void *res)
2203 struct pci_dev *dev = to_pci_dev(gendev);
2204 struct pci_devres *this = res;
2207 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2208 if (this->region_mask & (1 << i))
2209 pci_release_region(dev, i);
2214 if (this->restore_intx)
2215 pci_intx(dev, this->orig_intx);
2217 if (this->enabled && !this->pinned)
2218 pci_disable_device(dev);
2221 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2223 struct pci_devres *dr, *new_dr;
2225 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2229 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2232 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2235 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2237 if (pci_is_managed(pdev))
2238 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2243 * pcim_enable_device - Managed pci_enable_device()
2244 * @pdev: PCI device to be initialized
2246 * Managed pci_enable_device().
2248 int pcim_enable_device(struct pci_dev *pdev)
2250 struct pci_devres *dr;
2253 dr = get_pci_dr(pdev);
2259 rc = pci_enable_device(pdev);
2261 pdev->is_managed = 1;
2266 EXPORT_SYMBOL(pcim_enable_device);
2269 * pcim_pin_device - Pin managed PCI device
2270 * @pdev: PCI device to pin
2272 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2273 * driver detach. @pdev must have been enabled with
2274 * pcim_enable_device().
2276 void pcim_pin_device(struct pci_dev *pdev)
2278 struct pci_devres *dr;
2280 dr = find_pci_dr(pdev);
2281 WARN_ON(!dr || !dr->enabled);
2285 EXPORT_SYMBOL(pcim_pin_device);
2288 * pcibios_device_add - provide arch specific hooks when adding device dev
2289 * @dev: the PCI device being added
2291 * Permits the platform to provide architecture specific functionality when
2292 * devices are added. This is the default implementation. Architecture
2293 * implementations can override this.
2295 int __weak pcibios_device_add(struct pci_dev *dev)
2301 * pcibios_release_device - provide arch specific hooks when releasing
2303 * @dev: the PCI device being released
2305 * Permits the platform to provide architecture specific functionality when
2306 * devices are released. This is the default implementation. Architecture
2307 * implementations can override this.
2309 void __weak pcibios_release_device(struct pci_dev *dev) {}
2312 * pcibios_disable_device - disable arch specific PCI resources for device dev
2313 * @dev: the PCI device to disable
2315 * Disables architecture specific PCI resources for the device. This
2316 * is the default implementation. Architecture implementations can
2319 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2322 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2323 * @irq: ISA IRQ to penalize
2324 * @active: IRQ active or not
2326 * Permits the platform to provide architecture-specific functionality when
2327 * penalizing ISA IRQs. This is the default implementation. Architecture
2328 * implementations can override this.
2330 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2332 static void do_pci_disable_device(struct pci_dev *dev)
2336 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2337 if (pci_command & PCI_COMMAND_MASTER) {
2338 pci_command &= ~PCI_COMMAND_MASTER;
2339 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2342 pcibios_disable_device(dev);
2346 * pci_disable_enabled_device - Disable device without updating enable_cnt
2347 * @dev: PCI device to disable
2349 * NOTE: This function is a backend of PCI power management routines and is
2350 * not supposed to be called drivers.
2352 void pci_disable_enabled_device(struct pci_dev *dev)
2354 if (pci_is_enabled(dev))
2355 do_pci_disable_device(dev);
2359 * pci_disable_device - Disable PCI device after use
2360 * @dev: PCI device to be disabled
2362 * Signal to the system that the PCI device is not in use by the system
2363 * anymore. This only involves disabling PCI bus-mastering, if active.
2365 * Note we don't actually disable the device until all callers of
2366 * pci_enable_device() have called pci_disable_device().
2368 void pci_disable_device(struct pci_dev *dev)
2370 struct pci_devres *dr;
2372 dr = find_pci_dr(dev);
2376 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2377 "disabling already-disabled device");
2379 if (atomic_dec_return(&dev->enable_cnt) != 0)
2382 do_pci_disable_device(dev);
2384 dev->is_busmaster = 0;
2386 EXPORT_SYMBOL(pci_disable_device);
2389 * pcibios_set_pcie_reset_state - set reset state for device dev
2390 * @dev: the PCIe device reset
2391 * @state: Reset state to enter into
2393 * Set the PCIe reset state for the device. This is the default
2394 * implementation. Architecture implementations can override this.
2396 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2397 enum pcie_reset_state state)
2403 * pci_set_pcie_reset_state - set reset state for device dev
2404 * @dev: the PCIe device reset
2405 * @state: Reset state to enter into
2407 * Sets the PCI reset state for the device.
2409 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2411 return pcibios_set_pcie_reset_state(dev, state);
2413 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2415 #ifdef CONFIG_PCIEAER
2416 void pcie_clear_device_status(struct pci_dev *dev)
2420 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2421 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2426 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2427 * @dev: PCIe root port or event collector.
2429 void pcie_clear_root_pme_status(struct pci_dev *dev)
2431 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2435 * pci_check_pme_status - Check if given device has generated PME.
2436 * @dev: Device to check.
2438 * Check the PME status of the device and if set, clear it and clear PME enable
2439 * (if set). Return 'true' if PME status and PME enable were both set or
2440 * 'false' otherwise.
2442 bool pci_check_pme_status(struct pci_dev *dev)
2451 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2452 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2453 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2456 /* Clear PME status. */
2457 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2458 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2459 /* Disable PME to avoid interrupt flood. */
2460 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2464 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2470 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2471 * @dev: Device to handle.
2472 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2474 * Check if @dev has generated PME and queue a resume request for it in that
2477 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2479 if (pme_poll_reset && dev->pme_poll)
2480 dev->pme_poll = false;
2482 if (pci_check_pme_status(dev)) {
2483 pci_wakeup_event(dev);
2484 pm_request_resume(&dev->dev);
2490 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2491 * @bus: Top bus of the subtree to walk.
2493 void pci_pme_wakeup_bus(struct pci_bus *bus)
2496 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2501 * pci_pme_capable - check the capability of PCI device to generate PME#
2502 * @dev: PCI device to handle.
2503 * @state: PCI state from which device will issue PME#.
2505 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2510 return !!(dev->pme_support & (1 << state));
2512 EXPORT_SYMBOL(pci_pme_capable);
2514 static void pci_pme_list_scan(struct work_struct *work)
2516 struct pci_pme_device *pme_dev, *n;
2518 mutex_lock(&pci_pme_list_mutex);
2519 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2520 struct pci_dev *pdev = pme_dev->dev;
2522 if (pdev->pme_poll) {
2523 struct pci_dev *bridge = pdev->bus->self;
2524 struct device *dev = &pdev->dev;
2525 struct device *bdev = bridge ? &bridge->dev : NULL;
2529 * If we have a bridge, it should be in an active/D0
2530 * state or the configuration space of subordinate
2531 * devices may not be accessible or stable over the
2532 * course of the call.
2535 bref = pm_runtime_get_if_active(bdev, true);
2539 if (bridge->current_state != PCI_D0)
2544 * The device itself should be suspended but config
2545 * space must be accessible, therefore it cannot be in
2548 if (pm_runtime_suspended(dev) &&
2549 pdev->current_state != PCI_D3cold)
2550 pci_pme_wakeup(pdev, NULL);
2554 pm_runtime_put(bdev);
2556 list_del(&pme_dev->list);
2560 if (!list_empty(&pci_pme_list))
2561 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2562 msecs_to_jiffies(PME_TIMEOUT));
2563 mutex_unlock(&pci_pme_list_mutex);
2566 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2570 if (!dev->pme_support)
2573 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2574 /* Clear PME_Status by writing 1 to it and enable PME# */
2575 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2577 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2579 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2583 * pci_pme_restore - Restore PME configuration after config space restore.
2584 * @dev: PCI device to update.
2586 void pci_pme_restore(struct pci_dev *dev)
2590 if (!dev->pme_support)
2593 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2594 if (dev->wakeup_prepared) {
2595 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2596 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2598 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2599 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2601 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2605 * pci_pme_active - enable or disable PCI device's PME# function
2606 * @dev: PCI device to handle.
2607 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2609 * The caller must verify that the device is capable of generating PME# before
2610 * calling this function with @enable equal to 'true'.
2612 void pci_pme_active(struct pci_dev *dev, bool enable)
2614 __pci_pme_active(dev, enable);
2617 * PCI (as opposed to PCIe) PME requires that the device have
2618 * its PME# line hooked up correctly. Not all hardware vendors
2619 * do this, so the PME never gets delivered and the device
2620 * remains asleep. The easiest way around this is to
2621 * periodically walk the list of suspended devices and check
2622 * whether any have their PME flag set. The assumption is that
2623 * we'll wake up often enough anyway that this won't be a huge
2624 * hit, and the power savings from the devices will still be a
2627 * Although PCIe uses in-band PME message instead of PME# line
2628 * to report PME, PME does not work for some PCIe devices in
2629 * reality. For example, there are devices that set their PME
2630 * status bits, but don't really bother to send a PME message;
2631 * there are PCI Express Root Ports that don't bother to
2632 * trigger interrupts when they receive PME messages from the
2633 * devices below. So PME poll is used for PCIe devices too.
2636 if (dev->pme_poll) {
2637 struct pci_pme_device *pme_dev;
2639 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2642 pci_warn(dev, "can't enable PME#\n");
2646 mutex_lock(&pci_pme_list_mutex);
2647 list_add(&pme_dev->list, &pci_pme_list);
2648 if (list_is_singular(&pci_pme_list))
2649 queue_delayed_work(system_freezable_wq,
2651 msecs_to_jiffies(PME_TIMEOUT));
2652 mutex_unlock(&pci_pme_list_mutex);
2654 mutex_lock(&pci_pme_list_mutex);
2655 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2656 if (pme_dev->dev == dev) {
2657 list_del(&pme_dev->list);
2662 mutex_unlock(&pci_pme_list_mutex);
2666 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2668 EXPORT_SYMBOL(pci_pme_active);
2671 * __pci_enable_wake - enable PCI device as wakeup event source
2672 * @dev: PCI device affected
2673 * @state: PCI state from which device will issue wakeup events
2674 * @enable: True to enable event generation; false to disable
2676 * This enables the device as a wakeup event source, or disables it.
2677 * When such events involves platform-specific hooks, those hooks are
2678 * called automatically by this routine.
2680 * Devices with legacy power management (no standard PCI PM capabilities)
2681 * always require such platform hooks.
2684 * 0 is returned on success
2685 * -EINVAL is returned if device is not supposed to wake up the system
2686 * Error code depending on the platform is returned if both the platform and
2687 * the native mechanism fail to enable the generation of wake-up events
2689 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2694 * Bridges that are not power-manageable directly only signal
2695 * wakeup on behalf of subordinate devices which is set up
2696 * elsewhere, so skip them. However, bridges that are
2697 * power-manageable may signal wakeup for themselves (for example,
2698 * on a hotplug event) and they need to be covered here.
2700 if (!pci_power_manageable(dev))
2703 /* Don't do the same thing twice in a row for one device. */
2704 if (!!enable == !!dev->wakeup_prepared)
2708 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2709 * Anderson we should be doing PME# wake enable followed by ACPI wake
2710 * enable. To disable wake-up we call the platform first, for symmetry.
2717 * Enable PME signaling if the device can signal PME from
2718 * D3cold regardless of whether or not it can signal PME from
2719 * the current target state, because that will allow it to
2720 * signal PME when the hierarchy above it goes into D3cold and
2721 * the device itself ends up in D3cold as a result of that.
2723 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2724 pci_pme_active(dev, true);
2727 error = platform_pci_set_wakeup(dev, true);
2731 dev->wakeup_prepared = true;
2733 platform_pci_set_wakeup(dev, false);
2734 pci_pme_active(dev, false);
2735 dev->wakeup_prepared = false;
2742 * pci_enable_wake - change wakeup settings for a PCI device
2743 * @pci_dev: Target device
2744 * @state: PCI state from which device will issue wakeup events
2745 * @enable: Whether or not to enable event generation
2747 * If @enable is set, check device_may_wakeup() for the device before calling
2748 * __pci_enable_wake() for it.
2750 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2752 if (enable && !device_may_wakeup(&pci_dev->dev))
2755 return __pci_enable_wake(pci_dev, state, enable);
2757 EXPORT_SYMBOL(pci_enable_wake);
2760 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2761 * @dev: PCI device to prepare
2762 * @enable: True to enable wake-up event generation; false to disable
2764 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2765 * and this function allows them to set that up cleanly - pci_enable_wake()
2766 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2767 * ordering constraints.
2769 * This function only returns error code if the device is not allowed to wake
2770 * up the system from sleep or it is not capable of generating PME# from both
2771 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2773 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2775 return pci_pme_capable(dev, PCI_D3cold) ?
2776 pci_enable_wake(dev, PCI_D3cold, enable) :
2777 pci_enable_wake(dev, PCI_D3hot, enable);
2779 EXPORT_SYMBOL(pci_wake_from_d3);
2782 * pci_target_state - find an appropriate low power state for a given PCI dev
2784 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2786 * Use underlying platform code to find a supported low power state for @dev.
2787 * If the platform can't manage @dev, return the deepest state from which it
2788 * can generate wake events, based on any available PME info.
2790 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2792 if (platform_pci_power_manageable(dev)) {
2794 * Call the platform to find the target state for the device.
2796 pci_power_t state = platform_pci_choose_state(dev);
2799 case PCI_POWER_ERROR:
2805 if (pci_no_d1d2(dev))
2813 * If the device is in D3cold even though it's not power-manageable by
2814 * the platform, it may have been powered down by non-standard means.
2815 * Best to let it slumber.
2817 if (dev->current_state == PCI_D3cold)
2819 else if (!dev->pm_cap)
2822 if (wakeup && dev->pme_support) {
2823 pci_power_t state = PCI_D3hot;
2826 * Find the deepest state from which the device can generate
2829 while (state && !(dev->pme_support & (1 << state)))
2834 else if (dev->pme_support & 1)
2842 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2843 * into a sleep state
2844 * @dev: Device to handle.
2846 * Choose the power state appropriate for the device depending on whether
2847 * it can wake up the system and/or is power manageable by the platform
2848 * (PCI_D3hot is the default) and put the device into that state.
2850 int pci_prepare_to_sleep(struct pci_dev *dev)
2852 bool wakeup = device_may_wakeup(&dev->dev);
2853 pci_power_t target_state = pci_target_state(dev, wakeup);
2856 if (target_state == PCI_POWER_ERROR)
2859 pci_enable_wake(dev, target_state, wakeup);
2861 error = pci_set_power_state(dev, target_state);
2864 pci_enable_wake(dev, target_state, false);
2868 EXPORT_SYMBOL(pci_prepare_to_sleep);
2871 * pci_back_from_sleep - turn PCI device on during system-wide transition
2872 * into working state
2873 * @dev: Device to handle.
2875 * Disable device's system wake-up capability and put it into D0.
2877 int pci_back_from_sleep(struct pci_dev *dev)
2879 int ret = pci_set_power_state(dev, PCI_D0);
2884 pci_enable_wake(dev, PCI_D0, false);
2887 EXPORT_SYMBOL(pci_back_from_sleep);
2890 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2891 * @dev: PCI device being suspended.
2893 * Prepare @dev to generate wake-up events at run time and put it into a low
2896 int pci_finish_runtime_suspend(struct pci_dev *dev)
2898 pci_power_t target_state;
2901 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2902 if (target_state == PCI_POWER_ERROR)
2905 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2907 error = pci_set_power_state(dev, target_state);
2910 pci_enable_wake(dev, target_state, false);
2916 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2917 * @dev: Device to check.
2919 * Return true if the device itself is capable of generating wake-up events
2920 * (through the platform or using the native PCIe PME) or if the device supports
2921 * PME and one of its upstream bridges can generate wake-up events.
2923 bool pci_dev_run_wake(struct pci_dev *dev)
2925 struct pci_bus *bus = dev->bus;
2927 if (!dev->pme_support)
2930 /* PME-capable in principle, but not from the target power state */
2931 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2934 if (device_can_wakeup(&dev->dev))
2937 while (bus->parent) {
2938 struct pci_dev *bridge = bus->self;
2940 if (device_can_wakeup(&bridge->dev))
2946 /* We have reached the root bus. */
2948 return device_can_wakeup(bus->bridge);
2952 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2955 * pci_dev_need_resume - Check if it is necessary to resume the device.
2956 * @pci_dev: Device to check.
2958 * Return 'true' if the device is not runtime-suspended or it has to be
2959 * reconfigured due to wakeup settings difference between system and runtime
2960 * suspend, or the current power state of it is not suitable for the upcoming
2961 * (system-wide) transition.
2963 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2965 struct device *dev = &pci_dev->dev;
2966 pci_power_t target_state;
2968 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2971 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2974 * If the earlier platform check has not triggered, D3cold is just power
2975 * removal on top of D3hot, so no need to resume the device in that
2978 return target_state != pci_dev->current_state &&
2979 target_state != PCI_D3cold &&
2980 pci_dev->current_state != PCI_D3hot;
2984 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2985 * @pci_dev: Device to check.
2987 * If the device is suspended and it is not configured for system wakeup,
2988 * disable PME for it to prevent it from waking up the system unnecessarily.
2990 * Note that if the device's power state is D3cold and the platform check in
2991 * pci_dev_need_resume() has not triggered, the device's configuration need not
2994 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2996 struct device *dev = &pci_dev->dev;
2998 spin_lock_irq(&dev->power.lock);
3000 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
3001 pci_dev->current_state < PCI_D3cold)
3002 __pci_pme_active(pci_dev, false);
3004 spin_unlock_irq(&dev->power.lock);
3008 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
3009 * @pci_dev: Device to handle.
3011 * If the device is runtime suspended and wakeup-capable, enable PME for it as
3012 * it might have been disabled during the prepare phase of system suspend if
3013 * the device was not configured for system wakeup.
3015 void pci_dev_complete_resume(struct pci_dev *pci_dev)
3017 struct device *dev = &pci_dev->dev;
3019 if (!pci_dev_run_wake(pci_dev))
3022 spin_lock_irq(&dev->power.lock);
3024 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
3025 __pci_pme_active(pci_dev, true);
3027 spin_unlock_irq(&dev->power.lock);
3031 * pci_choose_state - Choose the power state of a PCI device.
3032 * @dev: Target PCI device.
3033 * @state: Target state for the whole system.
3035 * Returns PCI power state suitable for @dev and @state.
3037 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
3039 if (state.event == PM_EVENT_ON)
3042 return pci_target_state(dev, false);
3044 EXPORT_SYMBOL(pci_choose_state);
3046 void pci_config_pm_runtime_get(struct pci_dev *pdev)
3048 struct device *dev = &pdev->dev;
3049 struct device *parent = dev->parent;
3052 pm_runtime_get_sync(parent);
3053 pm_runtime_get_noresume(dev);
3055 * pdev->current_state is set to PCI_D3cold during suspending,
3056 * so wait until suspending completes
3058 pm_runtime_barrier(dev);
3060 * Only need to resume devices in D3cold, because config
3061 * registers are still accessible for devices suspended but
3064 if (pdev->current_state == PCI_D3cold)
3065 pm_runtime_resume(dev);
3068 void pci_config_pm_runtime_put(struct pci_dev *pdev)
3070 struct device *dev = &pdev->dev;
3071 struct device *parent = dev->parent;
3073 pm_runtime_put(dev);
3075 pm_runtime_put_sync(parent);
3078 static const struct dmi_system_id bridge_d3_blacklist[] = {
3082 * Gigabyte X299 root port is not marked as hotplug capable
3083 * which allows Linux to power manage it. However, this
3084 * confuses the BIOS SMI handler so don't power manage root
3085 * ports on that system.
3087 .ident = "X299 DESIGNARE EX-CF",
3089 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
3090 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
3095 * Downstream device is not accessible after putting a root port
3096 * into D3cold and back into D0 on Elo Continental Z2 board
3098 .ident = "Elo Continental Z2",
3100 DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"),
3101 DMI_MATCH(DMI_BOARD_NAME, "Geminilake"),
3102 DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"),
3110 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3111 * @bridge: Bridge to check
3113 * This function checks if it is possible to move the bridge to D3.
3114 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
3116 bool pci_bridge_d3_possible(struct pci_dev *bridge)
3118 if (!pci_is_pcie(bridge))
3121 switch (pci_pcie_type(bridge)) {
3122 case PCI_EXP_TYPE_ROOT_PORT:
3123 case PCI_EXP_TYPE_UPSTREAM:
3124 case PCI_EXP_TYPE_DOWNSTREAM:
3125 if (pci_bridge_d3_disable)
3129 * Hotplug ports handled by firmware in System Management Mode
3130 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
3132 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
3135 if (pci_bridge_d3_force)
3138 /* Even the oldest 2010 Thunderbolt controller supports D3. */
3139 if (bridge->is_thunderbolt)
3142 /* Platform might know better if the bridge supports D3 */
3143 if (platform_pci_bridge_d3(bridge))
3147 * Hotplug ports handled natively by the OS were not validated
3148 * by vendors for runtime D3 at least until 2018 because there
3149 * was no OS support.
3151 if (bridge->is_hotplug_bridge)
3154 if (dmi_check_system(bridge_d3_blacklist))
3158 * It should be safe to put PCIe ports from 2015 or newer
3161 if (dmi_get_bios_year() >= 2015)
3169 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
3171 bool *d3cold_ok = data;
3173 if (/* The device needs to be allowed to go D3cold ... */
3174 dev->no_d3cold || !dev->d3cold_allowed ||
3176 /* ... and if it is wakeup capable to do so from D3cold. */
3177 (device_may_wakeup(&dev->dev) &&
3178 !pci_pme_capable(dev, PCI_D3cold)) ||
3180 /* If it is a bridge it must be allowed to go to D3. */
3181 !pci_power_manageable(dev))
3189 * pci_bridge_d3_update - Update bridge D3 capabilities
3190 * @dev: PCI device which is changed
3192 * Update upstream bridge PM capabilities accordingly depending on if the
3193 * device PM configuration was changed or the device is being removed. The
3194 * change is also propagated upstream.
3196 void pci_bridge_d3_update(struct pci_dev *dev)
3198 bool remove = !device_is_registered(&dev->dev);
3199 struct pci_dev *bridge;
3200 bool d3cold_ok = true;
3202 bridge = pci_upstream_bridge(dev);
3203 if (!bridge || !pci_bridge_d3_possible(bridge))
3207 * If D3 is currently allowed for the bridge, removing one of its
3208 * children won't change that.
3210 if (remove && bridge->bridge_d3)
3214 * If D3 is currently allowed for the bridge and a child is added or
3215 * changed, disallowance of D3 can only be caused by that child, so
3216 * we only need to check that single device, not any of its siblings.
3218 * If D3 is currently not allowed for the bridge, checking the device
3219 * first may allow us to skip checking its siblings.
3222 pci_dev_check_d3cold(dev, &d3cold_ok);
3225 * If D3 is currently not allowed for the bridge, this may be caused
3226 * either by the device being changed/removed or any of its siblings,
3227 * so we need to go through all children to find out if one of them
3228 * continues to block D3.
3230 if (d3cold_ok && !bridge->bridge_d3)
3231 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3234 if (bridge->bridge_d3 != d3cold_ok) {
3235 bridge->bridge_d3 = d3cold_ok;
3236 /* Propagate change to upstream bridges */
3237 pci_bridge_d3_update(bridge);
3242 * pci_d3cold_enable - Enable D3cold for device
3243 * @dev: PCI device to handle
3245 * This function can be used in drivers to enable D3cold from the device
3246 * they handle. It also updates upstream PCI bridge PM capabilities
3249 void pci_d3cold_enable(struct pci_dev *dev)
3251 if (dev->no_d3cold) {
3252 dev->no_d3cold = false;
3253 pci_bridge_d3_update(dev);
3256 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3259 * pci_d3cold_disable - Disable D3cold for device
3260 * @dev: PCI device to handle
3262 * This function can be used in drivers to disable D3cold from the device
3263 * they handle. It also updates upstream PCI bridge PM capabilities
3266 void pci_d3cold_disable(struct pci_dev *dev)
3268 if (!dev->no_d3cold) {
3269 dev->no_d3cold = true;
3270 pci_bridge_d3_update(dev);
3273 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3276 * pci_pm_init - Initialize PM functions of given PCI device
3277 * @dev: PCI device to handle.
3279 void pci_pm_init(struct pci_dev *dev)
3285 pm_runtime_forbid(&dev->dev);
3286 pm_runtime_set_active(&dev->dev);
3287 pm_runtime_enable(&dev->dev);
3288 device_enable_async_suspend(&dev->dev);
3289 dev->wakeup_prepared = false;
3292 dev->pme_support = 0;
3294 /* find PCI PM capability in list */
3295 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3298 /* Check device's ability to generate PME# */
3299 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3301 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3302 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3303 pmc & PCI_PM_CAP_VER_MASK);
3308 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3309 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3310 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3311 dev->d3cold_allowed = true;
3313 dev->d1_support = false;
3314 dev->d2_support = false;
3315 if (!pci_no_d1d2(dev)) {
3316 if (pmc & PCI_PM_CAP_D1)
3317 dev->d1_support = true;
3318 if (pmc & PCI_PM_CAP_D2)
3319 dev->d2_support = true;
3321 if (dev->d1_support || dev->d2_support)
3322 pci_info(dev, "supports%s%s\n",
3323 dev->d1_support ? " D1" : "",
3324 dev->d2_support ? " D2" : "");
3327 pmc &= PCI_PM_CAP_PME_MASK;
3329 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3330 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3331 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3332 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3333 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3334 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3335 dev->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc);
3336 dev->pme_poll = true;
3338 * Make device's PM flags reflect the wake-up capability, but
3339 * let the user space enable it to wake up the system as needed.
3341 device_set_wakeup_capable(&dev->dev, true);
3342 /* Disable the PME# generation functionality */
3343 pci_pme_active(dev, false);
3346 pci_read_config_word(dev, PCI_STATUS, &status);
3347 if (status & PCI_STATUS_IMM_READY)
3351 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3353 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3357 case PCI_EA_P_VF_MEM:
3358 flags |= IORESOURCE_MEM;
3360 case PCI_EA_P_MEM_PREFETCH:
3361 case PCI_EA_P_VF_MEM_PREFETCH:
3362 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3365 flags |= IORESOURCE_IO;
3374 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3377 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3378 return &dev->resource[bei];
3379 #ifdef CONFIG_PCI_IOV
3380 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3381 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3382 return &dev->resource[PCI_IOV_RESOURCES +
3383 bei - PCI_EA_BEI_VF_BAR0];
3385 else if (bei == PCI_EA_BEI_ROM)
3386 return &dev->resource[PCI_ROM_RESOURCE];
3391 /* Read an Enhanced Allocation (EA) entry */
3392 static int pci_ea_read(struct pci_dev *dev, int offset)
3394 struct resource *res;
3395 const char *res_name;
3396 int ent_size, ent_offset = offset;
3397 resource_size_t start, end;
3398 unsigned long flags;
3399 u32 dw0, bei, base, max_offset;
3401 bool support_64 = (sizeof(resource_size_t) >= 8);
3403 pci_read_config_dword(dev, ent_offset, &dw0);
3406 /* Entry size field indicates DWORDs after 1st */
3407 ent_size = (FIELD_GET(PCI_EA_ES, dw0) + 1) << 2;
3409 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3412 bei = FIELD_GET(PCI_EA_BEI, dw0);
3413 prop = FIELD_GET(PCI_EA_PP, dw0);
3416 * If the Property is in the reserved range, try the Secondary
3419 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3420 prop = FIELD_GET(PCI_EA_SP, dw0);
3421 if (prop > PCI_EA_P_BRIDGE_IO)
3424 res = pci_ea_get_resource(dev, bei, prop);
3425 res_name = pci_resource_name(dev, bei);
3427 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3431 flags = pci_ea_flags(dev, prop);
3433 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3438 pci_read_config_dword(dev, ent_offset, &base);
3439 start = (base & PCI_EA_FIELD_MASK);
3442 /* Read MaxOffset */
3443 pci_read_config_dword(dev, ent_offset, &max_offset);
3446 /* Read Base MSBs (if 64-bit entry) */
3447 if (base & PCI_EA_IS_64) {
3450 pci_read_config_dword(dev, ent_offset, &base_upper);
3453 flags |= IORESOURCE_MEM_64;
3455 /* entry starts above 32-bit boundary, can't use */
3456 if (!support_64 && base_upper)
3460 start |= ((u64)base_upper << 32);
3463 end = start + (max_offset | 0x03);
3465 /* Read MaxOffset MSBs (if 64-bit entry) */
3466 if (max_offset & PCI_EA_IS_64) {
3467 u32 max_offset_upper;
3469 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3472 flags |= IORESOURCE_MEM_64;
3474 /* entry too big, can't use */
3475 if (!support_64 && max_offset_upper)
3479 end += ((u64)max_offset_upper << 32);
3483 pci_err(dev, "EA Entry crosses address boundary\n");
3487 if (ent_size != ent_offset - offset) {
3488 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3489 ent_size, ent_offset - offset);
3493 res->name = pci_name(dev);
3498 if (bei <= PCI_EA_BEI_BAR5)
3499 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3500 res_name, res, prop);
3501 else if (bei == PCI_EA_BEI_ROM)
3502 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3503 res_name, res, prop);
3504 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3505 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3506 res_name, res, prop);
3508 pci_info(dev, "BEI %d %pR: from Enhanced Allocation, properties %#02x\n",
3512 return offset + ent_size;
3515 /* Enhanced Allocation Initialization */
3516 void pci_ea_init(struct pci_dev *dev)
3523 /* find PCI EA capability in list */
3524 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3528 /* determine the number of entries */
3529 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3531 num_ent &= PCI_EA_NUM_ENT_MASK;
3533 offset = ea + PCI_EA_FIRST_ENT;
3535 /* Skip DWORD 2 for type 1 functions */
3536 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3539 /* parse each EA entry */
3540 for (i = 0; i < num_ent; ++i)
3541 offset = pci_ea_read(dev, offset);
3544 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3545 struct pci_cap_saved_state *new_cap)
3547 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3551 * _pci_add_cap_save_buffer - allocate buffer for saving given
3552 * capability registers
3553 * @dev: the PCI device
3554 * @cap: the capability to allocate the buffer for
3555 * @extended: Standard or Extended capability ID
3556 * @size: requested size of the buffer
3558 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3559 bool extended, unsigned int size)
3562 struct pci_cap_saved_state *save_state;
3565 pos = pci_find_ext_capability(dev, cap);
3567 pos = pci_find_capability(dev, cap);
3572 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3576 save_state->cap.cap_nr = cap;
3577 save_state->cap.cap_extended = extended;
3578 save_state->cap.size = size;
3579 pci_add_saved_cap(dev, save_state);
3584 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3586 return _pci_add_cap_save_buffer(dev, cap, false, size);
3589 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3591 return _pci_add_cap_save_buffer(dev, cap, true, size);
3595 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3596 * @dev: the PCI device
3598 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3602 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3603 PCI_EXP_SAVE_REGS * sizeof(u16));
3605 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3607 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3609 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3611 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3614 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3616 pci_allocate_vc_save_buffers(dev);
3619 void pci_free_cap_save_buffers(struct pci_dev *dev)
3621 struct pci_cap_saved_state *tmp;
3622 struct hlist_node *n;
3624 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3629 * pci_configure_ari - enable or disable ARI forwarding
3630 * @dev: the PCI device
3632 * If @dev and its upstream bridge both support ARI, enable ARI in the
3633 * bridge. Otherwise, disable ARI in the bridge.
3635 void pci_configure_ari(struct pci_dev *dev)
3638 struct pci_dev *bridge;
3640 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3643 bridge = dev->bus->self;
3647 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3648 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3651 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3652 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3653 PCI_EXP_DEVCTL2_ARI);
3654 bridge->ari_enabled = 1;
3656 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3657 PCI_EXP_DEVCTL2_ARI);
3658 bridge->ari_enabled = 0;
3662 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3667 pos = pdev->acs_cap;
3672 * Except for egress control, capabilities are either required
3673 * or only required if controllable. Features missing from the
3674 * capability field can therefore be assumed as hard-wired enabled.
3676 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3677 acs_flags &= (cap | PCI_ACS_EC);
3679 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3680 return (ctrl & acs_flags) == acs_flags;
3684 * pci_acs_enabled - test ACS against required flags for a given device
3685 * @pdev: device to test
3686 * @acs_flags: required PCI ACS flags
3688 * Return true if the device supports the provided flags. Automatically
3689 * filters out flags that are not implemented on multifunction devices.
3691 * Note that this interface checks the effective ACS capabilities of the
3692 * device rather than the actual capabilities. For instance, most single
3693 * function endpoints are not required to support ACS because they have no
3694 * opportunity for peer-to-peer access. We therefore return 'true'
3695 * regardless of whether the device exposes an ACS capability. This makes
3696 * it much easier for callers of this function to ignore the actual type
3697 * or topology of the device when testing ACS support.
3699 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3703 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3708 * Conventional PCI and PCI-X devices never support ACS, either
3709 * effectively or actually. The shared bus topology implies that
3710 * any device on the bus can receive or snoop DMA.
3712 if (!pci_is_pcie(pdev))
3715 switch (pci_pcie_type(pdev)) {
3717 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3718 * but since their primary interface is PCI/X, we conservatively
3719 * handle them as we would a non-PCIe device.
3721 case PCI_EXP_TYPE_PCIE_BRIDGE:
3723 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3724 * applicable... must never implement an ACS Extended Capability...".
3725 * This seems arbitrary, but we take a conservative interpretation
3726 * of this statement.
3728 case PCI_EXP_TYPE_PCI_BRIDGE:
3729 case PCI_EXP_TYPE_RC_EC:
3732 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3733 * implement ACS in order to indicate their peer-to-peer capabilities,
3734 * regardless of whether they are single- or multi-function devices.
3736 case PCI_EXP_TYPE_DOWNSTREAM:
3737 case PCI_EXP_TYPE_ROOT_PORT:
3738 return pci_acs_flags_enabled(pdev, acs_flags);
3740 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3741 * implemented by the remaining PCIe types to indicate peer-to-peer
3742 * capabilities, but only when they are part of a multifunction
3743 * device. The footnote for section 6.12 indicates the specific
3744 * PCIe types included here.
3746 case PCI_EXP_TYPE_ENDPOINT:
3747 case PCI_EXP_TYPE_UPSTREAM:
3748 case PCI_EXP_TYPE_LEG_END:
3749 case PCI_EXP_TYPE_RC_END:
3750 if (!pdev->multifunction)
3753 return pci_acs_flags_enabled(pdev, acs_flags);
3757 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3758 * to single function devices with the exception of downstream ports.
3764 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3765 * @start: starting downstream device
3766 * @end: ending upstream device or NULL to search to the root bus
3767 * @acs_flags: required flags
3769 * Walk up a device tree from start to end testing PCI ACS support. If
3770 * any step along the way does not support the required flags, return false.
3772 bool pci_acs_path_enabled(struct pci_dev *start,
3773 struct pci_dev *end, u16 acs_flags)
3775 struct pci_dev *pdev, *parent = start;
3780 if (!pci_acs_enabled(pdev, acs_flags))
3783 if (pci_is_root_bus(pdev->bus))
3784 return (end == NULL);
3786 parent = pdev->bus->self;
3787 } while (pdev != end);
3793 * pci_acs_init - Initialize ACS if hardware supports it
3794 * @dev: the PCI device
3796 void pci_acs_init(struct pci_dev *dev)
3798 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3801 * Attempt to enable ACS regardless of capability because some Root
3802 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3803 * the standard ACS capability but still support ACS via those
3806 pci_enable_acs(dev);
3810 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3814 * Helper to find the position of the ctrl register for a BAR.
3815 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3816 * Returns -ENOENT if no ctrl register for the BAR could be found.
3818 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3820 unsigned int pos, nbars, i;
3823 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3827 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3828 nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
3830 for (i = 0; i < nbars; i++, pos += 8) {
3833 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3834 bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl);
3843 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3845 * @bar: BAR to query
3847 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3848 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3850 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3855 pos = pci_rebar_find_pos(pdev, bar);
3859 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3860 cap = FIELD_GET(PCI_REBAR_CAP_SIZES, cap);
3862 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3863 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3864 bar == 0 && cap == 0x700)
3869 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3872 * pci_rebar_get_current_size - get the current size of a BAR
3874 * @bar: BAR to set size to
3876 * Read the size of a BAR from the resizable BAR config.
3877 * Returns size if found or negative error code.
3879 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3884 pos = pci_rebar_find_pos(pdev, bar);
3888 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3889 return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl);
3893 * pci_rebar_set_size - set a new size for a BAR
3895 * @bar: BAR to set size to
3896 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3898 * Set the new size of a BAR as defined in the spec.
3899 * Returns zero if resizing was successful, error code otherwise.
3901 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3906 pos = pci_rebar_find_pos(pdev, bar);
3910 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3911 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3912 ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
3913 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3918 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3919 * @dev: the PCI device
3920 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3921 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3922 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3923 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3925 * Return 0 if all upstream bridges support AtomicOp routing, egress
3926 * blocking is disabled on all upstream ports, and the root port supports
3927 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3928 * AtomicOp completion), or negative otherwise.
3930 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3932 struct pci_bus *bus = dev->bus;
3933 struct pci_dev *bridge;
3937 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3938 * in Device Control 2 is reserved in VFs and the PF value applies
3939 * to all associated VFs.
3944 if (!pci_is_pcie(dev))
3948 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3949 * AtomicOp requesters. For now, we only support endpoints as
3950 * requesters and root ports as completers. No endpoints as
3951 * completers, and no peer-to-peer.
3954 switch (pci_pcie_type(dev)) {
3955 case PCI_EXP_TYPE_ENDPOINT:
3956 case PCI_EXP_TYPE_LEG_END:
3957 case PCI_EXP_TYPE_RC_END:
3963 while (bus->parent) {
3966 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3968 switch (pci_pcie_type(bridge)) {
3969 /* Ensure switch ports support AtomicOp routing */
3970 case PCI_EXP_TYPE_UPSTREAM:
3971 case PCI_EXP_TYPE_DOWNSTREAM:
3972 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3976 /* Ensure root port supports all the sizes we care about */
3977 case PCI_EXP_TYPE_ROOT_PORT:
3978 if ((cap & cap_mask) != cap_mask)
3983 /* Ensure upstream ports don't block AtomicOps on egress */
3984 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3985 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3987 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3994 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3995 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3998 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
4001 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
4002 * @dev: the PCI device
4003 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
4005 * Perform INTx swizzling for a device behind one level of bridge. This is
4006 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
4007 * behind bridges on add-in cards. For devices with ARI enabled, the slot
4008 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
4009 * the PCI Express Base Specification, Revision 2.1)
4011 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
4015 if (pci_ari_enabled(dev->bus))
4018 slot = PCI_SLOT(dev->devfn);
4020 return (((pin - 1) + slot) % 4) + 1;
4023 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
4031 while (!pci_is_root_bus(dev->bus)) {
4032 pin = pci_swizzle_interrupt_pin(dev, pin);
4033 dev = dev->bus->self;
4040 * pci_common_swizzle - swizzle INTx all the way to root bridge
4041 * @dev: the PCI device
4042 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
4044 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
4045 * bridges all the way up to a PCI root bus.
4047 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
4051 while (!pci_is_root_bus(dev->bus)) {
4052 pin = pci_swizzle_interrupt_pin(dev, pin);
4053 dev = dev->bus->self;
4056 return PCI_SLOT(dev->devfn);
4058 EXPORT_SYMBOL_GPL(pci_common_swizzle);
4061 * pci_release_region - Release a PCI bar
4062 * @pdev: PCI device whose resources were previously reserved by
4063 * pci_request_region()
4064 * @bar: BAR to release
4066 * Releases the PCI I/O and memory resources previously reserved by a
4067 * successful call to pci_request_region(). Call this function only
4068 * after all use of the PCI regions has ceased.
4070 void pci_release_region(struct pci_dev *pdev, int bar)
4072 struct pci_devres *dr;
4074 if (pci_resource_len(pdev, bar) == 0)
4076 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
4077 release_region(pci_resource_start(pdev, bar),
4078 pci_resource_len(pdev, bar));
4079 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
4080 release_mem_region(pci_resource_start(pdev, bar),
4081 pci_resource_len(pdev, bar));
4083 dr = find_pci_dr(pdev);
4085 dr->region_mask &= ~(1 << bar);
4087 EXPORT_SYMBOL(pci_release_region);
4090 * __pci_request_region - Reserved PCI I/O and memory resource
4091 * @pdev: PCI device whose resources are to be reserved
4092 * @bar: BAR to be reserved
4093 * @res_name: Name to be associated with resource.
4094 * @exclusive: whether the region access is exclusive or not
4096 * Mark the PCI region associated with PCI device @pdev BAR @bar as
4097 * being reserved by owner @res_name. Do not access any
4098 * address inside the PCI regions unless this call returns
4101 * If @exclusive is set, then the region is marked so that userspace
4102 * is explicitly not allowed to map the resource via /dev/mem or
4103 * sysfs MMIO access.
4105 * Returns 0 on success, or %EBUSY on error. A warning
4106 * message is also printed on failure.
4108 static int __pci_request_region(struct pci_dev *pdev, int bar,
4109 const char *res_name, int exclusive)
4111 struct pci_devres *dr;
4113 if (pci_resource_len(pdev, bar) == 0)
4116 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
4117 if (!request_region(pci_resource_start(pdev, bar),
4118 pci_resource_len(pdev, bar), res_name))
4120 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
4121 if (!__request_mem_region(pci_resource_start(pdev, bar),
4122 pci_resource_len(pdev, bar), res_name,
4127 dr = find_pci_dr(pdev);
4129 dr->region_mask |= 1 << bar;
4134 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
4135 &pdev->resource[bar]);
4140 * pci_request_region - Reserve PCI I/O and memory resource
4141 * @pdev: PCI device whose resources are to be reserved
4142 * @bar: BAR to be reserved
4143 * @res_name: Name to be associated with resource
4145 * Mark the PCI region associated with PCI device @pdev BAR @bar as
4146 * being reserved by owner @res_name. Do not access any
4147 * address inside the PCI regions unless this call returns
4150 * Returns 0 on success, or %EBUSY on error. A warning
4151 * message is also printed on failure.
4153 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
4155 return __pci_request_region(pdev, bar, res_name, 0);
4157 EXPORT_SYMBOL(pci_request_region);
4160 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4161 * @pdev: PCI device whose resources were previously reserved
4162 * @bars: Bitmask of BARs to be released
4164 * Release selected PCI I/O and memory resources previously reserved.
4165 * Call this function only after all use of the PCI regions has ceased.
4167 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
4171 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4172 if (bars & (1 << i))
4173 pci_release_region(pdev, i);
4175 EXPORT_SYMBOL(pci_release_selected_regions);
4177 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
4178 const char *res_name, int excl)
4182 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4183 if (bars & (1 << i))
4184 if (__pci_request_region(pdev, i, res_name, excl))
4190 if (bars & (1 << i))
4191 pci_release_region(pdev, i);
4198 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4199 * @pdev: PCI device whose resources are to be reserved
4200 * @bars: Bitmask of BARs to be requested
4201 * @res_name: Name to be associated with resource
4203 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4204 const char *res_name)
4206 return __pci_request_selected_regions(pdev, bars, res_name, 0);
4208 EXPORT_SYMBOL(pci_request_selected_regions);
4210 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4211 const char *res_name)
4213 return __pci_request_selected_regions(pdev, bars, res_name,
4214 IORESOURCE_EXCLUSIVE);
4216 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4219 * pci_release_regions - Release reserved PCI I/O and memory resources
4220 * @pdev: PCI device whose resources were previously reserved by
4221 * pci_request_regions()
4223 * Releases all PCI I/O and memory resources previously reserved by a
4224 * successful call to pci_request_regions(). Call this function only
4225 * after all use of the PCI regions has ceased.
4228 void pci_release_regions(struct pci_dev *pdev)
4230 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4232 EXPORT_SYMBOL(pci_release_regions);
4235 * pci_request_regions - Reserve PCI I/O and memory resources
4236 * @pdev: PCI device whose resources are to be reserved
4237 * @res_name: Name to be associated with resource.
4239 * Mark all PCI regions associated with PCI device @pdev as
4240 * being reserved by owner @res_name. Do not access any
4241 * address inside the PCI regions unless this call returns
4244 * Returns 0 on success, or %EBUSY on error. A warning
4245 * message is also printed on failure.
4247 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4249 return pci_request_selected_regions(pdev,
4250 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4252 EXPORT_SYMBOL(pci_request_regions);
4255 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4256 * @pdev: PCI device whose resources are to be reserved
4257 * @res_name: Name to be associated with resource.
4259 * Mark all PCI regions associated with PCI device @pdev as being reserved
4260 * by owner @res_name. Do not access any address inside the PCI regions
4261 * unless this call returns successfully.
4263 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4264 * and the sysfs MMIO access will not be allowed.
4266 * Returns 0 on success, or %EBUSY on error. A warning message is also
4267 * printed on failure.
4269 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4271 return pci_request_selected_regions_exclusive(pdev,
4272 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4274 EXPORT_SYMBOL(pci_request_regions_exclusive);
4277 * Record the PCI IO range (expressed as CPU physical address + size).
4278 * Return a negative value if an error has occurred, zero otherwise
4280 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4281 resource_size_t size)
4285 struct logic_pio_hwaddr *range;
4287 if (!size || addr + size < addr)
4290 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4294 range->fwnode = fwnode;
4296 range->hw_start = addr;
4297 range->flags = LOGIC_PIO_CPU_MMIO;
4299 ret = logic_pio_register_range(range);
4303 /* Ignore duplicates due to deferred probing */
4311 phys_addr_t pci_pio_to_address(unsigned long pio)
4314 if (pio < MMIO_UPPER_LIMIT)
4315 return logic_pio_to_hwaddr(pio);
4318 return (phys_addr_t) OF_BAD_ADDR;
4320 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4322 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4325 return logic_pio_trans_cpuaddr(address);
4327 if (address > IO_SPACE_LIMIT)
4328 return (unsigned long)-1;
4330 return (unsigned long) address;
4335 * pci_remap_iospace - Remap the memory mapped I/O space
4336 * @res: Resource describing the I/O space
4337 * @phys_addr: physical address of range to be mapped
4339 * Remap the memory mapped I/O space described by the @res and the CPU
4340 * physical address @phys_addr into virtual address space. Only
4341 * architectures that have memory mapped IO functions defined (and the
4342 * PCI_IOBASE value defined) should call this function.
4344 #ifndef pci_remap_iospace
4345 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4347 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4348 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4350 if (!(res->flags & IORESOURCE_IO))
4353 if (res->end > IO_SPACE_LIMIT)
4356 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4357 pgprot_device(PAGE_KERNEL));
4360 * This architecture does not have memory mapped I/O space,
4361 * so this function should never be called
4363 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4367 EXPORT_SYMBOL(pci_remap_iospace);
4371 * pci_unmap_iospace - Unmap the memory mapped I/O space
4372 * @res: resource to be unmapped
4374 * Unmap the CPU virtual address @res from virtual address space. Only
4375 * architectures that have memory mapped IO functions defined (and the
4376 * PCI_IOBASE value defined) should call this function.
4378 void pci_unmap_iospace(struct resource *res)
4380 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4381 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4383 vunmap_range(vaddr, vaddr + resource_size(res));
4386 EXPORT_SYMBOL(pci_unmap_iospace);
4388 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4390 struct resource **res = ptr;
4392 pci_unmap_iospace(*res);
4396 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4397 * @dev: Generic device to remap IO address for
4398 * @res: Resource describing the I/O space
4399 * @phys_addr: physical address of range to be mapped
4401 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4404 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4405 phys_addr_t phys_addr)
4407 const struct resource **ptr;
4410 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4414 error = pci_remap_iospace(res, phys_addr);
4419 devres_add(dev, ptr);
4424 EXPORT_SYMBOL(devm_pci_remap_iospace);
4427 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4428 * @dev: Generic device to remap IO address for
4429 * @offset: Resource address to map
4430 * @size: Size of map
4432 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4435 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4436 resource_size_t offset,
4437 resource_size_t size)
4439 void __iomem **ptr, *addr;
4441 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4445 addr = pci_remap_cfgspace(offset, size);
4448 devres_add(dev, ptr);
4454 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4457 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4458 * @dev: generic device to handle the resource for
4459 * @res: configuration space resource to be handled
4461 * Checks that a resource is a valid memory region, requests the memory
4462 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4463 * proper PCI configuration space memory attributes are guaranteed.
4465 * All operations are managed and will be undone on driver detach.
4467 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4468 * on failure. Usage example::
4470 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4471 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4473 * return PTR_ERR(base);
4475 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4476 struct resource *res)
4478 resource_size_t size;
4480 void __iomem *dest_ptr;
4484 if (!res || resource_type(res) != IORESOURCE_MEM) {
4485 dev_err(dev, "invalid resource\n");
4486 return IOMEM_ERR_PTR(-EINVAL);
4489 size = resource_size(res);
4492 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4495 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4497 return IOMEM_ERR_PTR(-ENOMEM);
4499 if (!devm_request_mem_region(dev, res->start, size, name)) {
4500 dev_err(dev, "can't request region for resource %pR\n", res);
4501 return IOMEM_ERR_PTR(-EBUSY);
4504 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4506 dev_err(dev, "ioremap failed for resource %pR\n", res);
4507 devm_release_mem_region(dev, res->start, size);
4508 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4513 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4515 static void __pci_set_master(struct pci_dev *dev, bool enable)
4519 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4521 cmd = old_cmd | PCI_COMMAND_MASTER;
4523 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4524 if (cmd != old_cmd) {
4525 pci_dbg(dev, "%s bus mastering\n",
4526 enable ? "enabling" : "disabling");
4527 pci_write_config_word(dev, PCI_COMMAND, cmd);
4529 dev->is_busmaster = enable;
4533 * pcibios_setup - process "pci=" kernel boot arguments
4534 * @str: string used to pass in "pci=" kernel boot arguments
4536 * Process kernel boot arguments. This is the default implementation.
4537 * Architecture specific implementations can override this as necessary.
4539 char * __weak __init pcibios_setup(char *str)
4545 * pcibios_set_master - enable PCI bus-mastering for device dev
4546 * @dev: the PCI device to enable
4548 * Enables PCI bus-mastering for the device. This is the default
4549 * implementation. Architecture specific implementations can override
4550 * this if necessary.
4552 void __weak pcibios_set_master(struct pci_dev *dev)
4556 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4557 if (pci_is_pcie(dev))
4560 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4562 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4563 else if (lat > pcibios_max_latency)
4564 lat = pcibios_max_latency;
4568 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4572 * pci_set_master - enables bus-mastering for device dev
4573 * @dev: the PCI device to enable
4575 * Enables bus-mastering on the device and calls pcibios_set_master()
4576 * to do the needed arch specific settings.
4578 void pci_set_master(struct pci_dev *dev)
4580 __pci_set_master(dev, true);
4581 pcibios_set_master(dev);
4583 EXPORT_SYMBOL(pci_set_master);
4586 * pci_clear_master - disables bus-mastering for device dev
4587 * @dev: the PCI device to disable
4589 void pci_clear_master(struct pci_dev *dev)
4591 __pci_set_master(dev, false);
4593 EXPORT_SYMBOL(pci_clear_master);
4596 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4597 * @dev: the PCI device for which MWI is to be enabled
4599 * Helper function for pci_set_mwi.
4600 * Originally copied from drivers/net/acenic.c.
4601 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4603 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4605 int pci_set_cacheline_size(struct pci_dev *dev)
4609 if (!pci_cache_line_size)
4612 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4613 equal to or multiple of the right value. */
4614 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4615 if (cacheline_size >= pci_cache_line_size &&
4616 (cacheline_size % pci_cache_line_size) == 0)
4619 /* Write the correct value. */
4620 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4622 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4623 if (cacheline_size == pci_cache_line_size)
4626 pci_dbg(dev, "cache line size of %d is not supported\n",
4627 pci_cache_line_size << 2);
4631 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4634 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4635 * @dev: the PCI device for which MWI is enabled
4637 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4639 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4641 int pci_set_mwi(struct pci_dev *dev)
4643 #ifdef PCI_DISABLE_MWI
4649 rc = pci_set_cacheline_size(dev);
4653 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4654 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4655 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4656 cmd |= PCI_COMMAND_INVALIDATE;
4657 pci_write_config_word(dev, PCI_COMMAND, cmd);
4662 EXPORT_SYMBOL(pci_set_mwi);
4665 * pcim_set_mwi - a device-managed pci_set_mwi()
4666 * @dev: the PCI device for which MWI is enabled
4668 * Managed pci_set_mwi().
4670 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4672 int pcim_set_mwi(struct pci_dev *dev)
4674 struct pci_devres *dr;
4676 dr = find_pci_dr(dev);
4681 return pci_set_mwi(dev);
4683 EXPORT_SYMBOL(pcim_set_mwi);
4686 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4687 * @dev: the PCI device for which MWI is enabled
4689 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4690 * Callers are not required to check the return value.
4692 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4694 int pci_try_set_mwi(struct pci_dev *dev)
4696 #ifdef PCI_DISABLE_MWI
4699 return pci_set_mwi(dev);
4702 EXPORT_SYMBOL(pci_try_set_mwi);
4705 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4706 * @dev: the PCI device to disable
4708 * Disables PCI Memory-Write-Invalidate transaction on the device
4710 void pci_clear_mwi(struct pci_dev *dev)
4712 #ifndef PCI_DISABLE_MWI
4715 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4716 if (cmd & PCI_COMMAND_INVALIDATE) {
4717 cmd &= ~PCI_COMMAND_INVALIDATE;
4718 pci_write_config_word(dev, PCI_COMMAND, cmd);
4722 EXPORT_SYMBOL(pci_clear_mwi);
4725 * pci_disable_parity - disable parity checking for device
4726 * @dev: the PCI device to operate on
4728 * Disable parity checking for device @dev
4730 void pci_disable_parity(struct pci_dev *dev)
4734 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4735 if (cmd & PCI_COMMAND_PARITY) {
4736 cmd &= ~PCI_COMMAND_PARITY;
4737 pci_write_config_word(dev, PCI_COMMAND, cmd);
4742 * pci_intx - enables/disables PCI INTx for device dev
4743 * @pdev: the PCI device to operate on
4744 * @enable: boolean: whether to enable or disable PCI INTx
4746 * Enables/disables PCI INTx for device @pdev
4748 void pci_intx(struct pci_dev *pdev, int enable)
4750 u16 pci_command, new;
4752 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4755 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4757 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4759 if (new != pci_command) {
4760 struct pci_devres *dr;
4762 pci_write_config_word(pdev, PCI_COMMAND, new);
4764 dr = find_pci_dr(pdev);
4765 if (dr && !dr->restore_intx) {
4766 dr->restore_intx = 1;
4767 dr->orig_intx = !enable;
4771 EXPORT_SYMBOL_GPL(pci_intx);
4773 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4775 struct pci_bus *bus = dev->bus;
4776 bool mask_updated = true;
4777 u32 cmd_status_dword;
4778 u16 origcmd, newcmd;
4779 unsigned long flags;
4783 * We do a single dword read to retrieve both command and status.
4784 * Document assumptions that make this possible.
4786 BUILD_BUG_ON(PCI_COMMAND % 4);
4787 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4789 raw_spin_lock_irqsave(&pci_lock, flags);
4791 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4793 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4796 * Check interrupt status register to see whether our device
4797 * triggered the interrupt (when masking) or the next IRQ is
4798 * already pending (when unmasking).
4800 if (mask != irq_pending) {
4801 mask_updated = false;
4805 origcmd = cmd_status_dword;
4806 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4808 newcmd |= PCI_COMMAND_INTX_DISABLE;
4809 if (newcmd != origcmd)
4810 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4813 raw_spin_unlock_irqrestore(&pci_lock, flags);
4815 return mask_updated;
4819 * pci_check_and_mask_intx - mask INTx on pending interrupt
4820 * @dev: the PCI device to operate on
4822 * Check if the device dev has its INTx line asserted, mask it and return
4823 * true in that case. False is returned if no interrupt was pending.
4825 bool pci_check_and_mask_intx(struct pci_dev *dev)
4827 return pci_check_and_set_intx_mask(dev, true);
4829 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4832 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4833 * @dev: the PCI device to operate on
4835 * Check if the device dev has its INTx line asserted, unmask it if not and
4836 * return true. False is returned and the mask remains active if there was
4837 * still an interrupt pending.
4839 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4841 return pci_check_and_set_intx_mask(dev, false);
4843 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4846 * pci_wait_for_pending_transaction - wait for pending transaction
4847 * @dev: the PCI device to operate on
4849 * Return 0 if transaction is pending 1 otherwise.
4851 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4853 if (!pci_is_pcie(dev))
4856 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4857 PCI_EXP_DEVSTA_TRPND);
4859 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4862 * pcie_flr - initiate a PCIe function level reset
4863 * @dev: device to reset
4865 * Initiate a function level reset unconditionally on @dev without
4866 * checking any flags and DEVCAP
4868 int pcie_flr(struct pci_dev *dev)
4870 if (!pci_wait_for_pending_transaction(dev))
4871 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4873 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4879 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4880 * 100ms, but may silently discard requests while the FLR is in
4881 * progress. Wait 100ms before trying to access the device.
4885 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4887 EXPORT_SYMBOL_GPL(pcie_flr);
4890 * pcie_reset_flr - initiate a PCIe function level reset
4891 * @dev: device to reset
4892 * @probe: if true, return 0 if device can be reset this way
4894 * Initiate a function level reset on @dev.
4896 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4898 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4901 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4907 return pcie_flr(dev);
4909 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4911 static int pci_af_flr(struct pci_dev *dev, bool probe)
4916 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4920 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4923 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4924 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4931 * Wait for Transaction Pending bit to clear. A word-aligned test
4932 * is used, so we use the control offset rather than status and shift
4933 * the test bit to match.
4935 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4936 PCI_AF_STATUS_TP << 8))
4937 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4939 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4945 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4946 * updated 27 July 2006; a device must complete an FLR within
4947 * 100ms, but may silently discard requests while the FLR is in
4948 * progress. Wait 100ms before trying to access the device.
4952 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4956 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4957 * @dev: Device to reset.
4958 * @probe: if true, return 0 if the device can be reset this way.
4960 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4961 * unset, it will be reinitialized internally when going from PCI_D3hot to
4962 * PCI_D0. If that's the case and the device is not in a low-power state
4963 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4965 * NOTE: This causes the caller to sleep for twice the device power transition
4966 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4967 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4968 * Moreover, only devices in D0 can be reset by this function.
4970 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4974 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4977 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4978 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4984 if (dev->current_state != PCI_D0)
4987 csr &= ~PCI_PM_CTRL_STATE_MASK;
4989 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4990 pci_dev_d3_sleep(dev);
4992 csr &= ~PCI_PM_CTRL_STATE_MASK;
4994 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4995 pci_dev_d3_sleep(dev);
4997 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
5001 * pcie_wait_for_link_status - Wait for link status change
5002 * @pdev: Device whose link to wait for.
5003 * @use_lt: Use the LT bit if TRUE, or the DLLLA bit if FALSE.
5004 * @active: Waiting for active or inactive?
5006 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
5007 * PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds.
5009 static int pcie_wait_for_link_status(struct pci_dev *pdev,
5010 bool use_lt, bool active)
5012 u16 lnksta_mask, lnksta_match;
5013 unsigned long end_jiffies;
5016 lnksta_mask = use_lt ? PCI_EXP_LNKSTA_LT : PCI_EXP_LNKSTA_DLLLA;
5017 lnksta_match = active ? lnksta_mask : 0;
5019 end_jiffies = jiffies + msecs_to_jiffies(PCIE_LINK_RETRAIN_TIMEOUT_MS);
5021 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
5022 if ((lnksta & lnksta_mask) == lnksta_match)
5025 } while (time_before(jiffies, end_jiffies));
5031 * pcie_retrain_link - Request a link retrain and wait for it to complete
5032 * @pdev: Device whose link to retrain.
5033 * @use_lt: Use the LT bit if TRUE, or the DLLLA bit if FALSE, for status.
5035 * Retrain completion status is retrieved from the Link Status Register
5036 * according to @use_lt. It is not verified whether the use of the DLLLA
5039 * Return 0 if successful, or -ETIMEDOUT if training has not completed
5040 * within PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds.
5042 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt)
5047 * Ensure the updated LNKCTL parameters are used during link
5048 * training by checking that there is no ongoing link training to
5049 * avoid LTSSM race as recommended in Implementation Note at the
5050 * end of PCIe r6.0.1 sec 7.5.3.7.
5052 rc = pcie_wait_for_link_status(pdev, use_lt, !use_lt);
5056 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RL);
5057 if (pdev->clear_retrain_link) {
5059 * Due to an erratum in some devices the Retrain Link bit
5060 * needs to be cleared again manually to allow the link
5061 * training to succeed.
5063 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RL);
5066 return pcie_wait_for_link_status(pdev, use_lt, !use_lt);
5070 * pcie_wait_for_link_delay - Wait until link is active or inactive
5071 * @pdev: Bridge device
5072 * @active: waiting for active or inactive?
5073 * @delay: Delay to wait after link has become active (in ms)
5075 * Use this to wait till link becomes active or inactive.
5077 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
5083 * Some controllers might not implement link active reporting. In this
5084 * case, we wait for 1000 ms + any delay requested by the caller.
5086 if (!pdev->link_active_reporting) {
5087 msleep(PCIE_LINK_RETRAIN_TIMEOUT_MS + delay);
5092 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
5093 * after which we should expect an link active if the reset was
5094 * successful. If so, software must wait a minimum 100ms before sending
5095 * configuration requests to devices downstream this port.
5097 * If the link fails to activate, either the device was physically
5098 * removed or the link is permanently failed.
5102 rc = pcie_wait_for_link_status(pdev, false, active);
5105 rc = pcie_failed_link_retrain(pdev);
5120 * pcie_wait_for_link - Wait until link is active or inactive
5121 * @pdev: Bridge device
5122 * @active: waiting for active or inactive?
5124 * Use this to wait till link becomes active or inactive.
5126 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
5128 return pcie_wait_for_link_delay(pdev, active, 100);
5132 * Find maximum D3cold delay required by all the devices on the bus. The
5133 * spec says 100 ms, but firmware can lower it and we allow drivers to
5134 * increase it as well.
5136 * Called with @pci_bus_sem locked for reading.
5138 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
5140 const struct pci_dev *pdev;
5141 int min_delay = 100;
5144 list_for_each_entry(pdev, &bus->devices, bus_list) {
5145 if (pdev->d3cold_delay < min_delay)
5146 min_delay = pdev->d3cold_delay;
5147 if (pdev->d3cold_delay > max_delay)
5148 max_delay = pdev->d3cold_delay;
5151 return max(min_delay, max_delay);
5155 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
5157 * @reset_type: reset type in human-readable form
5159 * Handle necessary delays before access to the devices on the secondary
5160 * side of the bridge are permitted after D3cold to D0 transition
5161 * or Conventional Reset.
5163 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
5164 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
5167 * Return 0 on success or -ENOTTY if the first device on the secondary bus
5168 * failed to become accessible.
5170 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
5172 struct pci_dev *child;
5175 if (pci_dev_is_disconnected(dev))
5178 if (!pci_is_bridge(dev))
5181 down_read(&pci_bus_sem);
5184 * We only deal with devices that are present currently on the bus.
5185 * For any hot-added devices the access delay is handled in pciehp
5186 * board_added(). In case of ACPI hotplug the firmware is expected
5187 * to configure the devices before OS is notified.
5189 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
5190 up_read(&pci_bus_sem);
5194 /* Take d3cold_delay requirements into account */
5195 delay = pci_bus_max_d3cold_delay(dev->subordinate);
5197 up_read(&pci_bus_sem);
5201 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
5203 up_read(&pci_bus_sem);
5206 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
5207 * accessing the device after reset (that is 1000 ms + 100 ms).
5209 if (!pci_is_pcie(dev)) {
5210 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5211 msleep(1000 + delay);
5216 * For PCIe downstream and root ports that do not support speeds
5217 * greater than 5 GT/s need to wait minimum 100 ms. For higher
5218 * speeds (gen3) we need to wait first for the data link layer to
5221 * However, 100 ms is the minimum and the PCIe spec says the
5222 * software must allow at least 1s before it can determine that the
5223 * device that did not respond is a broken device. Also device can
5224 * take longer than that to respond if it indicates so through Request
5225 * Retry Status completions.
5227 * Therefore we wait for 100 ms and check for the device presence
5228 * until the timeout expires.
5230 if (!pcie_downstream_port(dev))
5233 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
5236 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5239 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay))
5243 * If the port supports active link reporting we now check
5244 * whether the link is active and if not bail out early with
5245 * the assumption that the device is not present anymore.
5247 if (!dev->link_active_reporting)
5250 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &status);
5251 if (!(status & PCI_EXP_LNKSTA_DLLLA))
5254 return pci_dev_wait(child, reset_type,
5255 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT);
5258 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5260 if (!pcie_wait_for_link_delay(dev, true, delay)) {
5261 /* Did not train, no need to wait any further */
5262 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
5266 return pci_dev_wait(child, reset_type,
5267 PCIE_RESET_READY_POLL_MS - delay);
5270 void pci_reset_secondary_bus(struct pci_dev *dev)
5274 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5275 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
5276 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5279 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5280 * this to 2ms to ensure that we meet the minimum requirement.
5284 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5285 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5288 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5290 pci_reset_secondary_bus(dev);
5294 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5295 * @dev: Bridge device
5297 * Use the bridge control register to assert reset on the secondary bus.
5298 * Devices on the secondary bus are left in power-on state.
5300 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5302 pcibios_reset_secondary_bus(dev);
5304 return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
5306 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5308 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5310 struct pci_dev *pdev;
5312 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5313 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5316 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5323 return pci_bridge_secondary_bus_reset(dev->bus->self);
5326 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5330 if (!hotplug || !try_module_get(hotplug->owner))
5333 if (hotplug->ops->reset_slot)
5334 rc = hotplug->ops->reset_slot(hotplug, probe);
5336 module_put(hotplug->owner);
5341 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5343 if (dev->multifunction || dev->subordinate || !dev->slot ||
5344 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5347 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5350 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5354 rc = pci_dev_reset_slot_function(dev, probe);
5357 return pci_parent_bus_reset(dev, probe);
5360 void pci_dev_lock(struct pci_dev *dev)
5362 /* block PM suspend, driver probe, etc. */
5363 device_lock(&dev->dev);
5364 pci_cfg_access_lock(dev);
5366 EXPORT_SYMBOL_GPL(pci_dev_lock);
5368 /* Return 1 on successful lock, 0 on contention */
5369 int pci_dev_trylock(struct pci_dev *dev)
5371 if (device_trylock(&dev->dev)) {
5372 if (pci_cfg_access_trylock(dev))
5374 device_unlock(&dev->dev);
5379 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5381 void pci_dev_unlock(struct pci_dev *dev)
5383 pci_cfg_access_unlock(dev);
5384 device_unlock(&dev->dev);
5386 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5388 static void pci_dev_save_and_disable(struct pci_dev *dev)
5390 const struct pci_error_handlers *err_handler =
5391 dev->driver ? dev->driver->err_handler : NULL;
5394 * dev->driver->err_handler->reset_prepare() is protected against
5395 * races with ->remove() by the device lock, which must be held by
5398 if (err_handler && err_handler->reset_prepare)
5399 err_handler->reset_prepare(dev);
5402 * Wake-up device prior to save. PM registers default to D0 after
5403 * reset and a simple register restore doesn't reliably return
5404 * to a non-D0 state anyway.
5406 pci_set_power_state(dev, PCI_D0);
5408 pci_save_state(dev);
5410 * Disable the device by clearing the Command register, except for
5411 * INTx-disable which is set. This not only disables MMIO and I/O port
5412 * BARs, but also prevents the device from being Bus Master, preventing
5413 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5414 * compliant devices, INTx-disable prevents legacy interrupts.
5416 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5419 static void pci_dev_restore(struct pci_dev *dev)
5421 const struct pci_error_handlers *err_handler =
5422 dev->driver ? dev->driver->err_handler : NULL;
5424 pci_restore_state(dev);
5427 * dev->driver->err_handler->reset_done() is protected against
5428 * races with ->remove() by the device lock, which must be held by
5431 if (err_handler && err_handler->reset_done)
5432 err_handler->reset_done(dev);
5435 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5436 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5438 { pci_dev_specific_reset, .name = "device_specific" },
5439 { pci_dev_acpi_reset, .name = "acpi" },
5440 { pcie_reset_flr, .name = "flr" },
5441 { pci_af_flr, .name = "af_flr" },
5442 { pci_pm_reset, .name = "pm" },
5443 { pci_reset_bus_function, .name = "bus" },
5446 static ssize_t reset_method_show(struct device *dev,
5447 struct device_attribute *attr, char *buf)
5449 struct pci_dev *pdev = to_pci_dev(dev);
5453 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5454 m = pdev->reset_methods[i];
5458 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5459 pci_reset_fn_methods[m].name);
5463 len += sysfs_emit_at(buf, len, "\n");
5468 static int reset_method_lookup(const char *name)
5472 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5473 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5477 return 0; /* not found */
5480 static ssize_t reset_method_store(struct device *dev,
5481 struct device_attribute *attr,
5482 const char *buf, size_t count)
5484 struct pci_dev *pdev = to_pci_dev(dev);
5485 char *options, *name;
5487 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5489 if (sysfs_streq(buf, "")) {
5490 pdev->reset_methods[0] = 0;
5491 pci_warn(pdev, "All device reset methods disabled by user");
5495 if (sysfs_streq(buf, "default")) {
5496 pci_init_reset_methods(pdev);
5500 options = kstrndup(buf, count, GFP_KERNEL);
5505 while ((name = strsep(&options, " ")) != NULL) {
5506 if (sysfs_streq(name, ""))
5511 m = reset_method_lookup(name);
5513 pci_err(pdev, "Invalid reset method '%s'", name);
5517 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5518 pci_err(pdev, "Unsupported reset method '%s'", name);
5522 if (n == PCI_NUM_RESET_METHODS - 1) {
5523 pci_err(pdev, "Too many reset methods\n");
5527 reset_methods[n++] = m;
5530 reset_methods[n] = 0;
5532 /* Warn if dev-specific supported but not highest priority */
5533 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5534 reset_methods[0] != 1)
5535 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5536 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5541 /* Leave previous methods unchanged */
5545 static DEVICE_ATTR_RW(reset_method);
5547 static struct attribute *pci_dev_reset_method_attrs[] = {
5548 &dev_attr_reset_method.attr,
5552 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5553 struct attribute *a, int n)
5555 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5557 if (!pci_reset_supported(pdev))
5563 const struct attribute_group pci_dev_reset_method_attr_group = {
5564 .attrs = pci_dev_reset_method_attrs,
5565 .is_visible = pci_dev_reset_method_attr_is_visible,
5569 * __pci_reset_function_locked - reset a PCI device function while holding
5570 * the @dev mutex lock.
5571 * @dev: PCI device to reset
5573 * Some devices allow an individual function to be reset without affecting
5574 * other functions in the same device. The PCI device must be responsive
5575 * to PCI config space in order to use this function.
5577 * The device function is presumed to be unused and the caller is holding
5578 * the device mutex lock when this function is called.
5580 * Resetting the device will make the contents of PCI configuration space
5581 * random, so any caller of this must be prepared to reinitialise the
5582 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5585 * Returns 0 if the device function was successfully reset or negative if the
5586 * device doesn't support resetting a single function.
5588 int __pci_reset_function_locked(struct pci_dev *dev)
5595 * A reset method returns -ENOTTY if it doesn't support this device and
5596 * we should try the next method.
5598 * If it returns 0 (success), we're finished. If it returns any other
5599 * error, we're also finished: this indicates that further reset
5600 * mechanisms might be broken on the device.
5602 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5603 m = dev->reset_methods[i];
5607 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5616 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5619 * pci_init_reset_methods - check whether device can be safely reset
5620 * and store supported reset mechanisms.
5621 * @dev: PCI device to check for reset mechanisms
5623 * Some devices allow an individual function to be reset without affecting
5624 * other functions in the same device. The PCI device must be in D0-D3hot
5627 * Stores reset mechanisms supported by device in reset_methods byte array
5628 * which is a member of struct pci_dev.
5630 void pci_init_reset_methods(struct pci_dev *dev)
5634 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5639 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5640 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5642 dev->reset_methods[i++] = m;
5643 else if (rc != -ENOTTY)
5647 dev->reset_methods[i] = 0;
5651 * pci_reset_function - quiesce and reset a PCI device function
5652 * @dev: PCI device to reset
5654 * Some devices allow an individual function to be reset without affecting
5655 * other functions in the same device. The PCI device must be responsive
5656 * to PCI config space in order to use this function.
5658 * This function does not just reset the PCI portion of a device, but
5659 * clears all the state associated with the device. This function differs
5660 * from __pci_reset_function_locked() in that it saves and restores device state
5661 * over the reset and takes the PCI device lock.
5663 * Returns 0 if the device function was successfully reset or negative if the
5664 * device doesn't support resetting a single function.
5666 int pci_reset_function(struct pci_dev *dev)
5670 if (!pci_reset_supported(dev))
5674 pci_dev_save_and_disable(dev);
5676 rc = __pci_reset_function_locked(dev);
5678 pci_dev_restore(dev);
5679 pci_dev_unlock(dev);
5683 EXPORT_SYMBOL_GPL(pci_reset_function);
5686 * pci_reset_function_locked - quiesce and reset a PCI device function
5687 * @dev: PCI device to reset
5689 * Some devices allow an individual function to be reset without affecting
5690 * other functions in the same device. The PCI device must be responsive
5691 * to PCI config space in order to use this function.
5693 * This function does not just reset the PCI portion of a device, but
5694 * clears all the state associated with the device. This function differs
5695 * from __pci_reset_function_locked() in that it saves and restores device state
5696 * over the reset. It also differs from pci_reset_function() in that it
5697 * requires the PCI device lock to be held.
5699 * Returns 0 if the device function was successfully reset or negative if the
5700 * device doesn't support resetting a single function.
5702 int pci_reset_function_locked(struct pci_dev *dev)
5706 if (!pci_reset_supported(dev))
5709 pci_dev_save_and_disable(dev);
5711 rc = __pci_reset_function_locked(dev);
5713 pci_dev_restore(dev);
5717 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5720 * pci_try_reset_function - quiesce and reset a PCI device function
5721 * @dev: PCI device to reset
5723 * Same as above, except return -EAGAIN if unable to lock device.
5725 int pci_try_reset_function(struct pci_dev *dev)
5729 if (!pci_reset_supported(dev))
5732 if (!pci_dev_trylock(dev))
5735 pci_dev_save_and_disable(dev);
5736 rc = __pci_reset_function_locked(dev);
5737 pci_dev_restore(dev);
5738 pci_dev_unlock(dev);
5742 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5744 /* Do any devices on or below this bus prevent a bus reset? */
5745 static bool pci_bus_resettable(struct pci_bus *bus)
5747 struct pci_dev *dev;
5750 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5753 list_for_each_entry(dev, &bus->devices, bus_list) {
5754 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5755 (dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5762 /* Lock devices from the top of the tree down */
5763 static void pci_bus_lock(struct pci_bus *bus)
5765 struct pci_dev *dev;
5767 list_for_each_entry(dev, &bus->devices, bus_list) {
5769 if (dev->subordinate)
5770 pci_bus_lock(dev->subordinate);
5774 /* Unlock devices from the bottom of the tree up */
5775 static void pci_bus_unlock(struct pci_bus *bus)
5777 struct pci_dev *dev;
5779 list_for_each_entry(dev, &bus->devices, bus_list) {
5780 if (dev->subordinate)
5781 pci_bus_unlock(dev->subordinate);
5782 pci_dev_unlock(dev);
5786 /* Return 1 on successful lock, 0 on contention */
5787 static int pci_bus_trylock(struct pci_bus *bus)
5789 struct pci_dev *dev;
5791 list_for_each_entry(dev, &bus->devices, bus_list) {
5792 if (!pci_dev_trylock(dev))
5794 if (dev->subordinate) {
5795 if (!pci_bus_trylock(dev->subordinate)) {
5796 pci_dev_unlock(dev);
5804 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5805 if (dev->subordinate)
5806 pci_bus_unlock(dev->subordinate);
5807 pci_dev_unlock(dev);
5812 /* Do any devices on or below this slot prevent a bus reset? */
5813 static bool pci_slot_resettable(struct pci_slot *slot)
5815 struct pci_dev *dev;
5817 if (slot->bus->self &&
5818 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5821 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5822 if (!dev->slot || dev->slot != slot)
5824 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5825 (dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5832 /* Lock devices from the top of the tree down */
5833 static void pci_slot_lock(struct pci_slot *slot)
5835 struct pci_dev *dev;
5837 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5838 if (!dev->slot || dev->slot != slot)
5841 if (dev->subordinate)
5842 pci_bus_lock(dev->subordinate);
5846 /* Unlock devices from the bottom of the tree up */
5847 static void pci_slot_unlock(struct pci_slot *slot)
5849 struct pci_dev *dev;
5851 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5852 if (!dev->slot || dev->slot != slot)
5854 if (dev->subordinate)
5855 pci_bus_unlock(dev->subordinate);
5856 pci_dev_unlock(dev);
5860 /* Return 1 on successful lock, 0 on contention */
5861 static int pci_slot_trylock(struct pci_slot *slot)
5863 struct pci_dev *dev;
5865 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5866 if (!dev->slot || dev->slot != slot)
5868 if (!pci_dev_trylock(dev))
5870 if (dev->subordinate) {
5871 if (!pci_bus_trylock(dev->subordinate)) {
5872 pci_dev_unlock(dev);
5880 list_for_each_entry_continue_reverse(dev,
5881 &slot->bus->devices, bus_list) {
5882 if (!dev->slot || dev->slot != slot)
5884 if (dev->subordinate)
5885 pci_bus_unlock(dev->subordinate);
5886 pci_dev_unlock(dev);
5892 * Save and disable devices from the top of the tree down while holding
5893 * the @dev mutex lock for the entire tree.
5895 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5897 struct pci_dev *dev;
5899 list_for_each_entry(dev, &bus->devices, bus_list) {
5900 pci_dev_save_and_disable(dev);
5901 if (dev->subordinate)
5902 pci_bus_save_and_disable_locked(dev->subordinate);
5907 * Restore devices from top of the tree down while holding @dev mutex lock
5908 * for the entire tree. Parent bridges need to be restored before we can
5909 * get to subordinate devices.
5911 static void pci_bus_restore_locked(struct pci_bus *bus)
5913 struct pci_dev *dev;
5915 list_for_each_entry(dev, &bus->devices, bus_list) {
5916 pci_dev_restore(dev);
5917 if (dev->subordinate)
5918 pci_bus_restore_locked(dev->subordinate);
5923 * Save and disable devices from the top of the tree down while holding
5924 * the @dev mutex lock for the entire tree.
5926 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5928 struct pci_dev *dev;
5930 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5931 if (!dev->slot || dev->slot != slot)
5933 pci_dev_save_and_disable(dev);
5934 if (dev->subordinate)
5935 pci_bus_save_and_disable_locked(dev->subordinate);
5940 * Restore devices from top of the tree down while holding @dev mutex lock
5941 * for the entire tree. Parent bridges need to be restored before we can
5942 * get to subordinate devices.
5944 static void pci_slot_restore_locked(struct pci_slot *slot)
5946 struct pci_dev *dev;
5948 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5949 if (!dev->slot || dev->slot != slot)
5951 pci_dev_restore(dev);
5952 if (dev->subordinate)
5953 pci_bus_restore_locked(dev->subordinate);
5957 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5961 if (!slot || !pci_slot_resettable(slot))
5965 pci_slot_lock(slot);
5969 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5972 pci_slot_unlock(slot);
5978 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5979 * @slot: PCI slot to probe
5981 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5983 int pci_probe_reset_slot(struct pci_slot *slot)
5985 return pci_slot_reset(slot, PCI_RESET_PROBE);
5987 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5990 * __pci_reset_slot - Try to reset a PCI slot
5991 * @slot: PCI slot to reset
5993 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5994 * independent of other slots. For instance, some slots may support slot power
5995 * control. In the case of a 1:1 bus to slot architecture, this function may
5996 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5997 * Generally a slot reset should be attempted before a bus reset. All of the
5998 * function of the slot and any subordinate buses behind the slot are reset
5999 * through this function. PCI config space of all devices in the slot and
6000 * behind the slot is saved before and restored after reset.
6002 * Same as above except return -EAGAIN if the slot cannot be locked
6004 static int __pci_reset_slot(struct pci_slot *slot)
6008 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
6012 if (pci_slot_trylock(slot)) {
6013 pci_slot_save_and_disable_locked(slot);
6015 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
6016 pci_slot_restore_locked(slot);
6017 pci_slot_unlock(slot);
6024 static int pci_bus_reset(struct pci_bus *bus, bool probe)
6028 if (!bus->self || !pci_bus_resettable(bus))
6038 ret = pci_bridge_secondary_bus_reset(bus->self);
6040 pci_bus_unlock(bus);
6046 * pci_bus_error_reset - reset the bridge's subordinate bus
6047 * @bridge: The parent device that connects to the bus to reset
6049 * This function will first try to reset the slots on this bus if the method is
6050 * available. If slot reset fails or is not available, this will fall back to a
6051 * secondary bus reset.
6053 int pci_bus_error_reset(struct pci_dev *bridge)
6055 struct pci_bus *bus = bridge->subordinate;
6056 struct pci_slot *slot;
6061 mutex_lock(&pci_slot_mutex);
6062 if (list_empty(&bus->slots))
6065 list_for_each_entry(slot, &bus->slots, list)
6066 if (pci_probe_reset_slot(slot))
6069 list_for_each_entry(slot, &bus->slots, list)
6070 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
6073 mutex_unlock(&pci_slot_mutex);
6076 mutex_unlock(&pci_slot_mutex);
6077 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
6081 * pci_probe_reset_bus - probe whether a PCI bus can be reset
6082 * @bus: PCI bus to probe
6084 * Return 0 if bus can be reset, negative if a bus reset is not supported.
6086 int pci_probe_reset_bus(struct pci_bus *bus)
6088 return pci_bus_reset(bus, PCI_RESET_PROBE);
6090 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
6093 * __pci_reset_bus - Try to reset a PCI bus
6094 * @bus: top level PCI bus to reset
6096 * Same as above except return -EAGAIN if the bus cannot be locked
6098 static int __pci_reset_bus(struct pci_bus *bus)
6102 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
6106 if (pci_bus_trylock(bus)) {
6107 pci_bus_save_and_disable_locked(bus);
6109 rc = pci_bridge_secondary_bus_reset(bus->self);
6110 pci_bus_restore_locked(bus);
6111 pci_bus_unlock(bus);
6119 * pci_reset_bus - Try to reset a PCI bus
6120 * @pdev: top level PCI device to reset via slot/bus
6122 * Same as above except return -EAGAIN if the bus cannot be locked
6124 int pci_reset_bus(struct pci_dev *pdev)
6126 return (!pci_probe_reset_slot(pdev->slot)) ?
6127 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
6129 EXPORT_SYMBOL_GPL(pci_reset_bus);
6132 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
6133 * @dev: PCI device to query
6135 * Returns mmrbc: maximum designed memory read count in bytes or
6136 * appropriate error value.
6138 int pcix_get_max_mmrbc(struct pci_dev *dev)
6143 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6147 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
6150 return 512 << FIELD_GET(PCI_X_STATUS_MAX_READ, stat);
6152 EXPORT_SYMBOL(pcix_get_max_mmrbc);
6155 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
6156 * @dev: PCI device to query
6158 * Returns mmrbc: maximum memory read count in bytes or appropriate error
6161 int pcix_get_mmrbc(struct pci_dev *dev)
6166 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6170 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
6173 return 512 << FIELD_GET(PCI_X_CMD_MAX_READ, cmd);
6175 EXPORT_SYMBOL(pcix_get_mmrbc);
6178 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
6179 * @dev: PCI device to query
6180 * @mmrbc: maximum memory read count in bytes
6181 * valid values are 512, 1024, 2048, 4096
6183 * If possible sets maximum memory read byte count, some bridges have errata
6184 * that prevent this.
6186 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
6192 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
6195 v = ffs(mmrbc) - 10;
6197 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6201 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
6204 if (v > FIELD_GET(PCI_X_STATUS_MAX_READ, stat))
6207 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
6210 o = FIELD_GET(PCI_X_CMD_MAX_READ, cmd);
6212 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
6215 cmd &= ~PCI_X_CMD_MAX_READ;
6216 cmd |= FIELD_PREP(PCI_X_CMD_MAX_READ, v);
6217 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
6222 EXPORT_SYMBOL(pcix_set_mmrbc);
6225 * pcie_get_readrq - get PCI Express read request size
6226 * @dev: PCI device to query
6228 * Returns maximum memory read request in bytes or appropriate error value.
6230 int pcie_get_readrq(struct pci_dev *dev)
6234 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6236 return 128 << FIELD_GET(PCI_EXP_DEVCTL_READRQ, ctl);
6238 EXPORT_SYMBOL(pcie_get_readrq);
6241 * pcie_set_readrq - set PCI Express maximum memory read request
6242 * @dev: PCI device to query
6243 * @rq: maximum memory read count in bytes
6244 * valid values are 128, 256, 512, 1024, 2048, 4096
6246 * If possible sets maximum memory read request in bytes
6248 int pcie_set_readrq(struct pci_dev *dev, int rq)
6252 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
6254 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
6258 * If using the "performance" PCIe config, we clamp the read rq
6259 * size to the max packet size to keep the host bridge from
6260 * generating requests larger than we can cope with.
6262 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
6263 int mps = pcie_get_mps(dev);
6269 v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, ffs(rq) - 8);
6271 if (bridge->no_inc_mrrs) {
6272 int max_mrrs = pcie_get_readrq(dev);
6274 if (rq > max_mrrs) {
6275 pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
6280 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6281 PCI_EXP_DEVCTL_READRQ, v);
6283 return pcibios_err_to_errno(ret);
6285 EXPORT_SYMBOL(pcie_set_readrq);
6288 * pcie_get_mps - get PCI Express maximum payload size
6289 * @dev: PCI device to query
6291 * Returns maximum payload size in bytes
6293 int pcie_get_mps(struct pci_dev *dev)
6297 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6299 return 128 << FIELD_GET(PCI_EXP_DEVCTL_PAYLOAD, ctl);
6301 EXPORT_SYMBOL(pcie_get_mps);
6304 * pcie_set_mps - set PCI Express maximum payload size
6305 * @dev: PCI device to query
6306 * @mps: maximum payload size in bytes
6307 * valid values are 128, 256, 512, 1024, 2048, 4096
6309 * If possible sets maximum payload size
6311 int pcie_set_mps(struct pci_dev *dev, int mps)
6316 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6320 if (v > dev->pcie_mpss)
6322 v = FIELD_PREP(PCI_EXP_DEVCTL_PAYLOAD, v);
6324 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6325 PCI_EXP_DEVCTL_PAYLOAD, v);
6327 return pcibios_err_to_errno(ret);
6329 EXPORT_SYMBOL(pcie_set_mps);
6331 static enum pci_bus_speed to_pcie_link_speed(u16 lnksta)
6333 return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
6336 int pcie_link_speed_mbps(struct pci_dev *pdev)
6341 err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
6345 switch (to_pcie_link_speed(lnksta)) {
6346 case PCIE_SPEED_2_5GT:
6348 case PCIE_SPEED_5_0GT:
6350 case PCIE_SPEED_8_0GT:
6352 case PCIE_SPEED_16_0GT:
6354 case PCIE_SPEED_32_0GT:
6356 case PCIE_SPEED_64_0GT:
6364 EXPORT_SYMBOL(pcie_link_speed_mbps);
6367 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6368 * device and its bandwidth limitation
6369 * @dev: PCI device to query
6370 * @limiting_dev: storage for device causing the bandwidth limitation
6371 * @speed: storage for speed of limiting device
6372 * @width: storage for width of limiting device
6374 * Walk up the PCI device chain and find the point where the minimum
6375 * bandwidth is available. Return the bandwidth available there and (if
6376 * limiting_dev, speed, and width pointers are supplied) information about
6377 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6380 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6381 enum pci_bus_speed *speed,
6382 enum pcie_link_width *width)
6385 enum pci_bus_speed next_speed;
6386 enum pcie_link_width next_width;
6390 *speed = PCI_SPEED_UNKNOWN;
6392 *width = PCIE_LNK_WIDTH_UNKNOWN;
6397 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6399 next_speed = to_pcie_link_speed(lnksta);
6400 next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
6402 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6404 /* Check if current device limits the total bandwidth */
6405 if (!bw || next_bw <= bw) {
6409 *limiting_dev = dev;
6411 *speed = next_speed;
6413 *width = next_width;
6416 dev = pci_upstream_bridge(dev);
6421 EXPORT_SYMBOL(pcie_bandwidth_available);
6424 * pcie_get_speed_cap - query for the PCI device's link speed capability
6425 * @dev: PCI device to query
6427 * Query the PCI device speed capability. Return the maximum link speed
6428 * supported by the device.
6430 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6432 u32 lnkcap2, lnkcap;
6435 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6436 * implementation note there recommends using the Supported Link
6437 * Speeds Vector in Link Capabilities 2 when supported.
6439 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6440 * should use the Supported Link Speeds field in Link Capabilities,
6441 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6443 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6445 /* PCIe r3.0-compliant */
6447 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6449 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6450 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6451 return PCIE_SPEED_5_0GT;
6452 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6453 return PCIE_SPEED_2_5GT;
6455 return PCI_SPEED_UNKNOWN;
6457 EXPORT_SYMBOL(pcie_get_speed_cap);
6460 * pcie_get_width_cap - query for the PCI device's link width capability
6461 * @dev: PCI device to query
6463 * Query the PCI device width capability. Return the maximum link width
6464 * supported by the device.
6466 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6470 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6472 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap);
6474 return PCIE_LNK_WIDTH_UNKNOWN;
6476 EXPORT_SYMBOL(pcie_get_width_cap);
6479 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6481 * @speed: storage for link speed
6482 * @width: storage for link width
6484 * Calculate a PCI device's link bandwidth by querying for its link speed
6485 * and width, multiplying them, and applying encoding overhead. The result
6486 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6488 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6489 enum pcie_link_width *width)
6491 *speed = pcie_get_speed_cap(dev);
6492 *width = pcie_get_width_cap(dev);
6494 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6497 return *width * PCIE_SPEED2MBS_ENC(*speed);
6501 * __pcie_print_link_status - Report the PCI device's link speed and width
6502 * @dev: PCI device to query
6503 * @verbose: Print info even when enough bandwidth is available
6505 * If the available bandwidth at the device is less than the device is
6506 * capable of, report the device's maximum possible bandwidth and the
6507 * upstream link that limits its performance. If @verbose, always print
6508 * the available bandwidth, even if the device isn't constrained.
6510 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6512 enum pcie_link_width width, width_cap;
6513 enum pci_bus_speed speed, speed_cap;
6514 struct pci_dev *limiting_dev = NULL;
6515 u32 bw_avail, bw_cap;
6517 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6518 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6520 if (bw_avail >= bw_cap && verbose)
6521 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6522 bw_cap / 1000, bw_cap % 1000,
6523 pci_speed_string(speed_cap), width_cap);
6524 else if (bw_avail < bw_cap)
6525 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6526 bw_avail / 1000, bw_avail % 1000,
6527 pci_speed_string(speed), width,
6528 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6529 bw_cap / 1000, bw_cap % 1000,
6530 pci_speed_string(speed_cap), width_cap);
6534 * pcie_print_link_status - Report the PCI device's link speed and width
6535 * @dev: PCI device to query
6537 * Report the available bandwidth at the device.
6539 void pcie_print_link_status(struct pci_dev *dev)
6541 __pcie_print_link_status(dev, true);
6543 EXPORT_SYMBOL(pcie_print_link_status);
6546 * pci_select_bars - Make BAR mask from the type of resource
6547 * @dev: the PCI device for which BAR mask is made
6548 * @flags: resource type mask to be selected
6550 * This helper routine makes bar mask from the type of resource.
6552 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6555 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6556 if (pci_resource_flags(dev, i) & flags)
6560 EXPORT_SYMBOL(pci_select_bars);
6562 /* Some architectures require additional programming to enable VGA */
6563 static arch_set_vga_state_t arch_set_vga_state;
6565 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6567 arch_set_vga_state = func; /* NULL disables */
6570 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6571 unsigned int command_bits, u32 flags)
6573 if (arch_set_vga_state)
6574 return arch_set_vga_state(dev, decode, command_bits,
6580 * pci_set_vga_state - set VGA decode state on device and parents if requested
6581 * @dev: the PCI device
6582 * @decode: true = enable decoding, false = disable decoding
6583 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6584 * @flags: traverse ancestors and change bridges
6585 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6587 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6588 unsigned int command_bits, u32 flags)
6590 struct pci_bus *bus;
6591 struct pci_dev *bridge;
6595 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6597 /* ARCH specific VGA enables */
6598 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6602 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6603 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6605 cmd |= command_bits;
6607 cmd &= ~command_bits;
6608 pci_write_config_word(dev, PCI_COMMAND, cmd);
6611 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6618 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6621 cmd |= PCI_BRIDGE_CTL_VGA;
6623 cmd &= ~PCI_BRIDGE_CTL_VGA;
6624 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6633 bool pci_pr3_present(struct pci_dev *pdev)
6635 struct acpi_device *adev;
6640 adev = ACPI_COMPANION(&pdev->dev);
6644 return adev->power.flags.power_resources &&
6645 acpi_has_method(adev->handle, "_PR3");
6647 EXPORT_SYMBOL_GPL(pci_pr3_present);
6651 * pci_add_dma_alias - Add a DMA devfn alias for a device
6652 * @dev: the PCI device for which alias is added
6653 * @devfn_from: alias slot and function
6654 * @nr_devfns: number of subsequent devfns to alias
6656 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6657 * which is used to program permissible bus-devfn source addresses for DMA
6658 * requests in an IOMMU. These aliases factor into IOMMU group creation
6659 * and are useful for devices generating DMA requests beyond or different
6660 * from their logical bus-devfn. Examples include device quirks where the
6661 * device simply uses the wrong devfn, as well as non-transparent bridges
6662 * where the alias may be a proxy for devices in another domain.
6664 * IOMMU group creation is performed during device discovery or addition,
6665 * prior to any potential DMA mapping and therefore prior to driver probing
6666 * (especially for userspace assigned devices where IOMMU group definition
6667 * cannot be left as a userspace activity). DMA aliases should therefore
6668 * be configured via quirks, such as the PCI fixup header quirk.
6670 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6671 unsigned int nr_devfns)
6675 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);
6676 devfn_to = devfn_from + nr_devfns - 1;
6678 if (!dev->dma_alias_mask)
6679 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6680 if (!dev->dma_alias_mask) {
6681 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6685 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6688 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6689 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6690 else if (nr_devfns > 1)
6691 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6692 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6693 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6696 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6698 return (dev1->dma_alias_mask &&
6699 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6700 (dev2->dma_alias_mask &&
6701 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6702 pci_real_dma_dev(dev1) == dev2 ||
6703 pci_real_dma_dev(dev2) == dev1;
6706 bool pci_device_is_present(struct pci_dev *pdev)
6710 /* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6711 pdev = pci_physfn(pdev);
6712 if (pci_dev_is_disconnected(pdev))
6714 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6716 EXPORT_SYMBOL_GPL(pci_device_is_present);
6718 void pci_ignore_hotplug(struct pci_dev *dev)
6720 struct pci_dev *bridge = dev->bus->self;
6722 dev->ignore_hotplug = 1;
6723 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6725 bridge->ignore_hotplug = 1;
6727 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6730 * pci_real_dma_dev - Get PCI DMA device for PCI device
6731 * @dev: the PCI device that may have a PCI DMA alias
6733 * Permits the platform to provide architecture-specific functionality to
6734 * devices needing to alias DMA to another PCI device on another PCI bus. If
6735 * the PCI device is on the same bus, it is recommended to use
6736 * pci_add_dma_alias(). This is the default implementation. Architecture
6737 * implementations can override this.
6739 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6744 resource_size_t __weak pcibios_default_alignment(void)
6750 * Arches that don't want to expose struct resource to userland as-is in
6751 * sysfs and /proc can implement their own pci_resource_to_user().
6753 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6754 const struct resource *rsrc,
6755 resource_size_t *start, resource_size_t *end)
6757 *start = rsrc->start;
6761 static char *resource_alignment_param;
6762 static DEFINE_SPINLOCK(resource_alignment_lock);
6765 * pci_specified_resource_alignment - get resource alignment specified by user.
6766 * @dev: the PCI device to get
6767 * @resize: whether or not to change resources' size when reassigning alignment
6769 * RETURNS: Resource alignment if it is specified.
6770 * Zero if it is not specified.
6772 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6775 int align_order, count;
6776 resource_size_t align = pcibios_default_alignment();
6780 spin_lock(&resource_alignment_lock);
6781 p = resource_alignment_param;
6784 if (pci_has_flag(PCI_PROBE_ONLY)) {
6786 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6792 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6795 if (align_order > 63) {
6796 pr_err("PCI: Invalid requested alignment (order %d)\n",
6798 align_order = PAGE_SHIFT;
6801 align_order = PAGE_SHIFT;
6804 ret = pci_dev_str_match(dev, p, &p);
6807 align = 1ULL << align_order;
6809 } else if (ret < 0) {
6810 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6815 if (*p != ';' && *p != ',') {
6816 /* End of param or invalid format */
6822 spin_unlock(&resource_alignment_lock);
6826 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6827 resource_size_t align, bool resize)
6829 struct resource *r = &dev->resource[bar];
6830 const char *r_name = pci_resource_name(dev, bar);
6831 resource_size_t size;
6833 if (!(r->flags & IORESOURCE_MEM))
6836 if (r->flags & IORESOURCE_PCI_FIXED) {
6837 pci_info(dev, "%s %pR: ignoring requested alignment %#llx\n",
6838 r_name, r, (unsigned long long)align);
6842 size = resource_size(r);
6847 * Increase the alignment of the resource. There are two ways we
6850 * 1) Increase the size of the resource. BARs are aligned on their
6851 * size, so when we reallocate space for this resource, we'll
6852 * allocate it with the larger alignment. This also prevents
6853 * assignment of any other BARs inside the alignment region, so
6854 * if we're requesting page alignment, this means no other BARs
6855 * will share the page.
6857 * The disadvantage is that this makes the resource larger than
6858 * the hardware BAR, which may break drivers that compute things
6859 * based on the resource size, e.g., to find registers at a
6860 * fixed offset before the end of the BAR.
6862 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6863 * set r->start to the desired alignment. By itself this
6864 * doesn't prevent other BARs being put inside the alignment
6865 * region, but if we realign *every* resource of every device in
6866 * the system, none of them will share an alignment region.
6868 * When the user has requested alignment for only some devices via
6869 * the "pci=resource_alignment" argument, "resize" is true and we
6870 * use the first method. Otherwise we assume we're aligning all
6871 * devices and we use the second.
6874 pci_info(dev, "%s %pR: requesting alignment to %#llx\n",
6875 r_name, r, (unsigned long long)align);
6881 r->flags &= ~IORESOURCE_SIZEALIGN;
6882 r->flags |= IORESOURCE_STARTALIGN;
6884 r->end = r->start + size - 1;
6886 r->flags |= IORESOURCE_UNSET;
6890 * This function disables memory decoding and releases memory resources
6891 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6892 * It also rounds up size to specified alignment.
6893 * Later on, the kernel will assign page-aligned memory resource back
6896 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6900 resource_size_t align;
6902 bool resize = false;
6905 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6906 * 3.4.1.11. Their resources are allocated from the space
6907 * described by the VF BARx register in the PF's SR-IOV capability.
6908 * We can't influence their alignment here.
6913 /* check if specified PCI is target device to reassign */
6914 align = pci_specified_resource_alignment(dev, &resize);
6918 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6919 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6920 pci_warn(dev, "Can't reassign resources to host bridge\n");
6924 pci_read_config_word(dev, PCI_COMMAND, &command);
6925 command &= ~PCI_COMMAND_MEMORY;
6926 pci_write_config_word(dev, PCI_COMMAND, command);
6928 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6929 pci_request_resource_alignment(dev, i, align, resize);
6932 * Need to disable bridge's resource window,
6933 * to enable the kernel to reassign new resource
6936 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6937 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6938 r = &dev->resource[i];
6939 if (!(r->flags & IORESOURCE_MEM))
6941 r->flags |= IORESOURCE_UNSET;
6942 r->end = resource_size(r) - 1;
6945 pci_disable_bridge_window(dev);
6949 static ssize_t resource_alignment_show(const struct bus_type *bus, char *buf)
6953 spin_lock(&resource_alignment_lock);
6954 if (resource_alignment_param)
6955 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6956 spin_unlock(&resource_alignment_lock);
6961 static ssize_t resource_alignment_store(const struct bus_type *bus,
6962 const char *buf, size_t count)
6964 char *param, *old, *end;
6966 if (count >= (PAGE_SIZE - 1))
6969 param = kstrndup(buf, count, GFP_KERNEL);
6973 end = strchr(param, '\n');
6977 spin_lock(&resource_alignment_lock);
6978 old = resource_alignment_param;
6979 if (strlen(param)) {
6980 resource_alignment_param = param;
6983 resource_alignment_param = NULL;
6985 spin_unlock(&resource_alignment_lock);
6992 static BUS_ATTR_RW(resource_alignment);
6994 static int __init pci_resource_alignment_sysfs_init(void)
6996 return bus_create_file(&pci_bus_type,
6997 &bus_attr_resource_alignment);
6999 late_initcall(pci_resource_alignment_sysfs_init);
7001 static void pci_no_domains(void)
7003 #ifdef CONFIG_PCI_DOMAINS
7004 pci_domains_supported = 0;
7008 #ifdef CONFIG_PCI_DOMAINS_GENERIC
7009 static DEFINE_IDA(pci_domain_nr_static_ida);
7010 static DEFINE_IDA(pci_domain_nr_dynamic_ida);
7012 static void of_pci_reserve_static_domain_nr(void)
7014 struct device_node *np;
7017 for_each_node_by_type(np, "pci") {
7018 domain_nr = of_get_pci_domain_nr(np);
7022 * Permanently allocate domain_nr in dynamic_ida
7023 * to prevent it from dynamic allocation.
7025 ida_alloc_range(&pci_domain_nr_dynamic_ida,
7026 domain_nr, domain_nr, GFP_KERNEL);
7030 static int of_pci_bus_find_domain_nr(struct device *parent)
7032 static bool static_domains_reserved = false;
7035 /* On the first call scan device tree for static allocations. */
7036 if (!static_domains_reserved) {
7037 of_pci_reserve_static_domain_nr();
7038 static_domains_reserved = true;
7043 * If domain is in DT, allocate it in static IDA. This
7044 * prevents duplicate static allocations in case of errors
7047 domain_nr = of_get_pci_domain_nr(parent->of_node);
7049 return ida_alloc_range(&pci_domain_nr_static_ida,
7050 domain_nr, domain_nr,
7055 * If domain was not specified in DT, choose a free ID from dynamic
7056 * allocations. All domain numbers from DT are permanently in
7057 * dynamic allocations to prevent assigning them to other DT nodes
7058 * without static domain.
7060 return ida_alloc(&pci_domain_nr_dynamic_ida, GFP_KERNEL);
7063 static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
7065 if (bus->domain_nr < 0)
7068 /* Release domain from IDA where it was allocated. */
7069 if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr)
7070 ida_free(&pci_domain_nr_static_ida, bus->domain_nr);
7072 ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr);
7075 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
7077 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
7078 acpi_pci_bus_find_domain_nr(bus);
7081 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
7085 of_pci_bus_release_domain_nr(bus, parent);
7090 * pci_ext_cfg_avail - can we access extended PCI config space?
7092 * Returns 1 if we can access PCI extended config space (offsets
7093 * greater than 0xff). This is the default implementation. Architecture
7094 * implementations can override this.
7096 int __weak pci_ext_cfg_avail(void)
7101 void __weak pci_fixup_cardbus(struct pci_bus *bus)
7104 EXPORT_SYMBOL(pci_fixup_cardbus);
7106 static int __init pci_setup(char *str)
7109 char *k = strchr(str, ',');
7112 if (*str && (str = pcibios_setup(str)) && *str) {
7113 if (!strcmp(str, "nomsi")) {
7115 } else if (!strncmp(str, "noats", 5)) {
7116 pr_info("PCIe: ATS is disabled\n");
7117 pcie_ats_disabled = true;
7118 } else if (!strcmp(str, "noaer")) {
7120 } else if (!strcmp(str, "earlydump")) {
7121 pci_early_dump = true;
7122 } else if (!strncmp(str, "realloc=", 8)) {
7123 pci_realloc_get_opt(str + 8);
7124 } else if (!strncmp(str, "realloc", 7)) {
7125 pci_realloc_get_opt("on");
7126 } else if (!strcmp(str, "nodomains")) {
7128 } else if (!strncmp(str, "noari", 5)) {
7129 pcie_ari_disabled = true;
7130 } else if (!strncmp(str, "cbiosize=", 9)) {
7131 pci_cardbus_io_size = memparse(str + 9, &str);
7132 } else if (!strncmp(str, "cbmemsize=", 10)) {
7133 pci_cardbus_mem_size = memparse(str + 10, &str);
7134 } else if (!strncmp(str, "resource_alignment=", 19)) {
7135 resource_alignment_param = str + 19;
7136 } else if (!strncmp(str, "ecrc=", 5)) {
7137 pcie_ecrc_get_policy(str + 5);
7138 } else if (!strncmp(str, "hpiosize=", 9)) {
7139 pci_hotplug_io_size = memparse(str + 9, &str);
7140 } else if (!strncmp(str, "hpmmiosize=", 11)) {
7141 pci_hotplug_mmio_size = memparse(str + 11, &str);
7142 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
7143 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
7144 } else if (!strncmp(str, "hpmemsize=", 10)) {
7145 pci_hotplug_mmio_size = memparse(str + 10, &str);
7146 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
7147 } else if (!strncmp(str, "hpbussize=", 10)) {
7148 pci_hotplug_bus_size =
7149 simple_strtoul(str + 10, &str, 0);
7150 if (pci_hotplug_bus_size > 0xff)
7151 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
7152 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
7153 pcie_bus_config = PCIE_BUS_TUNE_OFF;
7154 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
7155 pcie_bus_config = PCIE_BUS_SAFE;
7156 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
7157 pcie_bus_config = PCIE_BUS_PERFORMANCE;
7158 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
7159 pcie_bus_config = PCIE_BUS_PEER2PEER;
7160 } else if (!strncmp(str, "pcie_scan_all", 13)) {
7161 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
7162 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
7163 disable_acs_redir_param = str + 18;
7165 pr_err("PCI: Unknown option `%s'\n", str);
7172 early_param("pci", pci_setup);
7175 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
7176 * in pci_setup(), above, to point to data in the __initdata section which
7177 * will be freed after the init sequence is complete. We can't allocate memory
7178 * in pci_setup() because some architectures do not have any memory allocation
7179 * service available during an early_param() call. So we allocate memory and
7180 * copy the variable here before the init section is freed.
7183 static int __init pci_realloc_setup_params(void)
7185 resource_alignment_param = kstrdup(resource_alignment_param,
7187 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
7191 pure_initcall(pci_realloc_setup_params);