2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/interrupt.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pci_hotplug.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pci-ats.h>
32 #include <asm/setup.h>
34 #include <linux/aer.h>
37 const char *pci_power_names[] = {
38 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
40 EXPORT_SYMBOL_GPL(pci_power_names);
42 int isa_dma_bridge_buggy;
43 EXPORT_SYMBOL(isa_dma_bridge_buggy);
46 EXPORT_SYMBOL(pci_pci_problems);
48 unsigned int pci_pm_d3_delay;
50 static void pci_pme_list_scan(struct work_struct *work);
52 static LIST_HEAD(pci_pme_list);
53 static DEFINE_MUTEX(pci_pme_list_mutex);
54 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
56 struct pci_pme_device {
57 struct list_head list;
61 #define PME_TIMEOUT 1000 /* How long between PME checks */
63 static void pci_dev_d3_sleep(struct pci_dev *dev)
65 unsigned int delay = dev->d3_delay;
67 if (delay < pci_pm_d3_delay)
68 delay = pci_pm_d3_delay;
74 #ifdef CONFIG_PCI_DOMAINS
75 int pci_domains_supported = 1;
78 #define DEFAULT_CARDBUS_IO_SIZE (256)
79 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
80 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
81 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
82 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
84 #define DEFAULT_HOTPLUG_IO_SIZE (256)
85 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
86 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
87 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
88 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
90 #define DEFAULT_HOTPLUG_BUS_SIZE 1
91 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
93 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
96 * The default CLS is used if arch didn't set CLS explicitly and not
97 * all pci devices agree on the same value. Arch can override either
98 * the dfl or actual value as it sees fit. Don't forget this is
99 * measured in 32-bit words, not bytes.
101 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
102 u8 pci_cache_line_size;
105 * If we set up a device for bus mastering, we need to check the latency
106 * timer as certain BIOSes forget to set it properly.
108 unsigned int pcibios_max_latency = 255;
110 /* If set, the PCIe ARI capability will not be used. */
111 static bool pcie_ari_disabled;
113 /* Disable bridge_d3 for all PCIe ports */
114 static bool pci_bridge_d3_disable;
115 /* Force bridge_d3 for all PCIe ports */
116 static bool pci_bridge_d3_force;
118 static int __init pcie_port_pm_setup(char *str)
120 if (!strcmp(str, "off"))
121 pci_bridge_d3_disable = true;
122 else if (!strcmp(str, "force"))
123 pci_bridge_d3_force = true;
126 __setup("pcie_port_pm=", pcie_port_pm_setup);
129 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
130 * @bus: pointer to PCI bus structure to search
132 * Given a PCI bus, returns the highest PCI bus number present in the set
133 * including the given PCI bus and its list of child PCI buses.
135 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
138 unsigned char max, n;
140 max = bus->busn_res.end;
141 list_for_each_entry(tmp, &bus->children, node) {
142 n = pci_bus_max_busnr(tmp);
148 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
150 #ifdef CONFIG_HAS_IOMEM
151 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
153 struct resource *res = &pdev->resource[bar];
156 * Make sure the BAR is actually a memory resource, not an IO resource
158 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
159 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
162 return ioremap_nocache(res->start, resource_size(res));
164 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
166 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
169 * Make sure the BAR is actually a memory resource, not an IO resource
171 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
175 return ioremap_wc(pci_resource_start(pdev, bar),
176 pci_resource_len(pdev, bar));
178 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
182 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
183 u8 pos, int cap, int *ttl)
188 pci_bus_read_config_byte(bus, devfn, pos, &pos);
194 pci_bus_read_config_word(bus, devfn, pos, &ent);
206 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
209 int ttl = PCI_FIND_CAP_TTL;
211 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
214 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
216 return __pci_find_next_cap(dev->bus, dev->devfn,
217 pos + PCI_CAP_LIST_NEXT, cap);
219 EXPORT_SYMBOL_GPL(pci_find_next_capability);
221 static int __pci_bus_find_cap_start(struct pci_bus *bus,
222 unsigned int devfn, u8 hdr_type)
226 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
227 if (!(status & PCI_STATUS_CAP_LIST))
231 case PCI_HEADER_TYPE_NORMAL:
232 case PCI_HEADER_TYPE_BRIDGE:
233 return PCI_CAPABILITY_LIST;
234 case PCI_HEADER_TYPE_CARDBUS:
235 return PCI_CB_CAPABILITY_LIST;
242 * pci_find_capability - query for devices' capabilities
243 * @dev: PCI device to query
244 * @cap: capability code
246 * Tell if a device supports a given PCI capability.
247 * Returns the address of the requested capability structure within the
248 * device's PCI configuration space or 0 in case the device does not
249 * support it. Possible values for @cap:
251 * %PCI_CAP_ID_PM Power Management
252 * %PCI_CAP_ID_AGP Accelerated Graphics Port
253 * %PCI_CAP_ID_VPD Vital Product Data
254 * %PCI_CAP_ID_SLOTID Slot Identification
255 * %PCI_CAP_ID_MSI Message Signalled Interrupts
256 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
257 * %PCI_CAP_ID_PCIX PCI-X
258 * %PCI_CAP_ID_EXP PCI Express
260 int pci_find_capability(struct pci_dev *dev, int cap)
264 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
266 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
270 EXPORT_SYMBOL(pci_find_capability);
273 * pci_bus_find_capability - query for devices' capabilities
274 * @bus: the PCI bus to query
275 * @devfn: PCI device to query
276 * @cap: capability code
278 * Like pci_find_capability() but works for pci devices that do not have a
279 * pci_dev structure set up yet.
281 * Returns the address of the requested capability structure within the
282 * device's PCI configuration space or 0 in case the device does not
285 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
290 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
292 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
294 pos = __pci_find_next_cap(bus, devfn, pos, cap);
298 EXPORT_SYMBOL(pci_bus_find_capability);
301 * pci_find_next_ext_capability - Find an extended capability
302 * @dev: PCI device to query
303 * @start: address at which to start looking (0 to start at beginning of list)
304 * @cap: capability code
306 * Returns the address of the next matching extended capability structure
307 * within the device's PCI configuration space or 0 if the device does
308 * not support it. Some capabilities can occur several times, e.g., the
309 * vendor-specific capability, and this provides a way to find them all.
311 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
315 int pos = PCI_CFG_SPACE_SIZE;
317 /* minimum 8 bytes per capability */
318 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
320 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
326 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
330 * If we have no capabilities, this is indicated by cap ID,
331 * cap version and next pointer all being 0.
337 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
340 pos = PCI_EXT_CAP_NEXT(header);
341 if (pos < PCI_CFG_SPACE_SIZE)
344 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
350 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
353 * pci_find_ext_capability - Find an extended capability
354 * @dev: PCI device to query
355 * @cap: capability code
357 * Returns the address of the requested extended capability structure
358 * within the device's PCI configuration space or 0 if the device does
359 * not support it. Possible values for @cap:
361 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
362 * %PCI_EXT_CAP_ID_VC Virtual Channel
363 * %PCI_EXT_CAP_ID_DSN Device Serial Number
364 * %PCI_EXT_CAP_ID_PWR Power Budgeting
366 int pci_find_ext_capability(struct pci_dev *dev, int cap)
368 return pci_find_next_ext_capability(dev, 0, cap);
370 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
372 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
374 int rc, ttl = PCI_FIND_CAP_TTL;
377 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
378 mask = HT_3BIT_CAP_MASK;
380 mask = HT_5BIT_CAP_MASK;
382 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
383 PCI_CAP_ID_HT, &ttl);
385 rc = pci_read_config_byte(dev, pos + 3, &cap);
386 if (rc != PCIBIOS_SUCCESSFUL)
389 if ((cap & mask) == ht_cap)
392 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
393 pos + PCI_CAP_LIST_NEXT,
394 PCI_CAP_ID_HT, &ttl);
400 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
401 * @dev: PCI device to query
402 * @pos: Position from which to continue searching
403 * @ht_cap: Hypertransport capability code
405 * To be used in conjunction with pci_find_ht_capability() to search for
406 * all capabilities matching @ht_cap. @pos should always be a value returned
407 * from pci_find_ht_capability().
409 * NB. To be 100% safe against broken PCI devices, the caller should take
410 * steps to avoid an infinite loop.
412 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
414 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
416 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
419 * pci_find_ht_capability - query a device's Hypertransport capabilities
420 * @dev: PCI device to query
421 * @ht_cap: Hypertransport capability code
423 * Tell if a device supports a given Hypertransport capability.
424 * Returns an address within the device's PCI configuration space
425 * or 0 in case the device does not support the request capability.
426 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
427 * which has a Hypertransport capability matching @ht_cap.
429 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
433 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
435 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
439 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
442 * pci_find_parent_resource - return resource region of parent bus of given region
443 * @dev: PCI device structure contains resources to be searched
444 * @res: child resource record for which parent is sought
446 * For given resource region of given device, return the resource
447 * region of parent bus the given region is contained in.
449 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
450 struct resource *res)
452 const struct pci_bus *bus = dev->bus;
456 pci_bus_for_each_resource(bus, r, i) {
459 if (resource_contains(r, res)) {
462 * If the window is prefetchable but the BAR is
463 * not, the allocator made a mistake.
465 if (r->flags & IORESOURCE_PREFETCH &&
466 !(res->flags & IORESOURCE_PREFETCH))
470 * If we're below a transparent bridge, there may
471 * be both a positively-decoded aperture and a
472 * subtractively-decoded region that contain the BAR.
473 * We want the positively-decoded one, so this depends
474 * on pci_bus_for_each_resource() giving us those
482 EXPORT_SYMBOL(pci_find_parent_resource);
485 * pci_find_resource - Return matching PCI device resource
486 * @dev: PCI device to query
487 * @res: Resource to look for
489 * Goes over standard PCI resources (BARs) and checks if the given resource
490 * is partially or fully contained in any of them. In that case the
491 * matching resource is returned, %NULL otherwise.
493 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
497 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
498 struct resource *r = &dev->resource[i];
500 if (r->start && resource_contains(r, res))
506 EXPORT_SYMBOL(pci_find_resource);
509 * pci_find_pcie_root_port - return PCIe Root Port
510 * @dev: PCI device to query
512 * Traverse up the parent chain and return the PCIe Root Port PCI Device
513 * for a given PCI Device.
515 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
517 struct pci_dev *bridge, *highest_pcie_bridge = dev;
519 bridge = pci_upstream_bridge(dev);
520 while (bridge && pci_is_pcie(bridge)) {
521 highest_pcie_bridge = bridge;
522 bridge = pci_upstream_bridge(bridge);
525 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
528 return highest_pcie_bridge;
530 EXPORT_SYMBOL(pci_find_pcie_root_port);
533 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
534 * @dev: the PCI device to operate on
535 * @pos: config space offset of status word
536 * @mask: mask of bit(s) to care about in status word
538 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
540 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
544 /* Wait for Transaction Pending bit clean */
545 for (i = 0; i < 4; i++) {
548 msleep((1 << (i - 1)) * 100);
550 pci_read_config_word(dev, pos, &status);
551 if (!(status & mask))
559 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
560 * @dev: PCI device to have its BARs restored
562 * Restore the BAR values for a given device, so as to make it
563 * accessible by its driver.
565 static void pci_restore_bars(struct pci_dev *dev)
569 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
570 pci_update_resource(dev, i);
573 static const struct pci_platform_pm_ops *pci_platform_pm;
575 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
577 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
578 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
580 pci_platform_pm = ops;
584 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
586 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
589 static inline int platform_pci_set_power_state(struct pci_dev *dev,
592 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
595 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
597 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
600 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
602 return pci_platform_pm ?
603 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
606 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
608 return pci_platform_pm ?
609 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
612 static inline bool platform_pci_need_resume(struct pci_dev *dev)
614 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
618 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
620 * @dev: PCI device to handle.
621 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
624 * -EINVAL if the requested state is invalid.
625 * -EIO if device does not support PCI PM or its PM capabilities register has a
626 * wrong version, or device doesn't support the requested state.
627 * 0 if device already is in the requested state.
628 * 0 if device's power state has been successfully changed.
630 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
633 bool need_restore = false;
635 /* Check if we're already there */
636 if (dev->current_state == state)
642 if (state < PCI_D0 || state > PCI_D3hot)
645 /* Validate current state:
646 * Can enter D0 from any state, but if we can only go deeper
647 * to sleep if we're already in a low power state
649 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
650 && dev->current_state > state) {
651 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
652 dev->current_state, state);
656 /* check if this device supports the desired state */
657 if ((state == PCI_D1 && !dev->d1_support)
658 || (state == PCI_D2 && !dev->d2_support))
661 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
663 /* If we're (effectively) in D3, force entire word to 0.
664 * This doesn't affect PME_Status, disables PME_En, and
665 * sets PowerState to 0.
667 switch (dev->current_state) {
671 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
676 case PCI_UNKNOWN: /* Boot-up */
677 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
678 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
680 /* Fall-through: force to D0 */
686 /* enter specified state */
687 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
689 /* Mandatory power management transition delays */
690 /* see PCI PM 1.1 5.6.1 table 18 */
691 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
692 pci_dev_d3_sleep(dev);
693 else if (state == PCI_D2 || dev->current_state == PCI_D2)
694 udelay(PCI_PM_D2_DELAY);
696 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
697 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
698 if (dev->current_state != state && printk_ratelimit())
699 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
703 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
704 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
705 * from D3hot to D0 _may_ perform an internal reset, thereby
706 * going to "D0 Uninitialized" rather than "D0 Initialized".
707 * For example, at least some versions of the 3c905B and the
708 * 3c556B exhibit this behaviour.
710 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
711 * devices in a D3hot state at boot. Consequently, we need to
712 * restore at least the BARs so that the device will be
713 * accessible to its driver.
716 pci_restore_bars(dev);
719 pcie_aspm_pm_state_change(dev->bus->self);
725 * pci_update_current_state - Read power state of given device and cache it
726 * @dev: PCI device to handle.
727 * @state: State to cache in case the device doesn't have the PM capability
729 * The power state is read from the PMCSR register, which however is
730 * inaccessible in D3cold. The platform firmware is therefore queried first
731 * to detect accessibility of the register. In case the platform firmware
732 * reports an incorrect state or the device isn't power manageable by the
733 * platform at all, we try to detect D3cold by testing accessibility of the
734 * vendor ID in config space.
736 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
738 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
739 !pci_device_is_present(dev)) {
740 dev->current_state = PCI_D3cold;
741 } else if (dev->pm_cap) {
744 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
745 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
747 dev->current_state = state;
752 * pci_platform_power_transition - Use platform to change device power state
753 * @dev: PCI device to handle.
754 * @state: State to put the device into.
756 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
760 if (platform_pci_power_manageable(dev)) {
761 error = platform_pci_set_power_state(dev, state);
763 pci_update_current_state(dev, state);
767 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
768 dev->current_state = PCI_D0;
774 * pci_wakeup - Wake up a PCI device
775 * @pci_dev: Device to handle.
776 * @ign: ignored parameter
778 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
780 pci_wakeup_event(pci_dev);
781 pm_request_resume(&pci_dev->dev);
786 * pci_wakeup_bus - Walk given bus and wake up devices on it
787 * @bus: Top bus of the subtree to walk.
789 static void pci_wakeup_bus(struct pci_bus *bus)
792 pci_walk_bus(bus, pci_wakeup, NULL);
796 * __pci_start_power_transition - Start power transition of a PCI device
797 * @dev: PCI device to handle.
798 * @state: State to put the device into.
800 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
802 if (state == PCI_D0) {
803 pci_platform_power_transition(dev, PCI_D0);
805 * Mandatory power management transition delays, see
806 * PCI Express Base Specification Revision 2.0 Section
807 * 6.6.1: Conventional Reset. Do not delay for
808 * devices powered on/off by corresponding bridge,
809 * because have already delayed for the bridge.
811 if (dev->runtime_d3cold) {
812 if (dev->d3cold_delay)
813 msleep(dev->d3cold_delay);
815 * When powering on a bridge from D3cold, the
816 * whole hierarchy may be powered on into
817 * D0uninitialized state, resume them to give
818 * them a chance to suspend again
820 pci_wakeup_bus(dev->subordinate);
826 * __pci_dev_set_current_state - Set current state of a PCI device
827 * @dev: Device to handle
828 * @data: pointer to state to be set
830 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
832 pci_power_t state = *(pci_power_t *)data;
834 dev->current_state = state;
839 * __pci_bus_set_current_state - Walk given bus and set current state of devices
840 * @bus: Top bus of the subtree to walk.
841 * @state: state to be set
843 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
846 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
850 * __pci_complete_power_transition - Complete power transition of a PCI device
851 * @dev: PCI device to handle.
852 * @state: State to put the device into.
854 * This function should not be called directly by device drivers.
856 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
862 ret = pci_platform_power_transition(dev, state);
863 /* Power off the bridge may power off the whole hierarchy */
864 if (!ret && state == PCI_D3cold)
865 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
868 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
871 * pci_set_power_state - Set the power state of a PCI device
872 * @dev: PCI device to handle.
873 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
875 * Transition a device to a new power state, using the platform firmware and/or
876 * the device's PCI PM registers.
879 * -EINVAL if the requested state is invalid.
880 * -EIO if device does not support PCI PM or its PM capabilities register has a
881 * wrong version, or device doesn't support the requested state.
882 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
883 * 0 if device already is in the requested state.
884 * 0 if the transition is to D3 but D3 is not supported.
885 * 0 if device's power state has been successfully changed.
887 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
891 /* bound the state we're entering */
892 if (state > PCI_D3cold)
894 else if (state < PCI_D0)
896 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
898 * If the device or the parent bridge do not support PCI PM,
899 * ignore the request if we're doing anything other than putting
900 * it into D0 (which would only happen on boot).
904 /* Check if we're already there */
905 if (dev->current_state == state)
908 __pci_start_power_transition(dev, state);
910 /* This device is quirked not to be put into D3, so
911 don't put it in D3 */
912 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
916 * To put device in D3cold, we put device into D3hot in native
917 * way, then put device into D3cold with platform ops
919 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
922 if (!__pci_complete_power_transition(dev, state))
927 EXPORT_SYMBOL(pci_set_power_state);
930 * pci_power_up - Put the given device into D0 forcibly
931 * @dev: PCI device to power up
933 void pci_power_up(struct pci_dev *dev)
935 __pci_start_power_transition(dev, PCI_D0);
936 pci_raw_set_power_state(dev, PCI_D0);
937 pci_update_current_state(dev, PCI_D0);
941 * pci_choose_state - Choose the power state of a PCI device
942 * @dev: PCI device to be suspended
943 * @state: target sleep state for the whole system. This is the value
944 * that is passed to suspend() function.
946 * Returns PCI power state suitable for given device and given system
950 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
957 ret = platform_pci_choose_state(dev);
958 if (ret != PCI_POWER_ERROR)
961 switch (state.event) {
964 case PM_EVENT_FREEZE:
965 case PM_EVENT_PRETHAW:
966 /* REVISIT both freeze and pre-thaw "should" use D0 */
967 case PM_EVENT_SUSPEND:
968 case PM_EVENT_HIBERNATE:
971 dev_info(&dev->dev, "unrecognized suspend event %d\n",
977 EXPORT_SYMBOL(pci_choose_state);
979 #define PCI_EXP_SAVE_REGS 7
981 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
982 u16 cap, bool extended)
984 struct pci_cap_saved_state *tmp;
986 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
987 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
993 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
995 return _pci_find_saved_cap(dev, cap, false);
998 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1000 return _pci_find_saved_cap(dev, cap, true);
1003 static int pci_save_pcie_state(struct pci_dev *dev)
1006 struct pci_cap_saved_state *save_state;
1009 if (!pci_is_pcie(dev))
1012 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1014 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1018 cap = (u16 *)&save_state->cap.data[0];
1019 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1020 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1021 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1022 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1023 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1024 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1025 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1030 static void pci_restore_pcie_state(struct pci_dev *dev)
1033 struct pci_cap_saved_state *save_state;
1036 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1040 cap = (u16 *)&save_state->cap.data[0];
1041 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1042 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1043 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1044 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1045 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1046 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1047 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1051 static int pci_save_pcix_state(struct pci_dev *dev)
1054 struct pci_cap_saved_state *save_state;
1056 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1060 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1062 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1066 pci_read_config_word(dev, pos + PCI_X_CMD,
1067 (u16 *)save_state->cap.data);
1072 static void pci_restore_pcix_state(struct pci_dev *dev)
1075 struct pci_cap_saved_state *save_state;
1078 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1079 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1080 if (!save_state || !pos)
1082 cap = (u16 *)&save_state->cap.data[0];
1084 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1089 * pci_save_state - save the PCI configuration space of a device before suspending
1090 * @dev: - PCI device that we're dealing with
1092 int pci_save_state(struct pci_dev *dev)
1095 /* XXX: 100% dword access ok here? */
1096 for (i = 0; i < 16; i++)
1097 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1098 dev->state_saved = true;
1100 i = pci_save_pcie_state(dev);
1104 i = pci_save_pcix_state(dev);
1108 return pci_save_vc_state(dev);
1110 EXPORT_SYMBOL(pci_save_state);
1112 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1113 u32 saved_val, int retry, bool force)
1117 pci_read_config_dword(pdev, offset, &val);
1118 if (!force && val == saved_val)
1122 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1123 offset, val, saved_val);
1124 pci_write_config_dword(pdev, offset, saved_val);
1128 pci_read_config_dword(pdev, offset, &val);
1129 if (val == saved_val)
1136 static void pci_restore_config_space_range(struct pci_dev *pdev,
1137 int start, int end, int retry,
1142 for (index = end; index >= start; index--)
1143 pci_restore_config_dword(pdev, 4 * index,
1144 pdev->saved_config_space[index],
1148 static void pci_restore_config_space(struct pci_dev *pdev)
1150 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1151 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1152 /* Restore BARs before the command register. */
1153 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1154 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1155 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1156 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1159 * Force rewriting of prefetch registers to avoid S3 resume
1160 * issues on Intel PCI bridges that occur when these
1161 * registers are not explicitly written.
1163 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1164 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1166 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1171 * pci_restore_state - Restore the saved state of a PCI device
1172 * @dev: - PCI device that we're dealing with
1174 void pci_restore_state(struct pci_dev *dev)
1176 if (!dev->state_saved)
1179 /* PCI Express register must be restored first */
1180 pci_restore_pcie_state(dev);
1181 pci_restore_pasid_state(dev);
1182 pci_restore_pri_state(dev);
1183 pci_restore_ats_state(dev);
1184 pci_restore_vc_state(dev);
1186 pci_cleanup_aer_error_status_regs(dev);
1188 pci_restore_config_space(dev);
1190 pci_restore_pcix_state(dev);
1191 pci_restore_msi_state(dev);
1193 /* Restore ACS and IOV configuration state */
1194 pci_enable_acs(dev);
1195 pci_restore_iov_state(dev);
1197 dev->state_saved = false;
1199 EXPORT_SYMBOL(pci_restore_state);
1201 struct pci_saved_state {
1202 u32 config_space[16];
1203 struct pci_cap_saved_data cap[0];
1207 * pci_store_saved_state - Allocate and return an opaque struct containing
1208 * the device saved state.
1209 * @dev: PCI device that we're dealing with
1211 * Return NULL if no state or error.
1213 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1215 struct pci_saved_state *state;
1216 struct pci_cap_saved_state *tmp;
1217 struct pci_cap_saved_data *cap;
1220 if (!dev->state_saved)
1223 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1225 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1226 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1228 state = kzalloc(size, GFP_KERNEL);
1232 memcpy(state->config_space, dev->saved_config_space,
1233 sizeof(state->config_space));
1236 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1237 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1238 memcpy(cap, &tmp->cap, len);
1239 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1241 /* Empty cap_save terminates list */
1245 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1248 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1249 * @dev: PCI device that we're dealing with
1250 * @state: Saved state returned from pci_store_saved_state()
1252 int pci_load_saved_state(struct pci_dev *dev,
1253 struct pci_saved_state *state)
1255 struct pci_cap_saved_data *cap;
1257 dev->state_saved = false;
1262 memcpy(dev->saved_config_space, state->config_space,
1263 sizeof(state->config_space));
1267 struct pci_cap_saved_state *tmp;
1269 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1270 if (!tmp || tmp->cap.size != cap->size)
1273 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1274 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1275 sizeof(struct pci_cap_saved_data) + cap->size);
1278 dev->state_saved = true;
1281 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1284 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1285 * and free the memory allocated for it.
1286 * @dev: PCI device that we're dealing with
1287 * @state: Pointer to saved state returned from pci_store_saved_state()
1289 int pci_load_and_free_saved_state(struct pci_dev *dev,
1290 struct pci_saved_state **state)
1292 int ret = pci_load_saved_state(dev, *state);
1297 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1299 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1301 return pci_enable_resources(dev, bars);
1304 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1307 struct pci_dev *bridge;
1311 err = pci_set_power_state(dev, PCI_D0);
1312 if (err < 0 && err != -EIO)
1315 bridge = pci_upstream_bridge(dev);
1317 pcie_aspm_powersave_config_link(bridge);
1319 err = pcibios_enable_device(dev, bars);
1322 pci_fixup_device(pci_fixup_enable, dev);
1324 if (dev->msi_enabled || dev->msix_enabled)
1327 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1329 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1330 if (cmd & PCI_COMMAND_INTX_DISABLE)
1331 pci_write_config_word(dev, PCI_COMMAND,
1332 cmd & ~PCI_COMMAND_INTX_DISABLE);
1339 * pci_reenable_device - Resume abandoned device
1340 * @dev: PCI device to be resumed
1342 * Note this function is a backend of pci_default_resume and is not supposed
1343 * to be called by normal code, write proper resume handler and use it instead.
1345 int pci_reenable_device(struct pci_dev *dev)
1347 if (pci_is_enabled(dev))
1348 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1351 EXPORT_SYMBOL(pci_reenable_device);
1353 static void pci_enable_bridge(struct pci_dev *dev)
1355 struct pci_dev *bridge;
1358 bridge = pci_upstream_bridge(dev);
1360 pci_enable_bridge(bridge);
1362 if (pci_is_enabled(dev)) {
1363 if (!dev->is_busmaster)
1364 pci_set_master(dev);
1368 retval = pci_enable_device(dev);
1370 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1372 pci_set_master(dev);
1375 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1377 struct pci_dev *bridge;
1382 * Power state could be unknown at this point, either due to a fresh
1383 * boot or a device removal call. So get the current power state
1384 * so that things like MSI message writing will behave as expected
1385 * (e.g. if the device really is in D0 at enable time).
1387 pci_update_current_state(dev, dev->current_state);
1389 if (atomic_inc_return(&dev->enable_cnt) > 1)
1390 return 0; /* already enabled */
1392 bridge = pci_upstream_bridge(dev);
1394 pci_enable_bridge(bridge);
1396 /* only skip sriov related */
1397 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1398 if (dev->resource[i].flags & flags)
1400 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1401 if (dev->resource[i].flags & flags)
1404 err = do_pci_enable_device(dev, bars);
1406 atomic_dec(&dev->enable_cnt);
1411 * pci_enable_device_io - Initialize a device for use with IO space
1412 * @dev: PCI device to be initialized
1414 * Initialize device before it's used by a driver. Ask low-level code
1415 * to enable I/O resources. Wake up the device if it was suspended.
1416 * Beware, this function can fail.
1418 int pci_enable_device_io(struct pci_dev *dev)
1420 return pci_enable_device_flags(dev, IORESOURCE_IO);
1422 EXPORT_SYMBOL(pci_enable_device_io);
1425 * pci_enable_device_mem - Initialize a device for use with Memory space
1426 * @dev: PCI device to be initialized
1428 * Initialize device before it's used by a driver. Ask low-level code
1429 * to enable Memory resources. Wake up the device if it was suspended.
1430 * Beware, this function can fail.
1432 int pci_enable_device_mem(struct pci_dev *dev)
1434 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1436 EXPORT_SYMBOL(pci_enable_device_mem);
1439 * pci_enable_device - Initialize device before it's used by a driver.
1440 * @dev: PCI device to be initialized
1442 * Initialize device before it's used by a driver. Ask low-level code
1443 * to enable I/O and memory. Wake up the device if it was suspended.
1444 * Beware, this function can fail.
1446 * Note we don't actually enable the device many times if we call
1447 * this function repeatedly (we just increment the count).
1449 int pci_enable_device(struct pci_dev *dev)
1451 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1453 EXPORT_SYMBOL(pci_enable_device);
1456 * Managed PCI resources. This manages device on/off, intx/msi/msix
1457 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1458 * there's no need to track it separately. pci_devres is initialized
1459 * when a device is enabled using managed PCI device enable interface.
1462 unsigned int enabled:1;
1463 unsigned int pinned:1;
1464 unsigned int orig_intx:1;
1465 unsigned int restore_intx:1;
1469 static void pcim_release(struct device *gendev, void *res)
1471 struct pci_dev *dev = to_pci_dev(gendev);
1472 struct pci_devres *this = res;
1475 if (dev->msi_enabled)
1476 pci_disable_msi(dev);
1477 if (dev->msix_enabled)
1478 pci_disable_msix(dev);
1480 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1481 if (this->region_mask & (1 << i))
1482 pci_release_region(dev, i);
1484 if (this->restore_intx)
1485 pci_intx(dev, this->orig_intx);
1487 if (this->enabled && !this->pinned)
1488 pci_disable_device(dev);
1491 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1493 struct pci_devres *dr, *new_dr;
1495 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1499 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1502 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1505 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1507 if (pci_is_managed(pdev))
1508 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1513 * pcim_enable_device - Managed pci_enable_device()
1514 * @pdev: PCI device to be initialized
1516 * Managed pci_enable_device().
1518 int pcim_enable_device(struct pci_dev *pdev)
1520 struct pci_devres *dr;
1523 dr = get_pci_dr(pdev);
1529 rc = pci_enable_device(pdev);
1531 pdev->is_managed = 1;
1536 EXPORT_SYMBOL(pcim_enable_device);
1539 * pcim_pin_device - Pin managed PCI device
1540 * @pdev: PCI device to pin
1542 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1543 * driver detach. @pdev must have been enabled with
1544 * pcim_enable_device().
1546 void pcim_pin_device(struct pci_dev *pdev)
1548 struct pci_devres *dr;
1550 dr = find_pci_dr(pdev);
1551 WARN_ON(!dr || !dr->enabled);
1555 EXPORT_SYMBOL(pcim_pin_device);
1558 * pcibios_add_device - provide arch specific hooks when adding device dev
1559 * @dev: the PCI device being added
1561 * Permits the platform to provide architecture specific functionality when
1562 * devices are added. This is the default implementation. Architecture
1563 * implementations can override this.
1565 int __weak pcibios_add_device(struct pci_dev *dev)
1571 * pcibios_release_device - provide arch specific hooks when releasing device dev
1572 * @dev: the PCI device being released
1574 * Permits the platform to provide architecture specific functionality when
1575 * devices are released. This is the default implementation. Architecture
1576 * implementations can override this.
1578 void __weak pcibios_release_device(struct pci_dev *dev) {}
1581 * pcibios_disable_device - disable arch specific PCI resources for device dev
1582 * @dev: the PCI device to disable
1584 * Disables architecture specific PCI resources for the device. This
1585 * is the default implementation. Architecture implementations can
1588 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1591 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1592 * @irq: ISA IRQ to penalize
1593 * @active: IRQ active or not
1595 * Permits the platform to provide architecture-specific functionality when
1596 * penalizing ISA IRQs. This is the default implementation. Architecture
1597 * implementations can override this.
1599 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1601 static void do_pci_disable_device(struct pci_dev *dev)
1605 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1606 if (pci_command & PCI_COMMAND_MASTER) {
1607 pci_command &= ~PCI_COMMAND_MASTER;
1608 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1611 pcibios_disable_device(dev);
1615 * pci_disable_enabled_device - Disable device without updating enable_cnt
1616 * @dev: PCI device to disable
1618 * NOTE: This function is a backend of PCI power management routines and is
1619 * not supposed to be called drivers.
1621 void pci_disable_enabled_device(struct pci_dev *dev)
1623 if (pci_is_enabled(dev))
1624 do_pci_disable_device(dev);
1628 * pci_disable_device - Disable PCI device after use
1629 * @dev: PCI device to be disabled
1631 * Signal to the system that the PCI device is not in use by the system
1632 * anymore. This only involves disabling PCI bus-mastering, if active.
1634 * Note we don't actually disable the device until all callers of
1635 * pci_enable_device() have called pci_disable_device().
1637 void pci_disable_device(struct pci_dev *dev)
1639 struct pci_devres *dr;
1641 dr = find_pci_dr(dev);
1645 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1646 "disabling already-disabled device");
1648 if (atomic_dec_return(&dev->enable_cnt) != 0)
1651 do_pci_disable_device(dev);
1653 dev->is_busmaster = 0;
1655 EXPORT_SYMBOL(pci_disable_device);
1658 * pcibios_set_pcie_reset_state - set reset state for device dev
1659 * @dev: the PCIe device reset
1660 * @state: Reset state to enter into
1663 * Sets the PCIe reset state for the device. This is the default
1664 * implementation. Architecture implementations can override this.
1666 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1667 enum pcie_reset_state state)
1673 * pci_set_pcie_reset_state - set reset state for device dev
1674 * @dev: the PCIe device reset
1675 * @state: Reset state to enter into
1678 * Sets the PCI reset state for the device.
1680 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1682 return pcibios_set_pcie_reset_state(dev, state);
1684 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1687 * pci_check_pme_status - Check if given device has generated PME.
1688 * @dev: Device to check.
1690 * Check the PME status of the device and if set, clear it and clear PME enable
1691 * (if set). Return 'true' if PME status and PME enable were both set or
1692 * 'false' otherwise.
1694 bool pci_check_pme_status(struct pci_dev *dev)
1703 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1704 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1705 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1708 /* Clear PME status. */
1709 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1710 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1711 /* Disable PME to avoid interrupt flood. */
1712 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1716 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1722 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1723 * @dev: Device to handle.
1724 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1726 * Check if @dev has generated PME and queue a resume request for it in that
1729 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1731 if (pme_poll_reset && dev->pme_poll)
1732 dev->pme_poll = false;
1734 if (pci_check_pme_status(dev)) {
1735 pci_wakeup_event(dev);
1736 pm_request_resume(&dev->dev);
1742 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1743 * @bus: Top bus of the subtree to walk.
1745 void pci_pme_wakeup_bus(struct pci_bus *bus)
1748 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1753 * pci_pme_capable - check the capability of PCI device to generate PME#
1754 * @dev: PCI device to handle.
1755 * @state: PCI state from which device will issue PME#.
1757 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1762 return !!(dev->pme_support & (1 << state));
1764 EXPORT_SYMBOL(pci_pme_capable);
1766 static void pci_pme_list_scan(struct work_struct *work)
1768 struct pci_pme_device *pme_dev, *n;
1770 mutex_lock(&pci_pme_list_mutex);
1771 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1772 if (pme_dev->dev->pme_poll) {
1773 struct pci_dev *bridge;
1775 bridge = pme_dev->dev->bus->self;
1777 * If bridge is in low power state, the
1778 * configuration space of subordinate devices
1779 * may be not accessible
1781 if (bridge && bridge->current_state != PCI_D0)
1784 * If the device is in D3cold it should not be
1787 if (pme_dev->dev->current_state == PCI_D3cold)
1790 pci_pme_wakeup(pme_dev->dev, NULL);
1792 list_del(&pme_dev->list);
1796 if (!list_empty(&pci_pme_list))
1797 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1798 msecs_to_jiffies(PME_TIMEOUT));
1799 mutex_unlock(&pci_pme_list_mutex);
1802 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1806 if (!dev->pme_support)
1809 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1810 /* Clear PME_Status by writing 1 to it and enable PME# */
1811 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1813 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1815 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1819 * pci_pme_restore - Restore PME configuration after config space restore.
1820 * @dev: PCI device to update.
1822 void pci_pme_restore(struct pci_dev *dev)
1826 if (!dev->pme_support)
1829 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1830 if (dev->wakeup_prepared) {
1831 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
1832 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
1834 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1835 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1837 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1841 * pci_pme_active - enable or disable PCI device's PME# function
1842 * @dev: PCI device to handle.
1843 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1845 * The caller must verify that the device is capable of generating PME# before
1846 * calling this function with @enable equal to 'true'.
1848 void pci_pme_active(struct pci_dev *dev, bool enable)
1850 __pci_pme_active(dev, enable);
1853 * PCI (as opposed to PCIe) PME requires that the device have
1854 * its PME# line hooked up correctly. Not all hardware vendors
1855 * do this, so the PME never gets delivered and the device
1856 * remains asleep. The easiest way around this is to
1857 * periodically walk the list of suspended devices and check
1858 * whether any have their PME flag set. The assumption is that
1859 * we'll wake up often enough anyway that this won't be a huge
1860 * hit, and the power savings from the devices will still be a
1863 * Although PCIe uses in-band PME message instead of PME# line
1864 * to report PME, PME does not work for some PCIe devices in
1865 * reality. For example, there are devices that set their PME
1866 * status bits, but don't really bother to send a PME message;
1867 * there are PCI Express Root Ports that don't bother to
1868 * trigger interrupts when they receive PME messages from the
1869 * devices below. So PME poll is used for PCIe devices too.
1872 if (dev->pme_poll) {
1873 struct pci_pme_device *pme_dev;
1875 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1878 dev_warn(&dev->dev, "can't enable PME#\n");
1882 mutex_lock(&pci_pme_list_mutex);
1883 list_add(&pme_dev->list, &pci_pme_list);
1884 if (list_is_singular(&pci_pme_list))
1885 queue_delayed_work(system_freezable_wq,
1887 msecs_to_jiffies(PME_TIMEOUT));
1888 mutex_unlock(&pci_pme_list_mutex);
1890 mutex_lock(&pci_pme_list_mutex);
1891 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1892 if (pme_dev->dev == dev) {
1893 list_del(&pme_dev->list);
1898 mutex_unlock(&pci_pme_list_mutex);
1902 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1904 EXPORT_SYMBOL(pci_pme_active);
1907 * __pci_enable_wake - enable PCI device as wakeup event source
1908 * @dev: PCI device affected
1909 * @state: PCI state from which device will issue wakeup events
1910 * @enable: True to enable event generation; false to disable
1912 * This enables the device as a wakeup event source, or disables it.
1913 * When such events involves platform-specific hooks, those hooks are
1914 * called automatically by this routine.
1916 * Devices with legacy power management (no standard PCI PM capabilities)
1917 * always require such platform hooks.
1920 * 0 is returned on success
1921 * -EINVAL is returned if device is not supposed to wake up the system
1922 * Error code depending on the platform is returned if both the platform and
1923 * the native mechanism fail to enable the generation of wake-up events
1925 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1930 * Bridges can only signal wakeup on behalf of subordinate devices,
1931 * but that is set up elsewhere, so skip them.
1933 if (pci_has_subordinate(dev))
1936 /* Don't do the same thing twice in a row for one device. */
1937 if (!!enable == !!dev->wakeup_prepared)
1941 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1942 * Anderson we should be doing PME# wake enable followed by ACPI wake
1943 * enable. To disable wake-up we call the platform first, for symmetry.
1950 * Enable PME signaling if the device can signal PME from
1951 * D3cold regardless of whether or not it can signal PME from
1952 * the current target state, because that will allow it to
1953 * signal PME when the hierarchy above it goes into D3cold and
1954 * the device itself ends up in D3cold as a result of that.
1956 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
1957 pci_pme_active(dev, true);
1960 error = platform_pci_set_wakeup(dev, true);
1964 dev->wakeup_prepared = true;
1966 platform_pci_set_wakeup(dev, false);
1967 pci_pme_active(dev, false);
1968 dev->wakeup_prepared = false;
1975 * pci_enable_wake - change wakeup settings for a PCI device
1976 * @pci_dev: Target device
1977 * @state: PCI state from which device will issue wakeup events
1978 * @enable: Whether or not to enable event generation
1980 * If @enable is set, check device_may_wakeup() for the device before calling
1981 * __pci_enable_wake() for it.
1983 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
1985 if (enable && !device_may_wakeup(&pci_dev->dev))
1988 return __pci_enable_wake(pci_dev, state, enable);
1990 EXPORT_SYMBOL(pci_enable_wake);
1993 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1994 * @dev: PCI device to prepare
1995 * @enable: True to enable wake-up event generation; false to disable
1997 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1998 * and this function allows them to set that up cleanly - pci_enable_wake()
1999 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2000 * ordering constraints.
2002 * This function only returns error code if the device is not allowed to wake
2003 * up the system from sleep or it is not capable of generating PME# from both
2004 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2006 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2008 return pci_pme_capable(dev, PCI_D3cold) ?
2009 pci_enable_wake(dev, PCI_D3cold, enable) :
2010 pci_enable_wake(dev, PCI_D3hot, enable);
2012 EXPORT_SYMBOL(pci_wake_from_d3);
2015 * pci_target_state - find an appropriate low power state for a given PCI dev
2017 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2019 * Use underlying platform code to find a supported low power state for @dev.
2020 * If the platform can't manage @dev, return the deepest state from which it
2021 * can generate wake events, based on any available PME info.
2023 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2025 pci_power_t target_state = PCI_D3hot;
2027 if (platform_pci_power_manageable(dev)) {
2029 * Call the platform to choose the target state of the device
2030 * and enable wake-up from this state if supported.
2032 pci_power_t state = platform_pci_choose_state(dev);
2035 case PCI_POWER_ERROR:
2040 if (pci_no_d1d2(dev))
2043 target_state = state;
2046 return target_state;
2050 target_state = PCI_D0;
2053 * If the device is in D3cold even though it's not power-manageable by
2054 * the platform, it may have been powered down by non-standard means.
2055 * Best to let it slumber.
2057 if (dev->current_state == PCI_D3cold)
2058 target_state = PCI_D3cold;
2060 if (wakeup && dev->pme_support) {
2061 pci_power_t state = target_state;
2064 * Find the deepest state from which the device can generate
2065 * wake-up events, make it the target state and enable device
2068 while (state && !(dev->pme_support & (1 << state)))
2073 else if (dev->pme_support & 1)
2077 return target_state;
2081 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2082 * @dev: Device to handle.
2084 * Choose the power state appropriate for the device depending on whether
2085 * it can wake up the system and/or is power manageable by the platform
2086 * (PCI_D3hot is the default) and put the device into that state.
2088 int pci_prepare_to_sleep(struct pci_dev *dev)
2090 bool wakeup = device_may_wakeup(&dev->dev);
2091 pci_power_t target_state = pci_target_state(dev, wakeup);
2094 if (target_state == PCI_POWER_ERROR)
2097 pci_enable_wake(dev, target_state, wakeup);
2099 error = pci_set_power_state(dev, target_state);
2102 pci_enable_wake(dev, target_state, false);
2106 EXPORT_SYMBOL(pci_prepare_to_sleep);
2109 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2110 * @dev: Device to handle.
2112 * Disable device's system wake-up capability and put it into D0.
2114 int pci_back_from_sleep(struct pci_dev *dev)
2116 pci_enable_wake(dev, PCI_D0, false);
2117 return pci_set_power_state(dev, PCI_D0);
2119 EXPORT_SYMBOL(pci_back_from_sleep);
2122 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2123 * @dev: PCI device being suspended.
2125 * Prepare @dev to generate wake-up events at run time and put it into a low
2128 int pci_finish_runtime_suspend(struct pci_dev *dev)
2130 pci_power_t target_state;
2133 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2134 if (target_state == PCI_POWER_ERROR)
2137 dev->runtime_d3cold = target_state == PCI_D3cold;
2139 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2141 error = pci_set_power_state(dev, target_state);
2144 pci_enable_wake(dev, target_state, false);
2145 dev->runtime_d3cold = false;
2152 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2153 * @dev: Device to check.
2155 * Return true if the device itself is capable of generating wake-up events
2156 * (through the platform or using the native PCIe PME) or if the device supports
2157 * PME and one of its upstream bridges can generate wake-up events.
2159 bool pci_dev_run_wake(struct pci_dev *dev)
2161 struct pci_bus *bus = dev->bus;
2163 if (!dev->pme_support)
2166 /* PME-capable in principle, but not from the target power state */
2167 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2170 if (device_can_wakeup(&dev->dev))
2173 while (bus->parent) {
2174 struct pci_dev *bridge = bus->self;
2176 if (device_can_wakeup(&bridge->dev))
2182 /* We have reached the root bus. */
2184 return device_can_wakeup(bus->bridge);
2188 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2191 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2192 * @pci_dev: Device to check.
2194 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2195 * reconfigured due to wakeup settings difference between system and runtime
2196 * suspend and the current power state of it is suitable for the upcoming
2197 * (system) transition.
2199 * If the device is not configured for system wakeup, disable PME for it before
2200 * returning 'true' to prevent it from waking up the system unnecessarily.
2202 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2204 struct device *dev = &pci_dev->dev;
2205 bool wakeup = device_may_wakeup(dev);
2207 if (!pm_runtime_suspended(dev)
2208 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2209 || platform_pci_need_resume(pci_dev)
2210 || (pci_dev->dev_flags & PCI_DEV_FLAGS_NEEDS_RESUME))
2214 * At this point the device is good to go unless it's been configured
2215 * to generate PME at the runtime suspend time, but it is not supposed
2216 * to wake up the system. In that case, simply disable PME for it
2217 * (it will have to be re-enabled on exit from system resume).
2219 * If the device's power state is D3cold and the platform check above
2220 * hasn't triggered, the device's configuration is suitable and we don't
2221 * need to manipulate it at all.
2223 spin_lock_irq(&dev->power.lock);
2225 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2227 __pci_pme_active(pci_dev, false);
2229 spin_unlock_irq(&dev->power.lock);
2234 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2235 * @pci_dev: Device to handle.
2237 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2238 * it might have been disabled during the prepare phase of system suspend if
2239 * the device was not configured for system wakeup.
2241 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2243 struct device *dev = &pci_dev->dev;
2245 if (!pci_dev_run_wake(pci_dev))
2248 spin_lock_irq(&dev->power.lock);
2250 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2251 __pci_pme_active(pci_dev, true);
2253 spin_unlock_irq(&dev->power.lock);
2256 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2258 struct device *dev = &pdev->dev;
2259 struct device *parent = dev->parent;
2262 pm_runtime_get_sync(parent);
2263 pm_runtime_get_noresume(dev);
2265 * pdev->current_state is set to PCI_D3cold during suspending,
2266 * so wait until suspending completes
2268 pm_runtime_barrier(dev);
2270 * Only need to resume devices in D3cold, because config
2271 * registers are still accessible for devices suspended but
2274 if (pdev->current_state == PCI_D3cold)
2275 pm_runtime_resume(dev);
2278 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2280 struct device *dev = &pdev->dev;
2281 struct device *parent = dev->parent;
2283 pm_runtime_put(dev);
2285 pm_runtime_put_sync(parent);
2289 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2290 * @bridge: Bridge to check
2292 * This function checks if it is possible to move the bridge to D3.
2293 * Currently we only allow D3 for recent enough PCIe ports.
2295 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2299 if (!pci_is_pcie(bridge))
2302 switch (pci_pcie_type(bridge)) {
2303 case PCI_EXP_TYPE_ROOT_PORT:
2304 case PCI_EXP_TYPE_UPSTREAM:
2305 case PCI_EXP_TYPE_DOWNSTREAM:
2306 if (pci_bridge_d3_disable)
2310 * Hotplug interrupts cannot be delivered if the link is down,
2311 * so parents of a hotplug port must stay awake. In addition,
2312 * hotplug ports handled by firmware in System Management Mode
2313 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2314 * For simplicity, disallow in general for now.
2316 if (bridge->is_hotplug_bridge)
2319 if (pci_bridge_d3_force)
2323 * It should be safe to put PCIe ports from 2015 or newer
2326 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2336 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2338 bool *d3cold_ok = data;
2340 if (/* The device needs to be allowed to go D3cold ... */
2341 dev->no_d3cold || !dev->d3cold_allowed ||
2343 /* ... and if it is wakeup capable to do so from D3cold. */
2344 (device_may_wakeup(&dev->dev) &&
2345 !pci_pme_capable(dev, PCI_D3cold)) ||
2347 /* If it is a bridge it must be allowed to go to D3. */
2348 !pci_power_manageable(dev))
2356 * pci_bridge_d3_update - Update bridge D3 capabilities
2357 * @dev: PCI device which is changed
2359 * Update upstream bridge PM capabilities accordingly depending on if the
2360 * device PM configuration was changed or the device is being removed. The
2361 * change is also propagated upstream.
2363 void pci_bridge_d3_update(struct pci_dev *dev)
2365 bool remove = !device_is_registered(&dev->dev);
2366 struct pci_dev *bridge;
2367 bool d3cold_ok = true;
2369 bridge = pci_upstream_bridge(dev);
2370 if (!bridge || !pci_bridge_d3_possible(bridge))
2374 * If D3 is currently allowed for the bridge, removing one of its
2375 * children won't change that.
2377 if (remove && bridge->bridge_d3)
2381 * If D3 is currently allowed for the bridge and a child is added or
2382 * changed, disallowance of D3 can only be caused by that child, so
2383 * we only need to check that single device, not any of its siblings.
2385 * If D3 is currently not allowed for the bridge, checking the device
2386 * first may allow us to skip checking its siblings.
2389 pci_dev_check_d3cold(dev, &d3cold_ok);
2392 * If D3 is currently not allowed for the bridge, this may be caused
2393 * either by the device being changed/removed or any of its siblings,
2394 * so we need to go through all children to find out if one of them
2395 * continues to block D3.
2397 if (d3cold_ok && !bridge->bridge_d3)
2398 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2401 if (bridge->bridge_d3 != d3cold_ok) {
2402 bridge->bridge_d3 = d3cold_ok;
2403 /* Propagate change to upstream bridges */
2404 pci_bridge_d3_update(bridge);
2409 * pci_d3cold_enable - Enable D3cold for device
2410 * @dev: PCI device to handle
2412 * This function can be used in drivers to enable D3cold from the device
2413 * they handle. It also updates upstream PCI bridge PM capabilities
2416 void pci_d3cold_enable(struct pci_dev *dev)
2418 if (dev->no_d3cold) {
2419 dev->no_d3cold = false;
2420 pci_bridge_d3_update(dev);
2423 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2426 * pci_d3cold_disable - Disable D3cold for device
2427 * @dev: PCI device to handle
2429 * This function can be used in drivers to disable D3cold from the device
2430 * they handle. It also updates upstream PCI bridge PM capabilities
2433 void pci_d3cold_disable(struct pci_dev *dev)
2435 if (!dev->no_d3cold) {
2436 dev->no_d3cold = true;
2437 pci_bridge_d3_update(dev);
2440 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2443 * pci_pm_init - Initialize PM functions of given PCI device
2444 * @dev: PCI device to handle.
2446 void pci_pm_init(struct pci_dev *dev)
2451 pm_runtime_forbid(&dev->dev);
2452 pm_runtime_set_active(&dev->dev);
2453 pm_runtime_enable(&dev->dev);
2454 device_enable_async_suspend(&dev->dev);
2455 dev->wakeup_prepared = false;
2458 dev->pme_support = 0;
2460 /* find PCI PM capability in list */
2461 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2464 /* Check device's ability to generate PME# */
2465 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2467 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2468 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2469 pmc & PCI_PM_CAP_VER_MASK);
2474 dev->d3_delay = PCI_PM_D3_WAIT;
2475 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2476 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2477 dev->d3cold_allowed = true;
2479 dev->d1_support = false;
2480 dev->d2_support = false;
2481 if (!pci_no_d1d2(dev)) {
2482 if (pmc & PCI_PM_CAP_D1)
2483 dev->d1_support = true;
2484 if (pmc & PCI_PM_CAP_D2)
2485 dev->d2_support = true;
2487 if (dev->d1_support || dev->d2_support)
2488 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2489 dev->d1_support ? " D1" : "",
2490 dev->d2_support ? " D2" : "");
2493 pmc &= PCI_PM_CAP_PME_MASK;
2495 dev_printk(KERN_DEBUG, &dev->dev,
2496 "PME# supported from%s%s%s%s%s\n",
2497 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2498 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2499 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2500 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2501 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2502 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2503 dev->pme_poll = true;
2505 * Make device's PM flags reflect the wake-up capability, but
2506 * let the user space enable it to wake up the system as needed.
2508 device_set_wakeup_capable(&dev->dev, true);
2509 /* Disable the PME# generation functionality */
2510 pci_pme_active(dev, false);
2514 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2516 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2520 case PCI_EA_P_VF_MEM:
2521 flags |= IORESOURCE_MEM;
2523 case PCI_EA_P_MEM_PREFETCH:
2524 case PCI_EA_P_VF_MEM_PREFETCH:
2525 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2528 flags |= IORESOURCE_IO;
2537 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2540 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2541 return &dev->resource[bei];
2542 #ifdef CONFIG_PCI_IOV
2543 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2544 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2545 return &dev->resource[PCI_IOV_RESOURCES +
2546 bei - PCI_EA_BEI_VF_BAR0];
2548 else if (bei == PCI_EA_BEI_ROM)
2549 return &dev->resource[PCI_ROM_RESOURCE];
2554 /* Read an Enhanced Allocation (EA) entry */
2555 static int pci_ea_read(struct pci_dev *dev, int offset)
2557 struct resource *res;
2558 int ent_size, ent_offset = offset;
2559 resource_size_t start, end;
2560 unsigned long flags;
2561 u32 dw0, bei, base, max_offset;
2563 bool support_64 = (sizeof(resource_size_t) >= 8);
2565 pci_read_config_dword(dev, ent_offset, &dw0);
2568 /* Entry size field indicates DWORDs after 1st */
2569 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2571 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2574 bei = (dw0 & PCI_EA_BEI) >> 4;
2575 prop = (dw0 & PCI_EA_PP) >> 8;
2578 * If the Property is in the reserved range, try the Secondary
2581 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2582 prop = (dw0 & PCI_EA_SP) >> 16;
2583 if (prop > PCI_EA_P_BRIDGE_IO)
2586 res = pci_ea_get_resource(dev, bei, prop);
2588 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2592 flags = pci_ea_flags(dev, prop);
2594 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2599 pci_read_config_dword(dev, ent_offset, &base);
2600 start = (base & PCI_EA_FIELD_MASK);
2603 /* Read MaxOffset */
2604 pci_read_config_dword(dev, ent_offset, &max_offset);
2607 /* Read Base MSBs (if 64-bit entry) */
2608 if (base & PCI_EA_IS_64) {
2611 pci_read_config_dword(dev, ent_offset, &base_upper);
2614 flags |= IORESOURCE_MEM_64;
2616 /* entry starts above 32-bit boundary, can't use */
2617 if (!support_64 && base_upper)
2621 start |= ((u64)base_upper << 32);
2624 end = start + (max_offset | 0x03);
2626 /* Read MaxOffset MSBs (if 64-bit entry) */
2627 if (max_offset & PCI_EA_IS_64) {
2628 u32 max_offset_upper;
2630 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2633 flags |= IORESOURCE_MEM_64;
2635 /* entry too big, can't use */
2636 if (!support_64 && max_offset_upper)
2640 end += ((u64)max_offset_upper << 32);
2644 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2648 if (ent_size != ent_offset - offset) {
2650 "EA Entry Size (%d) does not match length read (%d)\n",
2651 ent_size, ent_offset - offset);
2655 res->name = pci_name(dev);
2660 if (bei <= PCI_EA_BEI_BAR5)
2661 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2663 else if (bei == PCI_EA_BEI_ROM)
2664 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2666 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2667 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2668 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2670 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2674 return offset + ent_size;
2677 /* Enhanced Allocation Initialization */
2678 void pci_ea_init(struct pci_dev *dev)
2685 /* find PCI EA capability in list */
2686 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2690 /* determine the number of entries */
2691 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2693 num_ent &= PCI_EA_NUM_ENT_MASK;
2695 offset = ea + PCI_EA_FIRST_ENT;
2697 /* Skip DWORD 2 for type 1 functions */
2698 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2701 /* parse each EA entry */
2702 for (i = 0; i < num_ent; ++i)
2703 offset = pci_ea_read(dev, offset);
2706 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2707 struct pci_cap_saved_state *new_cap)
2709 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2713 * _pci_add_cap_save_buffer - allocate buffer for saving given
2714 * capability registers
2715 * @dev: the PCI device
2716 * @cap: the capability to allocate the buffer for
2717 * @extended: Standard or Extended capability ID
2718 * @size: requested size of the buffer
2720 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2721 bool extended, unsigned int size)
2724 struct pci_cap_saved_state *save_state;
2727 pos = pci_find_ext_capability(dev, cap);
2729 pos = pci_find_capability(dev, cap);
2734 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2738 save_state->cap.cap_nr = cap;
2739 save_state->cap.cap_extended = extended;
2740 save_state->cap.size = size;
2741 pci_add_saved_cap(dev, save_state);
2746 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2748 return _pci_add_cap_save_buffer(dev, cap, false, size);
2751 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2753 return _pci_add_cap_save_buffer(dev, cap, true, size);
2757 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2758 * @dev: the PCI device
2760 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2764 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2765 PCI_EXP_SAVE_REGS * sizeof(u16));
2768 "unable to preallocate PCI Express save buffer\n");
2770 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2773 "unable to preallocate PCI-X save buffer\n");
2775 pci_allocate_vc_save_buffers(dev);
2778 void pci_free_cap_save_buffers(struct pci_dev *dev)
2780 struct pci_cap_saved_state *tmp;
2781 struct hlist_node *n;
2783 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2788 * pci_configure_ari - enable or disable ARI forwarding
2789 * @dev: the PCI device
2791 * If @dev and its upstream bridge both support ARI, enable ARI in the
2792 * bridge. Otherwise, disable ARI in the bridge.
2794 void pci_configure_ari(struct pci_dev *dev)
2797 struct pci_dev *bridge;
2799 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2802 bridge = dev->bus->self;
2806 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2807 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2810 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2811 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2812 PCI_EXP_DEVCTL2_ARI);
2813 bridge->ari_enabled = 1;
2815 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2816 PCI_EXP_DEVCTL2_ARI);
2817 bridge->ari_enabled = 0;
2821 static int pci_acs_enable;
2824 * pci_request_acs - ask for ACS to be enabled if supported
2826 void pci_request_acs(void)
2832 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2833 * @dev: the PCI device
2835 static void pci_std_enable_acs(struct pci_dev *dev)
2841 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2845 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2846 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2848 /* Source Validation */
2849 ctrl |= (cap & PCI_ACS_SV);
2851 /* P2P Request Redirect */
2852 ctrl |= (cap & PCI_ACS_RR);
2854 /* P2P Completion Redirect */
2855 ctrl |= (cap & PCI_ACS_CR);
2857 /* Upstream Forwarding */
2858 ctrl |= (cap & PCI_ACS_UF);
2860 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2864 * pci_enable_acs - enable ACS if hardware support it
2865 * @dev: the PCI device
2867 void pci_enable_acs(struct pci_dev *dev)
2869 if (!pci_acs_enable)
2872 if (!pci_dev_specific_enable_acs(dev))
2875 pci_std_enable_acs(dev);
2878 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2883 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2888 * Except for egress control, capabilities are either required
2889 * or only required if controllable. Features missing from the
2890 * capability field can therefore be assumed as hard-wired enabled.
2892 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2893 acs_flags &= (cap | PCI_ACS_EC);
2895 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2896 return (ctrl & acs_flags) == acs_flags;
2900 * pci_acs_enabled - test ACS against required flags for a given device
2901 * @pdev: device to test
2902 * @acs_flags: required PCI ACS flags
2904 * Return true if the device supports the provided flags. Automatically
2905 * filters out flags that are not implemented on multifunction devices.
2907 * Note that this interface checks the effective ACS capabilities of the
2908 * device rather than the actual capabilities. For instance, most single
2909 * function endpoints are not required to support ACS because they have no
2910 * opportunity for peer-to-peer access. We therefore return 'true'
2911 * regardless of whether the device exposes an ACS capability. This makes
2912 * it much easier for callers of this function to ignore the actual type
2913 * or topology of the device when testing ACS support.
2915 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2919 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2924 * Conventional PCI and PCI-X devices never support ACS, either
2925 * effectively or actually. The shared bus topology implies that
2926 * any device on the bus can receive or snoop DMA.
2928 if (!pci_is_pcie(pdev))
2931 switch (pci_pcie_type(pdev)) {
2933 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2934 * but since their primary interface is PCI/X, we conservatively
2935 * handle them as we would a non-PCIe device.
2937 case PCI_EXP_TYPE_PCIE_BRIDGE:
2939 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2940 * applicable... must never implement an ACS Extended Capability...".
2941 * This seems arbitrary, but we take a conservative interpretation
2942 * of this statement.
2944 case PCI_EXP_TYPE_PCI_BRIDGE:
2945 case PCI_EXP_TYPE_RC_EC:
2948 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2949 * implement ACS in order to indicate their peer-to-peer capabilities,
2950 * regardless of whether they are single- or multi-function devices.
2952 case PCI_EXP_TYPE_DOWNSTREAM:
2953 case PCI_EXP_TYPE_ROOT_PORT:
2954 return pci_acs_flags_enabled(pdev, acs_flags);
2956 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2957 * implemented by the remaining PCIe types to indicate peer-to-peer
2958 * capabilities, but only when they are part of a multifunction
2959 * device. The footnote for section 6.12 indicates the specific
2960 * PCIe types included here.
2962 case PCI_EXP_TYPE_ENDPOINT:
2963 case PCI_EXP_TYPE_UPSTREAM:
2964 case PCI_EXP_TYPE_LEG_END:
2965 case PCI_EXP_TYPE_RC_END:
2966 if (!pdev->multifunction)
2969 return pci_acs_flags_enabled(pdev, acs_flags);
2973 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2974 * to single function devices with the exception of downstream ports.
2980 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2981 * @start: starting downstream device
2982 * @end: ending upstream device or NULL to search to the root bus
2983 * @acs_flags: required flags
2985 * Walk up a device tree from start to end testing PCI ACS support. If
2986 * any step along the way does not support the required flags, return false.
2988 bool pci_acs_path_enabled(struct pci_dev *start,
2989 struct pci_dev *end, u16 acs_flags)
2991 struct pci_dev *pdev, *parent = start;
2996 if (!pci_acs_enabled(pdev, acs_flags))
2999 if (pci_is_root_bus(pdev->bus))
3000 return (end == NULL);
3002 parent = pdev->bus->self;
3003 } while (pdev != end);
3009 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3010 * @dev: the PCI device
3011 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3013 * Perform INTx swizzling for a device behind one level of bridge. This is
3014 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3015 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3016 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3017 * the PCI Express Base Specification, Revision 2.1)
3019 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3023 if (pci_ari_enabled(dev->bus))
3026 slot = PCI_SLOT(dev->devfn);
3028 return (((pin - 1) + slot) % 4) + 1;
3031 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3039 while (!pci_is_root_bus(dev->bus)) {
3040 pin = pci_swizzle_interrupt_pin(dev, pin);
3041 dev = dev->bus->self;
3048 * pci_common_swizzle - swizzle INTx all the way to root bridge
3049 * @dev: the PCI device
3050 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3052 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3053 * bridges all the way up to a PCI root bus.
3055 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3059 while (!pci_is_root_bus(dev->bus)) {
3060 pin = pci_swizzle_interrupt_pin(dev, pin);
3061 dev = dev->bus->self;
3064 return PCI_SLOT(dev->devfn);
3066 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3069 * pci_release_region - Release a PCI bar
3070 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3071 * @bar: BAR to release
3073 * Releases the PCI I/O and memory resources previously reserved by a
3074 * successful call to pci_request_region. Call this function only
3075 * after all use of the PCI regions has ceased.
3077 void pci_release_region(struct pci_dev *pdev, int bar)
3079 struct pci_devres *dr;
3081 if (pci_resource_len(pdev, bar) == 0)
3083 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3084 release_region(pci_resource_start(pdev, bar),
3085 pci_resource_len(pdev, bar));
3086 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3087 release_mem_region(pci_resource_start(pdev, bar),
3088 pci_resource_len(pdev, bar));
3090 dr = find_pci_dr(pdev);
3092 dr->region_mask &= ~(1 << bar);
3094 EXPORT_SYMBOL(pci_release_region);
3097 * __pci_request_region - Reserved PCI I/O and memory resource
3098 * @pdev: PCI device whose resources are to be reserved
3099 * @bar: BAR to be reserved
3100 * @res_name: Name to be associated with resource.
3101 * @exclusive: whether the region access is exclusive or not
3103 * Mark the PCI region associated with PCI device @pdev BR @bar as
3104 * being reserved by owner @res_name. Do not access any
3105 * address inside the PCI regions unless this call returns
3108 * If @exclusive is set, then the region is marked so that userspace
3109 * is explicitly not allowed to map the resource via /dev/mem or
3110 * sysfs MMIO access.
3112 * Returns 0 on success, or %EBUSY on error. A warning
3113 * message is also printed on failure.
3115 static int __pci_request_region(struct pci_dev *pdev, int bar,
3116 const char *res_name, int exclusive)
3118 struct pci_devres *dr;
3120 if (pci_resource_len(pdev, bar) == 0)
3123 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3124 if (!request_region(pci_resource_start(pdev, bar),
3125 pci_resource_len(pdev, bar), res_name))
3127 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3128 if (!__request_mem_region(pci_resource_start(pdev, bar),
3129 pci_resource_len(pdev, bar), res_name,
3134 dr = find_pci_dr(pdev);
3136 dr->region_mask |= 1 << bar;
3141 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
3142 &pdev->resource[bar]);
3147 * pci_request_region - Reserve PCI I/O and memory resource
3148 * @pdev: PCI device whose resources are to be reserved
3149 * @bar: BAR to be reserved
3150 * @res_name: Name to be associated with resource
3152 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3153 * being reserved by owner @res_name. Do not access any
3154 * address inside the PCI regions unless this call returns
3157 * Returns 0 on success, or %EBUSY on error. A warning
3158 * message is also printed on failure.
3160 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3162 return __pci_request_region(pdev, bar, res_name, 0);
3164 EXPORT_SYMBOL(pci_request_region);
3167 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3168 * @pdev: PCI device whose resources are to be reserved
3169 * @bar: BAR to be reserved
3170 * @res_name: Name to be associated with resource.
3172 * Mark the PCI region associated with PCI device @pdev BR @bar as
3173 * being reserved by owner @res_name. Do not access any
3174 * address inside the PCI regions unless this call returns
3177 * Returns 0 on success, or %EBUSY on error. A warning
3178 * message is also printed on failure.
3180 * The key difference that _exclusive makes it that userspace is
3181 * explicitly not allowed to map the resource via /dev/mem or
3184 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3185 const char *res_name)
3187 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3189 EXPORT_SYMBOL(pci_request_region_exclusive);
3192 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3193 * @pdev: PCI device whose resources were previously reserved
3194 * @bars: Bitmask of BARs to be released
3196 * Release selected PCI I/O and memory resources previously reserved.
3197 * Call this function only after all use of the PCI regions has ceased.
3199 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3203 for (i = 0; i < 6; i++)
3204 if (bars & (1 << i))
3205 pci_release_region(pdev, i);
3207 EXPORT_SYMBOL(pci_release_selected_regions);
3209 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3210 const char *res_name, int excl)
3214 for (i = 0; i < 6; i++)
3215 if (bars & (1 << i))
3216 if (__pci_request_region(pdev, i, res_name, excl))
3222 if (bars & (1 << i))
3223 pci_release_region(pdev, i);
3230 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3231 * @pdev: PCI device whose resources are to be reserved
3232 * @bars: Bitmask of BARs to be requested
3233 * @res_name: Name to be associated with resource
3235 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3236 const char *res_name)
3238 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3240 EXPORT_SYMBOL(pci_request_selected_regions);
3242 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3243 const char *res_name)
3245 return __pci_request_selected_regions(pdev, bars, res_name,
3246 IORESOURCE_EXCLUSIVE);
3248 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3251 * pci_release_regions - Release reserved PCI I/O and memory resources
3252 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3254 * Releases all PCI I/O and memory resources previously reserved by a
3255 * successful call to pci_request_regions. Call this function only
3256 * after all use of the PCI regions has ceased.
3259 void pci_release_regions(struct pci_dev *pdev)
3261 pci_release_selected_regions(pdev, (1 << 6) - 1);
3263 EXPORT_SYMBOL(pci_release_regions);
3266 * pci_request_regions - Reserved PCI I/O and memory resources
3267 * @pdev: PCI device whose resources are to be reserved
3268 * @res_name: Name to be associated with resource.
3270 * Mark all PCI regions associated with PCI device @pdev as
3271 * being reserved by owner @res_name. Do not access any
3272 * address inside the PCI regions unless this call returns
3275 * Returns 0 on success, or %EBUSY on error. A warning
3276 * message is also printed on failure.
3278 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3280 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3282 EXPORT_SYMBOL(pci_request_regions);
3285 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3286 * @pdev: PCI device whose resources are to be reserved
3287 * @res_name: Name to be associated with resource.
3289 * Mark all PCI regions associated with PCI device @pdev as
3290 * being reserved by owner @res_name. Do not access any
3291 * address inside the PCI regions unless this call returns
3294 * pci_request_regions_exclusive() will mark the region so that
3295 * /dev/mem and the sysfs MMIO access will not be allowed.
3297 * Returns 0 on success, or %EBUSY on error. A warning
3298 * message is also printed on failure.
3300 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3302 return pci_request_selected_regions_exclusive(pdev,
3303 ((1 << 6) - 1), res_name);
3305 EXPORT_SYMBOL(pci_request_regions_exclusive);
3309 struct list_head list;
3311 resource_size_t size;
3314 static LIST_HEAD(io_range_list);
3315 static DEFINE_SPINLOCK(io_range_lock);
3319 * Record the PCI IO range (expressed as CPU physical address + size).
3320 * Return a negative value if an error has occured, zero otherwise
3322 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3327 struct io_range *range;
3328 resource_size_t allocated_size = 0;
3330 /* check if the range hasn't been previously recorded */
3331 spin_lock(&io_range_lock);
3332 list_for_each_entry(range, &io_range_list, list) {
3333 if (addr >= range->start && addr + size <= range->start + size) {
3334 /* range already registered, bail out */
3337 allocated_size += range->size;
3340 /* range not registed yet, check for available space */
3341 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3342 /* if it's too big check if 64K space can be reserved */
3343 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3349 pr_warn("Requested IO range too big, new size set to 64K\n");
3352 /* add the range to the list */
3353 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3359 range->start = addr;
3362 list_add_tail(&range->list, &io_range_list);
3365 spin_unlock(&io_range_lock);
3371 phys_addr_t pci_pio_to_address(unsigned long pio)
3373 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3376 struct io_range *range;
3377 resource_size_t allocated_size = 0;
3379 if (pio > IO_SPACE_LIMIT)
3382 spin_lock(&io_range_lock);
3383 list_for_each_entry(range, &io_range_list, list) {
3384 if (pio >= allocated_size && pio < allocated_size + range->size) {
3385 address = range->start + pio - allocated_size;
3388 allocated_size += range->size;
3390 spin_unlock(&io_range_lock);
3396 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3399 struct io_range *res;
3400 resource_size_t offset = 0;
3401 unsigned long addr = -1;
3403 spin_lock(&io_range_lock);
3404 list_for_each_entry(res, &io_range_list, list) {
3405 if (address >= res->start && address < res->start + res->size) {
3406 addr = address - res->start + offset;
3409 offset += res->size;
3411 spin_unlock(&io_range_lock);
3415 if (address > IO_SPACE_LIMIT)
3416 return (unsigned long)-1;
3418 return (unsigned long) address;
3423 * pci_remap_iospace - Remap the memory mapped I/O space
3424 * @res: Resource describing the I/O space
3425 * @phys_addr: physical address of range to be mapped
3427 * Remap the memory mapped I/O space described by the @res
3428 * and the CPU physical address @phys_addr into virtual address space.
3429 * Only architectures that have memory mapped IO functions defined
3430 * (and the PCI_IOBASE value defined) should call this function.
3432 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3434 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3435 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3437 if (!(res->flags & IORESOURCE_IO))
3440 if (res->end > IO_SPACE_LIMIT)
3443 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3444 pgprot_device(PAGE_KERNEL));
3446 /* this architecture does not have memory mapped I/O space,
3447 so this function should never be called */
3448 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3452 EXPORT_SYMBOL(pci_remap_iospace);
3455 * pci_unmap_iospace - Unmap the memory mapped I/O space
3456 * @res: resource to be unmapped
3458 * Unmap the CPU virtual address @res from virtual address space.
3459 * Only architectures that have memory mapped IO functions defined
3460 * (and the PCI_IOBASE value defined) should call this function.
3462 void pci_unmap_iospace(struct resource *res)
3464 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3465 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3467 unmap_kernel_range(vaddr, resource_size(res));
3470 EXPORT_SYMBOL(pci_unmap_iospace);
3472 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
3474 struct resource **res = ptr;
3476 pci_unmap_iospace(*res);
3480 * devm_pci_remap_iospace - Managed pci_remap_iospace()
3481 * @dev: Generic device to remap IO address for
3482 * @res: Resource describing the I/O space
3483 * @phys_addr: physical address of range to be mapped
3485 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
3488 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
3489 phys_addr_t phys_addr)
3491 const struct resource **ptr;
3494 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
3498 error = pci_remap_iospace(res, phys_addr);
3503 devres_add(dev, ptr);
3508 EXPORT_SYMBOL(devm_pci_remap_iospace);
3511 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3512 * @dev: Generic device to remap IO address for
3513 * @offset: Resource address to map
3514 * @size: Size of map
3516 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3519 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3520 resource_size_t offset,
3521 resource_size_t size)
3523 void __iomem **ptr, *addr;
3525 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3529 addr = pci_remap_cfgspace(offset, size);
3532 devres_add(dev, ptr);
3538 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3541 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3542 * @dev: generic device to handle the resource for
3543 * @res: configuration space resource to be handled
3545 * Checks that a resource is a valid memory region, requests the memory
3546 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3547 * proper PCI configuration space memory attributes are guaranteed.
3549 * All operations are managed and will be undone on driver detach.
3551 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3552 * on failure. Usage example:
3554 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3555 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3557 * return PTR_ERR(base);
3559 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3560 struct resource *res)
3562 resource_size_t size;
3564 void __iomem *dest_ptr;
3568 if (!res || resource_type(res) != IORESOURCE_MEM) {
3569 dev_err(dev, "invalid resource\n");
3570 return IOMEM_ERR_PTR(-EINVAL);
3573 size = resource_size(res);
3574 name = res->name ?: dev_name(dev);
3576 if (!devm_request_mem_region(dev, res->start, size, name)) {
3577 dev_err(dev, "can't request region for resource %pR\n", res);
3578 return IOMEM_ERR_PTR(-EBUSY);
3581 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3583 dev_err(dev, "ioremap failed for resource %pR\n", res);
3584 devm_release_mem_region(dev, res->start, size);
3585 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3590 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3592 static void __pci_set_master(struct pci_dev *dev, bool enable)
3596 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3598 cmd = old_cmd | PCI_COMMAND_MASTER;
3600 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3601 if (cmd != old_cmd) {
3602 dev_dbg(&dev->dev, "%s bus mastering\n",
3603 enable ? "enabling" : "disabling");
3604 pci_write_config_word(dev, PCI_COMMAND, cmd);
3606 dev->is_busmaster = enable;
3610 * pcibios_setup - process "pci=" kernel boot arguments
3611 * @str: string used to pass in "pci=" kernel boot arguments
3613 * Process kernel boot arguments. This is the default implementation.
3614 * Architecture specific implementations can override this as necessary.
3616 char * __weak __init pcibios_setup(char *str)
3622 * pcibios_set_master - enable PCI bus-mastering for device dev
3623 * @dev: the PCI device to enable
3625 * Enables PCI bus-mastering for the device. This is the default
3626 * implementation. Architecture specific implementations can override
3627 * this if necessary.
3629 void __weak pcibios_set_master(struct pci_dev *dev)
3633 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3634 if (pci_is_pcie(dev))
3637 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3639 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3640 else if (lat > pcibios_max_latency)
3641 lat = pcibios_max_latency;
3645 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3649 * pci_set_master - enables bus-mastering for device dev
3650 * @dev: the PCI device to enable
3652 * Enables bus-mastering on the device and calls pcibios_set_master()
3653 * to do the needed arch specific settings.
3655 void pci_set_master(struct pci_dev *dev)
3657 __pci_set_master(dev, true);
3658 pcibios_set_master(dev);
3660 EXPORT_SYMBOL(pci_set_master);
3663 * pci_clear_master - disables bus-mastering for device dev
3664 * @dev: the PCI device to disable
3666 void pci_clear_master(struct pci_dev *dev)
3668 __pci_set_master(dev, false);
3670 EXPORT_SYMBOL(pci_clear_master);
3673 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3674 * @dev: the PCI device for which MWI is to be enabled
3676 * Helper function for pci_set_mwi.
3677 * Originally copied from drivers/net/acenic.c.
3678 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3680 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3682 int pci_set_cacheline_size(struct pci_dev *dev)
3686 if (!pci_cache_line_size)
3689 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3690 equal to or multiple of the right value. */
3691 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3692 if (cacheline_size >= pci_cache_line_size &&
3693 (cacheline_size % pci_cache_line_size) == 0)
3696 /* Write the correct value. */
3697 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3699 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3700 if (cacheline_size == pci_cache_line_size)
3703 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3704 pci_cache_line_size << 2);
3708 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3711 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3712 * @dev: the PCI device for which MWI is enabled
3714 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3716 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3718 int pci_set_mwi(struct pci_dev *dev)
3720 #ifdef PCI_DISABLE_MWI
3726 rc = pci_set_cacheline_size(dev);
3730 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3731 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3732 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3733 cmd |= PCI_COMMAND_INVALIDATE;
3734 pci_write_config_word(dev, PCI_COMMAND, cmd);
3739 EXPORT_SYMBOL(pci_set_mwi);
3742 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3743 * @dev: the PCI device for which MWI is enabled
3745 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3746 * Callers are not required to check the return value.
3748 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3750 int pci_try_set_mwi(struct pci_dev *dev)
3752 #ifdef PCI_DISABLE_MWI
3755 return pci_set_mwi(dev);
3758 EXPORT_SYMBOL(pci_try_set_mwi);
3761 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3762 * @dev: the PCI device to disable
3764 * Disables PCI Memory-Write-Invalidate transaction on the device
3766 void pci_clear_mwi(struct pci_dev *dev)
3768 #ifndef PCI_DISABLE_MWI
3771 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3772 if (cmd & PCI_COMMAND_INVALIDATE) {
3773 cmd &= ~PCI_COMMAND_INVALIDATE;
3774 pci_write_config_word(dev, PCI_COMMAND, cmd);
3778 EXPORT_SYMBOL(pci_clear_mwi);
3781 * pci_intx - enables/disables PCI INTx for device dev
3782 * @pdev: the PCI device to operate on
3783 * @enable: boolean: whether to enable or disable PCI INTx
3785 * Enables/disables PCI INTx for device dev
3787 void pci_intx(struct pci_dev *pdev, int enable)
3789 u16 pci_command, new;
3791 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3794 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3796 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3798 if (new != pci_command) {
3799 struct pci_devres *dr;
3801 pci_write_config_word(pdev, PCI_COMMAND, new);
3803 dr = find_pci_dr(pdev);
3804 if (dr && !dr->restore_intx) {
3805 dr->restore_intx = 1;
3806 dr->orig_intx = !enable;
3810 EXPORT_SYMBOL_GPL(pci_intx);
3812 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3814 struct pci_bus *bus = dev->bus;
3815 bool mask_updated = true;
3816 u32 cmd_status_dword;
3817 u16 origcmd, newcmd;
3818 unsigned long flags;
3822 * We do a single dword read to retrieve both command and status.
3823 * Document assumptions that make this possible.
3825 BUILD_BUG_ON(PCI_COMMAND % 4);
3826 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3828 raw_spin_lock_irqsave(&pci_lock, flags);
3830 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3832 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3835 * Check interrupt status register to see whether our device
3836 * triggered the interrupt (when masking) or the next IRQ is
3837 * already pending (when unmasking).
3839 if (mask != irq_pending) {
3840 mask_updated = false;
3844 origcmd = cmd_status_dword;
3845 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3847 newcmd |= PCI_COMMAND_INTX_DISABLE;
3848 if (newcmd != origcmd)
3849 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3852 raw_spin_unlock_irqrestore(&pci_lock, flags);
3854 return mask_updated;
3858 * pci_check_and_mask_intx - mask INTx on pending interrupt
3859 * @dev: the PCI device to operate on
3861 * Check if the device dev has its INTx line asserted, mask it and
3862 * return true in that case. False is returned if no interrupt was
3865 bool pci_check_and_mask_intx(struct pci_dev *dev)
3867 return pci_check_and_set_intx_mask(dev, true);
3869 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3872 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3873 * @dev: the PCI device to operate on
3875 * Check if the device dev has its INTx line asserted, unmask it if not
3876 * and return true. False is returned and the mask remains active if
3877 * there was still an interrupt pending.
3879 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3881 return pci_check_and_set_intx_mask(dev, false);
3883 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3886 * pci_wait_for_pending_transaction - waits for pending transaction
3887 * @dev: the PCI device to operate on
3889 * Return 0 if transaction is pending 1 otherwise.
3891 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3893 if (!pci_is_pcie(dev))
3896 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3897 PCI_EXP_DEVSTA_TRPND);
3899 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3901 static void pci_flr_wait(struct pci_dev *dev)
3903 int delay = 1, timeout = 60000;
3907 * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
3908 * 100ms, but may silently discard requests while the FLR is in
3909 * progress. Wait 100ms before trying to access the device.
3914 * After 100ms, the device should not silently discard config
3915 * requests, but it may still indicate that it needs more time by
3916 * responding to them with CRS completions. The Root Port will
3917 * generally synthesize ~0 data to complete the read (except when
3918 * CRS SV is enabled and the read was for the Vendor ID; in that
3919 * case it synthesizes 0x0001 data).
3921 * Wait for the device to return a non-CRS completion. Read the
3922 * Command register instead of Vendor ID so we don't have to
3923 * contend with the CRS SV value.
3925 pci_read_config_dword(dev, PCI_COMMAND, &id);
3927 if (delay > timeout) {
3928 dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n",
3934 dev_info(&dev->dev, "not ready %dms after FLR; waiting\n",
3939 pci_read_config_dword(dev, PCI_COMMAND, &id);
3943 dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1);
3947 * pcie_has_flr - check if a device supports function level resets
3948 * @dev: device to check
3950 * Returns true if the device advertises support for PCIe function level
3953 static bool pcie_has_flr(struct pci_dev *dev)
3957 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
3960 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3961 return cap & PCI_EXP_DEVCAP_FLR;
3965 * pcie_flr - initiate a PCIe function level reset
3966 * @dev: device to reset
3968 * Initiate a function level reset on @dev. The caller should ensure the
3969 * device supports FLR before calling this function, e.g. by using the
3970 * pcie_has_flr() helper.
3972 void pcie_flr(struct pci_dev *dev)
3974 if (!pci_wait_for_pending_transaction(dev))
3975 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3977 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3980 EXPORT_SYMBOL_GPL(pcie_flr);
3982 static int pci_af_flr(struct pci_dev *dev, int probe)
3987 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3991 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
3994 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3995 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4002 * Wait for Transaction Pending bit to clear. A word-aligned test
4003 * is used, so we use the conrol offset rather than status and shift
4004 * the test bit to match.
4006 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4007 PCI_AF_STATUS_TP << 8))
4008 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4010 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4016 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4017 * @dev: Device to reset.
4018 * @probe: If set, only check if the device can be reset this way.
4020 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4021 * unset, it will be reinitialized internally when going from PCI_D3hot to
4022 * PCI_D0. If that's the case and the device is not in a low-power state
4023 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4025 * NOTE: This causes the caller to sleep for twice the device power transition
4026 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4027 * by default (i.e. unless the @dev's d3_delay field has a different value).
4028 * Moreover, only devices in D0 can be reset by this function.
4030 static int pci_pm_reset(struct pci_dev *dev, int probe)
4034 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4037 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4038 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4044 if (dev->current_state != PCI_D0)
4047 csr &= ~PCI_PM_CTRL_STATE_MASK;
4049 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4050 pci_dev_d3_sleep(dev);
4052 csr &= ~PCI_PM_CTRL_STATE_MASK;
4054 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4055 pci_dev_d3_sleep(dev);
4060 void pci_reset_secondary_bus(struct pci_dev *dev)
4064 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4065 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4066 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4068 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4069 * this to 2ms to ensure that we meet the minimum requirement.
4073 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4074 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4077 * Trhfa for conventional PCI is 2^25 clock cycles.
4078 * Assuming a minimum 33MHz clock this results in a 1s
4079 * delay before we can consider subordinate devices to
4080 * be re-initialized. PCIe has some ways to shorten this,
4081 * but we don't make use of them yet.
4086 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4088 pci_reset_secondary_bus(dev);
4092 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4093 * @dev: Bridge device
4095 * Use the bridge control register to assert reset on the secondary bus.
4096 * Devices on the secondary bus are left in power-on state.
4098 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
4100 pcibios_reset_secondary_bus(dev);
4102 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
4104 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4106 struct pci_dev *pdev;
4108 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4109 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4112 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4119 pci_reset_bridge_secondary_bus(dev->bus->self);
4124 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4128 if (!hotplug || !try_module_get(hotplug->ops->owner))
4131 if (hotplug->ops->reset_slot)
4132 rc = hotplug->ops->reset_slot(hotplug, probe);
4134 module_put(hotplug->ops->owner);
4139 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4141 struct pci_dev *pdev;
4143 if (dev->subordinate || !dev->slot ||
4144 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4147 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4148 if (pdev != dev && pdev->slot == dev->slot)
4151 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4154 static void pci_dev_lock(struct pci_dev *dev)
4156 pci_cfg_access_lock(dev);
4157 /* block PM suspend, driver probe, etc. */
4158 device_lock(&dev->dev);
4161 /* Return 1 on successful lock, 0 on contention */
4162 static int pci_dev_trylock(struct pci_dev *dev)
4164 if (pci_cfg_access_trylock(dev)) {
4165 if (device_trylock(&dev->dev))
4167 pci_cfg_access_unlock(dev);
4173 static void pci_dev_unlock(struct pci_dev *dev)
4175 device_unlock(&dev->dev);
4176 pci_cfg_access_unlock(dev);
4179 static void pci_dev_save_and_disable(struct pci_dev *dev)
4181 const struct pci_error_handlers *err_handler =
4182 dev->driver ? dev->driver->err_handler : NULL;
4185 * dev->driver->err_handler->reset_prepare() is protected against
4186 * races with ->remove() by the device lock, which must be held by
4189 if (err_handler && err_handler->reset_prepare)
4190 err_handler->reset_prepare(dev);
4193 * Wake-up device prior to save. PM registers default to D0 after
4194 * reset and a simple register restore doesn't reliably return
4195 * to a non-D0 state anyway.
4197 pci_set_power_state(dev, PCI_D0);
4199 pci_save_state(dev);
4201 * Disable the device by clearing the Command register, except for
4202 * INTx-disable which is set. This not only disables MMIO and I/O port
4203 * BARs, but also prevents the device from being Bus Master, preventing
4204 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4205 * compliant devices, INTx-disable prevents legacy interrupts.
4207 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4210 static void pci_dev_restore(struct pci_dev *dev)
4212 const struct pci_error_handlers *err_handler =
4213 dev->driver ? dev->driver->err_handler : NULL;
4215 pci_restore_state(dev);
4218 * dev->driver->err_handler->reset_done() is protected against
4219 * races with ->remove() by the device lock, which must be held by
4222 if (err_handler && err_handler->reset_done)
4223 err_handler->reset_done(dev);
4227 * __pci_reset_function - reset a PCI device function
4228 * @dev: PCI device to reset
4230 * Some devices allow an individual function to be reset without affecting
4231 * other functions in the same device. The PCI device must be responsive
4232 * to PCI config space in order to use this function.
4234 * The device function is presumed to be unused when this function is called.
4235 * Resetting the device will make the contents of PCI configuration space
4236 * random, so any caller of this must be prepared to reinitialise the
4237 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4240 * Returns 0 if the device function was successfully reset or negative if the
4241 * device doesn't support resetting a single function.
4243 int __pci_reset_function(struct pci_dev *dev)
4248 ret = __pci_reset_function_locked(dev);
4249 pci_dev_unlock(dev);
4253 EXPORT_SYMBOL_GPL(__pci_reset_function);
4256 * __pci_reset_function_locked - reset a PCI device function while holding
4257 * the @dev mutex lock.
4258 * @dev: PCI device to reset
4260 * Some devices allow an individual function to be reset without affecting
4261 * other functions in the same device. The PCI device must be responsive
4262 * to PCI config space in order to use this function.
4264 * The device function is presumed to be unused and the caller is holding
4265 * the device mutex lock when this function is called.
4266 * Resetting the device will make the contents of PCI configuration space
4267 * random, so any caller of this must be prepared to reinitialise the
4268 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4271 * Returns 0 if the device function was successfully reset or negative if the
4272 * device doesn't support resetting a single function.
4274 int __pci_reset_function_locked(struct pci_dev *dev)
4280 rc = pci_dev_specific_reset(dev, 0);
4283 if (pcie_has_flr(dev)) {
4287 rc = pci_af_flr(dev, 0);
4290 rc = pci_pm_reset(dev, 0);
4293 rc = pci_dev_reset_slot_function(dev, 0);
4296 return pci_parent_bus_reset(dev, 0);
4298 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4301 * pci_probe_reset_function - check whether the device can be safely reset
4302 * @dev: PCI device to reset
4304 * Some devices allow an individual function to be reset without affecting
4305 * other functions in the same device. The PCI device must be responsive
4306 * to PCI config space in order to use this function.
4308 * Returns 0 if the device function can be reset or negative if the
4309 * device doesn't support resetting a single function.
4311 int pci_probe_reset_function(struct pci_dev *dev)
4317 rc = pci_dev_specific_reset(dev, 1);
4320 if (pcie_has_flr(dev))
4322 rc = pci_af_flr(dev, 1);
4325 rc = pci_pm_reset(dev, 1);
4328 rc = pci_dev_reset_slot_function(dev, 1);
4332 return pci_parent_bus_reset(dev, 1);
4336 * pci_reset_function - quiesce and reset a PCI device function
4337 * @dev: PCI device to reset
4339 * Some devices allow an individual function to be reset without affecting
4340 * other functions in the same device. The PCI device must be responsive
4341 * to PCI config space in order to use this function.
4343 * This function does not just reset the PCI portion of a device, but
4344 * clears all the state associated with the device. This function differs
4345 * from __pci_reset_function in that it saves and restores device state
4348 * Returns 0 if the device function was successfully reset or negative if the
4349 * device doesn't support resetting a single function.
4351 int pci_reset_function(struct pci_dev *dev)
4355 rc = pci_probe_reset_function(dev);
4360 pci_dev_save_and_disable(dev);
4362 rc = __pci_reset_function_locked(dev);
4364 pci_dev_restore(dev);
4365 pci_dev_unlock(dev);
4369 EXPORT_SYMBOL_GPL(pci_reset_function);
4372 * pci_reset_function_locked - quiesce and reset a PCI device function
4373 * @dev: PCI device to reset
4375 * Some devices allow an individual function to be reset without affecting
4376 * other functions in the same device. The PCI device must be responsive
4377 * to PCI config space in order to use this function.
4379 * This function does not just reset the PCI portion of a device, but
4380 * clears all the state associated with the device. This function differs
4381 * from __pci_reset_function() in that it saves and restores device state
4382 * over the reset. It also differs from pci_reset_function() in that it
4383 * requires the PCI device lock to be held.
4385 * Returns 0 if the device function was successfully reset or negative if the
4386 * device doesn't support resetting a single function.
4388 int pci_reset_function_locked(struct pci_dev *dev)
4392 rc = pci_probe_reset_function(dev);
4396 pci_dev_save_and_disable(dev);
4398 rc = __pci_reset_function_locked(dev);
4400 pci_dev_restore(dev);
4404 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4407 * pci_try_reset_function - quiesce and reset a PCI device function
4408 * @dev: PCI device to reset
4410 * Same as above, except return -EAGAIN if unable to lock device.
4412 int pci_try_reset_function(struct pci_dev *dev)
4416 rc = pci_probe_reset_function(dev);
4420 if (!pci_dev_trylock(dev))
4423 pci_dev_save_and_disable(dev);
4424 rc = __pci_reset_function_locked(dev);
4425 pci_dev_unlock(dev);
4427 pci_dev_restore(dev);
4430 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4432 /* Do any devices on or below this bus prevent a bus reset? */
4433 static bool pci_bus_resetable(struct pci_bus *bus)
4435 struct pci_dev *dev;
4438 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4441 list_for_each_entry(dev, &bus->devices, bus_list) {
4442 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4443 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4450 /* Lock devices from the top of the tree down */
4451 static void pci_bus_lock(struct pci_bus *bus)
4453 struct pci_dev *dev;
4455 list_for_each_entry(dev, &bus->devices, bus_list) {
4457 if (dev->subordinate)
4458 pci_bus_lock(dev->subordinate);
4462 /* Unlock devices from the bottom of the tree up */
4463 static void pci_bus_unlock(struct pci_bus *bus)
4465 struct pci_dev *dev;
4467 list_for_each_entry(dev, &bus->devices, bus_list) {
4468 if (dev->subordinate)
4469 pci_bus_unlock(dev->subordinate);
4470 pci_dev_unlock(dev);
4474 /* Return 1 on successful lock, 0 on contention */
4475 static int pci_bus_trylock(struct pci_bus *bus)
4477 struct pci_dev *dev;
4479 list_for_each_entry(dev, &bus->devices, bus_list) {
4480 if (!pci_dev_trylock(dev))
4482 if (dev->subordinate) {
4483 if (!pci_bus_trylock(dev->subordinate)) {
4484 pci_dev_unlock(dev);
4492 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4493 if (dev->subordinate)
4494 pci_bus_unlock(dev->subordinate);
4495 pci_dev_unlock(dev);
4500 /* Do any devices on or below this slot prevent a bus reset? */
4501 static bool pci_slot_resetable(struct pci_slot *slot)
4503 struct pci_dev *dev;
4505 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4506 if (!dev->slot || dev->slot != slot)
4508 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4509 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4516 /* Lock devices from the top of the tree down */
4517 static void pci_slot_lock(struct pci_slot *slot)
4519 struct pci_dev *dev;
4521 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4522 if (!dev->slot || dev->slot != slot)
4525 if (dev->subordinate)
4526 pci_bus_lock(dev->subordinate);
4530 /* Unlock devices from the bottom of the tree up */
4531 static void pci_slot_unlock(struct pci_slot *slot)
4533 struct pci_dev *dev;
4535 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4536 if (!dev->slot || dev->slot != slot)
4538 if (dev->subordinate)
4539 pci_bus_unlock(dev->subordinate);
4540 pci_dev_unlock(dev);
4544 /* Return 1 on successful lock, 0 on contention */
4545 static int pci_slot_trylock(struct pci_slot *slot)
4547 struct pci_dev *dev;
4549 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4550 if (!dev->slot || dev->slot != slot)
4552 if (!pci_dev_trylock(dev))
4554 if (dev->subordinate) {
4555 if (!pci_bus_trylock(dev->subordinate)) {
4556 pci_dev_unlock(dev);
4564 list_for_each_entry_continue_reverse(dev,
4565 &slot->bus->devices, bus_list) {
4566 if (!dev->slot || dev->slot != slot)
4568 if (dev->subordinate)
4569 pci_bus_unlock(dev->subordinate);
4570 pci_dev_unlock(dev);
4575 /* Save and disable devices from the top of the tree down */
4576 static void pci_bus_save_and_disable(struct pci_bus *bus)
4578 struct pci_dev *dev;
4580 list_for_each_entry(dev, &bus->devices, bus_list) {
4582 pci_dev_save_and_disable(dev);
4583 pci_dev_unlock(dev);
4584 if (dev->subordinate)
4585 pci_bus_save_and_disable(dev->subordinate);
4590 * Restore devices from top of the tree down - parent bridges need to be
4591 * restored before we can get to subordinate devices.
4593 static void pci_bus_restore(struct pci_bus *bus)
4595 struct pci_dev *dev;
4597 list_for_each_entry(dev, &bus->devices, bus_list) {
4599 pci_dev_restore(dev);
4600 pci_dev_unlock(dev);
4601 if (dev->subordinate)
4602 pci_bus_restore(dev->subordinate);
4606 /* Save and disable devices from the top of the tree down */
4607 static void pci_slot_save_and_disable(struct pci_slot *slot)
4609 struct pci_dev *dev;
4611 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4612 if (!dev->slot || dev->slot != slot)
4614 pci_dev_save_and_disable(dev);
4615 if (dev->subordinate)
4616 pci_bus_save_and_disable(dev->subordinate);
4621 * Restore devices from top of the tree down - parent bridges need to be
4622 * restored before we can get to subordinate devices.
4624 static void pci_slot_restore(struct pci_slot *slot)
4626 struct pci_dev *dev;
4628 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4629 if (!dev->slot || dev->slot != slot)
4631 pci_dev_restore(dev);
4632 if (dev->subordinate)
4633 pci_bus_restore(dev->subordinate);
4637 static int pci_slot_reset(struct pci_slot *slot, int probe)
4641 if (!slot || !pci_slot_resetable(slot))
4645 pci_slot_lock(slot);
4649 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4652 pci_slot_unlock(slot);
4658 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4659 * @slot: PCI slot to probe
4661 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4663 int pci_probe_reset_slot(struct pci_slot *slot)
4665 return pci_slot_reset(slot, 1);
4667 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4670 * pci_reset_slot - reset a PCI slot
4671 * @slot: PCI slot to reset
4673 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4674 * independent of other slots. For instance, some slots may support slot power
4675 * control. In the case of a 1:1 bus to slot architecture, this function may
4676 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4677 * Generally a slot reset should be attempted before a bus reset. All of the
4678 * function of the slot and any subordinate buses behind the slot are reset
4679 * through this function. PCI config space of all devices in the slot and
4680 * behind the slot is saved before and restored after reset.
4682 * Return 0 on success, non-zero on error.
4684 int pci_reset_slot(struct pci_slot *slot)
4688 rc = pci_slot_reset(slot, 1);
4692 pci_slot_save_and_disable(slot);
4694 rc = pci_slot_reset(slot, 0);
4696 pci_slot_restore(slot);
4700 EXPORT_SYMBOL_GPL(pci_reset_slot);
4703 * pci_try_reset_slot - Try to reset a PCI slot
4704 * @slot: PCI slot to reset
4706 * Same as above except return -EAGAIN if the slot cannot be locked
4708 int pci_try_reset_slot(struct pci_slot *slot)
4712 rc = pci_slot_reset(slot, 1);
4716 pci_slot_save_and_disable(slot);
4718 if (pci_slot_trylock(slot)) {
4720 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4721 pci_slot_unlock(slot);
4725 pci_slot_restore(slot);
4729 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4731 static int pci_bus_reset(struct pci_bus *bus, int probe)
4733 if (!bus->self || !pci_bus_resetable(bus))
4743 pci_reset_bridge_secondary_bus(bus->self);
4745 pci_bus_unlock(bus);
4751 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4752 * @bus: PCI bus to probe
4754 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4756 int pci_probe_reset_bus(struct pci_bus *bus)
4758 return pci_bus_reset(bus, 1);
4760 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4763 * pci_reset_bus - reset a PCI bus
4764 * @bus: top level PCI bus to reset
4766 * Do a bus reset on the given bus and any subordinate buses, saving
4767 * and restoring state of all devices.
4769 * Return 0 on success, non-zero on error.
4771 int pci_reset_bus(struct pci_bus *bus)
4775 rc = pci_bus_reset(bus, 1);
4779 pci_bus_save_and_disable(bus);
4781 rc = pci_bus_reset(bus, 0);
4783 pci_bus_restore(bus);
4787 EXPORT_SYMBOL_GPL(pci_reset_bus);
4790 * pci_try_reset_bus - Try to reset a PCI bus
4791 * @bus: top level PCI bus to reset
4793 * Same as above except return -EAGAIN if the bus cannot be locked
4795 int pci_try_reset_bus(struct pci_bus *bus)
4799 rc = pci_bus_reset(bus, 1);
4803 pci_bus_save_and_disable(bus);
4805 if (pci_bus_trylock(bus)) {
4807 pci_reset_bridge_secondary_bus(bus->self);
4808 pci_bus_unlock(bus);
4812 pci_bus_restore(bus);
4816 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4819 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4820 * @dev: PCI device to query
4822 * Returns mmrbc: maximum designed memory read count in bytes
4823 * or appropriate error value.
4825 int pcix_get_max_mmrbc(struct pci_dev *dev)
4830 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4834 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4837 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4839 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4842 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4843 * @dev: PCI device to query
4845 * Returns mmrbc: maximum memory read count in bytes
4846 * or appropriate error value.
4848 int pcix_get_mmrbc(struct pci_dev *dev)
4853 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4857 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4860 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4862 EXPORT_SYMBOL(pcix_get_mmrbc);
4865 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4866 * @dev: PCI device to query
4867 * @mmrbc: maximum memory read count in bytes
4868 * valid values are 512, 1024, 2048, 4096
4870 * If possible sets maximum memory read byte count, some bridges have erratas
4871 * that prevent this.
4873 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4879 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4882 v = ffs(mmrbc) - 10;
4884 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4888 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4891 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4894 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4897 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4899 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4902 cmd &= ~PCI_X_CMD_MAX_READ;
4904 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4909 EXPORT_SYMBOL(pcix_set_mmrbc);
4912 * pcie_get_readrq - get PCI Express read request size
4913 * @dev: PCI device to query
4915 * Returns maximum memory read request in bytes
4916 * or appropriate error value.
4918 int pcie_get_readrq(struct pci_dev *dev)
4922 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4924 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4926 EXPORT_SYMBOL(pcie_get_readrq);
4929 * pcie_set_readrq - set PCI Express maximum memory read request
4930 * @dev: PCI device to query
4931 * @rq: maximum memory read count in bytes
4932 * valid values are 128, 256, 512, 1024, 2048, 4096
4934 * If possible sets maximum memory read request in bytes
4936 int pcie_set_readrq(struct pci_dev *dev, int rq)
4940 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4944 * If using the "performance" PCIe config, we clamp the
4945 * read rq size to the max packet size to prevent the
4946 * host bridge generating requests larger than we can
4949 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4950 int mps = pcie_get_mps(dev);
4956 v = (ffs(rq) - 8) << 12;
4958 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4959 PCI_EXP_DEVCTL_READRQ, v);
4961 EXPORT_SYMBOL(pcie_set_readrq);
4964 * pcie_get_mps - get PCI Express maximum payload size
4965 * @dev: PCI device to query
4967 * Returns maximum payload size in bytes
4969 int pcie_get_mps(struct pci_dev *dev)
4973 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4975 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4977 EXPORT_SYMBOL(pcie_get_mps);
4980 * pcie_set_mps - set PCI Express maximum payload size
4981 * @dev: PCI device to query
4982 * @mps: maximum payload size in bytes
4983 * valid values are 128, 256, 512, 1024, 2048, 4096
4985 * If possible sets maximum payload size
4987 int pcie_set_mps(struct pci_dev *dev, int mps)
4991 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4995 if (v > dev->pcie_mpss)
4999 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5000 PCI_EXP_DEVCTL_PAYLOAD, v);
5002 EXPORT_SYMBOL(pcie_set_mps);
5005 * pcie_get_minimum_link - determine minimum link settings of a PCI device
5006 * @dev: PCI device to query
5007 * @speed: storage for minimum speed
5008 * @width: storage for minimum width
5010 * This function will walk up the PCI device chain and determine the minimum
5011 * link width and speed of the device.
5013 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
5014 enum pcie_link_width *width)
5018 *speed = PCI_SPEED_UNKNOWN;
5019 *width = PCIE_LNK_WIDTH_UNKNOWN;
5023 enum pci_bus_speed next_speed;
5024 enum pcie_link_width next_width;
5026 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5030 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5031 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5032 PCI_EXP_LNKSTA_NLW_SHIFT;
5034 if (next_speed < *speed)
5035 *speed = next_speed;
5037 if (next_width < *width)
5038 *width = next_width;
5040 dev = dev->bus->self;
5045 EXPORT_SYMBOL(pcie_get_minimum_link);
5048 * pci_select_bars - Make BAR mask from the type of resource
5049 * @dev: the PCI device for which BAR mask is made
5050 * @flags: resource type mask to be selected
5052 * This helper routine makes bar mask from the type of resource.
5054 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5057 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5058 if (pci_resource_flags(dev, i) & flags)
5062 EXPORT_SYMBOL(pci_select_bars);
5064 /* Some architectures require additional programming to enable VGA */
5065 static arch_set_vga_state_t arch_set_vga_state;
5067 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5069 arch_set_vga_state = func; /* NULL disables */
5072 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5073 unsigned int command_bits, u32 flags)
5075 if (arch_set_vga_state)
5076 return arch_set_vga_state(dev, decode, command_bits,
5082 * pci_set_vga_state - set VGA decode state on device and parents if requested
5083 * @dev: the PCI device
5084 * @decode: true = enable decoding, false = disable decoding
5085 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5086 * @flags: traverse ancestors and change bridges
5087 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5089 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5090 unsigned int command_bits, u32 flags)
5092 struct pci_bus *bus;
5093 struct pci_dev *bridge;
5097 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5099 /* ARCH specific VGA enables */
5100 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5104 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5105 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5107 cmd |= command_bits;
5109 cmd &= ~command_bits;
5110 pci_write_config_word(dev, PCI_COMMAND, cmd);
5113 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5120 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5123 cmd |= PCI_BRIDGE_CTL_VGA;
5125 cmd &= ~PCI_BRIDGE_CTL_VGA;
5126 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5135 * pci_add_dma_alias - Add a DMA devfn alias for a device
5136 * @dev: the PCI device for which alias is added
5137 * @devfn: alias slot and function
5139 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5140 * It should be called early, preferably as PCI fixup header quirk.
5142 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5144 if (!dev->dma_alias_mask)
5145 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5146 sizeof(long), GFP_KERNEL);
5147 if (!dev->dma_alias_mask) {
5148 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
5152 set_bit(devfn, dev->dma_alias_mask);
5153 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
5154 PCI_SLOT(devfn), PCI_FUNC(devfn));
5157 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5159 return (dev1->dma_alias_mask &&
5160 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5161 (dev2->dma_alias_mask &&
5162 test_bit(dev1->devfn, dev2->dma_alias_mask));
5165 bool pci_device_is_present(struct pci_dev *pdev)
5169 if (pci_dev_is_disconnected(pdev))
5171 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5173 EXPORT_SYMBOL_GPL(pci_device_is_present);
5175 void pci_ignore_hotplug(struct pci_dev *dev)
5177 struct pci_dev *bridge = dev->bus->self;
5179 dev->ignore_hotplug = 1;
5180 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5182 bridge->ignore_hotplug = 1;
5184 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5186 resource_size_t __weak pcibios_default_alignment(void)
5191 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5192 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5193 static DEFINE_SPINLOCK(resource_alignment_lock);
5196 * pci_specified_resource_alignment - get resource alignment specified by user.
5197 * @dev: the PCI device to get
5198 * @resize: whether or not to change resources' size when reassigning alignment
5200 * RETURNS: Resource alignment if it is specified.
5201 * Zero if it is not specified.
5203 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5206 int seg, bus, slot, func, align_order, count;
5207 unsigned short vendor, device, subsystem_vendor, subsystem_device;
5208 resource_size_t align = pcibios_default_alignment();
5211 spin_lock(&resource_alignment_lock);
5212 p = resource_alignment_param;
5215 if (pci_has_flag(PCI_PROBE_ONLY)) {
5217 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5223 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5229 if (strncmp(p, "pci:", 4) == 0) {
5230 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5232 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
5233 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
5234 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5235 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5239 subsystem_vendor = subsystem_device = 0;
5242 if ((!vendor || (vendor == dev->vendor)) &&
5243 (!device || (device == dev->device)) &&
5244 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5245 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5247 if (align_order == -1)
5250 align = 1 << align_order;
5256 if (sscanf(p, "%x:%x:%x.%x%n",
5257 &seg, &bus, &slot, &func, &count) != 4) {
5259 if (sscanf(p, "%x:%x.%x%n",
5260 &bus, &slot, &func, &count) != 3) {
5261 /* Invalid format */
5262 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5268 if (seg == pci_domain_nr(dev->bus) &&
5269 bus == dev->bus->number &&
5270 slot == PCI_SLOT(dev->devfn) &&
5271 func == PCI_FUNC(dev->devfn)) {
5273 if (align_order == -1)
5276 align = 1 << align_order;
5281 if (*p != ';' && *p != ',') {
5282 /* End of param or invalid format */
5288 spin_unlock(&resource_alignment_lock);
5292 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5293 resource_size_t align, bool resize)
5295 struct resource *r = &dev->resource[bar];
5296 resource_size_t size;
5298 if (!(r->flags & IORESOURCE_MEM))
5301 if (r->flags & IORESOURCE_PCI_FIXED) {
5302 dev_info(&dev->dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5303 bar, r, (unsigned long long)align);
5307 size = resource_size(r);
5312 * Increase the alignment of the resource. There are two ways we
5315 * 1) Increase the size of the resource. BARs are aligned on their
5316 * size, so when we reallocate space for this resource, we'll
5317 * allocate it with the larger alignment. This also prevents
5318 * assignment of any other BARs inside the alignment region, so
5319 * if we're requesting page alignment, this means no other BARs
5320 * will share the page.
5322 * The disadvantage is that this makes the resource larger than
5323 * the hardware BAR, which may break drivers that compute things
5324 * based on the resource size, e.g., to find registers at a
5325 * fixed offset before the end of the BAR.
5327 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5328 * set r->start to the desired alignment. By itself this
5329 * doesn't prevent other BARs being put inside the alignment
5330 * region, but if we realign *every* resource of every device in
5331 * the system, none of them will share an alignment region.
5333 * When the user has requested alignment for only some devices via
5334 * the "pci=resource_alignment" argument, "resize" is true and we
5335 * use the first method. Otherwise we assume we're aligning all
5336 * devices and we use the second.
5339 dev_info(&dev->dev, "BAR%d %pR: requesting alignment to %#llx\n",
5340 bar, r, (unsigned long long)align);
5346 r->flags &= ~IORESOURCE_SIZEALIGN;
5347 r->flags |= IORESOURCE_STARTALIGN;
5349 r->end = r->start + size - 1;
5351 r->flags |= IORESOURCE_UNSET;
5355 * This function disables memory decoding and releases memory resources
5356 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5357 * It also rounds up size to specified alignment.
5358 * Later on, the kernel will assign page-aligned memory resource back
5361 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5365 resource_size_t align;
5367 bool resize = false;
5370 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5371 * 3.4.1.11. Their resources are allocated from the space
5372 * described by the VF BARx register in the PF's SR-IOV capability.
5373 * We can't influence their alignment here.
5378 /* check if specified PCI is target device to reassign */
5379 align = pci_specified_resource_alignment(dev, &resize);
5383 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5384 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5386 "Can't reassign resources to host bridge.\n");
5391 "Disabling memory decoding and releasing memory resources.\n");
5392 pci_read_config_word(dev, PCI_COMMAND, &command);
5393 command &= ~PCI_COMMAND_MEMORY;
5394 pci_write_config_word(dev, PCI_COMMAND, command);
5396 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5397 pci_request_resource_alignment(dev, i, align, resize);
5400 * Need to disable bridge's resource window,
5401 * to enable the kernel to reassign new resource
5404 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5405 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5406 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5407 r = &dev->resource[i];
5408 if (!(r->flags & IORESOURCE_MEM))
5410 r->flags |= IORESOURCE_UNSET;
5411 r->end = resource_size(r) - 1;
5414 pci_disable_bridge_window(dev);
5418 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5420 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5421 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5422 spin_lock(&resource_alignment_lock);
5423 strncpy(resource_alignment_param, buf, count);
5424 resource_alignment_param[count] = '\0';
5425 spin_unlock(&resource_alignment_lock);
5429 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5432 spin_lock(&resource_alignment_lock);
5433 count = snprintf(buf, size, "%s", resource_alignment_param);
5434 spin_unlock(&resource_alignment_lock);
5438 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5440 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5443 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5444 const char *buf, size_t count)
5446 return pci_set_resource_alignment_param(buf, count);
5449 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5450 pci_resource_alignment_store);
5452 static int __init pci_resource_alignment_sysfs_init(void)
5454 return bus_create_file(&pci_bus_type,
5455 &bus_attr_resource_alignment);
5457 late_initcall(pci_resource_alignment_sysfs_init);
5459 static void pci_no_domains(void)
5461 #ifdef CONFIG_PCI_DOMAINS
5462 pci_domains_supported = 0;
5466 #ifdef CONFIG_PCI_DOMAINS
5467 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5469 int pci_get_new_domain_nr(void)
5471 return atomic_inc_return(&__domain_nr);
5474 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5475 static int of_pci_bus_find_domain_nr(struct device *parent)
5477 static int use_dt_domains = -1;
5481 domain = of_get_pci_domain_nr(parent->of_node);
5483 * Check DT domain and use_dt_domains values.
5485 * If DT domain property is valid (domain >= 0) and
5486 * use_dt_domains != 0, the DT assignment is valid since this means
5487 * we have not previously allocated a domain number by using
5488 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5489 * 1, to indicate that we have just assigned a domain number from
5492 * If DT domain property value is not valid (ie domain < 0), and we
5493 * have not previously assigned a domain number from DT
5494 * (use_dt_domains != 1) we should assign a domain number by
5497 * pci_get_new_domain_nr()
5499 * API and update the use_dt_domains value to keep track of method we
5500 * are using to assign domain numbers (use_dt_domains = 0).
5502 * All other combinations imply we have a platform that is trying
5503 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5504 * which is a recipe for domain mishandling and it is prevented by
5505 * invalidating the domain value (domain = -1) and printing a
5506 * corresponding error.
5508 if (domain >= 0 && use_dt_domains) {
5510 } else if (domain < 0 && use_dt_domains != 1) {
5512 domain = pci_get_new_domain_nr();
5514 dev_err(parent, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n",
5522 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5524 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5525 acpi_pci_bus_find_domain_nr(bus);
5531 * pci_ext_cfg_avail - can we access extended PCI config space?
5533 * Returns 1 if we can access PCI extended config space (offsets
5534 * greater than 0xff). This is the default implementation. Architecture
5535 * implementations can override this.
5537 int __weak pci_ext_cfg_avail(void)
5542 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5545 EXPORT_SYMBOL(pci_fixup_cardbus);
5547 static int __init pci_setup(char *str)
5550 char *k = strchr(str, ',');
5553 if (*str && (str = pcibios_setup(str)) && *str) {
5554 if (!strcmp(str, "nomsi")) {
5556 } else if (!strcmp(str, "noaer")) {
5558 } else if (!strncmp(str, "realloc=", 8)) {
5559 pci_realloc_get_opt(str + 8);
5560 } else if (!strncmp(str, "realloc", 7)) {
5561 pci_realloc_get_opt("on");
5562 } else if (!strcmp(str, "nodomains")) {
5564 } else if (!strncmp(str, "noari", 5)) {
5565 pcie_ari_disabled = true;
5566 } else if (!strncmp(str, "cbiosize=", 9)) {
5567 pci_cardbus_io_size = memparse(str + 9, &str);
5568 } else if (!strncmp(str, "cbmemsize=", 10)) {
5569 pci_cardbus_mem_size = memparse(str + 10, &str);
5570 } else if (!strncmp(str, "resource_alignment=", 19)) {
5571 pci_set_resource_alignment_param(str + 19,
5573 } else if (!strncmp(str, "ecrc=", 5)) {
5574 pcie_ecrc_get_policy(str + 5);
5575 } else if (!strncmp(str, "hpiosize=", 9)) {
5576 pci_hotplug_io_size = memparse(str + 9, &str);
5577 } else if (!strncmp(str, "hpmemsize=", 10)) {
5578 pci_hotplug_mem_size = memparse(str + 10, &str);
5579 } else if (!strncmp(str, "hpbussize=", 10)) {
5580 pci_hotplug_bus_size =
5581 simple_strtoul(str + 10, &str, 0);
5582 if (pci_hotplug_bus_size > 0xff)
5583 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5584 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5585 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5586 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5587 pcie_bus_config = PCIE_BUS_SAFE;
5588 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5589 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5590 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5591 pcie_bus_config = PCIE_BUS_PEER2PEER;
5592 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5593 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5595 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5603 early_param("pci", pci_setup);