2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
14 #include <linux/of_pci.h>
15 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
21 #include <linux/log2.h>
22 #include <linux/pci-aspm.h>
23 #include <linux/pm_wakeup.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pci_hotplug.h>
28 #include <asm-generic/pci-bridge.h>
29 #include <asm/setup.h>
30 #include <linux/aer.h>
33 const char *pci_power_names[] = {
34 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
36 EXPORT_SYMBOL_GPL(pci_power_names);
38 int isa_dma_bridge_buggy;
39 EXPORT_SYMBOL(isa_dma_bridge_buggy);
42 EXPORT_SYMBOL(pci_pci_problems);
44 unsigned int pci_pm_d3_delay;
46 static void pci_pme_list_scan(struct work_struct *work);
48 static LIST_HEAD(pci_pme_list);
49 static DEFINE_MUTEX(pci_pme_list_mutex);
50 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
52 struct pci_pme_device {
53 struct list_head list;
57 #define PME_TIMEOUT 1000 /* How long between PME checks */
59 static void pci_dev_d3_sleep(struct pci_dev *dev)
61 unsigned int delay = dev->d3_delay;
63 if (delay < pci_pm_d3_delay)
64 delay = pci_pm_d3_delay;
69 #ifdef CONFIG_PCI_DOMAINS
70 int pci_domains_supported = 1;
73 #define DEFAULT_CARDBUS_IO_SIZE (256)
74 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
75 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
76 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
77 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
79 #define DEFAULT_HOTPLUG_IO_SIZE (256)
80 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
81 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
82 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
83 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
85 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
88 * The default CLS is used if arch didn't set CLS explicitly and not
89 * all pci devices agree on the same value. Arch can override either
90 * the dfl or actual value as it sees fit. Don't forget this is
91 * measured in 32-bit words, not bytes.
93 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
94 u8 pci_cache_line_size;
97 * If we set up a device for bus mastering, we need to check the latency
98 * timer as certain BIOSes forget to set it properly.
100 unsigned int pcibios_max_latency = 255;
102 /* If set, the PCIe ARI capability will not be used. */
103 static bool pcie_ari_disabled;
106 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
107 * @bus: pointer to PCI bus structure to search
109 * Given a PCI bus, returns the highest PCI bus number present in the set
110 * including the given PCI bus and its list of child PCI buses.
112 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
115 unsigned char max, n;
117 max = bus->busn_res.end;
118 list_for_each_entry(tmp, &bus->children, node) {
119 n = pci_bus_max_busnr(tmp);
125 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
127 #ifdef CONFIG_HAS_IOMEM
128 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
130 struct resource *res = &pdev->resource[bar];
133 * Make sure the BAR is actually a memory resource, not an IO resource
135 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
136 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
139 return ioremap_nocache(res->start, resource_size(res));
141 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
143 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
146 * Make sure the BAR is actually a memory resource, not an IO resource
148 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
152 return ioremap_wc(pci_resource_start(pdev, bar),
153 pci_resource_len(pdev, bar));
155 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
159 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
160 u8 pos, int cap, int *ttl)
165 pci_bus_read_config_byte(bus, devfn, pos, &pos);
171 pci_bus_read_config_word(bus, devfn, pos, &ent);
183 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
186 int ttl = PCI_FIND_CAP_TTL;
188 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
191 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
193 return __pci_find_next_cap(dev->bus, dev->devfn,
194 pos + PCI_CAP_LIST_NEXT, cap);
196 EXPORT_SYMBOL_GPL(pci_find_next_capability);
198 static int __pci_bus_find_cap_start(struct pci_bus *bus,
199 unsigned int devfn, u8 hdr_type)
203 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
204 if (!(status & PCI_STATUS_CAP_LIST))
208 case PCI_HEADER_TYPE_NORMAL:
209 case PCI_HEADER_TYPE_BRIDGE:
210 return PCI_CAPABILITY_LIST;
211 case PCI_HEADER_TYPE_CARDBUS:
212 return PCI_CB_CAPABILITY_LIST;
219 * pci_find_capability - query for devices' capabilities
220 * @dev: PCI device to query
221 * @cap: capability code
223 * Tell if a device supports a given PCI capability.
224 * Returns the address of the requested capability structure within the
225 * device's PCI configuration space or 0 in case the device does not
226 * support it. Possible values for @cap:
228 * %PCI_CAP_ID_PM Power Management
229 * %PCI_CAP_ID_AGP Accelerated Graphics Port
230 * %PCI_CAP_ID_VPD Vital Product Data
231 * %PCI_CAP_ID_SLOTID Slot Identification
232 * %PCI_CAP_ID_MSI Message Signalled Interrupts
233 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
234 * %PCI_CAP_ID_PCIX PCI-X
235 * %PCI_CAP_ID_EXP PCI Express
237 int pci_find_capability(struct pci_dev *dev, int cap)
241 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
243 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
247 EXPORT_SYMBOL(pci_find_capability);
250 * pci_bus_find_capability - query for devices' capabilities
251 * @bus: the PCI bus to query
252 * @devfn: PCI device to query
253 * @cap: capability code
255 * Like pci_find_capability() but works for pci devices that do not have a
256 * pci_dev structure set up yet.
258 * Returns the address of the requested capability structure within the
259 * device's PCI configuration space or 0 in case the device does not
262 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
267 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
269 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
271 pos = __pci_find_next_cap(bus, devfn, pos, cap);
275 EXPORT_SYMBOL(pci_bus_find_capability);
278 * pci_find_next_ext_capability - Find an extended capability
279 * @dev: PCI device to query
280 * @start: address at which to start looking (0 to start at beginning of list)
281 * @cap: capability code
283 * Returns the address of the next matching extended capability structure
284 * within the device's PCI configuration space or 0 if the device does
285 * not support it. Some capabilities can occur several times, e.g., the
286 * vendor-specific capability, and this provides a way to find them all.
288 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
292 int pos = PCI_CFG_SPACE_SIZE;
294 /* minimum 8 bytes per capability */
295 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
297 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
303 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
307 * If we have no capabilities, this is indicated by cap ID,
308 * cap version and next pointer all being 0.
314 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
317 pos = PCI_EXT_CAP_NEXT(header);
318 if (pos < PCI_CFG_SPACE_SIZE)
321 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
327 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
330 * pci_find_ext_capability - Find an extended capability
331 * @dev: PCI device to query
332 * @cap: capability code
334 * Returns the address of the requested extended capability structure
335 * within the device's PCI configuration space or 0 if the device does
336 * not support it. Possible values for @cap:
338 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
339 * %PCI_EXT_CAP_ID_VC Virtual Channel
340 * %PCI_EXT_CAP_ID_DSN Device Serial Number
341 * %PCI_EXT_CAP_ID_PWR Power Budgeting
343 int pci_find_ext_capability(struct pci_dev *dev, int cap)
345 return pci_find_next_ext_capability(dev, 0, cap);
347 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
349 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
351 int rc, ttl = PCI_FIND_CAP_TTL;
354 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
355 mask = HT_3BIT_CAP_MASK;
357 mask = HT_5BIT_CAP_MASK;
359 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
360 PCI_CAP_ID_HT, &ttl);
362 rc = pci_read_config_byte(dev, pos + 3, &cap);
363 if (rc != PCIBIOS_SUCCESSFUL)
366 if ((cap & mask) == ht_cap)
369 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
370 pos + PCI_CAP_LIST_NEXT,
371 PCI_CAP_ID_HT, &ttl);
377 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
378 * @dev: PCI device to query
379 * @pos: Position from which to continue searching
380 * @ht_cap: Hypertransport capability code
382 * To be used in conjunction with pci_find_ht_capability() to search for
383 * all capabilities matching @ht_cap. @pos should always be a value returned
384 * from pci_find_ht_capability().
386 * NB. To be 100% safe against broken PCI devices, the caller should take
387 * steps to avoid an infinite loop.
389 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
391 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
393 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
396 * pci_find_ht_capability - query a device's Hypertransport capabilities
397 * @dev: PCI device to query
398 * @ht_cap: Hypertransport capability code
400 * Tell if a device supports a given Hypertransport capability.
401 * Returns an address within the device's PCI configuration space
402 * or 0 in case the device does not support the request capability.
403 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
404 * which has a Hypertransport capability matching @ht_cap.
406 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
410 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
412 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
416 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
419 * pci_find_parent_resource - return resource region of parent bus of given region
420 * @dev: PCI device structure contains resources to be searched
421 * @res: child resource record for which parent is sought
423 * For given resource region of given device, return the resource
424 * region of parent bus the given region is contained in.
426 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
427 struct resource *res)
429 const struct pci_bus *bus = dev->bus;
433 pci_bus_for_each_resource(bus, r, i) {
436 if (res->start && resource_contains(r, res)) {
439 * If the window is prefetchable but the BAR is
440 * not, the allocator made a mistake.
442 if (r->flags & IORESOURCE_PREFETCH &&
443 !(res->flags & IORESOURCE_PREFETCH))
447 * If we're below a transparent bridge, there may
448 * be both a positively-decoded aperture and a
449 * subtractively-decoded region that contain the BAR.
450 * We want the positively-decoded one, so this depends
451 * on pci_bus_for_each_resource() giving us those
459 EXPORT_SYMBOL(pci_find_parent_resource);
462 * pci_find_pcie_root_port - return PCIe Root Port
463 * @dev: PCI device to query
465 * Traverse up the parent chain and return the PCIe Root Port PCI Device
466 * for a given PCI Device.
468 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
470 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
472 bridge = pci_upstream_bridge(dev);
473 while (bridge && pci_is_pcie(bridge)) {
474 highest_pcie_bridge = bridge;
475 bridge = pci_upstream_bridge(bridge);
478 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
481 return highest_pcie_bridge;
483 EXPORT_SYMBOL(pci_find_pcie_root_port);
486 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
487 * @dev: the PCI device to operate on
488 * @pos: config space offset of status word
489 * @mask: mask of bit(s) to care about in status word
491 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
493 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
497 /* Wait for Transaction Pending bit clean */
498 for (i = 0; i < 4; i++) {
501 msleep((1 << (i - 1)) * 100);
503 pci_read_config_word(dev, pos, &status);
504 if (!(status & mask))
512 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
513 * @dev: PCI device to have its BARs restored
515 * Restore the BAR values for a given device, so as to make it
516 * accessible by its driver.
518 static void pci_restore_bars(struct pci_dev *dev)
522 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
523 pci_update_resource(dev, i);
526 static struct pci_platform_pm_ops *pci_platform_pm;
528 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
530 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
533 pci_platform_pm = ops;
537 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
539 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
542 static inline int platform_pci_set_power_state(struct pci_dev *dev,
545 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
548 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
550 return pci_platform_pm ?
551 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
554 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
556 return pci_platform_pm ?
557 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
560 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
562 return pci_platform_pm ?
563 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
566 static inline bool platform_pci_need_resume(struct pci_dev *dev)
568 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
572 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
574 * @dev: PCI device to handle.
575 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
578 * -EINVAL if the requested state is invalid.
579 * -EIO if device does not support PCI PM or its PM capabilities register has a
580 * wrong version, or device doesn't support the requested state.
581 * 0 if device already is in the requested state.
582 * 0 if device's power state has been successfully changed.
584 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
587 bool need_restore = false;
589 /* Check if we're already there */
590 if (dev->current_state == state)
596 if (state < PCI_D0 || state > PCI_D3hot)
599 /* Validate current state:
600 * Can enter D0 from any state, but if we can only go deeper
601 * to sleep if we're already in a low power state
603 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
604 && dev->current_state > state) {
605 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
606 dev->current_state, state);
610 /* check if this device supports the desired state */
611 if ((state == PCI_D1 && !dev->d1_support)
612 || (state == PCI_D2 && !dev->d2_support))
615 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
617 /* If we're (effectively) in D3, force entire word to 0.
618 * This doesn't affect PME_Status, disables PME_En, and
619 * sets PowerState to 0.
621 switch (dev->current_state) {
625 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
630 case PCI_UNKNOWN: /* Boot-up */
631 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
632 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
634 /* Fall-through: force to D0 */
640 /* enter specified state */
641 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
643 /* Mandatory power management transition delays */
644 /* see PCI PM 1.1 5.6.1 table 18 */
645 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
646 pci_dev_d3_sleep(dev);
647 else if (state == PCI_D2 || dev->current_state == PCI_D2)
648 udelay(PCI_PM_D2_DELAY);
650 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
651 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
652 if (dev->current_state != state && printk_ratelimit())
653 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
657 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
658 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
659 * from D3hot to D0 _may_ perform an internal reset, thereby
660 * going to "D0 Uninitialized" rather than "D0 Initialized".
661 * For example, at least some versions of the 3c905B and the
662 * 3c556B exhibit this behaviour.
664 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
665 * devices in a D3hot state at boot. Consequently, we need to
666 * restore at least the BARs so that the device will be
667 * accessible to its driver.
670 pci_restore_bars(dev);
673 pcie_aspm_pm_state_change(dev->bus->self);
679 * pci_update_current_state - Read PCI power state of given device from its
680 * PCI PM registers and cache it
681 * @dev: PCI device to handle.
682 * @state: State to cache in case the device doesn't have the PM capability
684 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
690 * Configuration space is not accessible for device in
691 * D3cold, so just keep or set D3cold for safety
693 if (dev->current_state == PCI_D3cold)
695 if (state == PCI_D3cold) {
696 dev->current_state = PCI_D3cold;
699 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
700 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
702 dev->current_state = state;
707 * pci_platform_power_transition - Use platform to change device power state
708 * @dev: PCI device to handle.
709 * @state: State to put the device into.
711 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
715 if (platform_pci_power_manageable(dev)) {
716 error = platform_pci_set_power_state(dev, state);
718 pci_update_current_state(dev, state);
722 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
723 dev->current_state = PCI_D0;
729 * pci_wakeup - Wake up a PCI device
730 * @pci_dev: Device to handle.
731 * @ign: ignored parameter
733 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
735 pci_wakeup_event(pci_dev);
736 pm_request_resume(&pci_dev->dev);
741 * pci_wakeup_bus - Walk given bus and wake up devices on it
742 * @bus: Top bus of the subtree to walk.
744 static void pci_wakeup_bus(struct pci_bus *bus)
747 pci_walk_bus(bus, pci_wakeup, NULL);
751 * __pci_start_power_transition - Start power transition of a PCI device
752 * @dev: PCI device to handle.
753 * @state: State to put the device into.
755 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
757 if (state == PCI_D0) {
758 pci_platform_power_transition(dev, PCI_D0);
760 * Mandatory power management transition delays, see
761 * PCI Express Base Specification Revision 2.0 Section
762 * 6.6.1: Conventional Reset. Do not delay for
763 * devices powered on/off by corresponding bridge,
764 * because have already delayed for the bridge.
766 if (dev->runtime_d3cold) {
767 msleep(dev->d3cold_delay);
769 * When powering on a bridge from D3cold, the
770 * whole hierarchy may be powered on into
771 * D0uninitialized state, resume them to give
772 * them a chance to suspend again
774 pci_wakeup_bus(dev->subordinate);
780 * __pci_dev_set_current_state - Set current state of a PCI device
781 * @dev: Device to handle
782 * @data: pointer to state to be set
784 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
786 pci_power_t state = *(pci_power_t *)data;
788 dev->current_state = state;
793 * __pci_bus_set_current_state - Walk given bus and set current state of devices
794 * @bus: Top bus of the subtree to walk.
795 * @state: state to be set
797 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
800 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
804 * __pci_complete_power_transition - Complete power transition of a PCI device
805 * @dev: PCI device to handle.
806 * @state: State to put the device into.
808 * This function should not be called directly by device drivers.
810 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
816 ret = pci_platform_power_transition(dev, state);
817 /* Power off the bridge may power off the whole hierarchy */
818 if (!ret && state == PCI_D3cold)
819 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
822 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
825 * pci_set_power_state - Set the power state of a PCI device
826 * @dev: PCI device to handle.
827 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
829 * Transition a device to a new power state, using the platform firmware and/or
830 * the device's PCI PM registers.
833 * -EINVAL if the requested state is invalid.
834 * -EIO if device does not support PCI PM or its PM capabilities register has a
835 * wrong version, or device doesn't support the requested state.
836 * 0 if device already is in the requested state.
837 * 0 if device's power state has been successfully changed.
839 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
843 /* bound the state we're entering */
844 if (state > PCI_D3cold)
846 else if (state < PCI_D0)
848 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
850 * If the device or the parent bridge do not support PCI PM,
851 * ignore the request if we're doing anything other than putting
852 * it into D0 (which would only happen on boot).
856 /* Check if we're already there */
857 if (dev->current_state == state)
860 __pci_start_power_transition(dev, state);
862 /* This device is quirked not to be put into D3, so
863 don't put it in D3 */
864 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
868 * To put device in D3cold, we put device into D3hot in native
869 * way, then put device into D3cold with platform ops
871 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
874 if (!__pci_complete_power_transition(dev, state))
879 EXPORT_SYMBOL(pci_set_power_state);
882 * pci_power_up - Put the given device into D0 forcibly
883 * @dev: PCI device to power up
885 void pci_power_up(struct pci_dev *dev)
887 __pci_start_power_transition(dev, PCI_D0);
888 pci_raw_set_power_state(dev, PCI_D0);
889 pci_update_current_state(dev, PCI_D0);
893 * pci_choose_state - Choose the power state of a PCI device
894 * @dev: PCI device to be suspended
895 * @state: target sleep state for the whole system. This is the value
896 * that is passed to suspend() function.
898 * Returns PCI power state suitable for given device and given system
902 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
909 ret = platform_pci_choose_state(dev);
910 if (ret != PCI_POWER_ERROR)
913 switch (state.event) {
916 case PM_EVENT_FREEZE:
917 case PM_EVENT_PRETHAW:
918 /* REVISIT both freeze and pre-thaw "should" use D0 */
919 case PM_EVENT_SUSPEND:
920 case PM_EVENT_HIBERNATE:
923 dev_info(&dev->dev, "unrecognized suspend event %d\n",
929 EXPORT_SYMBOL(pci_choose_state);
931 #define PCI_EXP_SAVE_REGS 7
933 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
934 u16 cap, bool extended)
936 struct pci_cap_saved_state *tmp;
938 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
939 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
945 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
947 return _pci_find_saved_cap(dev, cap, false);
950 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
952 return _pci_find_saved_cap(dev, cap, true);
955 static int pci_save_pcie_state(struct pci_dev *dev)
958 struct pci_cap_saved_state *save_state;
961 if (!pci_is_pcie(dev))
964 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
966 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
970 cap = (u16 *)&save_state->cap.data[0];
971 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
972 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
973 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
974 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
975 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
976 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
977 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
982 static void pci_restore_pcie_state(struct pci_dev *dev)
985 struct pci_cap_saved_state *save_state;
988 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
992 cap = (u16 *)&save_state->cap.data[0];
993 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
994 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
995 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
996 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
997 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
998 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
999 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1003 static int pci_save_pcix_state(struct pci_dev *dev)
1006 struct pci_cap_saved_state *save_state;
1008 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1012 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1014 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1018 pci_read_config_word(dev, pos + PCI_X_CMD,
1019 (u16 *)save_state->cap.data);
1024 static void pci_restore_pcix_state(struct pci_dev *dev)
1027 struct pci_cap_saved_state *save_state;
1030 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1031 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1032 if (!save_state || !pos)
1034 cap = (u16 *)&save_state->cap.data[0];
1036 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1041 * pci_save_state - save the PCI configuration space of a device before suspending
1042 * @dev: - PCI device that we're dealing with
1044 int pci_save_state(struct pci_dev *dev)
1047 /* XXX: 100% dword access ok here? */
1048 for (i = 0; i < 16; i++)
1049 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1050 dev->state_saved = true;
1052 i = pci_save_pcie_state(dev);
1056 i = pci_save_pcix_state(dev);
1060 return pci_save_vc_state(dev);
1062 EXPORT_SYMBOL(pci_save_state);
1064 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1065 u32 saved_val, int retry, bool force)
1069 pci_read_config_dword(pdev, offset, &val);
1070 if (!force && val == saved_val)
1074 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1075 offset, val, saved_val);
1076 pci_write_config_dword(pdev, offset, saved_val);
1080 pci_read_config_dword(pdev, offset, &val);
1081 if (val == saved_val)
1088 static void pci_restore_config_space_range(struct pci_dev *pdev,
1089 int start, int end, int retry,
1094 for (index = end; index >= start; index--)
1095 pci_restore_config_dword(pdev, 4 * index,
1096 pdev->saved_config_space[index],
1100 static void pci_restore_config_space(struct pci_dev *pdev)
1102 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1103 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1104 /* Restore BARs before the command register. */
1105 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1106 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1107 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1108 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1111 * Force rewriting of prefetch registers to avoid S3 resume
1112 * issues on Intel PCI bridges that occur when these
1113 * registers are not explicitly written.
1115 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1116 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1118 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1123 * pci_restore_state - Restore the saved state of a PCI device
1124 * @dev: - PCI device that we're dealing with
1126 void pci_restore_state(struct pci_dev *dev)
1128 if (!dev->state_saved)
1131 /* PCI Express register must be restored first */
1132 pci_restore_pcie_state(dev);
1133 pci_restore_ats_state(dev);
1134 pci_restore_vc_state(dev);
1136 pci_cleanup_aer_error_status_regs(dev);
1138 pci_restore_config_space(dev);
1140 pci_restore_pcix_state(dev);
1141 pci_restore_msi_state(dev);
1143 /* Restore ACS and IOV configuration state */
1144 pci_enable_acs(dev);
1145 pci_restore_iov_state(dev);
1147 dev->state_saved = false;
1149 EXPORT_SYMBOL(pci_restore_state);
1151 struct pci_saved_state {
1152 u32 config_space[16];
1153 struct pci_cap_saved_data cap[0];
1157 * pci_store_saved_state - Allocate and return an opaque struct containing
1158 * the device saved state.
1159 * @dev: PCI device that we're dealing with
1161 * Return NULL if no state or error.
1163 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1165 struct pci_saved_state *state;
1166 struct pci_cap_saved_state *tmp;
1167 struct pci_cap_saved_data *cap;
1170 if (!dev->state_saved)
1173 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1175 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1176 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1178 state = kzalloc(size, GFP_KERNEL);
1182 memcpy(state->config_space, dev->saved_config_space,
1183 sizeof(state->config_space));
1186 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1187 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1188 memcpy(cap, &tmp->cap, len);
1189 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1191 /* Empty cap_save terminates list */
1195 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1198 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1199 * @dev: PCI device that we're dealing with
1200 * @state: Saved state returned from pci_store_saved_state()
1202 int pci_load_saved_state(struct pci_dev *dev,
1203 struct pci_saved_state *state)
1205 struct pci_cap_saved_data *cap;
1207 dev->state_saved = false;
1212 memcpy(dev->saved_config_space, state->config_space,
1213 sizeof(state->config_space));
1217 struct pci_cap_saved_state *tmp;
1219 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1220 if (!tmp || tmp->cap.size != cap->size)
1223 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1224 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1225 sizeof(struct pci_cap_saved_data) + cap->size);
1228 dev->state_saved = true;
1231 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1234 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1235 * and free the memory allocated for it.
1236 * @dev: PCI device that we're dealing with
1237 * @state: Pointer to saved state returned from pci_store_saved_state()
1239 int pci_load_and_free_saved_state(struct pci_dev *dev,
1240 struct pci_saved_state **state)
1242 int ret = pci_load_saved_state(dev, *state);
1247 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1249 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1251 return pci_enable_resources(dev, bars);
1254 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1257 struct pci_dev *bridge;
1261 err = pci_set_power_state(dev, PCI_D0);
1262 if (err < 0 && err != -EIO)
1265 bridge = pci_upstream_bridge(dev);
1267 pcie_aspm_powersave_config_link(bridge);
1269 err = pcibios_enable_device(dev, bars);
1272 pci_fixup_device(pci_fixup_enable, dev);
1274 if (dev->msi_enabled || dev->msix_enabled)
1277 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1279 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1280 if (cmd & PCI_COMMAND_INTX_DISABLE)
1281 pci_write_config_word(dev, PCI_COMMAND,
1282 cmd & ~PCI_COMMAND_INTX_DISABLE);
1289 * pci_reenable_device - Resume abandoned device
1290 * @dev: PCI device to be resumed
1292 * Note this function is a backend of pci_default_resume and is not supposed
1293 * to be called by normal code, write proper resume handler and use it instead.
1295 int pci_reenable_device(struct pci_dev *dev)
1297 if (pci_is_enabled(dev))
1298 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1301 EXPORT_SYMBOL(pci_reenable_device);
1303 static void pci_enable_bridge(struct pci_dev *dev)
1305 struct pci_dev *bridge;
1308 bridge = pci_upstream_bridge(dev);
1310 pci_enable_bridge(bridge);
1312 if (pci_is_enabled(dev)) {
1313 if (!dev->is_busmaster)
1314 pci_set_master(dev);
1318 retval = pci_enable_device(dev);
1320 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1322 pci_set_master(dev);
1325 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1327 struct pci_dev *bridge;
1332 * Power state could be unknown at this point, either due to a fresh
1333 * boot or a device removal call. So get the current power state
1334 * so that things like MSI message writing will behave as expected
1335 * (e.g. if the device really is in D0 at enable time).
1337 pci_update_current_state(dev, dev->current_state);
1339 if (atomic_inc_return(&dev->enable_cnt) > 1)
1340 return 0; /* already enabled */
1342 bridge = pci_upstream_bridge(dev);
1344 pci_enable_bridge(bridge);
1346 /* only skip sriov related */
1347 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1348 if (dev->resource[i].flags & flags)
1350 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1351 if (dev->resource[i].flags & flags)
1354 err = do_pci_enable_device(dev, bars);
1356 atomic_dec(&dev->enable_cnt);
1361 * pci_enable_device_io - Initialize a device for use with IO space
1362 * @dev: PCI device to be initialized
1364 * Initialize device before it's used by a driver. Ask low-level code
1365 * to enable I/O resources. Wake up the device if it was suspended.
1366 * Beware, this function can fail.
1368 int pci_enable_device_io(struct pci_dev *dev)
1370 return pci_enable_device_flags(dev, IORESOURCE_IO);
1372 EXPORT_SYMBOL(pci_enable_device_io);
1375 * pci_enable_device_mem - Initialize a device for use with Memory space
1376 * @dev: PCI device to be initialized
1378 * Initialize device before it's used by a driver. Ask low-level code
1379 * to enable Memory resources. Wake up the device if it was suspended.
1380 * Beware, this function can fail.
1382 int pci_enable_device_mem(struct pci_dev *dev)
1384 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1386 EXPORT_SYMBOL(pci_enable_device_mem);
1389 * pci_enable_device - Initialize device before it's used by a driver.
1390 * @dev: PCI device to be initialized
1392 * Initialize device before it's used by a driver. Ask low-level code
1393 * to enable I/O and memory. Wake up the device if it was suspended.
1394 * Beware, this function can fail.
1396 * Note we don't actually enable the device many times if we call
1397 * this function repeatedly (we just increment the count).
1399 int pci_enable_device(struct pci_dev *dev)
1401 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1403 EXPORT_SYMBOL(pci_enable_device);
1406 * Managed PCI resources. This manages device on/off, intx/msi/msix
1407 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1408 * there's no need to track it separately. pci_devres is initialized
1409 * when a device is enabled using managed PCI device enable interface.
1412 unsigned int enabled:1;
1413 unsigned int pinned:1;
1414 unsigned int orig_intx:1;
1415 unsigned int restore_intx:1;
1419 static void pcim_release(struct device *gendev, void *res)
1421 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1422 struct pci_devres *this = res;
1425 if (dev->msi_enabled)
1426 pci_disable_msi(dev);
1427 if (dev->msix_enabled)
1428 pci_disable_msix(dev);
1430 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1431 if (this->region_mask & (1 << i))
1432 pci_release_region(dev, i);
1434 if (this->restore_intx)
1435 pci_intx(dev, this->orig_intx);
1437 if (this->enabled && !this->pinned)
1438 pci_disable_device(dev);
1441 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1443 struct pci_devres *dr, *new_dr;
1445 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1449 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1452 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1455 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1457 if (pci_is_managed(pdev))
1458 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1463 * pcim_enable_device - Managed pci_enable_device()
1464 * @pdev: PCI device to be initialized
1466 * Managed pci_enable_device().
1468 int pcim_enable_device(struct pci_dev *pdev)
1470 struct pci_devres *dr;
1473 dr = get_pci_dr(pdev);
1479 rc = pci_enable_device(pdev);
1481 pdev->is_managed = 1;
1486 EXPORT_SYMBOL(pcim_enable_device);
1489 * pcim_pin_device - Pin managed PCI device
1490 * @pdev: PCI device to pin
1492 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1493 * driver detach. @pdev must have been enabled with
1494 * pcim_enable_device().
1496 void pcim_pin_device(struct pci_dev *pdev)
1498 struct pci_devres *dr;
1500 dr = find_pci_dr(pdev);
1501 WARN_ON(!dr || !dr->enabled);
1505 EXPORT_SYMBOL(pcim_pin_device);
1508 * pcibios_add_device - provide arch specific hooks when adding device dev
1509 * @dev: the PCI device being added
1511 * Permits the platform to provide architecture specific functionality when
1512 * devices are added. This is the default implementation. Architecture
1513 * implementations can override this.
1515 int __weak pcibios_add_device(struct pci_dev *dev)
1521 * pcibios_release_device - provide arch specific hooks when releasing device dev
1522 * @dev: the PCI device being released
1524 * Permits the platform to provide architecture specific functionality when
1525 * devices are released. This is the default implementation. Architecture
1526 * implementations can override this.
1528 void __weak pcibios_release_device(struct pci_dev *dev) {}
1531 * pcibios_disable_device - disable arch specific PCI resources for device dev
1532 * @dev: the PCI device to disable
1534 * Disables architecture specific PCI resources for the device. This
1535 * is the default implementation. Architecture implementations can
1538 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1541 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1542 * @irq: ISA IRQ to penalize
1543 * @active: IRQ active or not
1545 * Permits the platform to provide architecture-specific functionality when
1546 * penalizing ISA IRQs. This is the default implementation. Architecture
1547 * implementations can override this.
1549 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1551 static void do_pci_disable_device(struct pci_dev *dev)
1555 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1556 if (pci_command & PCI_COMMAND_MASTER) {
1557 pci_command &= ~PCI_COMMAND_MASTER;
1558 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1561 pcibios_disable_device(dev);
1565 * pci_disable_enabled_device - Disable device without updating enable_cnt
1566 * @dev: PCI device to disable
1568 * NOTE: This function is a backend of PCI power management routines and is
1569 * not supposed to be called drivers.
1571 void pci_disable_enabled_device(struct pci_dev *dev)
1573 if (pci_is_enabled(dev))
1574 do_pci_disable_device(dev);
1578 * pci_disable_device - Disable PCI device after use
1579 * @dev: PCI device to be disabled
1581 * Signal to the system that the PCI device is not in use by the system
1582 * anymore. This only involves disabling PCI bus-mastering, if active.
1584 * Note we don't actually disable the device until all callers of
1585 * pci_enable_device() have called pci_disable_device().
1587 void pci_disable_device(struct pci_dev *dev)
1589 struct pci_devres *dr;
1591 dr = find_pci_dr(dev);
1595 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1596 "disabling already-disabled device");
1598 if (atomic_dec_return(&dev->enable_cnt) != 0)
1601 do_pci_disable_device(dev);
1603 dev->is_busmaster = 0;
1605 EXPORT_SYMBOL(pci_disable_device);
1608 * pcibios_set_pcie_reset_state - set reset state for device dev
1609 * @dev: the PCIe device reset
1610 * @state: Reset state to enter into
1613 * Sets the PCIe reset state for the device. This is the default
1614 * implementation. Architecture implementations can override this.
1616 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1617 enum pcie_reset_state state)
1623 * pci_set_pcie_reset_state - set reset state for device dev
1624 * @dev: the PCIe device reset
1625 * @state: Reset state to enter into
1628 * Sets the PCI reset state for the device.
1630 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1632 return pcibios_set_pcie_reset_state(dev, state);
1634 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1637 * pci_check_pme_status - Check if given device has generated PME.
1638 * @dev: Device to check.
1640 * Check the PME status of the device and if set, clear it and clear PME enable
1641 * (if set). Return 'true' if PME status and PME enable were both set or
1642 * 'false' otherwise.
1644 bool pci_check_pme_status(struct pci_dev *dev)
1653 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1654 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1655 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1658 /* Clear PME status. */
1659 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1660 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1661 /* Disable PME to avoid interrupt flood. */
1662 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1666 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1672 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1673 * @dev: Device to handle.
1674 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1676 * Check if @dev has generated PME and queue a resume request for it in that
1679 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1681 if (pme_poll_reset && dev->pme_poll)
1682 dev->pme_poll = false;
1684 if (pci_check_pme_status(dev)) {
1685 pci_wakeup_event(dev);
1686 pm_request_resume(&dev->dev);
1692 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1693 * @bus: Top bus of the subtree to walk.
1695 void pci_pme_wakeup_bus(struct pci_bus *bus)
1698 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1703 * pci_pme_capable - check the capability of PCI device to generate PME#
1704 * @dev: PCI device to handle.
1705 * @state: PCI state from which device will issue PME#.
1707 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1712 return !!(dev->pme_support & (1 << state));
1714 EXPORT_SYMBOL(pci_pme_capable);
1716 static void pci_pme_list_scan(struct work_struct *work)
1718 struct pci_pme_device *pme_dev, *n;
1720 mutex_lock(&pci_pme_list_mutex);
1721 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1722 if (pme_dev->dev->pme_poll) {
1723 struct pci_dev *bridge;
1725 bridge = pme_dev->dev->bus->self;
1727 * If bridge is in low power state, the
1728 * configuration space of subordinate devices
1729 * may be not accessible
1731 if (bridge && bridge->current_state != PCI_D0)
1734 * If the device is in D3cold it should not be
1737 if (pme_dev->dev->current_state == PCI_D3cold)
1740 pci_pme_wakeup(pme_dev->dev, NULL);
1742 list_del(&pme_dev->list);
1746 if (!list_empty(&pci_pme_list))
1747 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1748 msecs_to_jiffies(PME_TIMEOUT));
1749 mutex_unlock(&pci_pme_list_mutex);
1752 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1756 if (!dev->pme_support)
1759 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1760 /* Clear PME_Status by writing 1 to it and enable PME# */
1761 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1763 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1765 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1769 * pci_pme_active - enable or disable PCI device's PME# function
1770 * @dev: PCI device to handle.
1771 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1773 * The caller must verify that the device is capable of generating PME# before
1774 * calling this function with @enable equal to 'true'.
1776 void pci_pme_active(struct pci_dev *dev, bool enable)
1778 __pci_pme_active(dev, enable);
1781 * PCI (as opposed to PCIe) PME requires that the device have
1782 * its PME# line hooked up correctly. Not all hardware vendors
1783 * do this, so the PME never gets delivered and the device
1784 * remains asleep. The easiest way around this is to
1785 * periodically walk the list of suspended devices and check
1786 * whether any have their PME flag set. The assumption is that
1787 * we'll wake up often enough anyway that this won't be a huge
1788 * hit, and the power savings from the devices will still be a
1791 * Although PCIe uses in-band PME message instead of PME# line
1792 * to report PME, PME does not work for some PCIe devices in
1793 * reality. For example, there are devices that set their PME
1794 * status bits, but don't really bother to send a PME message;
1795 * there are PCI Express Root Ports that don't bother to
1796 * trigger interrupts when they receive PME messages from the
1797 * devices below. So PME poll is used for PCIe devices too.
1800 if (dev->pme_poll) {
1801 struct pci_pme_device *pme_dev;
1803 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1806 dev_warn(&dev->dev, "can't enable PME#\n");
1810 mutex_lock(&pci_pme_list_mutex);
1811 list_add(&pme_dev->list, &pci_pme_list);
1812 if (list_is_singular(&pci_pme_list))
1813 queue_delayed_work(system_freezable_wq,
1815 msecs_to_jiffies(PME_TIMEOUT));
1816 mutex_unlock(&pci_pme_list_mutex);
1818 mutex_lock(&pci_pme_list_mutex);
1819 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1820 if (pme_dev->dev == dev) {
1821 list_del(&pme_dev->list);
1826 mutex_unlock(&pci_pme_list_mutex);
1830 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1832 EXPORT_SYMBOL(pci_pme_active);
1835 * __pci_enable_wake - enable PCI device as wakeup event source
1836 * @dev: PCI device affected
1837 * @state: PCI state from which device will issue wakeup events
1838 * @runtime: True if the events are to be generated at run time
1839 * @enable: True to enable event generation; false to disable
1841 * This enables the device as a wakeup event source, or disables it.
1842 * When such events involves platform-specific hooks, those hooks are
1843 * called automatically by this routine.
1845 * Devices with legacy power management (no standard PCI PM capabilities)
1846 * always require such platform hooks.
1849 * 0 is returned on success
1850 * -EINVAL is returned if device is not supposed to wake up the system
1851 * Error code depending on the platform is returned if both the platform and
1852 * the native mechanism fail to enable the generation of wake-up events
1854 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1855 bool runtime, bool enable)
1859 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1862 /* Don't do the same thing twice in a row for one device. */
1863 if (!!enable == !!dev->wakeup_prepared)
1867 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1868 * Anderson we should be doing PME# wake enable followed by ACPI wake
1869 * enable. To disable wake-up we call the platform first, for symmetry.
1876 * Enable PME signaling if the device can signal PME from
1877 * D3cold regardless of whether or not it can signal PME from
1878 * the current target state, because that will allow it to
1879 * signal PME when the hierarchy above it goes into D3cold and
1880 * the device itself ends up in D3cold as a result of that.
1882 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
1883 pci_pme_active(dev, true);
1886 error = runtime ? platform_pci_run_wake(dev, true) :
1887 platform_pci_sleep_wake(dev, true);
1891 dev->wakeup_prepared = true;
1894 platform_pci_run_wake(dev, false);
1896 platform_pci_sleep_wake(dev, false);
1897 pci_pme_active(dev, false);
1898 dev->wakeup_prepared = false;
1903 EXPORT_SYMBOL(__pci_enable_wake);
1906 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1907 * @dev: PCI device to prepare
1908 * @enable: True to enable wake-up event generation; false to disable
1910 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1911 * and this function allows them to set that up cleanly - pci_enable_wake()
1912 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1913 * ordering constraints.
1915 * This function only returns error code if the device is not capable of
1916 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1917 * enable wake-up power for it.
1919 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1921 return pci_pme_capable(dev, PCI_D3cold) ?
1922 pci_enable_wake(dev, PCI_D3cold, enable) :
1923 pci_enable_wake(dev, PCI_D3hot, enable);
1925 EXPORT_SYMBOL(pci_wake_from_d3);
1928 * pci_target_state - find an appropriate low power state for a given PCI dev
1931 * Use underlying platform code to find a supported low power state for @dev.
1932 * If the platform can't manage @dev, return the deepest state from which it
1933 * can generate wake events, based on any available PME info.
1935 static pci_power_t pci_target_state(struct pci_dev *dev)
1937 pci_power_t target_state = PCI_D3hot;
1939 if (platform_pci_power_manageable(dev)) {
1941 * Call the platform to choose the target state of the device
1942 * and enable wake-up from this state if supported.
1944 pci_power_t state = platform_pci_choose_state(dev);
1947 case PCI_POWER_ERROR:
1952 if (pci_no_d1d2(dev))
1955 target_state = state;
1957 } else if (!dev->pm_cap) {
1958 target_state = PCI_D0;
1959 } else if (device_may_wakeup(&dev->dev)) {
1961 * Find the deepest state from which the device can generate
1962 * wake-up events, make it the target state and enable device
1965 if (dev->pme_support) {
1967 && !(dev->pme_support & (1 << target_state)))
1972 return target_state;
1976 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1977 * @dev: Device to handle.
1979 * Choose the power state appropriate for the device depending on whether
1980 * it can wake up the system and/or is power manageable by the platform
1981 * (PCI_D3hot is the default) and put the device into that state.
1983 int pci_prepare_to_sleep(struct pci_dev *dev)
1985 pci_power_t target_state = pci_target_state(dev);
1988 if (target_state == PCI_POWER_ERROR)
1991 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1993 error = pci_set_power_state(dev, target_state);
1996 pci_enable_wake(dev, target_state, false);
2000 EXPORT_SYMBOL(pci_prepare_to_sleep);
2003 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2004 * @dev: Device to handle.
2006 * Disable device's system wake-up capability and put it into D0.
2008 int pci_back_from_sleep(struct pci_dev *dev)
2010 pci_enable_wake(dev, PCI_D0, false);
2011 return pci_set_power_state(dev, PCI_D0);
2013 EXPORT_SYMBOL(pci_back_from_sleep);
2016 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2017 * @dev: PCI device being suspended.
2019 * Prepare @dev to generate wake-up events at run time and put it into a low
2022 int pci_finish_runtime_suspend(struct pci_dev *dev)
2024 pci_power_t target_state = pci_target_state(dev);
2027 if (target_state == PCI_POWER_ERROR)
2030 dev->runtime_d3cold = target_state == PCI_D3cold;
2032 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2034 error = pci_set_power_state(dev, target_state);
2037 __pci_enable_wake(dev, target_state, true, false);
2038 dev->runtime_d3cold = false;
2045 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2046 * @dev: Device to check.
2048 * Return true if the device itself is capable of generating wake-up events
2049 * (through the platform or using the native PCIe PME) or if the device supports
2050 * PME and one of its upstream bridges can generate wake-up events.
2052 bool pci_dev_run_wake(struct pci_dev *dev)
2054 struct pci_bus *bus = dev->bus;
2056 if (device_run_wake(&dev->dev))
2059 if (!dev->pme_support)
2062 /* PME-capable in principle, but not from the intended sleep state */
2063 if (!pci_pme_capable(dev, pci_target_state(dev)))
2066 while (bus->parent) {
2067 struct pci_dev *bridge = bus->self;
2069 if (device_run_wake(&bridge->dev))
2075 /* We have reached the root bus. */
2077 return device_run_wake(bus->bridge);
2081 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2084 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2085 * @pci_dev: Device to check.
2087 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2088 * reconfigured due to wakeup settings difference between system and runtime
2089 * suspend and the current power state of it is suitable for the upcoming
2090 * (system) transition.
2092 * If the device is not configured for system wakeup, disable PME for it before
2093 * returning 'true' to prevent it from waking up the system unnecessarily.
2095 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2097 struct device *dev = &pci_dev->dev;
2099 if (!pm_runtime_suspended(dev)
2100 || pci_target_state(pci_dev) != pci_dev->current_state
2101 || platform_pci_need_resume(pci_dev))
2105 * At this point the device is good to go unless it's been configured
2106 * to generate PME at the runtime suspend time, but it is not supposed
2107 * to wake up the system. In that case, simply disable PME for it
2108 * (it will have to be re-enabled on exit from system resume).
2110 * If the device's power state is D3cold and the platform check above
2111 * hasn't triggered, the device's configuration is suitable and we don't
2112 * need to manipulate it at all.
2114 spin_lock_irq(&dev->power.lock);
2116 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2117 !device_may_wakeup(dev))
2118 __pci_pme_active(pci_dev, false);
2120 spin_unlock_irq(&dev->power.lock);
2125 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2126 * @pci_dev: Device to handle.
2128 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2129 * it might have been disabled during the prepare phase of system suspend if
2130 * the device was not configured for system wakeup.
2132 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2134 struct device *dev = &pci_dev->dev;
2136 if (!pci_dev_run_wake(pci_dev))
2139 spin_lock_irq(&dev->power.lock);
2141 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2142 __pci_pme_active(pci_dev, true);
2144 spin_unlock_irq(&dev->power.lock);
2147 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2149 struct device *dev = &pdev->dev;
2150 struct device *parent = dev->parent;
2153 pm_runtime_get_sync(parent);
2154 pm_runtime_get_noresume(dev);
2156 * pdev->current_state is set to PCI_D3cold during suspending,
2157 * so wait until suspending completes
2159 pm_runtime_barrier(dev);
2161 * Only need to resume devices in D3cold, because config
2162 * registers are still accessible for devices suspended but
2165 if (pdev->current_state == PCI_D3cold)
2166 pm_runtime_resume(dev);
2169 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2171 struct device *dev = &pdev->dev;
2172 struct device *parent = dev->parent;
2174 pm_runtime_put(dev);
2176 pm_runtime_put_sync(parent);
2180 * pci_pm_init - Initialize PM functions of given PCI device
2181 * @dev: PCI device to handle.
2183 void pci_pm_init(struct pci_dev *dev)
2188 pm_runtime_forbid(&dev->dev);
2189 pm_runtime_set_active(&dev->dev);
2190 pm_runtime_enable(&dev->dev);
2191 device_enable_async_suspend(&dev->dev);
2192 dev->wakeup_prepared = false;
2195 dev->pme_support = 0;
2197 /* find PCI PM capability in list */
2198 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2201 /* Check device's ability to generate PME# */
2202 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2204 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2205 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2206 pmc & PCI_PM_CAP_VER_MASK);
2211 dev->d3_delay = PCI_PM_D3_WAIT;
2212 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2213 dev->d3cold_allowed = true;
2215 dev->d1_support = false;
2216 dev->d2_support = false;
2217 if (!pci_no_d1d2(dev)) {
2218 if (pmc & PCI_PM_CAP_D1)
2219 dev->d1_support = true;
2220 if (pmc & PCI_PM_CAP_D2)
2221 dev->d2_support = true;
2223 if (dev->d1_support || dev->d2_support)
2224 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2225 dev->d1_support ? " D1" : "",
2226 dev->d2_support ? " D2" : "");
2229 pmc &= PCI_PM_CAP_PME_MASK;
2231 dev_printk(KERN_DEBUG, &dev->dev,
2232 "PME# supported from%s%s%s%s%s\n",
2233 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2234 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2235 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2236 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2237 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2238 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2239 dev->pme_poll = true;
2241 * Make device's PM flags reflect the wake-up capability, but
2242 * let the user space enable it to wake up the system as needed.
2244 device_set_wakeup_capable(&dev->dev, true);
2245 /* Disable the PME# generation functionality */
2246 pci_pme_active(dev, false);
2250 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2252 unsigned long flags = IORESOURCE_PCI_FIXED;
2256 case PCI_EA_P_VF_MEM:
2257 flags |= IORESOURCE_MEM;
2259 case PCI_EA_P_MEM_PREFETCH:
2260 case PCI_EA_P_VF_MEM_PREFETCH:
2261 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2264 flags |= IORESOURCE_IO;
2273 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2276 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2277 return &dev->resource[bei];
2278 #ifdef CONFIG_PCI_IOV
2279 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2280 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2281 return &dev->resource[PCI_IOV_RESOURCES +
2282 bei - PCI_EA_BEI_VF_BAR0];
2284 else if (bei == PCI_EA_BEI_ROM)
2285 return &dev->resource[PCI_ROM_RESOURCE];
2290 /* Read an Enhanced Allocation (EA) entry */
2291 static int pci_ea_read(struct pci_dev *dev, int offset)
2293 struct resource *res;
2294 int ent_size, ent_offset = offset;
2295 resource_size_t start, end;
2296 unsigned long flags;
2297 u32 dw0, bei, base, max_offset;
2299 bool support_64 = (sizeof(resource_size_t) >= 8);
2301 pci_read_config_dword(dev, ent_offset, &dw0);
2304 /* Entry size field indicates DWORDs after 1st */
2305 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2307 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2310 bei = (dw0 & PCI_EA_BEI) >> 4;
2311 prop = (dw0 & PCI_EA_PP) >> 8;
2314 * If the Property is in the reserved range, try the Secondary
2317 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2318 prop = (dw0 & PCI_EA_SP) >> 16;
2319 if (prop > PCI_EA_P_BRIDGE_IO)
2322 res = pci_ea_get_resource(dev, bei, prop);
2324 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2328 flags = pci_ea_flags(dev, prop);
2330 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2335 pci_read_config_dword(dev, ent_offset, &base);
2336 start = (base & PCI_EA_FIELD_MASK);
2339 /* Read MaxOffset */
2340 pci_read_config_dword(dev, ent_offset, &max_offset);
2343 /* Read Base MSBs (if 64-bit entry) */
2344 if (base & PCI_EA_IS_64) {
2347 pci_read_config_dword(dev, ent_offset, &base_upper);
2350 flags |= IORESOURCE_MEM_64;
2352 /* entry starts above 32-bit boundary, can't use */
2353 if (!support_64 && base_upper)
2357 start |= ((u64)base_upper << 32);
2360 end = start + (max_offset | 0x03);
2362 /* Read MaxOffset MSBs (if 64-bit entry) */
2363 if (max_offset & PCI_EA_IS_64) {
2364 u32 max_offset_upper;
2366 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2369 flags |= IORESOURCE_MEM_64;
2371 /* entry too big, can't use */
2372 if (!support_64 && max_offset_upper)
2376 end += ((u64)max_offset_upper << 32);
2380 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2384 if (ent_size != ent_offset - offset) {
2386 "EA Entry Size (%d) does not match length read (%d)\n",
2387 ent_size, ent_offset - offset);
2391 res->name = pci_name(dev);
2396 if (bei <= PCI_EA_BEI_BAR5)
2397 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2399 else if (bei == PCI_EA_BEI_ROM)
2400 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2402 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2403 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2404 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2406 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2410 return offset + ent_size;
2413 /* Enhanced Allocation Initalization */
2414 void pci_ea_init(struct pci_dev *dev)
2421 /* find PCI EA capability in list */
2422 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2426 /* determine the number of entries */
2427 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2429 num_ent &= PCI_EA_NUM_ENT_MASK;
2431 offset = ea + PCI_EA_FIRST_ENT;
2433 /* Skip DWORD 2 for type 1 functions */
2434 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2437 /* parse each EA entry */
2438 for (i = 0; i < num_ent; ++i)
2439 offset = pci_ea_read(dev, offset);
2442 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2443 struct pci_cap_saved_state *new_cap)
2445 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2449 * _pci_add_cap_save_buffer - allocate buffer for saving given
2450 * capability registers
2451 * @dev: the PCI device
2452 * @cap: the capability to allocate the buffer for
2453 * @extended: Standard or Extended capability ID
2454 * @size: requested size of the buffer
2456 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2457 bool extended, unsigned int size)
2460 struct pci_cap_saved_state *save_state;
2463 pos = pci_find_ext_capability(dev, cap);
2465 pos = pci_find_capability(dev, cap);
2470 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2474 save_state->cap.cap_nr = cap;
2475 save_state->cap.cap_extended = extended;
2476 save_state->cap.size = size;
2477 pci_add_saved_cap(dev, save_state);
2482 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2484 return _pci_add_cap_save_buffer(dev, cap, false, size);
2487 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2489 return _pci_add_cap_save_buffer(dev, cap, true, size);
2493 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2494 * @dev: the PCI device
2496 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2500 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2501 PCI_EXP_SAVE_REGS * sizeof(u16));
2504 "unable to preallocate PCI Express save buffer\n");
2506 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2509 "unable to preallocate PCI-X save buffer\n");
2511 pci_allocate_vc_save_buffers(dev);
2514 void pci_free_cap_save_buffers(struct pci_dev *dev)
2516 struct pci_cap_saved_state *tmp;
2517 struct hlist_node *n;
2519 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2524 * pci_configure_ari - enable or disable ARI forwarding
2525 * @dev: the PCI device
2527 * If @dev and its upstream bridge both support ARI, enable ARI in the
2528 * bridge. Otherwise, disable ARI in the bridge.
2530 void pci_configure_ari(struct pci_dev *dev)
2533 struct pci_dev *bridge;
2535 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2538 bridge = dev->bus->self;
2542 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2543 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2546 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2547 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2548 PCI_EXP_DEVCTL2_ARI);
2549 bridge->ari_enabled = 1;
2551 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2552 PCI_EXP_DEVCTL2_ARI);
2553 bridge->ari_enabled = 0;
2557 static int pci_acs_enable;
2560 * pci_request_acs - ask for ACS to be enabled if supported
2562 void pci_request_acs(void)
2568 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2569 * @dev: the PCI device
2571 static int pci_std_enable_acs(struct pci_dev *dev)
2577 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2581 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2582 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2584 /* Source Validation */
2585 ctrl |= (cap & PCI_ACS_SV);
2587 /* P2P Request Redirect */
2588 ctrl |= (cap & PCI_ACS_RR);
2590 /* P2P Completion Redirect */
2591 ctrl |= (cap & PCI_ACS_CR);
2593 /* Upstream Forwarding */
2594 ctrl |= (cap & PCI_ACS_UF);
2596 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2602 * pci_enable_acs - enable ACS if hardware support it
2603 * @dev: the PCI device
2605 void pci_enable_acs(struct pci_dev *dev)
2607 if (!pci_acs_enable)
2610 if (!pci_std_enable_acs(dev))
2613 pci_dev_specific_enable_acs(dev);
2616 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2621 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2626 * Except for egress control, capabilities are either required
2627 * or only required if controllable. Features missing from the
2628 * capability field can therefore be assumed as hard-wired enabled.
2630 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2631 acs_flags &= (cap | PCI_ACS_EC);
2633 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2634 return (ctrl & acs_flags) == acs_flags;
2638 * pci_acs_enabled - test ACS against required flags for a given device
2639 * @pdev: device to test
2640 * @acs_flags: required PCI ACS flags
2642 * Return true if the device supports the provided flags. Automatically
2643 * filters out flags that are not implemented on multifunction devices.
2645 * Note that this interface checks the effective ACS capabilities of the
2646 * device rather than the actual capabilities. For instance, most single
2647 * function endpoints are not required to support ACS because they have no
2648 * opportunity for peer-to-peer access. We therefore return 'true'
2649 * regardless of whether the device exposes an ACS capability. This makes
2650 * it much easier for callers of this function to ignore the actual type
2651 * or topology of the device when testing ACS support.
2653 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2657 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2662 * Conventional PCI and PCI-X devices never support ACS, either
2663 * effectively or actually. The shared bus topology implies that
2664 * any device on the bus can receive or snoop DMA.
2666 if (!pci_is_pcie(pdev))
2669 switch (pci_pcie_type(pdev)) {
2671 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2672 * but since their primary interface is PCI/X, we conservatively
2673 * handle them as we would a non-PCIe device.
2675 case PCI_EXP_TYPE_PCIE_BRIDGE:
2677 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2678 * applicable... must never implement an ACS Extended Capability...".
2679 * This seems arbitrary, but we take a conservative interpretation
2680 * of this statement.
2682 case PCI_EXP_TYPE_PCI_BRIDGE:
2683 case PCI_EXP_TYPE_RC_EC:
2686 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2687 * implement ACS in order to indicate their peer-to-peer capabilities,
2688 * regardless of whether they are single- or multi-function devices.
2690 case PCI_EXP_TYPE_DOWNSTREAM:
2691 case PCI_EXP_TYPE_ROOT_PORT:
2692 return pci_acs_flags_enabled(pdev, acs_flags);
2694 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2695 * implemented by the remaining PCIe types to indicate peer-to-peer
2696 * capabilities, but only when they are part of a multifunction
2697 * device. The footnote for section 6.12 indicates the specific
2698 * PCIe types included here.
2700 case PCI_EXP_TYPE_ENDPOINT:
2701 case PCI_EXP_TYPE_UPSTREAM:
2702 case PCI_EXP_TYPE_LEG_END:
2703 case PCI_EXP_TYPE_RC_END:
2704 if (!pdev->multifunction)
2707 return pci_acs_flags_enabled(pdev, acs_flags);
2711 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2712 * to single function devices with the exception of downstream ports.
2718 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2719 * @start: starting downstream device
2720 * @end: ending upstream device or NULL to search to the root bus
2721 * @acs_flags: required flags
2723 * Walk up a device tree from start to end testing PCI ACS support. If
2724 * any step along the way does not support the required flags, return false.
2726 bool pci_acs_path_enabled(struct pci_dev *start,
2727 struct pci_dev *end, u16 acs_flags)
2729 struct pci_dev *pdev, *parent = start;
2734 if (!pci_acs_enabled(pdev, acs_flags))
2737 if (pci_is_root_bus(pdev->bus))
2738 return (end == NULL);
2740 parent = pdev->bus->self;
2741 } while (pdev != end);
2747 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2748 * @dev: the PCI device
2749 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2751 * Perform INTx swizzling for a device behind one level of bridge. This is
2752 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2753 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2754 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2755 * the PCI Express Base Specification, Revision 2.1)
2757 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2761 if (pci_ari_enabled(dev->bus))
2764 slot = PCI_SLOT(dev->devfn);
2766 return (((pin - 1) + slot) % 4) + 1;
2769 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2777 while (!pci_is_root_bus(dev->bus)) {
2778 pin = pci_swizzle_interrupt_pin(dev, pin);
2779 dev = dev->bus->self;
2786 * pci_common_swizzle - swizzle INTx all the way to root bridge
2787 * @dev: the PCI device
2788 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2790 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2791 * bridges all the way up to a PCI root bus.
2793 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2797 while (!pci_is_root_bus(dev->bus)) {
2798 pin = pci_swizzle_interrupt_pin(dev, pin);
2799 dev = dev->bus->self;
2802 return PCI_SLOT(dev->devfn);
2804 EXPORT_SYMBOL_GPL(pci_common_swizzle);
2807 * pci_release_region - Release a PCI bar
2808 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2809 * @bar: BAR to release
2811 * Releases the PCI I/O and memory resources previously reserved by a
2812 * successful call to pci_request_region. Call this function only
2813 * after all use of the PCI regions has ceased.
2815 void pci_release_region(struct pci_dev *pdev, int bar)
2817 struct pci_devres *dr;
2819 if (pci_resource_len(pdev, bar) == 0)
2821 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2822 release_region(pci_resource_start(pdev, bar),
2823 pci_resource_len(pdev, bar));
2824 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2825 release_mem_region(pci_resource_start(pdev, bar),
2826 pci_resource_len(pdev, bar));
2828 dr = find_pci_dr(pdev);
2830 dr->region_mask &= ~(1 << bar);
2832 EXPORT_SYMBOL(pci_release_region);
2835 * __pci_request_region - Reserved PCI I/O and memory resource
2836 * @pdev: PCI device whose resources are to be reserved
2837 * @bar: BAR to be reserved
2838 * @res_name: Name to be associated with resource.
2839 * @exclusive: whether the region access is exclusive or not
2841 * Mark the PCI region associated with PCI device @pdev BR @bar as
2842 * being reserved by owner @res_name. Do not access any
2843 * address inside the PCI regions unless this call returns
2846 * If @exclusive is set, then the region is marked so that userspace
2847 * is explicitly not allowed to map the resource via /dev/mem or
2848 * sysfs MMIO access.
2850 * Returns 0 on success, or %EBUSY on error. A warning
2851 * message is also printed on failure.
2853 static int __pci_request_region(struct pci_dev *pdev, int bar,
2854 const char *res_name, int exclusive)
2856 struct pci_devres *dr;
2858 if (pci_resource_len(pdev, bar) == 0)
2861 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2862 if (!request_region(pci_resource_start(pdev, bar),
2863 pci_resource_len(pdev, bar), res_name))
2865 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2866 if (!__request_mem_region(pci_resource_start(pdev, bar),
2867 pci_resource_len(pdev, bar), res_name,
2872 dr = find_pci_dr(pdev);
2874 dr->region_mask |= 1 << bar;
2879 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2880 &pdev->resource[bar]);
2885 * pci_request_region - Reserve PCI I/O and memory resource
2886 * @pdev: PCI device whose resources are to be reserved
2887 * @bar: BAR to be reserved
2888 * @res_name: Name to be associated with resource
2890 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2891 * being reserved by owner @res_name. Do not access any
2892 * address inside the PCI regions unless this call returns
2895 * Returns 0 on success, or %EBUSY on error. A warning
2896 * message is also printed on failure.
2898 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2900 return __pci_request_region(pdev, bar, res_name, 0);
2902 EXPORT_SYMBOL(pci_request_region);
2905 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2906 * @pdev: PCI device whose resources are to be reserved
2907 * @bar: BAR to be reserved
2908 * @res_name: Name to be associated with resource.
2910 * Mark the PCI region associated with PCI device @pdev BR @bar as
2911 * being reserved by owner @res_name. Do not access any
2912 * address inside the PCI regions unless this call returns
2915 * Returns 0 on success, or %EBUSY on error. A warning
2916 * message is also printed on failure.
2918 * The key difference that _exclusive makes it that userspace is
2919 * explicitly not allowed to map the resource via /dev/mem or
2922 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
2923 const char *res_name)
2925 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2927 EXPORT_SYMBOL(pci_request_region_exclusive);
2930 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2931 * @pdev: PCI device whose resources were previously reserved
2932 * @bars: Bitmask of BARs to be released
2934 * Release selected PCI I/O and memory resources previously reserved.
2935 * Call this function only after all use of the PCI regions has ceased.
2937 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2941 for (i = 0; i < 6; i++)
2942 if (bars & (1 << i))
2943 pci_release_region(pdev, i);
2945 EXPORT_SYMBOL(pci_release_selected_regions);
2947 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2948 const char *res_name, int excl)
2952 for (i = 0; i < 6; i++)
2953 if (bars & (1 << i))
2954 if (__pci_request_region(pdev, i, res_name, excl))
2960 if (bars & (1 << i))
2961 pci_release_region(pdev, i);
2968 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2969 * @pdev: PCI device whose resources are to be reserved
2970 * @bars: Bitmask of BARs to be requested
2971 * @res_name: Name to be associated with resource
2973 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2974 const char *res_name)
2976 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2978 EXPORT_SYMBOL(pci_request_selected_regions);
2980 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
2981 const char *res_name)
2983 return __pci_request_selected_regions(pdev, bars, res_name,
2984 IORESOURCE_EXCLUSIVE);
2986 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2989 * pci_release_regions - Release reserved PCI I/O and memory resources
2990 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2992 * Releases all PCI I/O and memory resources previously reserved by a
2993 * successful call to pci_request_regions. Call this function only
2994 * after all use of the PCI regions has ceased.
2997 void pci_release_regions(struct pci_dev *pdev)
2999 pci_release_selected_regions(pdev, (1 << 6) - 1);
3001 EXPORT_SYMBOL(pci_release_regions);
3004 * pci_request_regions - Reserved PCI I/O and memory resources
3005 * @pdev: PCI device whose resources are to be reserved
3006 * @res_name: Name to be associated with resource.
3008 * Mark all PCI regions associated with PCI device @pdev as
3009 * being reserved by owner @res_name. Do not access any
3010 * address inside the PCI regions unless this call returns
3013 * Returns 0 on success, or %EBUSY on error. A warning
3014 * message is also printed on failure.
3016 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3018 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3020 EXPORT_SYMBOL(pci_request_regions);
3023 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3024 * @pdev: PCI device whose resources are to be reserved
3025 * @res_name: Name to be associated with resource.
3027 * Mark all PCI regions associated with PCI device @pdev as
3028 * being reserved by owner @res_name. Do not access any
3029 * address inside the PCI regions unless this call returns
3032 * pci_request_regions_exclusive() will mark the region so that
3033 * /dev/mem and the sysfs MMIO access will not be allowed.
3035 * Returns 0 on success, or %EBUSY on error. A warning
3036 * message is also printed on failure.
3038 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3040 return pci_request_selected_regions_exclusive(pdev,
3041 ((1 << 6) - 1), res_name);
3043 EXPORT_SYMBOL(pci_request_regions_exclusive);
3046 * pci_remap_iospace - Remap the memory mapped I/O space
3047 * @res: Resource describing the I/O space
3048 * @phys_addr: physical address of range to be mapped
3050 * Remap the memory mapped I/O space described by the @res
3051 * and the CPU physical address @phys_addr into virtual address space.
3052 * Only architectures that have memory mapped IO functions defined
3053 * (and the PCI_IOBASE value defined) should call this function.
3055 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3057 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3058 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3060 if (!(res->flags & IORESOURCE_IO))
3063 if (res->end > IO_SPACE_LIMIT)
3066 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3067 pgprot_device(PAGE_KERNEL));
3069 /* this architecture does not have memory mapped I/O space,
3070 so this function should never be called */
3071 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3076 static void __pci_set_master(struct pci_dev *dev, bool enable)
3080 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3082 cmd = old_cmd | PCI_COMMAND_MASTER;
3084 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3085 if (cmd != old_cmd) {
3086 dev_dbg(&dev->dev, "%s bus mastering\n",
3087 enable ? "enabling" : "disabling");
3088 pci_write_config_word(dev, PCI_COMMAND, cmd);
3090 dev->is_busmaster = enable;
3094 * pcibios_setup - process "pci=" kernel boot arguments
3095 * @str: string used to pass in "pci=" kernel boot arguments
3097 * Process kernel boot arguments. This is the default implementation.
3098 * Architecture specific implementations can override this as necessary.
3100 char * __weak __init pcibios_setup(char *str)
3106 * pcibios_set_master - enable PCI bus-mastering for device dev
3107 * @dev: the PCI device to enable
3109 * Enables PCI bus-mastering for the device. This is the default
3110 * implementation. Architecture specific implementations can override
3111 * this if necessary.
3113 void __weak pcibios_set_master(struct pci_dev *dev)
3117 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3118 if (pci_is_pcie(dev))
3121 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3123 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3124 else if (lat > pcibios_max_latency)
3125 lat = pcibios_max_latency;
3129 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3133 * pci_set_master - enables bus-mastering for device dev
3134 * @dev: the PCI device to enable
3136 * Enables bus-mastering on the device and calls pcibios_set_master()
3137 * to do the needed arch specific settings.
3139 void pci_set_master(struct pci_dev *dev)
3141 __pci_set_master(dev, true);
3142 pcibios_set_master(dev);
3144 EXPORT_SYMBOL(pci_set_master);
3147 * pci_clear_master - disables bus-mastering for device dev
3148 * @dev: the PCI device to disable
3150 void pci_clear_master(struct pci_dev *dev)
3152 __pci_set_master(dev, false);
3154 EXPORT_SYMBOL(pci_clear_master);
3157 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3158 * @dev: the PCI device for which MWI is to be enabled
3160 * Helper function for pci_set_mwi.
3161 * Originally copied from drivers/net/acenic.c.
3162 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3164 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3166 int pci_set_cacheline_size(struct pci_dev *dev)
3170 if (!pci_cache_line_size)
3173 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3174 equal to or multiple of the right value. */
3175 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3176 if (cacheline_size >= pci_cache_line_size &&
3177 (cacheline_size % pci_cache_line_size) == 0)
3180 /* Write the correct value. */
3181 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3183 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3184 if (cacheline_size == pci_cache_line_size)
3187 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3188 pci_cache_line_size << 2);
3192 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3195 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3196 * @dev: the PCI device for which MWI is enabled
3198 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3200 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3202 int pci_set_mwi(struct pci_dev *dev)
3204 #ifdef PCI_DISABLE_MWI
3210 rc = pci_set_cacheline_size(dev);
3214 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3215 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3216 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3217 cmd |= PCI_COMMAND_INVALIDATE;
3218 pci_write_config_word(dev, PCI_COMMAND, cmd);
3223 EXPORT_SYMBOL(pci_set_mwi);
3226 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3227 * @dev: the PCI device for which MWI is enabled
3229 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3230 * Callers are not required to check the return value.
3232 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3234 int pci_try_set_mwi(struct pci_dev *dev)
3236 #ifdef PCI_DISABLE_MWI
3239 return pci_set_mwi(dev);
3242 EXPORT_SYMBOL(pci_try_set_mwi);
3245 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3246 * @dev: the PCI device to disable
3248 * Disables PCI Memory-Write-Invalidate transaction on the device
3250 void pci_clear_mwi(struct pci_dev *dev)
3252 #ifndef PCI_DISABLE_MWI
3255 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3256 if (cmd & PCI_COMMAND_INVALIDATE) {
3257 cmd &= ~PCI_COMMAND_INVALIDATE;
3258 pci_write_config_word(dev, PCI_COMMAND, cmd);
3262 EXPORT_SYMBOL(pci_clear_mwi);
3265 * pci_intx - enables/disables PCI INTx for device dev
3266 * @pdev: the PCI device to operate on
3267 * @enable: boolean: whether to enable or disable PCI INTx
3269 * Enables/disables PCI INTx for device dev
3271 void pci_intx(struct pci_dev *pdev, int enable)
3273 u16 pci_command, new;
3275 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3278 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3280 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3282 if (new != pci_command) {
3283 struct pci_devres *dr;
3285 pci_write_config_word(pdev, PCI_COMMAND, new);
3287 dr = find_pci_dr(pdev);
3288 if (dr && !dr->restore_intx) {
3289 dr->restore_intx = 1;
3290 dr->orig_intx = !enable;
3294 EXPORT_SYMBOL_GPL(pci_intx);
3297 * pci_intx_mask_supported - probe for INTx masking support
3298 * @dev: the PCI device to operate on
3300 * Check if the device dev support INTx masking via the config space
3303 bool pci_intx_mask_supported(struct pci_dev *dev)
3305 bool mask_supported = false;
3308 if (dev->broken_intx_masking)
3311 pci_cfg_access_lock(dev);
3313 pci_read_config_word(dev, PCI_COMMAND, &orig);
3314 pci_write_config_word(dev, PCI_COMMAND,
3315 orig ^ PCI_COMMAND_INTX_DISABLE);
3316 pci_read_config_word(dev, PCI_COMMAND, &new);
3319 * There's no way to protect against hardware bugs or detect them
3320 * reliably, but as long as we know what the value should be, let's
3321 * go ahead and check it.
3323 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3324 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3326 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3327 mask_supported = true;
3328 pci_write_config_word(dev, PCI_COMMAND, orig);
3331 pci_cfg_access_unlock(dev);
3332 return mask_supported;
3334 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3336 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3338 struct pci_bus *bus = dev->bus;
3339 bool mask_updated = true;
3340 u32 cmd_status_dword;
3341 u16 origcmd, newcmd;
3342 unsigned long flags;
3346 * We do a single dword read to retrieve both command and status.
3347 * Document assumptions that make this possible.
3349 BUILD_BUG_ON(PCI_COMMAND % 4);
3350 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3352 raw_spin_lock_irqsave(&pci_lock, flags);
3354 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3356 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3359 * Check interrupt status register to see whether our device
3360 * triggered the interrupt (when masking) or the next IRQ is
3361 * already pending (when unmasking).
3363 if (mask != irq_pending) {
3364 mask_updated = false;
3368 origcmd = cmd_status_dword;
3369 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3371 newcmd |= PCI_COMMAND_INTX_DISABLE;
3372 if (newcmd != origcmd)
3373 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3376 raw_spin_unlock_irqrestore(&pci_lock, flags);
3378 return mask_updated;
3382 * pci_check_and_mask_intx - mask INTx on pending interrupt
3383 * @dev: the PCI device to operate on
3385 * Check if the device dev has its INTx line asserted, mask it and
3386 * return true in that case. False is returned if not interrupt was
3389 bool pci_check_and_mask_intx(struct pci_dev *dev)
3391 return pci_check_and_set_intx_mask(dev, true);
3393 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3396 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3397 * @dev: the PCI device to operate on
3399 * Check if the device dev has its INTx line asserted, unmask it if not
3400 * and return true. False is returned and the mask remains active if
3401 * there was still an interrupt pending.
3403 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3405 return pci_check_and_set_intx_mask(dev, false);
3407 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3409 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3411 return dma_set_max_seg_size(&dev->dev, size);
3413 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3415 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3417 return dma_set_seg_boundary(&dev->dev, mask);
3419 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3422 * pci_wait_for_pending_transaction - waits for pending transaction
3423 * @dev: the PCI device to operate on
3425 * Return 0 if transaction is pending 1 otherwise.
3427 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3429 if (!pci_is_pcie(dev))
3432 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3433 PCI_EXP_DEVSTA_TRPND);
3435 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3437 static int pcie_flr(struct pci_dev *dev, int probe)
3441 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3442 if (!(cap & PCI_EXP_DEVCAP_FLR))
3448 if (!pci_wait_for_pending_transaction(dev))
3449 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3451 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3456 static int pci_af_flr(struct pci_dev *dev, int probe)
3461 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3465 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3466 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3473 * Wait for Transaction Pending bit to clear. A word-aligned test
3474 * is used, so we use the conrol offset rather than status and shift
3475 * the test bit to match.
3477 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3478 PCI_AF_STATUS_TP << 8))
3479 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3481 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3487 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3488 * @dev: Device to reset.
3489 * @probe: If set, only check if the device can be reset this way.
3491 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3492 * unset, it will be reinitialized internally when going from PCI_D3hot to
3493 * PCI_D0. If that's the case and the device is not in a low-power state
3494 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3496 * NOTE: This causes the caller to sleep for twice the device power transition
3497 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3498 * by default (i.e. unless the @dev's d3_delay field has a different value).
3499 * Moreover, only devices in D0 can be reset by this function.
3501 static int pci_pm_reset(struct pci_dev *dev, int probe)
3505 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3508 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3509 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3515 if (dev->current_state != PCI_D0)
3518 csr &= ~PCI_PM_CTRL_STATE_MASK;
3520 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3521 pci_dev_d3_sleep(dev);
3523 csr &= ~PCI_PM_CTRL_STATE_MASK;
3525 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3526 pci_dev_d3_sleep(dev);
3531 void pci_reset_secondary_bus(struct pci_dev *dev)
3535 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3536 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3537 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3539 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3540 * this to 2ms to ensure that we meet the minimum requirement.
3544 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3545 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3548 * Trhfa for conventional PCI is 2^25 clock cycles.
3549 * Assuming a minimum 33MHz clock this results in a 1s
3550 * delay before we can consider subordinate devices to
3551 * be re-initialized. PCIe has some ways to shorten this,
3552 * but we don't make use of them yet.
3557 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3559 pci_reset_secondary_bus(dev);
3563 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3564 * @dev: Bridge device
3566 * Use the bridge control register to assert reset on the secondary bus.
3567 * Devices on the secondary bus are left in power-on state.
3569 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3571 pcibios_reset_secondary_bus(dev);
3573 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3575 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3577 struct pci_dev *pdev;
3579 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3580 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3583 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3590 pci_reset_bridge_secondary_bus(dev->bus->self);
3595 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3599 if (!hotplug || !try_module_get(hotplug->ops->owner))
3602 if (hotplug->ops->reset_slot)
3603 rc = hotplug->ops->reset_slot(hotplug, probe);
3605 module_put(hotplug->ops->owner);
3610 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3612 struct pci_dev *pdev;
3614 if (dev->subordinate || !dev->slot ||
3615 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3618 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3619 if (pdev != dev && pdev->slot == dev->slot)
3622 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3625 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3631 rc = pci_dev_specific_reset(dev, probe);
3635 rc = pcie_flr(dev, probe);
3639 rc = pci_af_flr(dev, probe);
3643 rc = pci_pm_reset(dev, probe);
3647 rc = pci_dev_reset_slot_function(dev, probe);
3651 rc = pci_parent_bus_reset(dev, probe);
3656 static void pci_dev_lock(struct pci_dev *dev)
3658 pci_cfg_access_lock(dev);
3659 /* block PM suspend, driver probe, etc. */
3660 device_lock(&dev->dev);
3663 /* Return 1 on successful lock, 0 on contention */
3664 static int pci_dev_trylock(struct pci_dev *dev)
3666 if (pci_cfg_access_trylock(dev)) {
3667 if (device_trylock(&dev->dev))
3669 pci_cfg_access_unlock(dev);
3675 static void pci_dev_unlock(struct pci_dev *dev)
3677 device_unlock(&dev->dev);
3678 pci_cfg_access_unlock(dev);
3682 * pci_reset_notify - notify device driver of reset
3683 * @dev: device to be notified of reset
3684 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3687 * Must be called prior to device access being disabled and after device
3688 * access is restored.
3690 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3692 const struct pci_error_handlers *err_handler =
3693 dev->driver ? dev->driver->err_handler : NULL;
3694 if (err_handler && err_handler->reset_notify)
3695 err_handler->reset_notify(dev, prepare);
3698 static void pci_dev_save_and_disable(struct pci_dev *dev)
3700 pci_reset_notify(dev, true);
3703 * Wake-up device prior to save. PM registers default to D0 after
3704 * reset and a simple register restore doesn't reliably return
3705 * to a non-D0 state anyway.
3707 pci_set_power_state(dev, PCI_D0);
3709 pci_save_state(dev);
3711 * Disable the device by clearing the Command register, except for
3712 * INTx-disable which is set. This not only disables MMIO and I/O port
3713 * BARs, but also prevents the device from being Bus Master, preventing
3714 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3715 * compliant devices, INTx-disable prevents legacy interrupts.
3717 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3720 static void pci_dev_restore(struct pci_dev *dev)
3722 pci_restore_state(dev);
3723 pci_reset_notify(dev, false);
3726 static int pci_dev_reset(struct pci_dev *dev, int probe)
3733 rc = __pci_dev_reset(dev, probe);
3736 pci_dev_unlock(dev);
3742 * __pci_reset_function - reset a PCI device function
3743 * @dev: PCI device to reset
3745 * Some devices allow an individual function to be reset without affecting
3746 * other functions in the same device. The PCI device must be responsive
3747 * to PCI config space in order to use this function.
3749 * The device function is presumed to be unused when this function is called.
3750 * Resetting the device will make the contents of PCI configuration space
3751 * random, so any caller of this must be prepared to reinitialise the
3752 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3755 * Returns 0 if the device function was successfully reset or negative if the
3756 * device doesn't support resetting a single function.
3758 int __pci_reset_function(struct pci_dev *dev)
3760 return pci_dev_reset(dev, 0);
3762 EXPORT_SYMBOL_GPL(__pci_reset_function);
3765 * __pci_reset_function_locked - reset a PCI device function while holding
3766 * the @dev mutex lock.
3767 * @dev: PCI device to reset
3769 * Some devices allow an individual function to be reset without affecting
3770 * other functions in the same device. The PCI device must be responsive
3771 * to PCI config space in order to use this function.
3773 * The device function is presumed to be unused and the caller is holding
3774 * the device mutex lock when this function is called.
3775 * Resetting the device will make the contents of PCI configuration space
3776 * random, so any caller of this must be prepared to reinitialise the
3777 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3780 * Returns 0 if the device function was successfully reset or negative if the
3781 * device doesn't support resetting a single function.
3783 int __pci_reset_function_locked(struct pci_dev *dev)
3785 return __pci_dev_reset(dev, 0);
3787 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3790 * pci_probe_reset_function - check whether the device can be safely reset
3791 * @dev: PCI device to reset
3793 * Some devices allow an individual function to be reset without affecting
3794 * other functions in the same device. The PCI device must be responsive
3795 * to PCI config space in order to use this function.
3797 * Returns 0 if the device function can be reset or negative if the
3798 * device doesn't support resetting a single function.
3800 int pci_probe_reset_function(struct pci_dev *dev)
3802 return pci_dev_reset(dev, 1);
3806 * pci_reset_function - quiesce and reset a PCI device function
3807 * @dev: PCI device to reset
3809 * Some devices allow an individual function to be reset without affecting
3810 * other functions in the same device. The PCI device must be responsive
3811 * to PCI config space in order to use this function.
3813 * This function does not just reset the PCI portion of a device, but
3814 * clears all the state associated with the device. This function differs
3815 * from __pci_reset_function in that it saves and restores device state
3818 * Returns 0 if the device function was successfully reset or negative if the
3819 * device doesn't support resetting a single function.
3821 int pci_reset_function(struct pci_dev *dev)
3825 rc = pci_dev_reset(dev, 1);
3829 pci_dev_save_and_disable(dev);
3831 rc = pci_dev_reset(dev, 0);
3833 pci_dev_restore(dev);
3837 EXPORT_SYMBOL_GPL(pci_reset_function);
3840 * pci_try_reset_function - quiesce and reset a PCI device function
3841 * @dev: PCI device to reset
3843 * Same as above, except return -EAGAIN if unable to lock device.
3845 int pci_try_reset_function(struct pci_dev *dev)
3849 rc = pci_dev_reset(dev, 1);
3853 pci_dev_save_and_disable(dev);
3855 if (pci_dev_trylock(dev)) {
3856 rc = __pci_dev_reset(dev, 0);
3857 pci_dev_unlock(dev);
3861 pci_dev_restore(dev);
3865 EXPORT_SYMBOL_GPL(pci_try_reset_function);
3867 /* Do any devices on or below this bus prevent a bus reset? */
3868 static bool pci_bus_resetable(struct pci_bus *bus)
3870 struct pci_dev *dev;
3873 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
3876 list_for_each_entry(dev, &bus->devices, bus_list) {
3877 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3878 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3885 /* Lock devices from the top of the tree down */
3886 static void pci_bus_lock(struct pci_bus *bus)
3888 struct pci_dev *dev;
3890 list_for_each_entry(dev, &bus->devices, bus_list) {
3892 if (dev->subordinate)
3893 pci_bus_lock(dev->subordinate);
3897 /* Unlock devices from the bottom of the tree up */
3898 static void pci_bus_unlock(struct pci_bus *bus)
3900 struct pci_dev *dev;
3902 list_for_each_entry(dev, &bus->devices, bus_list) {
3903 if (dev->subordinate)
3904 pci_bus_unlock(dev->subordinate);
3905 pci_dev_unlock(dev);
3909 /* Return 1 on successful lock, 0 on contention */
3910 static int pci_bus_trylock(struct pci_bus *bus)
3912 struct pci_dev *dev;
3914 list_for_each_entry(dev, &bus->devices, bus_list) {
3915 if (!pci_dev_trylock(dev))
3917 if (dev->subordinate) {
3918 if (!pci_bus_trylock(dev->subordinate)) {
3919 pci_dev_unlock(dev);
3927 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3928 if (dev->subordinate)
3929 pci_bus_unlock(dev->subordinate);
3930 pci_dev_unlock(dev);
3935 /* Do any devices on or below this slot prevent a bus reset? */
3936 static bool pci_slot_resetable(struct pci_slot *slot)
3938 struct pci_dev *dev;
3940 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3941 if (!dev->slot || dev->slot != slot)
3943 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3944 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3951 /* Lock devices from the top of the tree down */
3952 static void pci_slot_lock(struct pci_slot *slot)
3954 struct pci_dev *dev;
3956 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3957 if (!dev->slot || dev->slot != slot)
3960 if (dev->subordinate)
3961 pci_bus_lock(dev->subordinate);
3965 /* Unlock devices from the bottom of the tree up */
3966 static void pci_slot_unlock(struct pci_slot *slot)
3968 struct pci_dev *dev;
3970 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3971 if (!dev->slot || dev->slot != slot)
3973 if (dev->subordinate)
3974 pci_bus_unlock(dev->subordinate);
3975 pci_dev_unlock(dev);
3979 /* Return 1 on successful lock, 0 on contention */
3980 static int pci_slot_trylock(struct pci_slot *slot)
3982 struct pci_dev *dev;
3984 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3985 if (!dev->slot || dev->slot != slot)
3987 if (!pci_dev_trylock(dev))
3989 if (dev->subordinate) {
3990 if (!pci_bus_trylock(dev->subordinate)) {
3991 pci_dev_unlock(dev);
3999 list_for_each_entry_continue_reverse(dev,
4000 &slot->bus->devices, bus_list) {
4001 if (!dev->slot || dev->slot != slot)
4003 if (dev->subordinate)
4004 pci_bus_unlock(dev->subordinate);
4005 pci_dev_unlock(dev);
4010 /* Save and disable devices from the top of the tree down */
4011 static void pci_bus_save_and_disable(struct pci_bus *bus)
4013 struct pci_dev *dev;
4015 list_for_each_entry(dev, &bus->devices, bus_list) {
4016 pci_dev_save_and_disable(dev);
4017 if (dev->subordinate)
4018 pci_bus_save_and_disable(dev->subordinate);
4023 * Restore devices from top of the tree down - parent bridges need to be
4024 * restored before we can get to subordinate devices.
4026 static void pci_bus_restore(struct pci_bus *bus)
4028 struct pci_dev *dev;
4030 list_for_each_entry(dev, &bus->devices, bus_list) {
4031 pci_dev_restore(dev);
4032 if (dev->subordinate)
4033 pci_bus_restore(dev->subordinate);
4037 /* Save and disable devices from the top of the tree down */
4038 static void pci_slot_save_and_disable(struct pci_slot *slot)
4040 struct pci_dev *dev;
4042 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4043 if (!dev->slot || dev->slot != slot)
4045 pci_dev_save_and_disable(dev);
4046 if (dev->subordinate)
4047 pci_bus_save_and_disable(dev->subordinate);
4052 * Restore devices from top of the tree down - parent bridges need to be
4053 * restored before we can get to subordinate devices.
4055 static void pci_slot_restore(struct pci_slot *slot)
4057 struct pci_dev *dev;
4059 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4060 if (!dev->slot || dev->slot != slot)
4062 pci_dev_restore(dev);
4063 if (dev->subordinate)
4064 pci_bus_restore(dev->subordinate);
4068 static int pci_slot_reset(struct pci_slot *slot, int probe)
4072 if (!slot || !pci_slot_resetable(slot))
4076 pci_slot_lock(slot);
4080 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4083 pci_slot_unlock(slot);
4089 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4090 * @slot: PCI slot to probe
4092 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4094 int pci_probe_reset_slot(struct pci_slot *slot)
4096 return pci_slot_reset(slot, 1);
4098 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4101 * pci_reset_slot - reset a PCI slot
4102 * @slot: PCI slot to reset
4104 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4105 * independent of other slots. For instance, some slots may support slot power
4106 * control. In the case of a 1:1 bus to slot architecture, this function may
4107 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4108 * Generally a slot reset should be attempted before a bus reset. All of the
4109 * function of the slot and any subordinate buses behind the slot are reset
4110 * through this function. PCI config space of all devices in the slot and
4111 * behind the slot is saved before and restored after reset.
4113 * Return 0 on success, non-zero on error.
4115 int pci_reset_slot(struct pci_slot *slot)
4119 rc = pci_slot_reset(slot, 1);
4123 pci_slot_save_and_disable(slot);
4125 rc = pci_slot_reset(slot, 0);
4127 pci_slot_restore(slot);
4131 EXPORT_SYMBOL_GPL(pci_reset_slot);
4134 * pci_try_reset_slot - Try to reset a PCI slot
4135 * @slot: PCI slot to reset
4137 * Same as above except return -EAGAIN if the slot cannot be locked
4139 int pci_try_reset_slot(struct pci_slot *slot)
4143 rc = pci_slot_reset(slot, 1);
4147 pci_slot_save_and_disable(slot);
4149 if (pci_slot_trylock(slot)) {
4151 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4152 pci_slot_unlock(slot);
4156 pci_slot_restore(slot);
4160 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4162 static int pci_bus_reset(struct pci_bus *bus, int probe)
4164 if (!bus->self || !pci_bus_resetable(bus))
4174 pci_reset_bridge_secondary_bus(bus->self);
4176 pci_bus_unlock(bus);
4182 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4183 * @bus: PCI bus to probe
4185 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4187 int pci_probe_reset_bus(struct pci_bus *bus)
4189 return pci_bus_reset(bus, 1);
4191 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4194 * pci_reset_bus - reset a PCI bus
4195 * @bus: top level PCI bus to reset
4197 * Do a bus reset on the given bus and any subordinate buses, saving
4198 * and restoring state of all devices.
4200 * Return 0 on success, non-zero on error.
4202 int pci_reset_bus(struct pci_bus *bus)
4206 rc = pci_bus_reset(bus, 1);
4210 pci_bus_save_and_disable(bus);
4212 rc = pci_bus_reset(bus, 0);
4214 pci_bus_restore(bus);
4218 EXPORT_SYMBOL_GPL(pci_reset_bus);
4221 * pci_try_reset_bus - Try to reset a PCI bus
4222 * @bus: top level PCI bus to reset
4224 * Same as above except return -EAGAIN if the bus cannot be locked
4226 int pci_try_reset_bus(struct pci_bus *bus)
4230 rc = pci_bus_reset(bus, 1);
4234 pci_bus_save_and_disable(bus);
4236 if (pci_bus_trylock(bus)) {
4238 pci_reset_bridge_secondary_bus(bus->self);
4239 pci_bus_unlock(bus);
4243 pci_bus_restore(bus);
4247 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4250 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4251 * @dev: PCI device to query
4253 * Returns mmrbc: maximum designed memory read count in bytes
4254 * or appropriate error value.
4256 int pcix_get_max_mmrbc(struct pci_dev *dev)
4261 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4265 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4268 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4270 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4273 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4274 * @dev: PCI device to query
4276 * Returns mmrbc: maximum memory read count in bytes
4277 * or appropriate error value.
4279 int pcix_get_mmrbc(struct pci_dev *dev)
4284 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4288 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4291 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4293 EXPORT_SYMBOL(pcix_get_mmrbc);
4296 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4297 * @dev: PCI device to query
4298 * @mmrbc: maximum memory read count in bytes
4299 * valid values are 512, 1024, 2048, 4096
4301 * If possible sets maximum memory read byte count, some bridges have erratas
4302 * that prevent this.
4304 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4310 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4313 v = ffs(mmrbc) - 10;
4315 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4319 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4322 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4325 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4328 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4330 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4333 cmd &= ~PCI_X_CMD_MAX_READ;
4335 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4340 EXPORT_SYMBOL(pcix_set_mmrbc);
4343 * pcie_get_readrq - get PCI Express read request size
4344 * @dev: PCI device to query
4346 * Returns maximum memory read request in bytes
4347 * or appropriate error value.
4349 int pcie_get_readrq(struct pci_dev *dev)
4353 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4355 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4357 EXPORT_SYMBOL(pcie_get_readrq);
4360 * pcie_set_readrq - set PCI Express maximum memory read request
4361 * @dev: PCI device to query
4362 * @rq: maximum memory read count in bytes
4363 * valid values are 128, 256, 512, 1024, 2048, 4096
4365 * If possible sets maximum memory read request in bytes
4367 int pcie_set_readrq(struct pci_dev *dev, int rq)
4371 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4375 * If using the "performance" PCIe config, we clamp the
4376 * read rq size to the max packet size to prevent the
4377 * host bridge generating requests larger than we can
4380 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4381 int mps = pcie_get_mps(dev);
4387 v = (ffs(rq) - 8) << 12;
4389 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4390 PCI_EXP_DEVCTL_READRQ, v);
4392 EXPORT_SYMBOL(pcie_set_readrq);
4395 * pcie_get_mps - get PCI Express maximum payload size
4396 * @dev: PCI device to query
4398 * Returns maximum payload size in bytes
4400 int pcie_get_mps(struct pci_dev *dev)
4404 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4406 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4408 EXPORT_SYMBOL(pcie_get_mps);
4411 * pcie_set_mps - set PCI Express maximum payload size
4412 * @dev: PCI device to query
4413 * @mps: maximum payload size in bytes
4414 * valid values are 128, 256, 512, 1024, 2048, 4096
4416 * If possible sets maximum payload size
4418 int pcie_set_mps(struct pci_dev *dev, int mps)
4422 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4426 if (v > dev->pcie_mpss)
4430 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4431 PCI_EXP_DEVCTL_PAYLOAD, v);
4433 EXPORT_SYMBOL(pcie_set_mps);
4436 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4437 * @dev: PCI device to query
4438 * @speed: storage for minimum speed
4439 * @width: storage for minimum width
4441 * This function will walk up the PCI device chain and determine the minimum
4442 * link width and speed of the device.
4444 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4445 enum pcie_link_width *width)
4449 *speed = PCI_SPEED_UNKNOWN;
4450 *width = PCIE_LNK_WIDTH_UNKNOWN;
4454 enum pci_bus_speed next_speed;
4455 enum pcie_link_width next_width;
4457 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4461 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4462 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4463 PCI_EXP_LNKSTA_NLW_SHIFT;
4465 if (next_speed < *speed)
4466 *speed = next_speed;
4468 if (next_width < *width)
4469 *width = next_width;
4471 dev = dev->bus->self;
4476 EXPORT_SYMBOL(pcie_get_minimum_link);
4479 * pci_select_bars - Make BAR mask from the type of resource
4480 * @dev: the PCI device for which BAR mask is made
4481 * @flags: resource type mask to be selected
4483 * This helper routine makes bar mask from the type of resource.
4485 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4488 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4489 if (pci_resource_flags(dev, i) & flags)
4493 EXPORT_SYMBOL(pci_select_bars);
4495 /* Some architectures require additional programming to enable VGA */
4496 static arch_set_vga_state_t arch_set_vga_state;
4498 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4500 arch_set_vga_state = func; /* NULL disables */
4503 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4504 unsigned int command_bits, u32 flags)
4506 if (arch_set_vga_state)
4507 return arch_set_vga_state(dev, decode, command_bits,
4513 * pci_set_vga_state - set VGA decode state on device and parents if requested
4514 * @dev: the PCI device
4515 * @decode: true = enable decoding, false = disable decoding
4516 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4517 * @flags: traverse ancestors and change bridges
4518 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4520 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4521 unsigned int command_bits, u32 flags)
4523 struct pci_bus *bus;
4524 struct pci_dev *bridge;
4528 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4530 /* ARCH specific VGA enables */
4531 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4535 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4536 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4538 cmd |= command_bits;
4540 cmd &= ~command_bits;
4541 pci_write_config_word(dev, PCI_COMMAND, cmd);
4544 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4551 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4554 cmd |= PCI_BRIDGE_CTL_VGA;
4556 cmd &= ~PCI_BRIDGE_CTL_VGA;
4557 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4565 bool pci_device_is_present(struct pci_dev *pdev)
4569 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4571 EXPORT_SYMBOL_GPL(pci_device_is_present);
4573 void pci_ignore_hotplug(struct pci_dev *dev)
4575 struct pci_dev *bridge = dev->bus->self;
4577 dev->ignore_hotplug = 1;
4578 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4580 bridge->ignore_hotplug = 1;
4582 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4584 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4585 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4586 static DEFINE_SPINLOCK(resource_alignment_lock);
4589 * pci_specified_resource_alignment - get resource alignment specified by user.
4590 * @dev: the PCI device to get
4592 * RETURNS: Resource alignment if it is specified.
4593 * Zero if it is not specified.
4595 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4597 int seg, bus, slot, func, align_order, count;
4598 resource_size_t align = 0;
4601 spin_lock(&resource_alignment_lock);
4602 p = resource_alignment_param;
4605 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4611 if (sscanf(p, "%x:%x:%x.%x%n",
4612 &seg, &bus, &slot, &func, &count) != 4) {
4614 if (sscanf(p, "%x:%x.%x%n",
4615 &bus, &slot, &func, &count) != 3) {
4616 /* Invalid format */
4617 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4623 if (seg == pci_domain_nr(dev->bus) &&
4624 bus == dev->bus->number &&
4625 slot == PCI_SLOT(dev->devfn) &&
4626 func == PCI_FUNC(dev->devfn)) {
4627 if (align_order == -1)
4630 align = 1 << align_order;
4634 if (*p != ';' && *p != ',') {
4635 /* End of param or invalid format */
4640 spin_unlock(&resource_alignment_lock);
4645 * This function disables memory decoding and releases memory resources
4646 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4647 * It also rounds up size to specified alignment.
4648 * Later on, the kernel will assign page-aligned memory resource back
4651 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4655 resource_size_t align, size;
4658 /* check if specified PCI is target device to reassign */
4659 align = pci_specified_resource_alignment(dev);
4663 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4664 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4666 "Can't reassign resources to host bridge.\n");
4671 "Disabling memory decoding and releasing memory resources.\n");
4672 pci_read_config_word(dev, PCI_COMMAND, &command);
4673 command &= ~PCI_COMMAND_MEMORY;
4674 pci_write_config_word(dev, PCI_COMMAND, command);
4676 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4677 r = &dev->resource[i];
4678 if (!(r->flags & IORESOURCE_MEM))
4680 size = resource_size(r);
4684 "Rounding up size of resource #%d to %#llx.\n",
4685 i, (unsigned long long)size);
4687 r->flags |= IORESOURCE_UNSET;
4691 /* Need to disable bridge's resource window,
4692 * to enable the kernel to reassign new resource
4695 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4696 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4697 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4698 r = &dev->resource[i];
4699 if (!(r->flags & IORESOURCE_MEM))
4701 r->flags |= IORESOURCE_UNSET;
4702 r->end = resource_size(r) - 1;
4705 pci_disable_bridge_window(dev);
4709 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4711 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4712 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4713 spin_lock(&resource_alignment_lock);
4714 strncpy(resource_alignment_param, buf, count);
4715 resource_alignment_param[count] = '\0';
4716 spin_unlock(&resource_alignment_lock);
4720 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4723 spin_lock(&resource_alignment_lock);
4724 count = snprintf(buf, size, "%s", resource_alignment_param);
4725 spin_unlock(&resource_alignment_lock);
4729 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4731 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4734 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4735 const char *buf, size_t count)
4737 return pci_set_resource_alignment_param(buf, count);
4740 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4741 pci_resource_alignment_store);
4743 static int __init pci_resource_alignment_sysfs_init(void)
4745 return bus_create_file(&pci_bus_type,
4746 &bus_attr_resource_alignment);
4748 late_initcall(pci_resource_alignment_sysfs_init);
4750 static void pci_no_domains(void)
4752 #ifdef CONFIG_PCI_DOMAINS
4753 pci_domains_supported = 0;
4757 #ifdef CONFIG_PCI_DOMAINS
4758 static atomic_t __domain_nr = ATOMIC_INIT(-1);
4760 int pci_get_new_domain_nr(void)
4762 return atomic_inc_return(&__domain_nr);
4765 #ifdef CONFIG_PCI_DOMAINS_GENERIC
4766 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
4768 static int use_dt_domains = -1;
4772 domain = of_get_pci_domain_nr(parent->of_node);
4774 * Check DT domain and use_dt_domains values.
4776 * If DT domain property is valid (domain >= 0) and
4777 * use_dt_domains != 0, the DT assignment is valid since this means
4778 * we have not previously allocated a domain number by using
4779 * pci_get_new_domain_nr(); we should also update use_dt_domains to
4780 * 1, to indicate that we have just assigned a domain number from
4783 * If DT domain property value is not valid (ie domain < 0), and we
4784 * have not previously assigned a domain number from DT
4785 * (use_dt_domains != 1) we should assign a domain number by
4788 * pci_get_new_domain_nr()
4790 * API and update the use_dt_domains value to keep track of method we
4791 * are using to assign domain numbers (use_dt_domains = 0).
4793 * All other combinations imply we have a platform that is trying
4794 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
4795 * which is a recipe for domain mishandling and it is prevented by
4796 * invalidating the domain value (domain = -1) and printing a
4797 * corresponding error.
4799 if (domain >= 0 && use_dt_domains) {
4801 } else if (domain < 0 && use_dt_domains != 1) {
4803 domain = pci_get_new_domain_nr();
4805 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
4806 parent->of_node->full_name);
4810 bus->domain_nr = domain;
4816 * pci_ext_cfg_avail - can we access extended PCI config space?
4818 * Returns 1 if we can access PCI extended config space (offsets
4819 * greater than 0xff). This is the default implementation. Architecture
4820 * implementations can override this.
4822 int __weak pci_ext_cfg_avail(void)
4827 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4830 EXPORT_SYMBOL(pci_fixup_cardbus);
4832 static int __init pci_setup(char *str)
4835 char *k = strchr(str, ',');
4838 if (*str && (str = pcibios_setup(str)) && *str) {
4839 if (!strcmp(str, "nomsi")) {
4841 } else if (!strcmp(str, "noaer")) {
4843 } else if (!strncmp(str, "realloc=", 8)) {
4844 pci_realloc_get_opt(str + 8);
4845 } else if (!strncmp(str, "realloc", 7)) {
4846 pci_realloc_get_opt("on");
4847 } else if (!strcmp(str, "nodomains")) {
4849 } else if (!strncmp(str, "noari", 5)) {
4850 pcie_ari_disabled = true;
4851 } else if (!strncmp(str, "cbiosize=", 9)) {
4852 pci_cardbus_io_size = memparse(str + 9, &str);
4853 } else if (!strncmp(str, "cbmemsize=", 10)) {
4854 pci_cardbus_mem_size = memparse(str + 10, &str);
4855 } else if (!strncmp(str, "resource_alignment=", 19)) {
4856 pci_set_resource_alignment_param(str + 19,
4858 } else if (!strncmp(str, "ecrc=", 5)) {
4859 pcie_ecrc_get_policy(str + 5);
4860 } else if (!strncmp(str, "hpiosize=", 9)) {
4861 pci_hotplug_io_size = memparse(str + 9, &str);
4862 } else if (!strncmp(str, "hpmemsize=", 10)) {
4863 pci_hotplug_mem_size = memparse(str + 10, &str);
4864 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4865 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4866 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4867 pcie_bus_config = PCIE_BUS_SAFE;
4868 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4869 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4870 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4871 pcie_bus_config = PCIE_BUS_PEER2PEER;
4872 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4873 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4875 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4883 early_param("pci", pci_setup);