1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/acpi_iort.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
29 static int pci_msi_enable = 1;
30 int pci_msi_ignore_mask;
32 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
34 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
35 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
37 struct irq_domain *domain;
39 domain = dev_get_msi_domain(&dev->dev);
40 if (domain && irq_domain_is_hierarchy(domain))
41 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
43 return arch_setup_msi_irqs(dev, nvec, type);
46 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
48 struct irq_domain *domain;
50 domain = dev_get_msi_domain(&dev->dev);
51 if (domain && irq_domain_is_hierarchy(domain))
52 msi_domain_free_irqs(domain, &dev->dev);
54 arch_teardown_msi_irqs(dev);
57 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
58 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
63 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
65 struct msi_controller *chip = dev->bus->msi;
68 if (!chip || !chip->setup_irq)
71 err = chip->setup_irq(chip, dev, desc);
75 irq_set_chip_data(desc->irq, chip);
80 void __weak arch_teardown_msi_irq(unsigned int irq)
82 struct msi_controller *chip = irq_get_chip_data(irq);
84 if (!chip || !chip->teardown_irq)
87 chip->teardown_irq(chip, irq);
90 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
92 struct msi_controller *chip = dev->bus->msi;
93 struct msi_desc *entry;
96 if (chip && chip->setup_irqs)
97 return chip->setup_irqs(chip, dev, nvec, type);
99 * If an architecture wants to support multiple MSI, it needs to
100 * override arch_setup_msi_irqs()
102 if (type == PCI_CAP_ID_MSI && nvec > 1)
105 for_each_pci_msi_entry(entry, dev) {
106 ret = arch_setup_msi_irq(dev, entry);
117 * We have a default implementation available as a separate non-weak
118 * function, as it is used by the Xen x86 PCI code
120 void default_teardown_msi_irqs(struct pci_dev *dev)
123 struct msi_desc *entry;
125 for_each_pci_msi_entry(entry, dev)
127 for (i = 0; i < entry->nvec_used; i++)
128 arch_teardown_msi_irq(entry->irq + i);
131 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
133 return default_teardown_msi_irqs(dev);
136 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
138 struct msi_desc *entry;
141 if (dev->msix_enabled) {
142 for_each_pci_msi_entry(entry, dev) {
143 if (irq == entry->irq)
146 } else if (dev->msi_enabled) {
147 entry = irq_get_msi_desc(irq);
151 __pci_write_msi_msg(entry, &entry->msg);
154 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
156 return default_restore_msi_irqs(dev);
159 static inline __attribute_const__ u32 msi_mask(unsigned x)
161 /* Don't shift by >= width of type */
164 return (1 << (1 << x)) - 1;
168 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
169 * mask all MSI interrupts by clearing the MSI enable bit does not work
170 * reliably as devices without an INTx disable bit will then generate a
171 * level IRQ which will never be cleared.
173 void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
175 raw_spinlock_t *lock = &desc->dev->msi_lock;
178 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
181 raw_spin_lock_irqsave(lock, flags);
182 desc->masked &= ~mask;
183 desc->masked |= flag;
184 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
186 raw_spin_unlock_irqrestore(lock, flags);
189 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
191 __pci_msi_desc_mask_irq(desc, mask, flag);
194 static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
196 if (desc->msi_attrib.is_virtual)
199 return desc->mask_base +
200 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
204 * This internal function does not flush PCI writes to the device.
205 * All users must ensure that they read from the device before either
206 * assuming that the device state is up to date, or returning out of this
207 * file. This saves a few milliseconds when initialising devices with lots
208 * of MSI-X interrupts.
210 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
212 u32 mask_bits = desc->masked;
213 void __iomem *desc_addr;
215 if (pci_msi_ignore_mask)
218 desc_addr = pci_msix_desc_addr(desc);
222 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
223 if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
224 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
226 writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
231 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
233 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
236 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
238 struct msi_desc *desc = irq_data_get_msi_desc(data);
240 if (desc->msi_attrib.is_msix) {
241 msix_mask_irq(desc, flag);
242 readl(desc->mask_base); /* Flush write to device */
244 unsigned offset = data->irq - desc->irq;
245 msi_mask_irq(desc, 1 << offset, flag << offset);
250 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
251 * @data: pointer to irqdata associated to that interrupt
253 void pci_msi_mask_irq(struct irq_data *data)
255 msi_set_mask_bit(data, 1);
257 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
260 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
261 * @data: pointer to irqdata associated to that interrupt
263 void pci_msi_unmask_irq(struct irq_data *data)
265 msi_set_mask_bit(data, 0);
267 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
269 void default_restore_msi_irqs(struct pci_dev *dev)
271 struct msi_desc *entry;
273 for_each_pci_msi_entry(entry, dev)
274 default_restore_msi_irq(dev, entry->irq);
277 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
279 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
281 BUG_ON(dev->current_state != PCI_D0);
283 if (entry->msi_attrib.is_msix) {
284 void __iomem *base = pci_msix_desc_addr(entry);
291 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
292 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
293 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
295 int pos = dev->msi_cap;
298 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
300 if (entry->msi_attrib.is_64) {
301 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
303 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
306 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
312 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
314 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
316 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
317 /* Don't touch the hardware now */
318 } else if (entry->msi_attrib.is_msix) {
319 void __iomem *base = pci_msix_desc_addr(entry);
320 bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
326 * The specification mandates that the entry is masked
327 * when the message is modified:
329 * "If software changes the Address or Data value of an
330 * entry while the entry is unmasked, the result is
334 __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
336 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
337 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
338 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
341 __pci_msix_desc_mask_irq(entry, 0);
343 /* Ensure that the writes are visible in the device */
344 readl(base + PCI_MSIX_ENTRY_DATA);
346 int pos = dev->msi_cap;
349 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
350 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
351 msgctl |= entry->msi_attrib.multiple << 4;
352 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
354 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
356 if (entry->msi_attrib.is_64) {
357 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
359 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
362 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
365 /* Ensure that the writes are visible in the device */
366 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
372 if (entry->write_msi_msg)
373 entry->write_msi_msg(entry, entry->write_msi_msg_data);
377 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
379 struct msi_desc *entry = irq_get_msi_desc(irq);
381 __pci_write_msi_msg(entry, msg);
383 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
385 static void free_msi_irqs(struct pci_dev *dev)
387 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
388 struct msi_desc *entry, *tmp;
389 struct attribute **msi_attrs;
390 struct device_attribute *dev_attr;
393 for_each_pci_msi_entry(entry, dev)
395 for (i = 0; i < entry->nvec_used; i++)
396 BUG_ON(irq_has_action(entry->irq + i));
398 if (dev->msi_irq_groups) {
399 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
400 msi_attrs = dev->msi_irq_groups[0]->attrs;
401 while (msi_attrs[count]) {
402 dev_attr = container_of(msi_attrs[count],
403 struct device_attribute, attr);
404 kfree(dev_attr->attr.name);
409 kfree(dev->msi_irq_groups[0]);
410 kfree(dev->msi_irq_groups);
411 dev->msi_irq_groups = NULL;
414 pci_msi_teardown_msi_irqs(dev);
416 list_for_each_entry_safe(entry, tmp, msi_list, list) {
417 if (entry->msi_attrib.is_msix) {
418 if (list_is_last(&entry->list, msi_list))
419 iounmap(entry->mask_base);
422 list_del(&entry->list);
423 free_msi_entry(entry);
427 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
429 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
430 pci_intx(dev, enable);
433 static void __pci_restore_msi_state(struct pci_dev *dev)
436 struct msi_desc *entry;
438 if (!dev->msi_enabled)
441 entry = irq_get_msi_desc(dev->irq);
443 pci_intx_for_msi(dev, 0);
444 pci_msi_set_enable(dev, 0);
445 arch_restore_msi_irqs(dev);
447 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
448 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
450 control &= ~PCI_MSI_FLAGS_QSIZE;
451 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
452 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
455 static void __pci_restore_msix_state(struct pci_dev *dev)
457 struct msi_desc *entry;
459 if (!dev->msix_enabled)
461 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
463 /* route the table */
464 pci_intx_for_msi(dev, 0);
465 pci_msix_clear_and_set_ctrl(dev, 0,
466 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
468 arch_restore_msi_irqs(dev);
469 for_each_pci_msi_entry(entry, dev)
470 msix_mask_irq(entry, entry->masked);
472 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
475 void pci_restore_msi_state(struct pci_dev *dev)
477 __pci_restore_msi_state(dev);
478 __pci_restore_msix_state(dev);
480 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
482 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
485 struct msi_desc *entry;
489 retval = kstrtoul(attr->attr.name, 10, &irq);
493 entry = irq_get_msi_desc(irq);
495 return sprintf(buf, "%s\n",
496 entry->msi_attrib.is_msix ? "msix" : "msi");
501 static int populate_msi_sysfs(struct pci_dev *pdev)
503 struct attribute **msi_attrs;
504 struct attribute *msi_attr;
505 struct device_attribute *msi_dev_attr;
506 struct attribute_group *msi_irq_group;
507 const struct attribute_group **msi_irq_groups;
508 struct msi_desc *entry;
514 /* Determine how many msi entries we have */
515 for_each_pci_msi_entry(entry, pdev)
516 num_msi += entry->nvec_used;
520 /* Dynamically create the MSI attributes for the PCI device */
521 msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
524 for_each_pci_msi_entry(entry, pdev) {
525 for (i = 0; i < entry->nvec_used; i++) {
526 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
529 msi_attrs[count] = &msi_dev_attr->attr;
531 sysfs_attr_init(&msi_dev_attr->attr);
532 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
534 if (!msi_dev_attr->attr.name)
536 msi_dev_attr->attr.mode = S_IRUGO;
537 msi_dev_attr->show = msi_mode_show;
542 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
545 msi_irq_group->name = "msi_irqs";
546 msi_irq_group->attrs = msi_attrs;
548 msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
550 goto error_irq_group;
551 msi_irq_groups[0] = msi_irq_group;
553 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
555 goto error_irq_groups;
556 pdev->msi_irq_groups = msi_irq_groups;
561 kfree(msi_irq_groups);
563 kfree(msi_irq_group);
566 msi_attr = msi_attrs[count];
568 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
569 kfree(msi_attr->name);
572 msi_attr = msi_attrs[count];
578 static struct msi_desc *
579 msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
581 struct irq_affinity_desc *masks = NULL;
582 struct msi_desc *entry;
586 masks = irq_create_affinity_masks(nvec, affd);
588 /* MSI Entry Initialization */
589 entry = alloc_msi_entry(&dev->dev, nvec, masks);
593 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
594 /* Lies, damned lies, and MSIs */
595 if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
596 control |= PCI_MSI_FLAGS_MASKBIT;
598 entry->msi_attrib.is_msix = 0;
599 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
600 entry->msi_attrib.is_virtual = 0;
601 entry->msi_attrib.entry_nr = 0;
602 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
603 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
604 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
605 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
607 if (control & PCI_MSI_FLAGS_64BIT)
608 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
610 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
612 /* Save the initial mask status */
613 if (entry->msi_attrib.maskbit)
614 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
621 static int msi_verify_entries(struct pci_dev *dev)
623 struct msi_desc *entry;
625 for_each_pci_msi_entry(entry, dev) {
626 if (!dev->no_64bit_msi || !entry->msg.address_hi)
628 pci_err(dev, "Device has broken 64-bit MSI but arch"
629 " tried to assign one above 4G\n");
636 * msi_capability_init - configure device's MSI capability structure
637 * @dev: pointer to the pci_dev data structure of MSI device function
638 * @nvec: number of interrupts to allocate
639 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
641 * Setup the MSI capability structure of the device with the requested
642 * number of interrupts. A return value of zero indicates the successful
643 * setup of an entry with the new MSI IRQ. A negative return value indicates
644 * an error, and a positive return value indicates the number of interrupts
645 * which could have been allocated.
647 static int msi_capability_init(struct pci_dev *dev, int nvec,
648 struct irq_affinity *affd)
650 struct msi_desc *entry;
654 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
656 entry = msi_setup_entry(dev, nvec, affd);
660 /* All MSIs are unmasked by default; mask them all */
661 mask = msi_mask(entry->msi_attrib.multi_cap);
662 msi_mask_irq(entry, mask, mask);
664 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
666 /* Configure MSI capability structure */
667 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
669 msi_mask_irq(entry, mask, 0);
674 ret = msi_verify_entries(dev);
676 msi_mask_irq(entry, mask, 0);
681 ret = populate_msi_sysfs(dev);
683 msi_mask_irq(entry, mask, 0);
688 /* Set MSI enabled bits */
689 pci_intx_for_msi(dev, 0);
690 pci_msi_set_enable(dev, 1);
691 dev->msi_enabled = 1;
693 pcibios_free_irq(dev);
694 dev->irq = entry->irq;
698 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
700 resource_size_t phys_addr;
705 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
707 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
708 flags = pci_resource_flags(dev, bir);
709 if (!flags || (flags & IORESOURCE_UNSET))
712 table_offset &= PCI_MSIX_TABLE_OFFSET;
713 phys_addr = pci_resource_start(dev, bir) + table_offset;
715 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
718 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
719 struct msix_entry *entries, int nvec,
720 struct irq_affinity *affd)
722 struct irq_affinity_desc *curmsk, *masks = NULL;
723 struct msi_desc *entry;
726 int vec_count = pci_msix_vec_count(dev);
729 masks = irq_create_affinity_masks(nvec, affd);
731 for (i = 0, curmsk = masks; i < nvec; i++) {
732 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
738 /* No enough memory. Don't try again */
743 entry->msi_attrib.is_msix = 1;
744 entry->msi_attrib.is_64 = 1;
747 entry->msi_attrib.entry_nr = entries[i].entry;
749 entry->msi_attrib.entry_nr = i;
751 entry->msi_attrib.is_virtual =
752 entry->msi_attrib.entry_nr >= vec_count;
754 entry->msi_attrib.default_irq = dev->irq;
755 entry->mask_base = base;
757 addr = pci_msix_desc_addr(entry);
759 entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
761 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
771 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
773 struct msi_desc *entry;
775 for_each_pci_msi_entry(entry, dev) {
777 entries->vector = entry->irq;
783 static void msix_mask_all(void __iomem *base, int tsize)
785 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
788 if (pci_msi_ignore_mask)
791 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
792 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
796 * msix_capability_init - configure device's MSI-X capability
797 * @dev: pointer to the pci_dev data structure of MSI-X device function
798 * @entries: pointer to an array of struct msix_entry entries
799 * @nvec: number of @entries
800 * @affd: Optional pointer to enable automatic affinity assignment
802 * Setup the MSI-X capability structure of device function with a
803 * single MSI-X IRQ. A return of zero indicates the successful setup of
804 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
806 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
807 int nvec, struct irq_affinity *affd)
814 * Some devices require MSI-X to be enabled before the MSI-X
815 * registers can be accessed. Mask all the vectors to prevent
816 * interrupts coming in before they're fully set up.
818 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
819 PCI_MSIX_FLAGS_ENABLE);
821 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
822 /* Request & Map MSI-X table region */
823 tsize = msix_table_size(control);
824 base = msix_map_region(dev, tsize);
830 ret = msix_setup_entries(dev, base, entries, nvec, affd);
834 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
838 /* Check if all MSI entries honor device restrictions */
839 ret = msi_verify_entries(dev);
843 msix_update_entries(dev, entries);
845 ret = populate_msi_sysfs(dev);
849 /* Set MSI-X enabled bits and unmask the function */
850 pci_intx_for_msi(dev, 0);
851 dev->msix_enabled = 1;
854 * Ensure that all table entries are masked to prevent
855 * stale entries from firing in a crash kernel.
857 * Done late to deal with a broken Marvell NVME device
858 * which takes the MSI-X mask bits into account even
859 * when MSI-X is disabled, which prevents MSI delivery.
861 msix_mask_all(base, tsize);
862 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
864 pcibios_free_irq(dev);
870 * If we had some success, report the number of IRQs
871 * we succeeded in setting up.
873 struct msi_desc *entry;
876 for_each_pci_msi_entry(entry, dev) {
888 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
894 * pci_msi_supported - check whether MSI may be enabled on a device
895 * @dev: pointer to the pci_dev data structure of MSI device function
896 * @nvec: how many MSIs have been requested?
898 * Look at global flags, the device itself, and its parent buses
899 * to determine if MSI/-X are supported for the device. If MSI/-X is
900 * supported return 1, else return 0.
902 static int pci_msi_supported(struct pci_dev *dev, int nvec)
906 /* MSI must be globally enabled and supported by the device */
910 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
914 * You can't ask to have 0 or less MSIs configured.
916 * b) the list manipulation code assumes nvec >= 1.
922 * Any bridge which does NOT route MSI transactions from its
923 * secondary bus to its primary bus must set NO_MSI flag on
924 * the secondary pci_bus.
925 * We expect only arch-specific PCI host bus controller driver
926 * or quirks for specific PCI bridges to be setting NO_MSI.
928 for (bus = dev->bus; bus; bus = bus->parent)
929 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
936 * pci_msi_vec_count - Return the number of MSI vectors a device can send
937 * @dev: device to report about
939 * This function returns the number of MSI vectors a device requested via
940 * Multiple Message Capable register. It returns a negative errno if the
941 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
942 * and returns a power of two, up to a maximum of 2^5 (32), according to the
945 int pci_msi_vec_count(struct pci_dev *dev)
953 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
954 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
958 EXPORT_SYMBOL(pci_msi_vec_count);
960 static void pci_msi_shutdown(struct pci_dev *dev)
962 struct msi_desc *desc;
965 if (!pci_msi_enable || !dev || !dev->msi_enabled)
968 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
969 desc = first_pci_msi_entry(dev);
971 pci_msi_set_enable(dev, 0);
972 pci_intx_for_msi(dev, 1);
973 dev->msi_enabled = 0;
975 /* Return the device with MSI unmasked as initial states */
976 mask = msi_mask(desc->msi_attrib.multi_cap);
977 msi_mask_irq(desc, mask, 0);
979 /* Restore dev->irq to its default pin-assertion IRQ */
980 dev->irq = desc->msi_attrib.default_irq;
981 pcibios_alloc_irq(dev);
984 void pci_disable_msi(struct pci_dev *dev)
986 if (!pci_msi_enable || !dev || !dev->msi_enabled)
989 pci_msi_shutdown(dev);
992 EXPORT_SYMBOL(pci_disable_msi);
995 * pci_msix_vec_count - return the number of device's MSI-X table entries
996 * @dev: pointer to the pci_dev data structure of MSI-X device function
997 * This function returns the number of device's MSI-X table entries and
998 * therefore the number of MSI-X vectors device is capable of sending.
999 * It returns a negative errno if the device is not capable of sending MSI-X
1002 int pci_msix_vec_count(struct pci_dev *dev)
1009 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
1010 return msix_table_size(control);
1012 EXPORT_SYMBOL(pci_msix_vec_count);
1014 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
1015 int nvec, struct irq_affinity *affd, int flags)
1020 if (!pci_msi_supported(dev, nvec))
1023 nr_entries = pci_msix_vec_count(dev);
1026 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
1030 /* Check for any invalid entries */
1031 for (i = 0; i < nvec; i++) {
1032 if (entries[i].entry >= nr_entries)
1033 return -EINVAL; /* invalid entry */
1034 for (j = i + 1; j < nvec; j++) {
1035 if (entries[i].entry == entries[j].entry)
1036 return -EINVAL; /* duplicate entry */
1041 /* Check whether driver already requested for MSI IRQ */
1042 if (dev->msi_enabled) {
1043 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
1046 return msix_capability_init(dev, entries, nvec, affd);
1049 static void pci_msix_shutdown(struct pci_dev *dev)
1051 struct msi_desc *entry;
1053 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1056 if (pci_dev_is_disconnected(dev)) {
1057 dev->msix_enabled = 0;
1061 /* Return the device with MSI-X masked as initial states */
1062 for_each_pci_msi_entry(entry, dev)
1063 __pci_msix_desc_mask_irq(entry, 1);
1065 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1066 pci_intx_for_msi(dev, 1);
1067 dev->msix_enabled = 0;
1068 pcibios_alloc_irq(dev);
1071 void pci_disable_msix(struct pci_dev *dev)
1073 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1076 pci_msix_shutdown(dev);
1079 EXPORT_SYMBOL(pci_disable_msix);
1081 void pci_no_msi(void)
1087 * pci_msi_enabled - is MSI enabled?
1089 * Returns true if MSI has not been disabled by the command-line option
1092 int pci_msi_enabled(void)
1094 return pci_msi_enable;
1096 EXPORT_SYMBOL(pci_msi_enabled);
1098 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1099 struct irq_affinity *affd)
1104 if (!pci_msi_supported(dev, minvec))
1107 /* Check whether driver already requested MSI-X IRQs */
1108 if (dev->msix_enabled) {
1109 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
1113 if (maxvec < minvec)
1116 if (WARN_ON_ONCE(dev->msi_enabled))
1119 nvec = pci_msi_vec_count(dev);
1130 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1135 rc = msi_capability_init(dev, nvec, affd);
1148 /* deprecated, don't use */
1149 int pci_enable_msi(struct pci_dev *dev)
1151 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
1156 EXPORT_SYMBOL(pci_enable_msi);
1158 static int __pci_enable_msix_range(struct pci_dev *dev,
1159 struct msix_entry *entries, int minvec,
1160 int maxvec, struct irq_affinity *affd,
1163 int rc, nvec = maxvec;
1165 if (maxvec < minvec)
1168 if (WARN_ON_ONCE(dev->msix_enabled))
1173 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1178 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
1192 * pci_enable_msix_range - configure device's MSI-X capability structure
1193 * @dev: pointer to the pci_dev data structure of MSI-X device function
1194 * @entries: pointer to an array of MSI-X entries
1195 * @minvec: minimum number of MSI-X IRQs requested
1196 * @maxvec: maximum number of MSI-X IRQs requested
1198 * Setup the MSI-X capability structure of device function with a maximum
1199 * possible number of interrupts in the range between @minvec and @maxvec
1200 * upon its software driver call to request for MSI-X mode enabled on its
1201 * hardware device function. It returns a negative errno if an error occurs.
1202 * If it succeeds, it returns the actual number of interrupts allocated and
1203 * indicates the successful configuration of MSI-X capability structure
1204 * with new allocated MSI-X interrupts.
1206 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1207 int minvec, int maxvec)
1209 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
1211 EXPORT_SYMBOL(pci_enable_msix_range);
1214 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1215 * @dev: PCI device to operate on
1216 * @min_vecs: minimum number of vectors required (must be >= 1)
1217 * @max_vecs: maximum (desired) number of vectors
1218 * @flags: flags or quirks for the allocation
1219 * @affd: optional description of the affinity requirements
1221 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1222 * vectors if available, and fall back to a single legacy vector
1223 * if neither is available. Return the number of vectors allocated,
1224 * (which might be smaller than @max_vecs) if successful, or a negative
1225 * error code on error. If less than @min_vecs interrupt vectors are
1226 * available for @dev the function will fail with -ENOSPC.
1228 * To get the Linux IRQ number used for a vector that can be passed to
1229 * request_irq() use the pci_irq_vector() helper.
1231 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1232 unsigned int max_vecs, unsigned int flags,
1233 struct irq_affinity *affd)
1235 struct irq_affinity msi_default_affd = {0};
1236 int msix_vecs = -ENOSPC;
1237 int msi_vecs = -ENOSPC;
1239 if (flags & PCI_IRQ_AFFINITY) {
1241 affd = &msi_default_affd;
1247 if (flags & PCI_IRQ_MSIX) {
1248 msix_vecs = __pci_enable_msix_range(dev, NULL, min_vecs,
1249 max_vecs, affd, flags);
1254 if (flags & PCI_IRQ_MSI) {
1255 msi_vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs,
1261 /* use legacy IRQ if allowed */
1262 if (flags & PCI_IRQ_LEGACY) {
1263 if (min_vecs == 1 && dev->irq) {
1265 * Invoke the affinity spreading logic to ensure that
1266 * the device driver can adjust queue configuration
1267 * for the single interrupt case.
1270 irq_create_affinity_masks(1, affd);
1276 if (msix_vecs == -ENOSPC)
1280 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1283 * pci_free_irq_vectors - free previously allocated IRQs for a device
1284 * @dev: PCI device to operate on
1286 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1288 void pci_free_irq_vectors(struct pci_dev *dev)
1290 pci_disable_msix(dev);
1291 pci_disable_msi(dev);
1293 EXPORT_SYMBOL(pci_free_irq_vectors);
1296 * pci_irq_vector - return Linux IRQ number of a device vector
1297 * @dev: PCI device to operate on
1298 * @nr: Interrupt vector index (0-based)
1300 * @nr has the following meanings depending on the interrupt mode:
1301 * MSI-X: The index in the MSI-X vector table
1302 * MSI: The index of the enabled MSI vectors
1305 * Return: The Linux interrupt number or -EINVAl if @nr is out of range.
1307 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1309 if (dev->msix_enabled) {
1310 struct msi_desc *entry;
1312 for_each_pci_msi_entry(entry, dev) {
1313 if (entry->msi_attrib.entry_nr == nr)
1320 if (dev->msi_enabled) {
1321 struct msi_desc *entry = first_pci_msi_entry(dev);
1323 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1326 if (WARN_ON_ONCE(nr > 0))
1330 return dev->irq + nr;
1332 EXPORT_SYMBOL(pci_irq_vector);
1335 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1336 * @dev: PCI device to operate on
1337 * @nr: device-relative interrupt vector index (0-based).
1339 * @nr has the following meanings depending on the interrupt mode:
1340 * MSI-X: The index in the MSI-X vector table
1341 * MSI: The index of the enabled MSI vectors
1344 * Return: A cpumask pointer or NULL if @nr is out of range
1346 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1348 if (dev->msix_enabled) {
1349 struct msi_desc *entry;
1351 for_each_pci_msi_entry(entry, dev) {
1352 if (entry->msi_attrib.entry_nr == nr)
1353 return &entry->affinity->mask;
1357 } else if (dev->msi_enabled) {
1358 struct msi_desc *entry = first_pci_msi_entry(dev);
1360 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1361 nr >= entry->nvec_used))
1364 return &entry->affinity[nr].mask;
1366 return cpu_possible_mask;
1369 EXPORT_SYMBOL(pci_irq_get_affinity);
1372 * pci_irq_get_node - return the NUMA node of a particular MSI vector
1373 * @pdev: PCI device to operate on
1374 * @vec: device-relative interrupt vector index (0-based).
1376 int pci_irq_get_node(struct pci_dev *pdev, int vec)
1378 const struct cpumask *mask;
1380 mask = pci_irq_get_affinity(pdev, vec);
1382 return local_memory_node(cpu_to_node(cpumask_first(mask)));
1383 return dev_to_node(&pdev->dev);
1385 EXPORT_SYMBOL(pci_irq_get_node);
1387 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1389 return to_pci_dev(desc->dev);
1391 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1393 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1395 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1397 return dev->bus->sysdata;
1399 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1401 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1403 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1404 * @irq_data: Pointer to interrupt data of the MSI interrupt
1405 * @msg: Pointer to the message
1407 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1409 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1412 * For MSI-X desc->irq is always equal to irq_data->irq. For
1413 * MSI only the first interrupt of MULTI MSI passes the test.
1415 if (desc->irq == irq_data->irq)
1416 __pci_write_msi_msg(desc, msg);
1420 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1421 * @dev: Pointer to the PCI device
1422 * @desc: Pointer to the MSI descriptor
1424 * The ID number is only used within the irqdomain.
1426 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1427 struct msi_desc *desc)
1429 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1430 pci_dev_id(dev) << 11 |
1431 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1434 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1436 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1440 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1442 * @domain: The interrupt domain to check
1443 * @info: The domain info for verification
1444 * @dev: The device to check
1447 * 0 if the functionality is supported
1448 * 1 if Multi MSI is requested, but the domain does not support it
1449 * -ENOTSUPP otherwise
1451 int pci_msi_domain_check_cap(struct irq_domain *domain,
1452 struct msi_domain_info *info, struct device *dev)
1454 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1456 /* Special handling to support __pci_enable_msi_range() */
1457 if (pci_msi_desc_is_multi_msi(desc) &&
1458 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1460 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1466 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1467 struct msi_desc *desc, int error)
1469 /* Special handling to support __pci_enable_msi_range() */
1470 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1476 #ifdef GENERIC_MSI_DOMAIN_OPS
1477 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1478 struct msi_desc *desc)
1481 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1485 #define pci_msi_domain_set_desc NULL
1488 static struct msi_domain_ops pci_msi_domain_ops_default = {
1489 .set_desc = pci_msi_domain_set_desc,
1490 .msi_check = pci_msi_domain_check_cap,
1491 .handle_error = pci_msi_domain_handle_error,
1494 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1496 struct msi_domain_ops *ops = info->ops;
1499 info->ops = &pci_msi_domain_ops_default;
1501 if (ops->set_desc == NULL)
1502 ops->set_desc = pci_msi_domain_set_desc;
1503 if (ops->msi_check == NULL)
1504 ops->msi_check = pci_msi_domain_check_cap;
1505 if (ops->handle_error == NULL)
1506 ops->handle_error = pci_msi_domain_handle_error;
1510 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1512 struct irq_chip *chip = info->chip;
1515 if (!chip->irq_write_msi_msg)
1516 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1517 if (!chip->irq_mask)
1518 chip->irq_mask = pci_msi_mask_irq;
1519 if (!chip->irq_unmask)
1520 chip->irq_unmask = pci_msi_unmask_irq;
1524 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1525 * @fwnode: Optional fwnode of the interrupt controller
1526 * @info: MSI domain info
1527 * @parent: Parent irq domain
1529 * Updates the domain and chip ops and creates a MSI interrupt domain.
1532 * A domain pointer or NULL in case of failure.
1534 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1535 struct msi_domain_info *info,
1536 struct irq_domain *parent)
1538 struct irq_domain *domain;
1540 if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
1541 info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
1543 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1544 pci_msi_domain_update_dom_ops(info);
1545 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1546 pci_msi_domain_update_chip_ops(info);
1548 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1549 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
1550 info->flags |= MSI_FLAG_MUST_REACTIVATE;
1552 /* PCI-MSI is oneshot-safe */
1553 info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
1555 domain = msi_create_irq_domain(fwnode, info, parent);
1559 irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
1562 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1565 * Users of the generic MSI infrastructure expect a device to have a single ID,
1566 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1567 * DMA phantom functions tend to still emit MSIs from the real function number,
1568 * so we ignore those and only consider topological aliases where either the
1569 * alias device or RID appears on a different bus number. We also make the
1570 * reasonable assumption that bridges are walked in an upstream direction (so
1571 * the last one seen wins), and the much braver assumption that the most likely
1572 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1573 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1574 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1575 * for taking ownership all we can really do is close our eyes and hope...
1577 static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1580 u8 bus = PCI_BUS_NUM(*pa);
1582 if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
1589 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1590 * @domain: The interrupt domain
1591 * @pdev: The PCI device.
1593 * The RID for a device is formed from the alias, with a firmware
1594 * supplied mapping applied
1598 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1600 struct device_node *of_node;
1601 u32 rid = pci_dev_id(pdev);
1603 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1605 of_node = irq_domain_get_of_node(domain);
1606 rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) :
1607 iort_msi_map_rid(&pdev->dev, rid);
1613 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1614 * @pdev: The PCI device
1616 * Use the firmware data to find a device-specific MSI domain
1617 * (i.e. not one that is set as a default).
1619 * Returns: The corresponding MSI domain or NULL if none has been found.
1621 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1623 struct irq_domain *dom;
1624 u32 rid = pci_dev_id(pdev);
1626 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1627 dom = of_msi_map_get_device_domain(&pdev->dev, rid);
1629 dom = iort_get_device_domain(&pdev->dev, rid);
1632 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */