3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/acpi_iort.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
29 static int pci_msi_enable = 1;
30 int pci_msi_ignore_mask;
32 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
34 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
35 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
37 struct irq_domain *domain;
39 domain = dev_get_msi_domain(&dev->dev);
40 if (domain && irq_domain_is_hierarchy(domain))
41 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
43 return arch_setup_msi_irqs(dev, nvec, type);
46 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
48 struct irq_domain *domain;
50 domain = dev_get_msi_domain(&dev->dev);
51 if (domain && irq_domain_is_hierarchy(domain))
52 msi_domain_free_irqs(domain, &dev->dev);
54 arch_teardown_msi_irqs(dev);
57 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
58 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
63 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
65 struct msi_controller *chip = dev->bus->msi;
68 if (!chip || !chip->setup_irq)
71 err = chip->setup_irq(chip, dev, desc);
75 irq_set_chip_data(desc->irq, chip);
80 void __weak arch_teardown_msi_irq(unsigned int irq)
82 struct msi_controller *chip = irq_get_chip_data(irq);
84 if (!chip || !chip->teardown_irq)
87 chip->teardown_irq(chip, irq);
90 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
92 struct msi_controller *chip = dev->bus->msi;
93 struct msi_desc *entry;
96 if (chip && chip->setup_irqs)
97 return chip->setup_irqs(chip, dev, nvec, type);
99 * If an architecture wants to support multiple MSI, it needs to
100 * override arch_setup_msi_irqs()
102 if (type == PCI_CAP_ID_MSI && nvec > 1)
105 for_each_pci_msi_entry(entry, dev) {
106 ret = arch_setup_msi_irq(dev, entry);
117 * We have a default implementation available as a separate non-weak
118 * function, as it is used by the Xen x86 PCI code
120 void default_teardown_msi_irqs(struct pci_dev *dev)
123 struct msi_desc *entry;
125 for_each_pci_msi_entry(entry, dev)
127 for (i = 0; i < entry->nvec_used; i++)
128 arch_teardown_msi_irq(entry->irq + i);
131 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
133 return default_teardown_msi_irqs(dev);
136 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
138 struct msi_desc *entry;
141 if (dev->msix_enabled) {
142 for_each_pci_msi_entry(entry, dev) {
143 if (irq == entry->irq)
146 } else if (dev->msi_enabled) {
147 entry = irq_get_msi_desc(irq);
151 __pci_write_msi_msg(entry, &entry->msg);
154 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
156 return default_restore_msi_irqs(dev);
159 static inline __attribute_const__ u32 msi_mask(unsigned x)
161 /* Don't shift by >= width of type */
164 return (1 << (1 << x)) - 1;
168 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
169 * mask all MSI interrupts by clearing the MSI enable bit does not work
170 * reliably as devices without an INTx disable bit will then generate a
171 * level IRQ which will never be cleared.
173 void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
175 raw_spinlock_t *lock = &desc->dev->msi_lock;
178 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
181 raw_spin_lock_irqsave(lock, flags);
182 desc->masked &= ~mask;
183 desc->masked |= flag;
184 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
186 raw_spin_unlock_irqrestore(lock, flags);
189 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
191 __pci_msi_desc_mask_irq(desc, mask, flag);
194 static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
196 return desc->mask_base +
197 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
201 * This internal function does not flush PCI writes to the device.
202 * All users must ensure that they read from the device before either
203 * assuming that the device state is up to date, or returning out of this
204 * file. This saves a few milliseconds when initialising devices with lots
205 * of MSI-X interrupts.
207 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
209 u32 mask_bits = desc->masked;
211 if (pci_msi_ignore_mask)
214 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
215 if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
216 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
217 writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
222 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
224 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
227 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
229 struct msi_desc *desc = irq_data_get_msi_desc(data);
231 if (desc->msi_attrib.is_msix) {
232 msix_mask_irq(desc, flag);
233 readl(desc->mask_base); /* Flush write to device */
235 unsigned offset = data->irq - desc->irq;
236 msi_mask_irq(desc, 1 << offset, flag << offset);
241 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
242 * @data: pointer to irqdata associated to that interrupt
244 void pci_msi_mask_irq(struct irq_data *data)
246 msi_set_mask_bit(data, 1);
248 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
251 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
252 * @data: pointer to irqdata associated to that interrupt
254 void pci_msi_unmask_irq(struct irq_data *data)
256 msi_set_mask_bit(data, 0);
258 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
260 void default_restore_msi_irqs(struct pci_dev *dev)
262 struct msi_desc *entry;
264 for_each_pci_msi_entry(entry, dev)
265 default_restore_msi_irq(dev, entry->irq);
268 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
270 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
272 BUG_ON(dev->current_state != PCI_D0);
274 if (entry->msi_attrib.is_msix) {
275 void __iomem *base = pci_msix_desc_addr(entry);
277 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
278 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
279 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
281 int pos = dev->msi_cap;
284 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
286 if (entry->msi_attrib.is_64) {
287 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
289 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
292 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
298 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
300 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
302 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
303 /* Don't touch the hardware now */
304 } else if (entry->msi_attrib.is_msix) {
305 void __iomem *base = pci_msix_desc_addr(entry);
306 bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
309 * The specification mandates that the entry is masked
310 * when the message is modified:
312 * "If software changes the Address or Data value of an
313 * entry while the entry is unmasked, the result is
317 __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
319 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
320 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
321 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
324 __pci_msix_desc_mask_irq(entry, 0);
326 /* Ensure that the writes are visible in the device */
327 readl(base + PCI_MSIX_ENTRY_DATA);
329 int pos = dev->msi_cap;
332 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
333 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
334 msgctl |= entry->msi_attrib.multiple << 4;
335 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
337 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
339 if (entry->msi_attrib.is_64) {
340 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
342 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
345 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
348 /* Ensure that the writes are visible in the device */
349 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
354 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
356 struct msi_desc *entry = irq_get_msi_desc(irq);
358 __pci_write_msi_msg(entry, msg);
360 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
362 static void free_msi_irqs(struct pci_dev *dev)
364 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
365 struct msi_desc *entry, *tmp;
366 struct attribute **msi_attrs;
367 struct device_attribute *dev_attr;
370 for_each_pci_msi_entry(entry, dev)
372 for (i = 0; i < entry->nvec_used; i++)
373 BUG_ON(irq_has_action(entry->irq + i));
375 pci_msi_teardown_msi_irqs(dev);
377 list_for_each_entry_safe(entry, tmp, msi_list, list) {
378 if (entry->msi_attrib.is_msix) {
379 if (list_is_last(&entry->list, msi_list))
380 iounmap(entry->mask_base);
383 list_del(&entry->list);
384 free_msi_entry(entry);
387 if (dev->msi_irq_groups) {
388 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
389 msi_attrs = dev->msi_irq_groups[0]->attrs;
390 while (msi_attrs[count]) {
391 dev_attr = container_of(msi_attrs[count],
392 struct device_attribute, attr);
393 kfree(dev_attr->attr.name);
398 kfree(dev->msi_irq_groups[0]);
399 kfree(dev->msi_irq_groups);
400 dev->msi_irq_groups = NULL;
404 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
406 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
407 pci_intx(dev, enable);
410 static void __pci_restore_msi_state(struct pci_dev *dev)
413 struct msi_desc *entry;
415 if (!dev->msi_enabled)
418 entry = irq_get_msi_desc(dev->irq);
420 pci_intx_for_msi(dev, 0);
421 pci_msi_set_enable(dev, 0);
422 arch_restore_msi_irqs(dev);
424 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
425 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
427 control &= ~PCI_MSI_FLAGS_QSIZE;
428 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
429 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
432 static void __pci_restore_msix_state(struct pci_dev *dev)
434 struct msi_desc *entry;
436 if (!dev->msix_enabled)
438 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
440 /* route the table */
441 pci_intx_for_msi(dev, 0);
442 pci_msix_clear_and_set_ctrl(dev, 0,
443 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
445 arch_restore_msi_irqs(dev);
446 for_each_pci_msi_entry(entry, dev)
447 msix_mask_irq(entry, entry->masked);
449 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
452 void pci_restore_msi_state(struct pci_dev *dev)
454 __pci_restore_msi_state(dev);
455 __pci_restore_msix_state(dev);
457 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
459 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
462 struct msi_desc *entry;
466 retval = kstrtoul(attr->attr.name, 10, &irq);
470 entry = irq_get_msi_desc(irq);
472 return sprintf(buf, "%s\n",
473 entry->msi_attrib.is_msix ? "msix" : "msi");
478 static int populate_msi_sysfs(struct pci_dev *pdev)
480 struct attribute **msi_attrs;
481 struct attribute *msi_attr;
482 struct device_attribute *msi_dev_attr;
483 struct attribute_group *msi_irq_group;
484 const struct attribute_group **msi_irq_groups;
485 struct msi_desc *entry;
491 /* Determine how many msi entries we have */
492 for_each_pci_msi_entry(entry, pdev)
493 num_msi += entry->nvec_used;
497 /* Dynamically create the MSI attributes for the PCI device */
498 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
501 for_each_pci_msi_entry(entry, pdev) {
502 for (i = 0; i < entry->nvec_used; i++) {
503 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
506 msi_attrs[count] = &msi_dev_attr->attr;
508 sysfs_attr_init(&msi_dev_attr->attr);
509 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
511 if (!msi_dev_attr->attr.name)
513 msi_dev_attr->attr.mode = S_IRUGO;
514 msi_dev_attr->show = msi_mode_show;
519 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
522 msi_irq_group->name = "msi_irqs";
523 msi_irq_group->attrs = msi_attrs;
525 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
527 goto error_irq_group;
528 msi_irq_groups[0] = msi_irq_group;
530 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
532 goto error_irq_groups;
533 pdev->msi_irq_groups = msi_irq_groups;
538 kfree(msi_irq_groups);
540 kfree(msi_irq_group);
543 msi_attr = msi_attrs[count];
545 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
546 kfree(msi_attr->name);
549 msi_attr = msi_attrs[count];
555 static struct msi_desc *
556 msi_setup_entry(struct pci_dev *dev, int nvec, const struct irq_affinity *affd)
558 struct cpumask *masks = NULL;
559 struct msi_desc *entry;
563 masks = irq_create_affinity_masks(nvec, affd);
566 /* MSI Entry Initialization */
567 entry = alloc_msi_entry(&dev->dev, nvec, masks);
571 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
573 entry->msi_attrib.is_msix = 0;
574 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
575 entry->msi_attrib.entry_nr = 0;
576 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
577 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
578 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
579 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
581 if (control & PCI_MSI_FLAGS_64BIT)
582 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
584 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
586 /* Save the initial mask status */
587 if (entry->msi_attrib.maskbit)
588 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
595 static int msi_verify_entries(struct pci_dev *dev)
597 struct msi_desc *entry;
599 for_each_pci_msi_entry(entry, dev) {
600 if (!dev->no_64bit_msi || !entry->msg.address_hi)
602 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
603 " tried to assign one above 4G\n");
610 * msi_capability_init - configure device's MSI capability structure
611 * @dev: pointer to the pci_dev data structure of MSI device function
612 * @nvec: number of interrupts to allocate
613 * @affd: description of automatic irq affinity assignments (may be %NULL)
615 * Setup the MSI capability structure of the device with the requested
616 * number of interrupts. A return value of zero indicates the successful
617 * setup of an entry with the new MSI irq. A negative return value indicates
618 * an error, and a positive return value indicates the number of interrupts
619 * which could have been allocated.
621 static int msi_capability_init(struct pci_dev *dev, int nvec,
622 const struct irq_affinity *affd)
624 struct msi_desc *entry;
628 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
630 entry = msi_setup_entry(dev, nvec, affd);
634 /* All MSIs are unmasked by default, Mask them all */
635 mask = msi_mask(entry->msi_attrib.multi_cap);
636 msi_mask_irq(entry, mask, mask);
638 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
640 /* Configure MSI capability structure */
641 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
643 msi_mask_irq(entry, mask, 0);
648 ret = msi_verify_entries(dev);
650 msi_mask_irq(entry, mask, 0);
655 ret = populate_msi_sysfs(dev);
657 msi_mask_irq(entry, mask, 0);
662 /* Set MSI enabled bits */
663 pci_intx_for_msi(dev, 0);
664 pci_msi_set_enable(dev, 1);
665 dev->msi_enabled = 1;
667 pcibios_free_irq(dev);
668 dev->irq = entry->irq;
672 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
674 resource_size_t phys_addr;
679 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
681 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
682 flags = pci_resource_flags(dev, bir);
683 if (!flags || (flags & IORESOURCE_UNSET))
686 table_offset &= PCI_MSIX_TABLE_OFFSET;
687 phys_addr = pci_resource_start(dev, bir) + table_offset;
689 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
692 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
693 struct msix_entry *entries, int nvec,
694 const struct irq_affinity *affd)
696 struct cpumask *curmsk, *masks = NULL;
697 struct msi_desc *entry;
702 masks = irq_create_affinity_masks(nvec, affd);
704 for (i = 0, curmsk = masks; i < nvec; i++) {
705 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
711 /* No enough memory. Don't try again */
716 entry->msi_attrib.is_msix = 1;
717 entry->msi_attrib.is_64 = 1;
720 entry->msi_attrib.entry_nr = entries[i].entry;
722 entry->msi_attrib.entry_nr = i;
723 entry->msi_attrib.default_irq = dev->irq;
724 entry->mask_base = base;
726 addr = pci_msix_desc_addr(entry);
728 entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
730 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
740 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
742 struct msi_desc *entry;
744 for_each_pci_msi_entry(entry, dev) {
746 entries->vector = entry->irq;
752 static void msix_mask_all(void __iomem *base, int tsize)
754 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
757 if (pci_msi_ignore_mask)
760 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
761 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
765 * msix_capability_init - configure device's MSI-X capability
766 * @dev: pointer to the pci_dev data structure of MSI-X device function
767 * @entries: pointer to an array of struct msix_entry entries
768 * @nvec: number of @entries
769 * @affd: Optional pointer to enable automatic affinity assignement
771 * Setup the MSI-X capability structure of device function with a
772 * single MSI-X irq. A return of zero indicates the successful setup of
773 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
775 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
776 int nvec, const struct irq_affinity *affd)
783 * Some devices require MSI-X to be enabled before the MSI-X
784 * registers can be accessed. Mask all the vectors to prevent
785 * interrupts coming in before they're fully set up.
787 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
788 PCI_MSIX_FLAGS_ENABLE);
790 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
791 /* Request & Map MSI-X table region */
792 tsize = msix_table_size(control);
793 base = msix_map_region(dev, tsize);
799 /* Ensure that all table entries are masked. */
800 msix_mask_all(base, tsize);
802 ret = msix_setup_entries(dev, base, entries, nvec, affd);
806 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
810 /* Check if all MSI entries honor device restrictions */
811 ret = msi_verify_entries(dev);
815 msix_update_entries(dev, entries);
817 ret = populate_msi_sysfs(dev);
821 /* Set MSI-X enabled bits and unmask the function */
822 pci_intx_for_msi(dev, 0);
823 dev->msix_enabled = 1;
824 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
826 pcibios_free_irq(dev);
832 * If we had some success, report the number of irqs
833 * we succeeded in setting up.
835 struct msi_desc *entry;
838 for_each_pci_msi_entry(entry, dev) {
850 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
856 * pci_msi_supported - check whether MSI may be enabled on a device
857 * @dev: pointer to the pci_dev data structure of MSI device function
858 * @nvec: how many MSIs have been requested ?
860 * Look at global flags, the device itself, and its parent buses
861 * to determine if MSI/-X are supported for the device. If MSI/-X is
862 * supported return 1, else return 0.
864 static int pci_msi_supported(struct pci_dev *dev, int nvec)
868 /* MSI must be globally enabled and supported by the device */
872 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
876 * You can't ask to have 0 or less MSIs configured.
878 * b) the list manipulation code assumes nvec >= 1.
884 * Any bridge which does NOT route MSI transactions from its
885 * secondary bus to its primary bus must set NO_MSI flag on
886 * the secondary pci_bus.
887 * We expect only arch-specific PCI host bus controller driver
888 * or quirks for specific PCI bridges to be setting NO_MSI.
890 for (bus = dev->bus; bus; bus = bus->parent)
891 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
898 * pci_msi_vec_count - Return the number of MSI vectors a device can send
899 * @dev: device to report about
901 * This function returns the number of MSI vectors a device requested via
902 * Multiple Message Capable register. It returns a negative errno if the
903 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
904 * and returns a power of two, up to a maximum of 2^5 (32), according to the
907 int pci_msi_vec_count(struct pci_dev *dev)
915 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
916 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
920 EXPORT_SYMBOL(pci_msi_vec_count);
922 static void pci_msi_shutdown(struct pci_dev *dev)
924 struct msi_desc *desc;
927 if (!pci_msi_enable || !dev || !dev->msi_enabled)
930 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
931 desc = first_pci_msi_entry(dev);
933 pci_msi_set_enable(dev, 0);
934 pci_intx_for_msi(dev, 1);
935 dev->msi_enabled = 0;
937 /* Return the device with MSI unmasked as initial states */
938 mask = msi_mask(desc->msi_attrib.multi_cap);
939 msi_mask_irq(desc, mask, 0);
941 /* Restore dev->irq to its default pin-assertion irq */
942 dev->irq = desc->msi_attrib.default_irq;
943 pcibios_alloc_irq(dev);
946 void pci_disable_msi(struct pci_dev *dev)
948 if (!pci_msi_enable || !dev || !dev->msi_enabled)
951 pci_msi_shutdown(dev);
954 EXPORT_SYMBOL(pci_disable_msi);
957 * pci_msix_vec_count - return the number of device's MSI-X table entries
958 * @dev: pointer to the pci_dev data structure of MSI-X device function
959 * This function returns the number of device's MSI-X table entries and
960 * therefore the number of MSI-X vectors device is capable of sending.
961 * It returns a negative errno if the device is not capable of sending MSI-X
964 int pci_msix_vec_count(struct pci_dev *dev)
971 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
972 return msix_table_size(control);
974 EXPORT_SYMBOL(pci_msix_vec_count);
976 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
977 int nvec, const struct irq_affinity *affd)
982 if (!pci_msi_supported(dev, nvec))
985 nr_entries = pci_msix_vec_count(dev);
988 if (nvec > nr_entries)
992 /* Check for any invalid entries */
993 for (i = 0; i < nvec; i++) {
994 if (entries[i].entry >= nr_entries)
995 return -EINVAL; /* invalid entry */
996 for (j = i + 1; j < nvec; j++) {
997 if (entries[i].entry == entries[j].entry)
998 return -EINVAL; /* duplicate entry */
1003 /* Check whether driver already requested for MSI irq */
1004 if (dev->msi_enabled) {
1005 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
1008 return msix_capability_init(dev, entries, nvec, affd);
1011 static void pci_msix_shutdown(struct pci_dev *dev)
1013 struct msi_desc *entry;
1015 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1018 if (pci_dev_is_disconnected(dev)) {
1019 dev->msix_enabled = 0;
1023 /* Return the device with MSI-X masked as initial states */
1024 for_each_pci_msi_entry(entry, dev)
1025 __pci_msix_desc_mask_irq(entry, 1);
1027 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1028 pci_intx_for_msi(dev, 1);
1029 dev->msix_enabled = 0;
1030 pcibios_alloc_irq(dev);
1033 void pci_disable_msix(struct pci_dev *dev)
1035 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1038 pci_msix_shutdown(dev);
1041 EXPORT_SYMBOL(pci_disable_msix);
1043 void pci_no_msi(void)
1049 * pci_msi_enabled - is MSI enabled?
1051 * Returns true if MSI has not been disabled by the command-line option
1054 int pci_msi_enabled(void)
1056 return pci_msi_enable;
1058 EXPORT_SYMBOL(pci_msi_enabled);
1060 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1061 const struct irq_affinity *affd)
1066 if (!pci_msi_supported(dev, minvec))
1069 /* Check whether driver already requested MSI-X irqs */
1070 if (dev->msix_enabled) {
1072 "can't enable MSI (MSI-X already enabled)\n");
1076 if (maxvec < minvec)
1079 if (WARN_ON_ONCE(dev->msi_enabled))
1082 nvec = pci_msi_vec_count(dev);
1093 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1098 rc = msi_capability_init(dev, nvec, affd);
1111 /* deprecated, don't use */
1112 int pci_enable_msi(struct pci_dev *dev)
1114 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
1119 EXPORT_SYMBOL(pci_enable_msi);
1121 static int __pci_enable_msix_range(struct pci_dev *dev,
1122 struct msix_entry *entries, int minvec,
1123 int maxvec, const struct irq_affinity *affd)
1125 int rc, nvec = maxvec;
1127 if (maxvec < minvec)
1130 if (WARN_ON_ONCE(dev->msix_enabled))
1135 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1140 rc = __pci_enable_msix(dev, entries, nvec, affd);
1154 * pci_enable_msix_range - configure device's MSI-X capability structure
1155 * @dev: pointer to the pci_dev data structure of MSI-X device function
1156 * @entries: pointer to an array of MSI-X entries
1157 * @minvec: minimum number of MSI-X irqs requested
1158 * @maxvec: maximum number of MSI-X irqs requested
1160 * Setup the MSI-X capability structure of device function with a maximum
1161 * possible number of interrupts in the range between @minvec and @maxvec
1162 * upon its software driver call to request for MSI-X mode enabled on its
1163 * hardware device function. It returns a negative errno if an error occurs.
1164 * If it succeeds, it returns the actual number of interrupts allocated and
1165 * indicates the successful configuration of MSI-X capability structure
1166 * with new allocated MSI-X interrupts.
1168 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1169 int minvec, int maxvec)
1171 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL);
1173 EXPORT_SYMBOL(pci_enable_msix_range);
1176 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1177 * @dev: PCI device to operate on
1178 * @min_vecs: minimum number of vectors required (must be >= 1)
1179 * @max_vecs: maximum (desired) number of vectors
1180 * @flags: flags or quirks for the allocation
1181 * @affd: optional description of the affinity requirements
1183 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1184 * vectors if available, and fall back to a single legacy vector
1185 * if neither is available. Return the number of vectors allocated,
1186 * (which might be smaller than @max_vecs) if successful, or a negative
1187 * error code on error. If less than @min_vecs interrupt vectors are
1188 * available for @dev the function will fail with -ENOSPC.
1190 * To get the Linux IRQ number used for a vector that can be passed to
1191 * request_irq() use the pci_irq_vector() helper.
1193 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1194 unsigned int max_vecs, unsigned int flags,
1195 const struct irq_affinity *affd)
1197 static const struct irq_affinity msi_default_affd;
1198 int msix_vecs = -ENOSPC;
1199 int msi_vecs = -ENOSPC;
1201 if (flags & PCI_IRQ_AFFINITY) {
1203 affd = &msi_default_affd;
1209 if (flags & PCI_IRQ_MSIX) {
1210 msix_vecs = __pci_enable_msix_range(dev, NULL, min_vecs,
1216 if (flags & PCI_IRQ_MSI) {
1217 msi_vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs,
1223 /* use legacy irq if allowed */
1224 if (flags & PCI_IRQ_LEGACY) {
1225 if (min_vecs == 1 && dev->irq) {
1231 if (msix_vecs == -ENOSPC)
1235 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1238 * pci_free_irq_vectors - free previously allocated IRQs for a device
1239 * @dev: PCI device to operate on
1241 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1243 void pci_free_irq_vectors(struct pci_dev *dev)
1245 pci_disable_msix(dev);
1246 pci_disable_msi(dev);
1248 EXPORT_SYMBOL(pci_free_irq_vectors);
1251 * pci_irq_vector - return Linux IRQ number of a device vector
1252 * @dev: PCI device to operate on
1253 * @nr: device-relative interrupt vector index (0-based).
1255 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1257 if (dev->msix_enabled) {
1258 struct msi_desc *entry;
1261 for_each_pci_msi_entry(entry, dev) {
1270 if (dev->msi_enabled) {
1271 struct msi_desc *entry = first_pci_msi_entry(dev);
1273 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1276 if (WARN_ON_ONCE(nr > 0))
1280 return dev->irq + nr;
1282 EXPORT_SYMBOL(pci_irq_vector);
1285 * pci_irq_get_affinity - return the affinity of a particular msi vector
1286 * @dev: PCI device to operate on
1287 * @nr: device-relative interrupt vector index (0-based).
1289 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1291 if (dev->msix_enabled) {
1292 struct msi_desc *entry;
1295 for_each_pci_msi_entry(entry, dev) {
1297 return entry->affinity;
1302 } else if (dev->msi_enabled) {
1303 struct msi_desc *entry = first_pci_msi_entry(dev);
1305 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1306 nr >= entry->nvec_used))
1309 return &entry->affinity[nr];
1311 return cpu_possible_mask;
1314 EXPORT_SYMBOL(pci_irq_get_affinity);
1317 * pci_irq_get_node - return the numa node of a particular msi vector
1318 * @pdev: PCI device to operate on
1319 * @vec: device-relative interrupt vector index (0-based).
1321 int pci_irq_get_node(struct pci_dev *pdev, int vec)
1323 const struct cpumask *mask;
1325 mask = pci_irq_get_affinity(pdev, vec);
1327 return local_memory_node(cpu_to_node(cpumask_first(mask)));
1328 return dev_to_node(&pdev->dev);
1330 EXPORT_SYMBOL(pci_irq_get_node);
1332 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1334 return to_pci_dev(desc->dev);
1336 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1338 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1340 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1342 return dev->bus->sysdata;
1344 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1346 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1348 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1349 * @irq_data: Pointer to interrupt data of the MSI interrupt
1350 * @msg: Pointer to the message
1352 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1354 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1357 * For MSI-X desc->irq is always equal to irq_data->irq. For
1358 * MSI only the first interrupt of MULTI MSI passes the test.
1360 if (desc->irq == irq_data->irq)
1361 __pci_write_msi_msg(desc, msg);
1365 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1366 * @dev: Pointer to the PCI device
1367 * @desc: Pointer to the msi descriptor
1369 * The ID number is only used within the irqdomain.
1371 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1372 struct msi_desc *desc)
1374 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1375 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1376 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1379 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1381 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1385 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1386 * @domain: The interrupt domain to check
1387 * @info: The domain info for verification
1388 * @dev: The device to check
1391 * 0 if the functionality is supported
1392 * 1 if Multi MSI is requested, but the domain does not support it
1393 * -ENOTSUPP otherwise
1395 int pci_msi_domain_check_cap(struct irq_domain *domain,
1396 struct msi_domain_info *info, struct device *dev)
1398 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1400 /* Special handling to support __pci_enable_msi_range() */
1401 if (pci_msi_desc_is_multi_msi(desc) &&
1402 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1404 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1410 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1411 struct msi_desc *desc, int error)
1413 /* Special handling to support __pci_enable_msi_range() */
1414 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1420 #ifdef GENERIC_MSI_DOMAIN_OPS
1421 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1422 struct msi_desc *desc)
1425 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1429 #define pci_msi_domain_set_desc NULL
1432 static struct msi_domain_ops pci_msi_domain_ops_default = {
1433 .set_desc = pci_msi_domain_set_desc,
1434 .msi_check = pci_msi_domain_check_cap,
1435 .handle_error = pci_msi_domain_handle_error,
1438 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1440 struct msi_domain_ops *ops = info->ops;
1443 info->ops = &pci_msi_domain_ops_default;
1445 if (ops->set_desc == NULL)
1446 ops->set_desc = pci_msi_domain_set_desc;
1447 if (ops->msi_check == NULL)
1448 ops->msi_check = pci_msi_domain_check_cap;
1449 if (ops->handle_error == NULL)
1450 ops->handle_error = pci_msi_domain_handle_error;
1454 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1456 struct irq_chip *chip = info->chip;
1459 if (!chip->irq_write_msi_msg)
1460 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1461 if (!chip->irq_mask)
1462 chip->irq_mask = pci_msi_mask_irq;
1463 if (!chip->irq_unmask)
1464 chip->irq_unmask = pci_msi_unmask_irq;
1468 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1469 * @fwnode: Optional fwnode of the interrupt controller
1470 * @info: MSI domain info
1471 * @parent: Parent irq domain
1473 * Updates the domain and chip ops and creates a MSI interrupt domain.
1476 * A domain pointer or NULL in case of failure.
1478 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1479 struct msi_domain_info *info,
1480 struct irq_domain *parent)
1482 struct irq_domain *domain;
1484 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1485 pci_msi_domain_update_dom_ops(info);
1486 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1487 pci_msi_domain_update_chip_ops(info);
1489 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1491 domain = msi_create_irq_domain(fwnode, info, parent);
1495 irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
1498 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1501 * Users of the generic MSI infrastructure expect a device to have a single ID,
1502 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1503 * DMA phantom functions tend to still emit MSIs from the real function number,
1504 * so we ignore those and only consider topological aliases where either the
1505 * alias device or RID appears on a different bus number. We also make the
1506 * reasonable assumption that bridges are walked in an upstream direction (so
1507 * the last one seen wins), and the much braver assumption that the most likely
1508 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1509 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1510 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1511 * for taking ownership all we can really do is close our eyes and hope...
1513 static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1516 u8 bus = PCI_BUS_NUM(*pa);
1518 if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
1525 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1526 * @domain: The interrupt domain
1527 * @pdev: The PCI device.
1529 * The RID for a device is formed from the alias, with a firmware
1530 * supplied mapping applied
1534 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1536 struct device_node *of_node;
1537 u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn);
1539 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1541 of_node = irq_domain_get_of_node(domain);
1542 rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) :
1543 iort_msi_map_rid(&pdev->dev, rid);
1549 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1550 * @pdev: The PCI device
1552 * Use the firmware data to find a device-specific MSI domain
1553 * (i.e. not one that is set as a default).
1555 * Returns: The corresponding MSI domain or NULL if none has been found.
1557 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1559 struct irq_domain *dom;
1560 u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn);
1562 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1563 dom = of_msi_map_get_device_domain(&pdev->dev, rid);
1565 dom = iort_get_device_domain(&pdev->dev, rid);
1568 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */