3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/acpi_iort.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
29 static int pci_msi_enable = 1;
30 int pci_msi_ignore_mask;
32 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
34 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
35 static struct irq_domain *pci_msi_default_domain;
36 static DEFINE_MUTEX(pci_msi_domain_lock);
38 struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
40 return pci_msi_default_domain;
43 static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
45 struct irq_domain *domain;
47 domain = dev_get_msi_domain(&dev->dev);
51 return arch_get_pci_msi_domain(dev);
54 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
56 struct irq_domain *domain;
58 domain = pci_msi_get_domain(dev);
59 if (domain && irq_domain_is_hierarchy(domain))
60 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
62 return arch_setup_msi_irqs(dev, nvec, type);
65 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
67 struct irq_domain *domain;
69 domain = pci_msi_get_domain(dev);
70 if (domain && irq_domain_is_hierarchy(domain))
71 pci_msi_domain_free_irqs(domain, dev);
73 arch_teardown_msi_irqs(dev);
76 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
77 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
82 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
84 struct msi_controller *chip = dev->bus->msi;
87 if (!chip || !chip->setup_irq)
90 err = chip->setup_irq(chip, dev, desc);
94 irq_set_chip_data(desc->irq, chip);
99 void __weak arch_teardown_msi_irq(unsigned int irq)
101 struct msi_controller *chip = irq_get_chip_data(irq);
103 if (!chip || !chip->teardown_irq)
106 chip->teardown_irq(chip, irq);
109 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
111 struct msi_controller *chip = dev->bus->msi;
112 struct msi_desc *entry;
115 if (chip && chip->setup_irqs)
116 return chip->setup_irqs(chip, dev, nvec, type);
118 * If an architecture wants to support multiple MSI, it needs to
119 * override arch_setup_msi_irqs()
121 if (type == PCI_CAP_ID_MSI && nvec > 1)
124 for_each_pci_msi_entry(entry, dev) {
125 ret = arch_setup_msi_irq(dev, entry);
136 * We have a default implementation available as a separate non-weak
137 * function, as it is used by the Xen x86 PCI code
139 void default_teardown_msi_irqs(struct pci_dev *dev)
142 struct msi_desc *entry;
144 for_each_pci_msi_entry(entry, dev)
146 for (i = 0; i < entry->nvec_used; i++)
147 arch_teardown_msi_irq(entry->irq + i);
150 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
152 return default_teardown_msi_irqs(dev);
155 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
157 struct msi_desc *entry;
160 if (dev->msix_enabled) {
161 for_each_pci_msi_entry(entry, dev) {
162 if (irq == entry->irq)
165 } else if (dev->msi_enabled) {
166 entry = irq_get_msi_desc(irq);
170 __pci_write_msi_msg(entry, &entry->msg);
173 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
175 return default_restore_msi_irqs(dev);
178 static inline __attribute_const__ u32 msi_mask(unsigned x)
180 /* Don't shift by >= width of type */
183 return (1 << (1 << x)) - 1;
187 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
188 * mask all MSI interrupts by clearing the MSI enable bit does not work
189 * reliably as devices without an INTx disable bit will then generate a
190 * level IRQ which will never be cleared.
192 void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
194 raw_spinlock_t *lock = &desc->dev->msi_lock;
197 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
200 raw_spin_lock_irqsave(lock, flags);
201 desc->masked &= ~mask;
202 desc->masked |= flag;
203 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
205 raw_spin_unlock_irqrestore(lock, flags);
208 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
210 __pci_msi_desc_mask_irq(desc, mask, flag);
213 static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
215 return desc->mask_base +
216 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
220 * This internal function does not flush PCI writes to the device.
221 * All users must ensure that they read from the device before either
222 * assuming that the device state is up to date, or returning out of this
223 * file. This saves a few milliseconds when initialising devices with lots
224 * of MSI-X interrupts.
226 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
228 u32 mask_bits = desc->masked;
230 if (pci_msi_ignore_mask)
233 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
234 if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
235 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
236 writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
241 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
243 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
246 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
248 struct msi_desc *desc = irq_data_get_msi_desc(data);
250 if (desc->msi_attrib.is_msix) {
251 msix_mask_irq(desc, flag);
252 readl(desc->mask_base); /* Flush write to device */
254 unsigned offset = data->irq - desc->irq;
255 msi_mask_irq(desc, 1 << offset, flag << offset);
260 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
261 * @data: pointer to irqdata associated to that interrupt
263 void pci_msi_mask_irq(struct irq_data *data)
265 msi_set_mask_bit(data, 1);
267 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
270 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
271 * @data: pointer to irqdata associated to that interrupt
273 void pci_msi_unmask_irq(struct irq_data *data)
275 msi_set_mask_bit(data, 0);
277 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
279 void default_restore_msi_irqs(struct pci_dev *dev)
281 struct msi_desc *entry;
283 for_each_pci_msi_entry(entry, dev)
284 default_restore_msi_irq(dev, entry->irq);
287 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
289 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
291 BUG_ON(dev->current_state != PCI_D0);
293 if (entry->msi_attrib.is_msix) {
294 void __iomem *base = pci_msix_desc_addr(entry);
296 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
297 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
298 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
300 int pos = dev->msi_cap;
303 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
305 if (entry->msi_attrib.is_64) {
306 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
308 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
311 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
317 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
319 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
321 if (dev->current_state != PCI_D0) {
322 /* Don't touch the hardware now */
323 } else if (entry->msi_attrib.is_msix) {
324 void __iomem *base = pci_msix_desc_addr(entry);
325 bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
328 * The specification mandates that the entry is masked
329 * when the message is modified:
331 * "If software changes the Address or Data value of an
332 * entry while the entry is unmasked, the result is
336 __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
338 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
339 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
340 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
343 __pci_msix_desc_mask_irq(entry, 0);
345 /* Ensure that the writes are visible in the device */
346 readl(base + PCI_MSIX_ENTRY_DATA);
348 int pos = dev->msi_cap;
351 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
352 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
353 msgctl |= entry->msi_attrib.multiple << 4;
354 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
356 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
358 if (entry->msi_attrib.is_64) {
359 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
361 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
364 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
367 /* Ensure that the writes are visible in the device */
368 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
373 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
375 struct msi_desc *entry = irq_get_msi_desc(irq);
377 __pci_write_msi_msg(entry, msg);
379 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
381 static void free_msi_irqs(struct pci_dev *dev)
383 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
384 struct msi_desc *entry, *tmp;
385 struct attribute **msi_attrs;
386 struct device_attribute *dev_attr;
389 for_each_pci_msi_entry(entry, dev)
391 for (i = 0; i < entry->nvec_used; i++)
392 BUG_ON(irq_has_action(entry->irq + i));
394 if (dev->msi_irq_groups) {
395 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
396 msi_attrs = dev->msi_irq_groups[0]->attrs;
397 while (msi_attrs[count]) {
398 dev_attr = container_of(msi_attrs[count],
399 struct device_attribute, attr);
400 kfree(dev_attr->attr.name);
405 kfree(dev->msi_irq_groups[0]);
406 kfree(dev->msi_irq_groups);
407 dev->msi_irq_groups = NULL;
410 pci_msi_teardown_msi_irqs(dev);
412 list_for_each_entry_safe(entry, tmp, msi_list, list) {
413 if (entry->msi_attrib.is_msix) {
414 if (list_is_last(&entry->list, msi_list))
415 iounmap(entry->mask_base);
418 list_del(&entry->list);
419 free_msi_entry(entry);
423 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
425 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
426 pci_intx(dev, enable);
429 static void __pci_restore_msi_state(struct pci_dev *dev)
432 struct msi_desc *entry;
434 if (!dev->msi_enabled)
437 entry = irq_get_msi_desc(dev->irq);
439 pci_intx_for_msi(dev, 0);
440 pci_msi_set_enable(dev, 0);
441 arch_restore_msi_irqs(dev);
443 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
444 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
446 control &= ~PCI_MSI_FLAGS_QSIZE;
447 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
448 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
451 static void __pci_restore_msix_state(struct pci_dev *dev)
453 struct msi_desc *entry;
455 if (!dev->msix_enabled)
457 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
459 /* route the table */
460 pci_intx_for_msi(dev, 0);
461 pci_msix_clear_and_set_ctrl(dev, 0,
462 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
464 arch_restore_msi_irqs(dev);
465 for_each_pci_msi_entry(entry, dev)
466 msix_mask_irq(entry, entry->masked);
468 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
471 void pci_restore_msi_state(struct pci_dev *dev)
473 __pci_restore_msi_state(dev);
474 __pci_restore_msix_state(dev);
476 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
478 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
481 struct msi_desc *entry;
485 retval = kstrtoul(attr->attr.name, 10, &irq);
489 entry = irq_get_msi_desc(irq);
491 return sprintf(buf, "%s\n",
492 entry->msi_attrib.is_msix ? "msix" : "msi");
497 static int populate_msi_sysfs(struct pci_dev *pdev)
499 struct attribute **msi_attrs;
500 struct attribute *msi_attr;
501 struct device_attribute *msi_dev_attr;
502 struct attribute_group *msi_irq_group;
503 const struct attribute_group **msi_irq_groups;
504 struct msi_desc *entry;
510 /* Determine how many msi entries we have */
511 for_each_pci_msi_entry(entry, pdev)
512 num_msi += entry->nvec_used;
516 /* Dynamically create the MSI attributes for the PCI device */
517 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
520 for_each_pci_msi_entry(entry, pdev) {
521 for (i = 0; i < entry->nvec_used; i++) {
522 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
525 msi_attrs[count] = &msi_dev_attr->attr;
527 sysfs_attr_init(&msi_dev_attr->attr);
528 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
530 if (!msi_dev_attr->attr.name)
532 msi_dev_attr->attr.mode = S_IRUGO;
533 msi_dev_attr->show = msi_mode_show;
538 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
541 msi_irq_group->name = "msi_irqs";
542 msi_irq_group->attrs = msi_attrs;
544 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
546 goto error_irq_group;
547 msi_irq_groups[0] = msi_irq_group;
549 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
551 goto error_irq_groups;
552 pdev->msi_irq_groups = msi_irq_groups;
557 kfree(msi_irq_groups);
559 kfree(msi_irq_group);
562 msi_attr = msi_attrs[count];
564 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
565 kfree(msi_attr->name);
568 msi_attr = msi_attrs[count];
574 static struct msi_desc *
575 msi_setup_entry(struct pci_dev *dev, int nvec, bool affinity)
577 struct cpumask *masks = NULL;
578 struct msi_desc *entry;
582 masks = irq_create_affinity_masks(dev->irq_affinity, nvec);
584 pr_err("Unable to allocate affinity masks, ignoring\n");
587 /* MSI Entry Initialization */
588 entry = alloc_msi_entry(&dev->dev, nvec, masks);
592 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
594 entry->msi_attrib.is_msix = 0;
595 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
596 entry->msi_attrib.entry_nr = 0;
597 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
598 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
599 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
600 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
602 if (control & PCI_MSI_FLAGS_64BIT)
603 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
605 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
607 /* Save the initial mask status */
608 if (entry->msi_attrib.maskbit)
609 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
616 static int msi_verify_entries(struct pci_dev *dev)
618 struct msi_desc *entry;
620 for_each_pci_msi_entry(entry, dev) {
621 if (!dev->no_64bit_msi || !entry->msg.address_hi)
623 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
624 " tried to assign one above 4G\n");
631 * msi_capability_init - configure device's MSI capability structure
632 * @dev: pointer to the pci_dev data structure of MSI device function
633 * @nvec: number of interrupts to allocate
634 * @affinity: flag to indicate cpu irq affinity mask should be set
636 * Setup the MSI capability structure of the device with the requested
637 * number of interrupts. A return value of zero indicates the successful
638 * setup of an entry with the new MSI irq. A negative return value indicates
639 * an error, and a positive return value indicates the number of interrupts
640 * which could have been allocated.
642 static int msi_capability_init(struct pci_dev *dev, int nvec, bool affinity)
644 struct msi_desc *entry;
648 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
650 entry = msi_setup_entry(dev, nvec, affinity);
654 /* All MSIs are unmasked by default, Mask them all */
655 mask = msi_mask(entry->msi_attrib.multi_cap);
656 msi_mask_irq(entry, mask, mask);
658 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
660 /* Configure MSI capability structure */
661 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
663 msi_mask_irq(entry, mask, 0);
668 ret = msi_verify_entries(dev);
670 msi_mask_irq(entry, mask, 0);
675 ret = populate_msi_sysfs(dev);
677 msi_mask_irq(entry, mask, 0);
682 /* Set MSI enabled bits */
683 pci_intx_for_msi(dev, 0);
684 pci_msi_set_enable(dev, 1);
685 dev->msi_enabled = 1;
687 pcibios_free_irq(dev);
688 dev->irq = entry->irq;
692 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
694 resource_size_t phys_addr;
699 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
701 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
702 flags = pci_resource_flags(dev, bir);
703 if (!flags || (flags & IORESOURCE_UNSET))
706 table_offset &= PCI_MSIX_TABLE_OFFSET;
707 phys_addr = pci_resource_start(dev, bir) + table_offset;
709 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
712 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
713 struct msix_entry *entries, int nvec,
716 struct cpumask *curmsk, *masks = NULL;
717 struct msi_desc *entry;
722 masks = irq_create_affinity_masks(dev->irq_affinity, nvec);
724 pr_err("Unable to allocate affinity masks, ignoring\n");
727 for (i = 0, curmsk = masks; i < nvec; i++) {
728 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
734 /* No enough memory. Don't try again */
739 entry->msi_attrib.is_msix = 1;
740 entry->msi_attrib.is_64 = 1;
743 entry->msi_attrib.entry_nr = entries[i].entry;
745 entry->msi_attrib.entry_nr = i;
746 entry->msi_attrib.default_irq = dev->irq;
747 entry->mask_base = base;
749 addr = pci_msix_desc_addr(entry);
751 entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
753 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
763 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
765 struct msi_desc *entry;
767 for_each_pci_msi_entry(entry, dev) {
769 entries->vector = entry->irq;
775 static void msix_mask_all(void __iomem *base, int tsize)
777 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
780 if (pci_msi_ignore_mask)
783 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
784 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
788 * msix_capability_init - configure device's MSI-X capability
789 * @dev: pointer to the pci_dev data structure of MSI-X device function
790 * @entries: pointer to an array of struct msix_entry entries
791 * @nvec: number of @entries
792 * @affinity: flag to indicate cpu irq affinity mask should be set
794 * Setup the MSI-X capability structure of device function with a
795 * single MSI-X irq. A return of zero indicates the successful setup of
796 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
798 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
799 int nvec, bool affinity)
806 * Some devices require MSI-X to be enabled before the MSI-X
807 * registers can be accessed. Mask all the vectors to prevent
808 * interrupts coming in before they're fully set up.
810 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
811 PCI_MSIX_FLAGS_ENABLE);
813 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
814 /* Request & Map MSI-X table region */
815 tsize = msix_table_size(control);
816 base = msix_map_region(dev, tsize);
817 base = msix_map_region(dev, msix_table_size(control));
823 /* Ensure that all table entries are masked. */
824 msix_mask_all(base, tsize);
826 ret = msix_setup_entries(dev, base, entries, nvec, affinity);
830 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
834 /* Check if all MSI entries honor device restrictions */
835 ret = msi_verify_entries(dev);
839 msix_update_entries(dev, entries);
841 ret = populate_msi_sysfs(dev);
845 /* Set MSI-X enabled bits and unmask the function */
846 pci_intx_for_msi(dev, 0);
847 dev->msix_enabled = 1;
848 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
850 pcibios_free_irq(dev);
856 * If we had some success, report the number of irqs
857 * we succeeded in setting up.
859 struct msi_desc *entry;
862 for_each_pci_msi_entry(entry, dev) {
874 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
880 * pci_msi_supported - check whether MSI may be enabled on a device
881 * @dev: pointer to the pci_dev data structure of MSI device function
882 * @nvec: how many MSIs have been requested ?
884 * Look at global flags, the device itself, and its parent buses
885 * to determine if MSI/-X are supported for the device. If MSI/-X is
886 * supported return 1, else return 0.
888 static int pci_msi_supported(struct pci_dev *dev, int nvec)
892 /* MSI must be globally enabled and supported by the device */
896 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
900 * You can't ask to have 0 or less MSIs configured.
902 * b) the list manipulation code assumes nvec >= 1.
908 * Any bridge which does NOT route MSI transactions from its
909 * secondary bus to its primary bus must set NO_MSI flag on
910 * the secondary pci_bus.
911 * We expect only arch-specific PCI host bus controller driver
912 * or quirks for specific PCI bridges to be setting NO_MSI.
914 for (bus = dev->bus; bus; bus = bus->parent)
915 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
922 * pci_msi_vec_count - Return the number of MSI vectors a device can send
923 * @dev: device to report about
925 * This function returns the number of MSI vectors a device requested via
926 * Multiple Message Capable register. It returns a negative errno if the
927 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
928 * and returns a power of two, up to a maximum of 2^5 (32), according to the
931 int pci_msi_vec_count(struct pci_dev *dev)
939 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
940 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
944 EXPORT_SYMBOL(pci_msi_vec_count);
946 void pci_msi_shutdown(struct pci_dev *dev)
948 struct msi_desc *desc;
951 if (!pci_msi_enable || !dev || !dev->msi_enabled)
954 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
955 desc = first_pci_msi_entry(dev);
957 pci_msi_set_enable(dev, 0);
958 pci_intx_for_msi(dev, 1);
959 dev->msi_enabled = 0;
961 /* Return the device with MSI unmasked as initial states */
962 mask = msi_mask(desc->msi_attrib.multi_cap);
963 msi_mask_irq(desc, mask, 0);
965 /* Restore dev->irq to its default pin-assertion irq */
966 dev->irq = desc->msi_attrib.default_irq;
967 pcibios_alloc_irq(dev);
970 void pci_disable_msi(struct pci_dev *dev)
972 if (!pci_msi_enable || !dev || !dev->msi_enabled)
975 pci_msi_shutdown(dev);
978 EXPORT_SYMBOL(pci_disable_msi);
981 * pci_msix_vec_count - return the number of device's MSI-X table entries
982 * @dev: pointer to the pci_dev data structure of MSI-X device function
983 * This function returns the number of device's MSI-X table entries and
984 * therefore the number of MSI-X vectors device is capable of sending.
985 * It returns a negative errno if the device is not capable of sending MSI-X
988 int pci_msix_vec_count(struct pci_dev *dev)
995 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
996 return msix_table_size(control);
998 EXPORT_SYMBOL(pci_msix_vec_count);
1000 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
1001 int nvec, bool affinity)
1006 if (!pci_msi_supported(dev, nvec))
1009 nr_entries = pci_msix_vec_count(dev);
1012 if (nvec > nr_entries)
1016 /* Check for any invalid entries */
1017 for (i = 0; i < nvec; i++) {
1018 if (entries[i].entry >= nr_entries)
1019 return -EINVAL; /* invalid entry */
1020 for (j = i + 1; j < nvec; j++) {
1021 if (entries[i].entry == entries[j].entry)
1022 return -EINVAL; /* duplicate entry */
1027 /* Check whether driver already requested for MSI irq */
1028 if (dev->msi_enabled) {
1029 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
1032 return msix_capability_init(dev, entries, nvec, affinity);
1036 * pci_enable_msix - configure device's MSI-X capability structure
1037 * @dev: pointer to the pci_dev data structure of MSI-X device function
1038 * @entries: pointer to an array of MSI-X entries (optional)
1039 * @nvec: number of MSI-X irqs requested for allocation by device driver
1041 * Setup the MSI-X capability structure of device function with the number
1042 * of requested irqs upon its software driver call to request for
1043 * MSI-X mode enabled on its hardware device function. A return of zero
1044 * indicates the successful configuration of MSI-X capability structure
1045 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
1046 * Or a return of > 0 indicates that driver request is exceeding the number
1047 * of irqs or MSI-X vectors available. Driver should use the returned value to
1048 * re-send its request.
1050 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
1052 return __pci_enable_msix(dev, entries, nvec, false);
1054 EXPORT_SYMBOL(pci_enable_msix);
1056 void pci_msix_shutdown(struct pci_dev *dev)
1058 struct msi_desc *entry;
1060 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1063 /* Return the device with MSI-X masked as initial states */
1064 for_each_pci_msi_entry(entry, dev)
1065 __pci_msix_desc_mask_irq(entry, 1);
1067 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1068 pci_intx_for_msi(dev, 1);
1069 dev->msix_enabled = 0;
1070 pcibios_alloc_irq(dev);
1073 void pci_disable_msix(struct pci_dev *dev)
1075 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1078 pci_msix_shutdown(dev);
1081 EXPORT_SYMBOL(pci_disable_msix);
1083 void pci_no_msi(void)
1089 * pci_msi_enabled - is MSI enabled?
1091 * Returns true if MSI has not been disabled by the command-line option
1094 int pci_msi_enabled(void)
1096 return pci_msi_enable;
1098 EXPORT_SYMBOL(pci_msi_enabled);
1100 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1103 bool affinity = flags & PCI_IRQ_AFFINITY;
1107 if (!pci_msi_supported(dev, minvec))
1110 /* Check whether driver already requested MSI-X irqs */
1111 if (dev->msix_enabled) {
1113 "can't enable MSI (MSI-X already enabled)\n");
1117 if (maxvec < minvec)
1120 if (WARN_ON_ONCE(dev->msi_enabled))
1123 nvec = pci_msi_vec_count(dev);
1134 nvec = irq_calc_affinity_vectors(dev->irq_affinity,
1140 rc = msi_capability_init(dev, nvec, affinity);
1154 * pci_enable_msi_range - configure device's MSI capability structure
1155 * @dev: device to configure
1156 * @minvec: minimal number of interrupts to configure
1157 * @maxvec: maximum number of interrupts to configure
1159 * This function tries to allocate a maximum possible number of interrupts in a
1160 * range between @minvec and @maxvec. It returns a negative errno if an error
1161 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1162 * and updates the @dev's irq member to the lowest new interrupt number;
1163 * the other interrupt numbers allocated to this device are consecutive.
1165 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1167 return __pci_enable_msi_range(dev, minvec, maxvec, 0);
1169 EXPORT_SYMBOL(pci_enable_msi_range);
1171 static int __pci_enable_msix_range(struct pci_dev *dev,
1172 struct msix_entry *entries, int minvec, int maxvec,
1175 bool affinity = flags & PCI_IRQ_AFFINITY;
1176 int rc, nvec = maxvec;
1178 if (maxvec < minvec)
1181 if (WARN_ON_ONCE(dev->msix_enabled))
1186 nvec = irq_calc_affinity_vectors(dev->irq_affinity,
1192 rc = __pci_enable_msix(dev, entries, nvec, affinity);
1206 * pci_enable_msix_range - configure device's MSI-X capability structure
1207 * @dev: pointer to the pci_dev data structure of MSI-X device function
1208 * @entries: pointer to an array of MSI-X entries
1209 * @minvec: minimum number of MSI-X irqs requested
1210 * @maxvec: maximum number of MSI-X irqs requested
1212 * Setup the MSI-X capability structure of device function with a maximum
1213 * possible number of interrupts in the range between @minvec and @maxvec
1214 * upon its software driver call to request for MSI-X mode enabled on its
1215 * hardware device function. It returns a negative errno if an error occurs.
1216 * If it succeeds, it returns the actual number of interrupts allocated and
1217 * indicates the successful configuration of MSI-X capability structure
1218 * with new allocated MSI-X interrupts.
1220 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1221 int minvec, int maxvec)
1223 return __pci_enable_msix_range(dev, entries, minvec, maxvec, 0);
1225 EXPORT_SYMBOL(pci_enable_msix_range);
1228 * pci_alloc_irq_vectors - allocate multiple IRQs for a device
1229 * @dev: PCI device to operate on
1230 * @min_vecs: minimum number of vectors required (must be >= 1)
1231 * @max_vecs: maximum (desired) number of vectors
1232 * @flags: flags or quirks for the allocation
1234 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1235 * vectors if available, and fall back to a single legacy vector
1236 * if neither is available. Return the number of vectors allocated,
1237 * (which might be smaller than @max_vecs) if successful, or a negative
1238 * error code on error. If less than @min_vecs interrupt vectors are
1239 * available for @dev the function will fail with -ENOSPC.
1241 * To get the Linux IRQ number used for a vector that can be passed to
1242 * request_irq() use the pci_irq_vector() helper.
1244 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1245 unsigned int max_vecs, unsigned int flags)
1249 if (flags & PCI_IRQ_MSIX) {
1250 vecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1256 if (flags & PCI_IRQ_MSI) {
1257 vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, flags);
1262 /* use legacy irq if allowed */
1263 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1) {
1270 EXPORT_SYMBOL(pci_alloc_irq_vectors);
1273 * pci_free_irq_vectors - free previously allocated IRQs for a device
1274 * @dev: PCI device to operate on
1276 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1278 void pci_free_irq_vectors(struct pci_dev *dev)
1280 pci_disable_msix(dev);
1281 pci_disable_msi(dev);
1283 EXPORT_SYMBOL(pci_free_irq_vectors);
1286 * pci_irq_vector - return Linux IRQ number of a device vector
1287 * @dev: PCI device to operate on
1288 * @nr: device-relative interrupt vector index (0-based).
1290 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1292 if (dev->msix_enabled) {
1293 struct msi_desc *entry;
1296 for_each_pci_msi_entry(entry, dev) {
1305 if (dev->msi_enabled) {
1306 struct msi_desc *entry = first_pci_msi_entry(dev);
1308 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1311 if (WARN_ON_ONCE(nr > 0))
1315 return dev->irq + nr;
1317 EXPORT_SYMBOL(pci_irq_vector);
1320 * pci_irq_get_affinity - return the affinity of a particular msi vector
1321 * @dev: PCI device to operate on
1322 * @nr: device-relative interrupt vector index (0-based).
1324 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1326 if (dev->msix_enabled) {
1327 struct msi_desc *entry;
1330 for_each_pci_msi_entry(entry, dev) {
1332 return entry->affinity;
1337 } else if (dev->msi_enabled) {
1338 struct msi_desc *entry = first_pci_msi_entry(dev);
1340 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1341 nr >= entry->nvec_used))
1344 return &entry->affinity[nr];
1346 return cpu_possible_mask;
1349 EXPORT_SYMBOL(pci_irq_get_affinity);
1351 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1353 return to_pci_dev(desc->dev);
1355 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1357 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1359 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1361 return dev->bus->sysdata;
1363 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1365 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1367 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1368 * @irq_data: Pointer to interrupt data of the MSI interrupt
1369 * @msg: Pointer to the message
1371 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1373 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1376 * For MSI-X desc->irq is always equal to irq_data->irq. For
1377 * MSI only the first interrupt of MULTI MSI passes the test.
1379 if (desc->irq == irq_data->irq)
1380 __pci_write_msi_msg(desc, msg);
1384 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1385 * @dev: Pointer to the PCI device
1386 * @desc: Pointer to the msi descriptor
1388 * The ID number is only used within the irqdomain.
1390 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1391 struct msi_desc *desc)
1393 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1394 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1395 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1398 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1400 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1404 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1405 * @domain: The interrupt domain to check
1406 * @info: The domain info for verification
1407 * @dev: The device to check
1410 * 0 if the functionality is supported
1411 * 1 if Multi MSI is requested, but the domain does not support it
1412 * -ENOTSUPP otherwise
1414 int pci_msi_domain_check_cap(struct irq_domain *domain,
1415 struct msi_domain_info *info, struct device *dev)
1417 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1419 /* Special handling to support pci_enable_msi_range() */
1420 if (pci_msi_desc_is_multi_msi(desc) &&
1421 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1423 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1429 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1430 struct msi_desc *desc, int error)
1432 /* Special handling to support pci_enable_msi_range() */
1433 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1439 #ifdef GENERIC_MSI_DOMAIN_OPS
1440 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1441 struct msi_desc *desc)
1444 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1448 #define pci_msi_domain_set_desc NULL
1451 static struct msi_domain_ops pci_msi_domain_ops_default = {
1452 .set_desc = pci_msi_domain_set_desc,
1453 .msi_check = pci_msi_domain_check_cap,
1454 .handle_error = pci_msi_domain_handle_error,
1457 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1459 struct msi_domain_ops *ops = info->ops;
1462 info->ops = &pci_msi_domain_ops_default;
1464 if (ops->set_desc == NULL)
1465 ops->set_desc = pci_msi_domain_set_desc;
1466 if (ops->msi_check == NULL)
1467 ops->msi_check = pci_msi_domain_check_cap;
1468 if (ops->handle_error == NULL)
1469 ops->handle_error = pci_msi_domain_handle_error;
1473 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1475 struct irq_chip *chip = info->chip;
1478 if (!chip->irq_write_msi_msg)
1479 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1480 if (!chip->irq_mask)
1481 chip->irq_mask = pci_msi_mask_irq;
1482 if (!chip->irq_unmask)
1483 chip->irq_unmask = pci_msi_unmask_irq;
1487 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1488 * @fwnode: Optional fwnode of the interrupt controller
1489 * @info: MSI domain info
1490 * @parent: Parent irq domain
1492 * Updates the domain and chip ops and creates a MSI interrupt domain.
1495 * A domain pointer or NULL in case of failure.
1497 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1498 struct msi_domain_info *info,
1499 struct irq_domain *parent)
1501 struct irq_domain *domain;
1503 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1504 pci_msi_domain_update_dom_ops(info);
1505 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1506 pci_msi_domain_update_chip_ops(info);
1508 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1510 domain = msi_create_irq_domain(fwnode, info, parent);
1514 domain->bus_token = DOMAIN_BUS_PCI_MSI;
1517 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1520 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1521 * @domain: The interrupt domain to allocate from
1522 * @dev: The device for which to allocate
1523 * @nvec: The number of interrupts to allocate
1524 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1527 * A virtual interrupt number or an error code in case of failure
1529 int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1532 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1536 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1537 * @domain: The interrupt domain
1538 * @dev: The device for which to free interrupts
1540 void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1542 msi_domain_free_irqs(domain, &dev->dev);
1546 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1547 * @fwnode: Optional fwnode of the interrupt controller
1548 * @info: MSI domain info
1549 * @parent: Parent irq domain
1551 * Returns: A domain pointer or NULL in case of failure. If successful
1552 * the default PCI/MSI irqdomain pointer is updated.
1554 struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
1555 struct msi_domain_info *info, struct irq_domain *parent)
1557 struct irq_domain *domain;
1559 mutex_lock(&pci_msi_domain_lock);
1560 if (pci_msi_default_domain) {
1561 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1564 domain = pci_msi_create_irq_domain(fwnode, info, parent);
1565 pci_msi_default_domain = domain;
1567 mutex_unlock(&pci_msi_domain_lock);
1572 static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1580 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1581 * @domain: The interrupt domain
1582 * @pdev: The PCI device.
1584 * The RID for a device is formed from the alias, with a firmware
1585 * supplied mapping applied
1589 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1591 struct device_node *of_node;
1594 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1596 of_node = irq_domain_get_of_node(domain);
1597 rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) :
1598 iort_msi_map_rid(&pdev->dev, rid);
1604 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1605 * @pdev: The PCI device
1607 * Use the firmware data to find a device-specific MSI domain
1608 * (i.e. not one that is ste as a default).
1610 * Returns: The coresponding MSI domain or NULL if none has been found.
1612 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1614 struct irq_domain *dom;
1617 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1618 dom = of_msi_map_get_device_domain(&pdev->dev, rid);
1620 dom = iort_get_device_domain(&pdev->dev, rid);
1623 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */