1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI Express PCI Hot Plug Driver
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
10 * All rights reserved.
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
15 #define dev_fmt(fmt) "pciehp: " fmt
17 #include <linux/dmi.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/jiffies.h>
21 #include <linux/kthread.h>
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
30 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
32 * Match all Dell systems, as some Dell systems have inband
33 * presence disabled on NVMe slots (but don't support the bit to
34 * report it). Setting inband presence disabled should have no
35 * negative effect, except on broken hotplug slots that never
36 * assert presence detect--and those will still work, they will
37 * just have a bit of extra delay before being probed.
40 .ident = "Dell System",
42 DMI_MATCH(DMI_OEM_STRING, "Dell System"),
48 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
50 return ctrl->pcie->port;
53 static irqreturn_t pciehp_isr(int irq, void *dev_id);
54 static irqreturn_t pciehp_ist(int irq, void *dev_id);
55 static int pciehp_poll(void *data);
57 static inline int pciehp_request_irq(struct controller *ctrl)
59 int retval, irq = ctrl->pcie->irq;
61 if (pciehp_poll_mode) {
62 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
65 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
68 /* Installs the interrupt handler */
69 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
70 IRQF_SHARED, "pciehp", ctrl);
72 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
77 static inline void pciehp_free_irq(struct controller *ctrl)
80 kthread_stop(ctrl->poll_thread);
82 free_irq(ctrl->pcie->irq, ctrl);
85 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
87 struct pci_dev *pdev = ctrl_dev(ctrl);
91 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
92 if (slot_status == (u16) ~0) {
93 ctrl_info(ctrl, "%s: no response from device\n",
98 if (slot_status & PCI_EXP_SLTSTA_CC) {
99 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
107 } while (timeout >= 0);
108 return 0; /* timeout */
111 static void pcie_wait_cmd(struct controller *ctrl)
113 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
114 unsigned long duration = msecs_to_jiffies(msecs);
115 unsigned long cmd_timeout = ctrl->cmd_started + duration;
116 unsigned long now, timeout;
120 * If the controller does not generate notifications for command
121 * completions, we never need to wait between writes.
123 if (NO_CMD_CMPL(ctrl))
130 * Even if the command has already timed out, we want to call
131 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
134 if (time_before_eq(cmd_timeout, now))
137 timeout = cmd_timeout - now;
139 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
140 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
141 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
143 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
146 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
148 jiffies_to_msecs(jiffies - ctrl->cmd_started));
151 #define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \
152 PCI_EXP_SLTCTL_PIC | \
153 PCI_EXP_SLTCTL_AIC | \
156 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
159 struct pci_dev *pdev = ctrl_dev(ctrl);
160 u16 slot_ctrl_orig, slot_ctrl;
162 mutex_lock(&ctrl->ctrl_lock);
165 * Always wait for any previous command that might still be in progress
169 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
170 if (slot_ctrl == (u16) ~0) {
171 ctrl_info(ctrl, "%s: no response from device\n", __func__);
175 slot_ctrl_orig = slot_ctrl;
177 slot_ctrl |= (cmd & mask);
180 ctrl->slot_ctrl = slot_ctrl;
181 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
182 ctrl->cmd_started = jiffies;
185 * Controllers with the Intel CF118 and similar errata advertise
186 * Command Completed support, but they only set Command Completed
187 * if we change the "Control" bits for power, power indicator,
188 * attention indicator, or interlock. If we only change the
189 * "Enable" bits, they never set the Command Completed bit.
191 if (pdev->broken_cmd_compl &&
192 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
196 * Optionally wait for the hardware to be ready for a new command,
197 * indicating completion of the above issued command.
203 mutex_unlock(&ctrl->ctrl_lock);
207 * pcie_write_cmd - Issue controller command
208 * @ctrl: controller to which the command is issued
209 * @cmd: command value written to slot control register
210 * @mask: bitmask of slot control register to be modified
212 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
214 pcie_do_write_cmd(ctrl, cmd, mask, true);
217 /* Same as above without waiting for the hardware to latch */
218 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
220 pcie_do_write_cmd(ctrl, cmd, mask, false);
224 * pciehp_check_link_active() - Is the link active
225 * @ctrl: PCIe hotplug controller
227 * Check whether the downstream link is currently active. Note it is
228 * possible that the card is removed immediately after this so the
229 * caller may need to take it into account.
231 * If the hotplug controller itself is not available anymore returns
234 int pciehp_check_link_active(struct controller *ctrl)
236 struct pci_dev *pdev = ctrl_dev(ctrl);
240 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
241 if (ret == PCIBIOS_DEVICE_NOT_FOUND || lnk_status == (u16)~0)
244 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
245 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
250 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
254 int delay = 1000, step = 20;
258 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
269 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
270 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
271 PCI_FUNC(devfn), count, step, l);
276 static void pcie_wait_for_presence(struct pci_dev *pdev)
282 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
283 if (slot_status & PCI_EXP_SLTSTA_PDS)
287 } while (timeout > 0);
290 int pciehp_check_link_status(struct controller *ctrl)
292 struct pci_dev *pdev = ctrl_dev(ctrl);
296 if (!pcie_wait_for_link(pdev, true)) {
297 ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
301 if (ctrl->inband_presence_disabled)
302 pcie_wait_for_presence(pdev);
304 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
307 /* ignore link or presence changes up to this point */
309 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
310 &ctrl->pending_events);
312 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
313 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
314 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
315 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
316 ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
317 slot_name(ctrl), lnk_status);
321 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
324 ctrl_info(ctrl, "Slot(%s): No device found\n",
332 static int __pciehp_link_set(struct controller *ctrl, bool enable)
334 struct pci_dev *pdev = ctrl_dev(ctrl);
336 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
338 enable ? 0 : PCI_EXP_LNKCTL_LD);
343 static int pciehp_link_enable(struct controller *ctrl)
345 return __pciehp_link_set(ctrl, true);
348 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
351 struct controller *ctrl = to_ctrl(hotplug_slot);
352 struct pci_dev *pdev = ctrl_dev(ctrl);
355 pci_config_pm_runtime_get(pdev);
356 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
357 pci_config_pm_runtime_put(pdev);
358 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
362 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
364 struct controller *ctrl = to_ctrl(hotplug_slot);
365 struct pci_dev *pdev = ctrl_dev(ctrl);
368 pci_config_pm_runtime_get(pdev);
369 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
370 pci_config_pm_runtime_put(pdev);
371 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
372 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
374 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
375 case PCI_EXP_SLTCTL_ATTN_IND_ON:
376 *status = 1; /* On */
378 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
379 *status = 2; /* Blink */
381 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
382 *status = 0; /* Off */
392 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
394 struct pci_dev *pdev = ctrl_dev(ctrl);
397 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
398 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
399 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
401 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
402 case PCI_EXP_SLTCTL_PWR_ON:
403 *status = 1; /* On */
405 case PCI_EXP_SLTCTL_PWR_OFF:
406 *status = 0; /* Off */
414 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
416 struct pci_dev *pdev = ctrl_dev(ctrl);
419 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
420 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
424 * pciehp_card_present() - Is the card present
425 * @ctrl: PCIe hotplug controller
427 * Function checks whether the card is currently present in the slot and
428 * in that case returns true. Note it is possible that the card is
429 * removed immediately after the check so the caller may need to take
432 * It the hotplug controller itself is not available anymore returns
435 int pciehp_card_present(struct controller *ctrl)
437 struct pci_dev *pdev = ctrl_dev(ctrl);
441 ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
442 if (ret == PCIBIOS_DEVICE_NOT_FOUND || slot_status == (u16)~0)
445 return !!(slot_status & PCI_EXP_SLTSTA_PDS);
449 * pciehp_card_present_or_link_active() - whether given slot is occupied
450 * @ctrl: PCIe hotplug controller
452 * Unlike pciehp_card_present(), which determines presence solely from the
453 * Presence Detect State bit, this helper also returns true if the Link Active
454 * bit is set. This is a concession to broken hotplug ports which hardwire
455 * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
457 * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
458 * port is not present anymore returns %-ENODEV.
460 int pciehp_card_present_or_link_active(struct controller *ctrl)
464 ret = pciehp_card_present(ctrl);
468 return pciehp_check_link_active(ctrl);
471 int pciehp_query_power_fault(struct controller *ctrl)
473 struct pci_dev *pdev = ctrl_dev(ctrl);
476 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
477 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
480 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
483 struct controller *ctrl = to_ctrl(hotplug_slot);
484 struct pci_dev *pdev = ctrl_dev(ctrl);
486 pci_config_pm_runtime_get(pdev);
487 pcie_write_cmd_nowait(ctrl, status << 6,
488 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
489 pci_config_pm_runtime_put(pdev);
494 * pciehp_set_indicators() - set attention indicator, power indicator, or both
495 * @ctrl: PCIe hotplug controller
497 * PCI_EXP_SLTCTL_PWR_IND_ON
498 * PCI_EXP_SLTCTL_PWR_IND_BLINK
499 * PCI_EXP_SLTCTL_PWR_IND_OFF
501 * PCI_EXP_SLTCTL_ATTN_IND_ON
502 * PCI_EXP_SLTCTL_ATTN_IND_BLINK
503 * PCI_EXP_SLTCTL_ATTN_IND_OFF
505 * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
508 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
510 u16 cmd = 0, mask = 0;
512 if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
513 cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
514 mask |= PCI_EXP_SLTCTL_PIC;
517 if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
518 cmd |= (attn & PCI_EXP_SLTCTL_AIC);
519 mask |= PCI_EXP_SLTCTL_AIC;
523 pcie_write_cmd_nowait(ctrl, cmd, mask);
524 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
525 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
529 int pciehp_power_on_slot(struct controller *ctrl)
531 struct pci_dev *pdev = ctrl_dev(ctrl);
535 /* Clear power-fault bit from previous power failures */
536 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
537 if (slot_status & PCI_EXP_SLTSTA_PFD)
538 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
540 ctrl->power_fault_detected = 0;
542 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
543 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
544 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
545 PCI_EXP_SLTCTL_PWR_ON);
547 retval = pciehp_link_enable(ctrl);
549 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
554 void pciehp_power_off_slot(struct controller *ctrl)
556 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
557 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
558 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
559 PCI_EXP_SLTCTL_PWR_OFF);
562 static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
563 struct pci_dev *pdev, int irq)
566 * Ignore link changes which occurred while waiting for DPC recovery.
567 * Could be several if DPC triggered multiple times consecutively.
569 synchronize_hardirq(irq);
570 atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
571 if (pciehp_poll_mode)
572 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
573 PCI_EXP_SLTSTA_DLLSC);
574 ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
578 * If the link is unexpectedly down after successful recovery,
579 * the corresponding link change may have been ignored above.
580 * Synthesize it to ensure that it is acted on.
582 down_read_nested(&ctrl->reset_lock, ctrl->depth);
583 if (!pciehp_check_link_active(ctrl))
584 pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
585 up_read(&ctrl->reset_lock);
588 static irqreturn_t pciehp_isr(int irq, void *dev_id)
590 struct controller *ctrl = (struct controller *)dev_id;
591 struct pci_dev *pdev = ctrl_dev(ctrl);
592 struct device *parent = pdev->dev.parent;
593 u16 status, events = 0;
596 * Interrupts only occur in D3hot or shallower and only if enabled
597 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
599 if (pdev->current_state == PCI_D3cold ||
600 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
604 * Keep the port accessible by holding a runtime PM ref on its parent.
605 * Defer resume of the parent to the IRQ thread if it's suspended.
606 * Mask the interrupt until then.
609 pm_runtime_get_noresume(parent);
610 if (!pm_runtime_active(parent)) {
611 pm_runtime_put(parent);
612 disable_irq_nosync(irq);
613 atomic_or(RERUN_ISR, &ctrl->pending_events);
614 return IRQ_WAKE_THREAD;
619 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
620 if (status == (u16) ~0) {
621 ctrl_info(ctrl, "%s: no response from device\n", __func__);
623 pm_runtime_put(parent);
628 * Slot Status contains plain status bits as well as event
629 * notification bits; right now we only want the event bits.
631 status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
632 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
633 PCI_EXP_SLTSTA_DLLSC;
636 * If we've already reported a power fault, don't report it again
637 * until we've done something to handle it.
639 if (ctrl->power_fault_detected)
640 status &= ~PCI_EXP_SLTSTA_PFD;
641 else if (status & PCI_EXP_SLTSTA_PFD)
642 ctrl->power_fault_detected = true;
647 pm_runtime_put(parent);
652 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status);
655 * In MSI mode, all event bits must be zero before the port
656 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
657 * So re-read the Slot Status register in case a bit was set
658 * between read and write.
660 if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
664 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
666 pm_runtime_put(parent);
669 * Command Completed notifications are not deferred to the
670 * IRQ thread because it may be waiting for their arrival.
672 if (events & PCI_EXP_SLTSTA_CC) {
675 wake_up(&ctrl->queue);
677 if (events == PCI_EXP_SLTSTA_CC)
680 events &= ~PCI_EXP_SLTSTA_CC;
683 if (pdev->ignore_hotplug) {
684 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
688 /* Save pending events for consumption by IRQ thread. */
689 atomic_or(events, &ctrl->pending_events);
690 return IRQ_WAKE_THREAD;
693 static irqreturn_t pciehp_ist(int irq, void *dev_id)
695 struct controller *ctrl = (struct controller *)dev_id;
696 struct pci_dev *pdev = ctrl_dev(ctrl);
700 ctrl->ist_running = true;
701 pci_config_pm_runtime_get(pdev);
703 /* rerun pciehp_isr() if the port was inaccessible on interrupt */
704 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
705 ret = pciehp_isr(irq, dev_id);
707 if (ret != IRQ_WAKE_THREAD)
711 synchronize_hardirq(irq);
712 events = atomic_xchg(&ctrl->pending_events, 0);
718 /* Check Attention Button Pressed */
719 if (events & PCI_EXP_SLTSTA_ABP) {
720 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
722 pciehp_handle_button_press(ctrl);
725 /* Check Power Fault Detected */
726 if (events & PCI_EXP_SLTSTA_PFD) {
727 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
728 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
729 PCI_EXP_SLTCTL_ATTN_IND_ON);
733 * Ignore Link Down/Up events caused by Downstream Port Containment
734 * if recovery from the error succeeded.
736 if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
737 ctrl->state == ON_STATE) {
738 events &= ~PCI_EXP_SLTSTA_DLLSC;
739 pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
743 * Disable requests have higher priority than Presence Detect Changed
744 * or Data Link Layer State Changed events.
746 down_read_nested(&ctrl->reset_lock, ctrl->depth);
747 if (events & DISABLE_SLOT)
748 pciehp_handle_disable_request(ctrl);
749 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
750 pciehp_handle_presence_or_link_change(ctrl, events);
751 up_read(&ctrl->reset_lock);
755 pci_config_pm_runtime_put(pdev);
756 ctrl->ist_running = false;
757 wake_up(&ctrl->requester);
761 static int pciehp_poll(void *data)
763 struct controller *ctrl = data;
765 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
767 while (!kthread_should_stop()) {
768 /* poll for interrupt events or user requests */
769 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
770 atomic_read(&ctrl->pending_events))
771 pciehp_ist(IRQ_NOTCONNECTED, ctrl);
773 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
774 pciehp_poll_time = 2; /* clamp to sane value */
776 schedule_timeout_idle(pciehp_poll_time * HZ);
782 static void pcie_enable_notification(struct controller *ctrl)
787 * TBD: Power fault detected software notification support.
789 * Power fault detected software notification is not enabled
790 * now, because it caused power fault detected interrupt storm
791 * on some machines. On those machines, power fault detected
792 * bit in the slot status register was set again immediately
793 * when it is cleared in the interrupt service routine, and
794 * next power fault detected interrupt was notified again.
798 * Always enable link events: thus link-up and link-down shall
799 * always be treated as hotplug and unplug respectively. Enable
800 * presence detect only if Attention Button is not present.
802 cmd = PCI_EXP_SLTCTL_DLLSCE;
803 if (ATTN_BUTTN(ctrl))
804 cmd |= PCI_EXP_SLTCTL_ABPE;
806 cmd |= PCI_EXP_SLTCTL_PDCE;
807 if (!pciehp_poll_mode)
808 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
810 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
811 PCI_EXP_SLTCTL_PFDE |
812 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
813 PCI_EXP_SLTCTL_DLLSCE);
815 pcie_write_cmd_nowait(ctrl, cmd, mask);
816 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
817 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
820 static void pcie_disable_notification(struct controller *ctrl)
824 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
825 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
826 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
827 PCI_EXP_SLTCTL_DLLSCE);
828 pcie_write_cmd(ctrl, 0, mask);
829 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
830 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
833 void pcie_clear_hotplug_events(struct controller *ctrl)
835 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
836 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
839 void pcie_enable_interrupt(struct controller *ctrl)
843 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
844 pcie_write_cmd(ctrl, mask, mask);
847 void pcie_disable_interrupt(struct controller *ctrl)
852 * Mask hot-plug interrupt to prevent it triggering immediately
853 * when the link goes inactive (we still get PME when any of the
854 * enabled events is detected). Same goes with Link Layer State
855 * changed event which generates PME immediately when the link goes
856 * inactive so mask it as well.
858 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
859 pcie_write_cmd(ctrl, 0, mask);
863 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
864 * bus reset of the bridge, but at the same time we want to ensure that it is
865 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
866 * disable link state notification and presence detection change notification
867 * momentarily, if we see that they could interfere. Also, clear any spurious
870 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe)
872 struct controller *ctrl = to_ctrl(hotplug_slot);
873 struct pci_dev *pdev = ctrl_dev(ctrl);
874 u16 stat_mask = 0, ctrl_mask = 0;
880 down_write_nested(&ctrl->reset_lock, ctrl->depth);
882 if (!ATTN_BUTTN(ctrl)) {
883 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
884 stat_mask |= PCI_EXP_SLTSTA_PDC;
886 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
887 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
889 pcie_write_cmd(ctrl, 0, ctrl_mask);
890 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
891 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
893 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
895 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
896 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
897 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
898 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
900 up_write(&ctrl->reset_lock);
904 int pcie_init_notification(struct controller *ctrl)
906 if (pciehp_request_irq(ctrl))
908 pcie_enable_notification(ctrl);
909 ctrl->notification_enabled = 1;
913 void pcie_shutdown_notification(struct controller *ctrl)
915 if (ctrl->notification_enabled) {
916 pcie_disable_notification(ctrl);
917 pciehp_free_irq(ctrl);
918 ctrl->notification_enabled = 0;
922 static inline void dbg_ctrl(struct controller *ctrl)
924 struct pci_dev *pdev = ctrl->pcie->port;
927 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
928 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
929 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16);
930 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
931 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16);
934 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
936 static inline int pcie_hotplug_depth(struct pci_dev *dev)
938 struct pci_bus *bus = dev->bus;
941 while (bus->parent) {
943 if (bus->self && bus->self->is_hotplug_bridge)
950 struct controller *pcie_init(struct pcie_device *dev)
952 struct controller *ctrl;
953 u32 slot_cap, slot_cap2, link_cap;
955 struct pci_dev *pdev = dev->port;
956 struct pci_bus *subordinate = pdev->subordinate;
958 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
963 ctrl->depth = pcie_hotplug_depth(dev->port);
964 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
966 if (pdev->hotplug_user_indicators)
967 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
970 * We assume no Thunderbolt controllers support Command Complete events,
971 * but some controllers falsely claim they do.
973 if (pdev->is_thunderbolt)
974 slot_cap |= PCI_EXP_SLTCAP_NCCS;
976 ctrl->slot_cap = slot_cap;
977 mutex_init(&ctrl->ctrl_lock);
978 mutex_init(&ctrl->state_lock);
979 init_rwsem(&ctrl->reset_lock);
980 init_waitqueue_head(&ctrl->requester);
981 init_waitqueue_head(&ctrl->queue);
982 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
985 down_read(&pci_bus_sem);
986 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
987 up_read(&pci_bus_sem);
989 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
990 if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
991 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
992 PCI_EXP_SLTCTL_IBPD_DISABLE);
993 ctrl->inband_presence_disabled = 1;
996 if (dmi_first_match(inband_presence_disabled_dmi_table))
997 ctrl->inband_presence_disabled = 1;
999 /* Check if Data Link Layer Link Active Reporting is implemented */
1000 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
1002 /* Clear all remaining event bits in Slot Status register. */
1003 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
1004 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
1005 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
1006 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
1008 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
1009 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
1010 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
1011 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
1012 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
1013 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
1014 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
1015 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
1016 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
1017 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
1018 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1019 FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
1020 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
1021 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
1024 * If empty slot's power status is on, turn power off. The IRQ isn't
1025 * requested yet, so avoid triggering a notification with this command.
1027 if (POWER_CTRL(ctrl)) {
1028 pciehp_get_power_status(ctrl, &poweron);
1029 if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
1030 pcie_disable_notification(ctrl);
1031 pciehp_power_off_slot(ctrl);
1038 void pciehp_release_ctrl(struct controller *ctrl)
1040 cancel_delayed_work_sync(&ctrl->button_work);
1044 static void quirk_cmd_compl(struct pci_dev *pdev)
1048 if (pci_is_pcie(pdev)) {
1049 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
1050 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
1051 !(slot_cap & PCI_EXP_SLTCAP_NCCS))
1052 pdev->broken_cmd_compl = 1;
1055 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1056 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1057 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110,
1058 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1059 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
1060 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1061 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
1062 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1063 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1064 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);