2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
46 return ctrl->pcie->port;
49 static irqreturn_t pcie_isr(int irq, void *dev_id);
50 static void start_int_poll_timer(struct controller *ctrl, int sec);
52 /* This is the interrupt polling timeout function. */
53 static void int_poll_timeout(unsigned long data)
55 struct controller *ctrl = (struct controller *)data;
57 /* Poll for interrupt events. regs == NULL => polling */
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
64 start_int_poll_timer(ctrl, pciehp_poll_time);
67 /* This function starts the interrupt polling timer. */
68 static void start_int_poll_timer(struct controller *ctrl, int sec)
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
80 static inline int pciehp_request_irq(struct controller *ctrl)
82 int retval, irq = ctrl->pcie->irq;
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
99 static inline void pciehp_free_irq(struct controller *ctrl)
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
104 free_irq(ctrl->pcie->irq, ctrl);
107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
109 struct pci_dev *pdev = ctrl_dev(ctrl);
113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
114 if (slot_status == (u16) ~0) {
115 ctrl_info(ctrl, "%s: no response from device\n",
120 if (slot_status & PCI_EXP_SLTSTA_CC) {
121 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
132 return 0; /* timeout */
135 static void pcie_wait_cmd(struct controller *ctrl)
137 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
138 unsigned long duration = msecs_to_jiffies(msecs);
139 unsigned long cmd_timeout = ctrl->cmd_started + duration;
140 unsigned long now, timeout;
144 * If the controller does not generate notifications for command
145 * completions, we never need to wait between writes.
147 if (NO_CMD_CMPL(ctrl))
154 * Even if the command has already timed out, we want to call
155 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
158 if (time_before_eq(cmd_timeout, now))
161 timeout = cmd_timeout - now;
163 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
164 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
165 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
167 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
170 * Controllers with errata like Intel CF118 don't generate
171 * completion notifications unless the power/indicator/interlock
172 * control bits are changed. On such controllers, we'll emit this
173 * timeout message when we wait for completion of commands that
174 * don't change those bits, e.g., commands that merely enable
178 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
180 jiffies_to_msecs(jiffies - ctrl->cmd_started));
183 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
186 struct pci_dev *pdev = ctrl_dev(ctrl);
189 mutex_lock(&ctrl->ctrl_lock);
192 * Always wait for any previous command that might still be in progress
196 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
197 if (slot_ctrl == (u16) ~0) {
198 ctrl_info(ctrl, "%s: no response from device\n", __func__);
203 slot_ctrl |= (cmd & mask);
206 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
207 ctrl->cmd_started = jiffies;
208 ctrl->slot_ctrl = slot_ctrl;
211 * Optionally wait for the hardware to be ready for a new command,
212 * indicating completion of the above issued command.
218 mutex_unlock(&ctrl->ctrl_lock);
222 * pcie_write_cmd - Issue controller command
223 * @ctrl: controller to which the command is issued
224 * @cmd: command value written to slot control register
225 * @mask: bitmask of slot control register to be modified
227 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
229 pcie_do_write_cmd(ctrl, cmd, mask, true);
232 /* Same as above without waiting for the hardware to latch */
233 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
235 pcie_do_write_cmd(ctrl, cmd, mask, false);
238 bool pciehp_check_link_active(struct controller *ctrl)
240 struct pci_dev *pdev = ctrl_dev(ctrl);
244 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
245 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
248 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
253 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
257 if (pciehp_check_link_active(ctrl) == active)
259 while (timeout > 0) {
262 if (pciehp_check_link_active(ctrl) == active)
265 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
266 active ? "set" : "cleared");
269 static void pcie_wait_link_active(struct controller *ctrl)
271 __pcie_wait_link_active(ctrl, true);
274 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
278 int delay = 1000, step = 20;
282 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
292 if (count > 1 && pciehp_debug)
293 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
294 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
295 PCI_FUNC(devfn), count, step, l);
300 int pciehp_check_link_status(struct controller *ctrl)
302 struct pci_dev *pdev = ctrl_dev(ctrl);
307 * Data Link Layer Link Active Reporting must be capable for
308 * hot-plug capable downstream port. But old controller might
309 * not implement it. In this case, we wait for 1000 ms.
311 if (ctrl->link_active_reporting)
312 pcie_wait_link_active(ctrl);
316 /* wait 100ms before read pci conf, and try in 1s */
318 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
321 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
322 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
323 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
324 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
325 ctrl_err(ctrl, "link training error: status %#06x\n",
330 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
338 static int __pciehp_link_set(struct controller *ctrl, bool enable)
340 struct pci_dev *pdev = ctrl_dev(ctrl);
342 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
344 enable ? 0 : PCI_EXP_LNKCTL_LD);
349 static int pciehp_link_enable(struct controller *ctrl)
351 return __pciehp_link_set(ctrl, true);
354 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
357 struct slot *slot = hotplug_slot->private;
358 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
361 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
362 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
366 void pciehp_get_attention_status(struct slot *slot, u8 *status)
368 struct controller *ctrl = slot->ctrl;
369 struct pci_dev *pdev = ctrl_dev(ctrl);
372 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
373 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
374 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
376 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
377 case PCI_EXP_SLTCTL_ATTN_IND_ON:
378 *status = 1; /* On */
380 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
381 *status = 2; /* Blink */
383 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
384 *status = 0; /* Off */
392 void pciehp_get_power_status(struct slot *slot, u8 *status)
394 struct controller *ctrl = slot->ctrl;
395 struct pci_dev *pdev = ctrl_dev(ctrl);
398 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
399 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
400 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
402 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
403 case PCI_EXP_SLTCTL_PWR_ON:
404 *status = 1; /* On */
406 case PCI_EXP_SLTCTL_PWR_OFF:
407 *status = 0; /* Off */
415 void pciehp_get_latch_status(struct slot *slot, u8 *status)
417 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
420 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
421 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
424 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
426 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
429 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
430 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
433 int pciehp_query_power_fault(struct slot *slot)
435 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
438 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
439 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
442 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
445 struct slot *slot = hotplug_slot->private;
446 struct controller *ctrl = slot->ctrl;
448 pcie_write_cmd_nowait(ctrl, status << 6,
449 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
453 void pciehp_set_attention_status(struct slot *slot, u8 value)
455 struct controller *ctrl = slot->ctrl;
462 case 0: /* turn off */
463 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
465 case 1: /* turn on */
466 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
468 case 2: /* turn blink */
469 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
474 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
475 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
476 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
479 void pciehp_green_led_on(struct slot *slot)
481 struct controller *ctrl = slot->ctrl;
486 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
488 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
489 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
490 PCI_EXP_SLTCTL_PWR_IND_ON);
493 void pciehp_green_led_off(struct slot *slot)
495 struct controller *ctrl = slot->ctrl;
500 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
502 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
503 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
504 PCI_EXP_SLTCTL_PWR_IND_OFF);
507 void pciehp_green_led_blink(struct slot *slot)
509 struct controller *ctrl = slot->ctrl;
514 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
516 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
517 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
518 PCI_EXP_SLTCTL_PWR_IND_BLINK);
521 int pciehp_power_on_slot(struct slot *slot)
523 struct controller *ctrl = slot->ctrl;
524 struct pci_dev *pdev = ctrl_dev(ctrl);
528 /* Clear sticky power-fault bit from previous power failures */
529 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
530 if (slot_status & PCI_EXP_SLTSTA_PFD)
531 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
533 ctrl->power_fault_detected = 0;
535 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
536 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
537 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
538 PCI_EXP_SLTCTL_PWR_ON);
540 retval = pciehp_link_enable(ctrl);
542 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
547 void pciehp_power_off_slot(struct slot *slot)
549 struct controller *ctrl = slot->ctrl;
551 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
552 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
553 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
554 PCI_EXP_SLTCTL_PWR_OFF);
557 static irqreturn_t pciehp_isr(int irq, void *dev_id)
559 struct controller *ctrl = (struct controller *)dev_id;
560 struct pci_dev *pdev = ctrl_dev(ctrl);
561 struct slot *slot = ctrl->slot;
566 /* Interrupts cannot originate from a controller that's asleep */
567 if (pdev->current_state == PCI_D3cold)
570 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
571 if (status == (u16) ~0) {
572 ctrl_info(ctrl, "%s: no response from device\n", __func__);
577 * Slot Status contains plain status bits as well as event
578 * notification bits; right now we only want the event bits.
580 events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
581 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
582 PCI_EXP_SLTSTA_DLLSC);
585 * If we've already reported a power fault, don't report it again
586 * until we've done something to handle it.
588 if (ctrl->power_fault_detected)
589 events &= ~PCI_EXP_SLTSTA_PFD;
594 /* Capture link status before clearing interrupts */
595 if (events & PCI_EXP_SLTSTA_DLLSC)
596 link = pciehp_check_link_active(ctrl);
598 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
599 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
601 /* Check Command Complete Interrupt Pending */
602 if (events & PCI_EXP_SLTSTA_CC) {
605 wake_up(&ctrl->queue);
608 if (pdev->ignore_hotplug) {
609 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
613 /* Check Attention Button Pressed */
614 if (events & PCI_EXP_SLTSTA_ABP) {
615 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
617 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
621 * Check Link Status Changed at higher precedence than Presence
622 * Detect Changed. The PDS value may be set to "card present" from
623 * out-of-band detection, which may be in conflict with a Link Down
624 * and cause the wrong event to queue.
626 if (events & PCI_EXP_SLTSTA_DLLSC) {
627 ctrl_info(ctrl, "Slot(%s): Link %s\n", slot_name(slot),
628 link ? "Up" : "Down");
629 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
631 } else if (events & PCI_EXP_SLTSTA_PDC) {
632 present = !!(status & PCI_EXP_SLTSTA_PDS);
633 ctrl_info(ctrl, "Slot(%s): Card %spresent\n", slot_name(slot),
634 present ? "" : "not ");
635 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
639 /* Check Power Fault Detected */
640 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
641 ctrl->power_fault_detected = 1;
642 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
643 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
649 static irqreturn_t pcie_isr(int irq, void *dev_id)
651 irqreturn_t rc, handled = IRQ_NONE;
654 * To guarantee that all interrupt events are serviced, we need to
655 * re-inspect Slot Status register after clearing what is presumed
656 * to be the last pending interrupt.
659 rc = pciehp_isr(irq, dev_id);
660 if (rc == IRQ_HANDLED)
661 handled = IRQ_HANDLED;
662 } while (rc == IRQ_HANDLED);
664 /* Return IRQ_HANDLED if we handled one or more events */
668 static void pcie_enable_notification(struct controller *ctrl)
673 * TBD: Power fault detected software notification support.
675 * Power fault detected software notification is not enabled
676 * now, because it caused power fault detected interrupt storm
677 * on some machines. On those machines, power fault detected
678 * bit in the slot status register was set again immediately
679 * when it is cleared in the interrupt service routine, and
680 * next power fault detected interrupt was notified again.
684 * Always enable link events: thus link-up and link-down shall
685 * always be treated as hotplug and unplug respectively. Enable
686 * presence detect only if Attention Button is not present.
688 cmd = PCI_EXP_SLTCTL_DLLSCE;
689 if (ATTN_BUTTN(ctrl))
690 cmd |= PCI_EXP_SLTCTL_ABPE;
692 cmd |= PCI_EXP_SLTCTL_PDCE;
693 if (!pciehp_poll_mode)
694 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
696 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
697 PCI_EXP_SLTCTL_PFDE |
698 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
699 PCI_EXP_SLTCTL_DLLSCE);
701 pcie_write_cmd_nowait(ctrl, cmd, mask);
702 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
703 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
706 void pcie_reenable_notification(struct controller *ctrl)
709 * Clear both Presence and Data Link Layer Changed to make sure
710 * those events still fire after we have re-enabled them.
712 pcie_capability_write_word(ctrl->pcie->port, PCI_EXP_SLTSTA,
713 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
714 pcie_enable_notification(ctrl);
717 static void pcie_disable_notification(struct controller *ctrl)
721 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
722 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
723 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
724 PCI_EXP_SLTCTL_DLLSCE);
725 pcie_write_cmd(ctrl, 0, mask);
726 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
727 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
731 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
732 * bus reset of the bridge, but at the same time we want to ensure that it is
733 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
734 * disable link state notification and presence detection change notification
735 * momentarily, if we see that they could interfere. Also, clear any spurious
738 int pciehp_reset_slot(struct slot *slot, int probe)
740 struct controller *ctrl = slot->ctrl;
741 struct pci_dev *pdev = ctrl_dev(ctrl);
742 u16 stat_mask = 0, ctrl_mask = 0;
747 if (!ATTN_BUTTN(ctrl)) {
748 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
749 stat_mask |= PCI_EXP_SLTSTA_PDC;
751 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
752 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
754 pcie_write_cmd(ctrl, 0, ctrl_mask);
755 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
756 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
757 if (pciehp_poll_mode)
758 del_timer_sync(&ctrl->poll_timer);
760 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
762 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
763 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
764 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
765 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
766 if (pciehp_poll_mode)
767 int_poll_timeout(ctrl->poll_timer.data);
772 int pcie_init_notification(struct controller *ctrl)
774 if (pciehp_request_irq(ctrl))
776 pcie_enable_notification(ctrl);
777 ctrl->notification_enabled = 1;
781 void pcie_shutdown_notification(struct controller *ctrl)
783 if (ctrl->notification_enabled) {
784 pcie_disable_notification(ctrl);
785 pciehp_free_irq(ctrl);
786 ctrl->notification_enabled = 0;
790 static int pcie_init_slot(struct controller *ctrl)
794 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
798 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
803 mutex_init(&slot->lock);
804 mutex_init(&slot->hotplug_lock);
805 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
813 static void pcie_cleanup_slot(struct controller *ctrl)
815 struct slot *slot = ctrl->slot;
817 destroy_workqueue(slot->wq);
821 static inline void dbg_ctrl(struct controller *ctrl)
823 struct pci_dev *pdev = ctrl->pcie->port;
829 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
830 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
831 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
832 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
833 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
836 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
838 struct controller *pcie_init(struct pcie_device *dev)
840 struct controller *ctrl;
841 u32 slot_cap, link_cap;
842 struct pci_dev *pdev = dev->port;
844 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
846 dev_err(&dev->device, "%s: Out of memory\n", __func__);
850 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
852 if (pdev->hotplug_user_indicators)
853 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
856 * We assume no Thunderbolt controllers support Command Complete events,
857 * but some controllers falsely claim they do.
859 if (pdev->is_thunderbolt)
860 slot_cap |= PCI_EXP_SLTCAP_NCCS;
862 ctrl->slot_cap = slot_cap;
863 mutex_init(&ctrl->ctrl_lock);
864 init_waitqueue_head(&ctrl->queue);
867 /* Check if Data Link Layer Link Active Reporting is implemented */
868 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
869 if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
870 ctrl->link_active_reporting = 1;
872 /* Clear all remaining event bits in Slot Status register */
873 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
874 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
875 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
876 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
878 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
879 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
880 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
881 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
882 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
883 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
884 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
885 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
886 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
887 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
888 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
889 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
891 if (pcie_init_slot(ctrl))
902 void pciehp_release_ctrl(struct controller *ctrl)
904 pcie_cleanup_slot(ctrl);